if_athvar.h revision 251484
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 251484 2013-06-07 05:18:07Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38241567Sadrian#include <machine/atomic.h> 39241567Sadrian 40185522Ssam#include <dev/ath/ath_hal/ah.h> 41185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 42119783Ssam#include <net80211/ieee80211_radiotap.h> 43116743Ssam#include <dev/ath/if_athioctl.h> 44138570Ssam#include <dev/ath/if_athrate.h> 45242782Sadrian#ifdef ATH_DEBUG_ALQ 46242782Sadrian#include <dev/ath/if_ath_alq.h> 47242782Sadrian#endif 48116743Ssam 49116743Ssam#define ATH_TIMEOUT 1000 50116743Ssam 51220033Sadrian/* 52237000Sadrian * There is a separate TX ath_buf pool for management frames. 53237000Sadrian * This ensures that management frames such as probe responses 54237000Sadrian * and BAR frames can be transmitted during periods of high 55237000Sadrian * TX activity. 56237000Sadrian */ 57237000Sadrian#define ATH_MGMT_TXBUF 32 58237000Sadrian 59237000Sadrian/* 60220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 61220033Sadrian */ 62220053Sadrian#ifdef ATH_ENABLE_11N 63235804Sadrian#define ATH_TXBUF 512 64220033Sadrian#define ATH_RXBUF 512 65220033Sadrian#endif 66220033Sadrian 67155481Ssam#ifndef ATH_RXBUF 68116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 69155481Ssam#endif 70155481Ssam#ifndef ATH_TXBUF 71170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 72155481Ssam#endif 73178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 74178354Ssam 75140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 76138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79116743Ssam 80225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83147067Ssam 84147057Ssam/* 85147057Ssam * The key cache is used for h/w cipher state and also for 86147057Ssam * tracking station state such as the current tx antenna. 87147057Ssam * We also setup a mapping table between key cache slot indices 88147057Ssam * and station state to short-circuit node lookups on rx. 89147057Ssam * Different parts have different size key caches. We handle 90147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 91147057Ssam */ 92147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 93147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 94147057Ssam 95170530Ssamstruct taskqueue; 96170530Ssamstruct kthread; 97170530Ssamstruct ath_buf; 98170530Ssam 99227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 100227328Sadrian 101227328Sadrian/* 102227328Sadrian * Per-TID state 103227328Sadrian * 104227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 105227328Sadrian */ 106227328Sadrianstruct ath_tid { 107241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 108227328Sadrian struct ath_node *an; /* pointer to parent */ 109227328Sadrian int tid; /* tid */ 110227328Sadrian int ac; /* which AC gets this trafic */ 111227328Sadrian int hwq_depth; /* how many buffers are on HW */ 112243786Sadrian u_int axq_depth; /* SW queue depth */ 113227328Sadrian 114240585Sadrian struct { 115241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 116240585Sadrian u_int axq_depth; /* SW queue depth */ 117240585Sadrian } filtq; 118240585Sadrian 119227328Sadrian /* 120227328Sadrian * Entry on the ath_txq; when there's traffic 121227328Sadrian * to send 122227328Sadrian */ 123227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 124227328Sadrian int sched; 125227328Sadrian int paused; /* >0 if the TID has been paused */ 126240585Sadrian 127240585Sadrian /* 128240585Sadrian * These are flags - perhaps later collapse 129240585Sadrian * down to a single uint32_t ? 130240585Sadrian */ 131235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 132233908Sadrian int bar_wait; /* waiting for BAR */ 133233908Sadrian int bar_tx; /* BAR TXed */ 134240585Sadrian int isfiltered; /* is this node currently filtered */ 135227328Sadrian 136227328Sadrian /* 137227328Sadrian * Is the TID being cleaned up after a transition 138227328Sadrian * from aggregation to non-aggregation? 139227328Sadrian * When this is set to 1, this TID will be paused 140227328Sadrian * and no further traffic will be queued until all 141227328Sadrian * the hardware packets pending for this TID have been 142227328Sadrian * TXed/completed; at which point (non-aggregation) 143227328Sadrian * traffic will resume being TXed. 144227328Sadrian */ 145227328Sadrian int cleanup_inprogress; 146227328Sadrian /* 147227328Sadrian * How many hardware-queued packets are 148227328Sadrian * waiting to be cleaned up. 149227328Sadrian * This is only valid if cleanup_inprogress is 1. 150227328Sadrian */ 151227328Sadrian int incomp; 152227328Sadrian 153227328Sadrian /* 154227328Sadrian * The following implements a ring representing 155227328Sadrian * the frames in the current BAW. 156227328Sadrian * To avoid copying the array content each time 157227328Sadrian * the BAW is moved, the baw_head/baw_tail point 158227328Sadrian * to the current BAW begin/end; when the BAW is 159227328Sadrian * shifted the head/tail of the array are also 160227328Sadrian * appropriately shifted. 161227328Sadrian */ 162227328Sadrian /* active tx buffers, beginning at current BAW */ 163227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 164227328Sadrian /* where the baw head is in the array */ 165227328Sadrian int baw_head; 166227328Sadrian /* where the BAW tail is in the array */ 167227328Sadrian int baw_tail; 168227328Sadrian}; 169227328Sadrian 170138570Ssam/* driver-specific node state */ 171116743Ssamstruct ath_node { 172119150Ssam struct ieee80211_node an_node; /* base class */ 173178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 174178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 175241170Sadrian uint32_t an_is_powersave; /* node is sleeping */ 176242271Sadrian uint32_t an_stack_psq; /* net80211 psq isn't empty */ 177242271Sadrian uint32_t an_tim_set; /* TIM has been set */ 178170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 179227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 180227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 181250607Sadrian struct mtx an_mtx; /* protecting the rate control state */ 182241567Sadrian uint32_t an_swq_depth; /* how many SWQ packets for this 183241567Sadrian node */ 184245708Sadrian int clrdmask; /* has clrdmask been set */ 185250665Sadrian uint32_t an_leak_count; /* How many frames to leak during pause */ 186138570Ssam /* variable-length rate control state follows */ 187116743Ssam}; 188138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 189138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 190116743Ssam 191138570Ssam#define ATH_RSSI_LPF_LEN 10 192138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 193138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 194138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 195138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 196138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 197138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 198138570Ssam if ((y) >= -20) \ 199138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 200138570Ssam} while (0) 201184358Ssam#define ATH_EP_RND(x,mul) \ 202184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 203184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 204138570Ssam 205237000Sadriantypedef enum { 206237000Sadrian ATH_BUFTYPE_NORMAL = 0, 207237000Sadrian ATH_BUFTYPE_MGMT = 1, 208237000Sadrian} ath_buf_type_t; 209237000Sadrian 210116743Ssamstruct ath_buf { 211227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 212227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 213116743Ssam int bf_nseg; 214238436Sadrian HAL_STATUS bf_rxstatus; 215186904Ssam uint16_t bf_flags; /* status flags (below) */ 216239282Sadrian uint16_t bf_descid; /* 16 bit descriptor ID */ 217116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 218165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 219116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 220138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 221116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 222116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 223227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 224227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 225116743Ssam bus_size_t bf_mapsize; 226140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 227116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 228251014Sadrian uint32_t bf_nextfraglen; /* length of next fragment */ 229227328Sadrian 230227328Sadrian /* Completion function to call on TX complete (fail or not) */ 231227328Sadrian /* 232227328Sadrian * "fail" here is set to 1 if the queue entries were removed 233227328Sadrian * through a call to ath_tx_draintxq(). 234227328Sadrian */ 235227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 236227328Sadrian 237227328Sadrian /* This state is kept to support software retries and aggregation */ 238227328Sadrian struct { 239237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 240227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 241227328Sadrian 242237046Sadrian uint8_t bfs_retries; /* retry count */ 243237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 244237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 245237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 246244109Sadrian uint8_t bfs_tx_queue; /* destination hardware TX queue */ 247237046Sadrian 248234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 249234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 250234109Sadrian bfs_isretried:1, /* retried frame? */ 251234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 252234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 253234109Sadrian bfs_shpream:1, /* use short preamble */ 254234109Sadrian bfs_istxfrag:1, /* is fragmented */ 255234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 256234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 257236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 258234109Sadrian 259227328Sadrian /* 260227328Sadrian * These fields are passed into the 261227328Sadrian * descriptor setup functions. 262227328Sadrian */ 263237153Sadrian 264237153Sadrian /* Make this an 8 bit value? */ 265227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 266237153Sadrian 267237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 268237153Sadrian 269237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 270227328Sadrian uint16_t bfs_al; /* length of aggregate */ 271237153Sadrian 272237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 273237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 274237153Sadrian uint8_t bfs_try0; /* first try count */ 275237153Sadrian 276237153Sadrian uint16_t bfs_txpower; /* tx power */ 277227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 278237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 279237153Sadrian 280237153Sadrian /* 16 bit? */ 281237153Sadrian int32_t bfs_keyix; /* crypto key index */ 282237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 283237153Sadrian 284237153Sadrian /* Make this an 8 bit value? */ 285227328Sadrian enum ieee80211_protmode bfs_protmode; 286237153Sadrian 287237153Sadrian /* 16 bit? */ 288237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 289227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 290227328Sadrian } bf_state; 291116743Ssam}; 292227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 293116743Ssam 294237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 295186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 296248745Sadrian#define ATH_BUF_FIFOEND 0x00000004 297248745Sadrian#define ATH_BUF_FIFOPTR 0x00000008 298186904Ssam 299248745Sadrian#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 300248745Sadrian 301138570Ssam/* 302138570Ssam * DMA state for tx/rx descriptors. 303138570Ssam */ 304138570Ssamstruct ath_descdma { 305138570Ssam const char* dd_name; 306138570Ssam struct ath_desc *dd_desc; /* descriptors */ 307238708Sadrian int dd_descsize; /* size of single descriptor */ 308138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 309158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 310138570Ssam bus_dma_segment_t dd_dseg; 311138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 312138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 313138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 314138570Ssam}; 315138570Ssam 316138570Ssam/* 317138570Ssam * Data transmit queue state. One of these exists for each 318138570Ssam * hardware transmit queue. Packets sent to us from above 319138570Ssam * are assigned to queues based on their priority. Not all 320138570Ssam * devices support a complete set of hardware transmit queues. 321138570Ssam * For those devices the array sc_ac2q will map multiple 322138570Ssam * priorities to fewer hardware queues (typically all to one 323138570Ssam * hardware queue). 324138570Ssam */ 325138570Ssamstruct ath_txq { 326227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 327138570Ssam u_int axq_qnum; /* hardware q number */ 328178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 329190579Ssam u_int axq_ac; /* WME AC */ 330186904Ssam u_int axq_flags; 331250783Sadrian//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 332250783Sadrian#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 333156073Ssam u_int axq_depth; /* queue depth (stat only) */ 334227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 335138570Ssam u_int axq_intrcnt; /* interrupt count */ 336138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 337227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 338248671Sadrian struct mtx axq_lock; /* lock on q and link */ 339248671Sadrian 340248311Sadrian /* 341248745Sadrian * This is the FIFO staging buffer when doing EDMA. 342248745Sadrian * 343248745Sadrian * For legacy chips, we just push the head pointer to 344248745Sadrian * the hardware and we ignore this list. 345248745Sadrian * 346248745Sadrian * For EDMA, the staging buffer is treated as normal; 347248745Sadrian * when it's time to push a list of frames to the hardware 348248745Sadrian * we move that list here and we stamp buffers with 349248745Sadrian * flags to identify the beginning/end of that particular 350248745Sadrian * FIFO entry. 351248745Sadrian */ 352248745Sadrian struct { 353248745Sadrian TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 354248745Sadrian u_int axq_depth; 355248745Sadrian } fifo; 356248745Sadrian u_int axq_fifo_depth; /* depth of FIFO frames */ 357248745Sadrian 358248745Sadrian /* 359248311Sadrian * XXX the holdingbf field is protected by the TXBUF lock 360248671Sadrian * for now, NOT the TXQ lock. 361248311Sadrian * 362248311Sadrian * Architecturally, it would likely be better to move 363248311Sadrian * the holdingbf field to a separate array in ath_softc 364248311Sadrian * just to highlight that it's not protected by the normal 365248311Sadrian * TX path lock. 366248311Sadrian */ 367248264Sadrian struct ath_buf *axq_holdingbf; /* holding TX buffer */ 368155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 369227344Sadrian 370227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 371248671Sadrian /* 372248671Sadrian * This is protected by the general TX path lock, not (for now) 373248671Sadrian * by the TXQ lock. 374248671Sadrian */ 375227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 376138570Ssam}; 377138570Ssam 378248671Sadrian#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 379248671Sadrian snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 380248671Sadrian device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 381248671Sadrian mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 382248671Sadrian } while (0) 383248671Sadrian#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 384248671Sadrian#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 385248671Sadrian#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 386248671Sadrian#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 387250391Sadrian#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 388250391Sadrian MA_NOTOWNED) 389248671Sadrian 390248671Sadrian 391227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 392227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 393227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 394241170Sadrian#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 395241170Sadrian MA_NOTOWNED) 396227328Sadrian 397241336Sadrian/* 398241336Sadrian * These are for the hardware queue. 399241336Sadrian */ 400227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 401227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 402227344Sadrian (_tq)->axq_depth++; \ 403227344Sadrian} while (0) 404138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 405227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 406138570Ssam (_tq)->axq_depth++; \ 407138570Ssam} while (0) 408227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 409227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 410138570Ssam (_tq)->axq_depth--; \ 411138570Ssam} while (0) 412239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 413227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 414138570Ssam 415241336Sadrian/* 416241566Sadrian * These are for the TID software queue. 417241336Sadrian */ 418241336Sadrian#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 419241336Sadrian TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 420241336Sadrian (_tq)->axq_depth++; \ 421250609Sadrian (_tq)->an->an_swq_depth++; \ 422241336Sadrian} while (0) 423241336Sadrian#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 424241336Sadrian TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 425241336Sadrian (_tq)->axq_depth++; \ 426250609Sadrian (_tq)->an->an_swq_depth++; \ 427241336Sadrian} while (0) 428241336Sadrian#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 429241336Sadrian TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 430241336Sadrian (_tq)->axq_depth--; \ 431250609Sadrian (_tq)->an->an_swq_depth--; \ 432241336Sadrian} while (0) 433241336Sadrian#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 434241336Sadrian#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 435241336Sadrian 436241566Sadrian/* 437241566Sadrian * These are for the TID filtered frame queue 438241566Sadrian */ 439241566Sadrian#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 440241566Sadrian TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 441241566Sadrian (_tq)->axq_depth++; \ 442250609Sadrian (_tq)->an->an_swq_depth++; \ 443241566Sadrian} while (0) 444241566Sadrian#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 445241566Sadrian TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 446241566Sadrian (_tq)->axq_depth++; \ 447250609Sadrian (_tq)->an->an_swq_depth++; \ 448241566Sadrian} while (0) 449241566Sadrian#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 450241566Sadrian TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 451241566Sadrian (_tq)->axq_depth--; \ 452250609Sadrian (_tq)->an->an_swq_depth--; \ 453241566Sadrian} while (0) 454241566Sadrian#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 455241566Sadrian#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 456241566Sadrian 457178354Ssamstruct ath_vap { 458178354Ssam struct ieee80211vap av_vap; /* base class */ 459178354Ssam int av_bslot; /* beacon slot index */ 460178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 461178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 462178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 463178354Ssam 464178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 465192468Ssam struct mbuf *, int, int, int); 466178354Ssam int (*av_newstate)(struct ieee80211vap *, 467178354Ssam enum ieee80211_state, int); 468178354Ssam void (*av_bmiss)(struct ieee80211vap *); 469241170Sadrian void (*av_node_ps)(struct ieee80211_node *, int); 470242271Sadrian int (*av_set_tim)(struct ieee80211_node *, int); 471250665Sadrian void (*av_recv_pspoll)(struct ieee80211_node *, 472250665Sadrian struct mbuf *); 473178354Ssam}; 474178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 475178354Ssam 476155491Ssamstruct taskqueue; 477155486Ssamstruct ath_tx99; 478155486Ssam 479227328Sadrian/* 480227328Sadrian * Whether to reset the TX/RX queue with or without 481227328Sadrian * a queue flush. 482227328Sadrian */ 483227328Sadriantypedef enum { 484227328Sadrian ATH_RESET_DEFAULT = 0, 485227328Sadrian ATH_RESET_NOLOSS = 1, 486227328Sadrian ATH_RESET_FULL = 2, 487227328Sadrian} ATH_RESET_TYPE; 488227328Sadrian 489238055Sadrianstruct ath_rx_methods { 490248529Sadrian void (*recv_sched_queue)(struct ath_softc *sc, 491248529Sadrian HAL_RX_QUEUE q, int dosched); 492248529Sadrian void (*recv_sched)(struct ath_softc *sc, int dosched); 493238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 494238055Sadrian int (*recv_start)(struct ath_softc *sc); 495238055Sadrian void (*recv_flush)(struct ath_softc *sc); 496238055Sadrian void (*recv_tasklet)(void *arg, int npending); 497238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 498238055Sadrian struct ath_buf *bf); 499238284Sadrian int (*recv_setup)(struct ath_softc *sc); 500238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 501238055Sadrian}; 502238055Sadrian 503238284Sadrian/* 504238284Sadrian * Represent the current state of the RX FIFO. 505238284Sadrian */ 506238284Sadrianstruct ath_rx_edma { 507238284Sadrian struct ath_buf **m_fifo; 508238284Sadrian int m_fifolen; 509238284Sadrian int m_fifo_head; 510238284Sadrian int m_fifo_tail; 511238284Sadrian int m_fifo_depth; 512238284Sadrian struct mbuf *m_rxpending; 513238284Sadrian}; 514238284Sadrian 515238855Sadrianstruct ath_tx_edma_fifo { 516238855Sadrian struct ath_buf **m_fifo; 517238855Sadrian int m_fifolen; 518238855Sadrian int m_fifo_head; 519238855Sadrian int m_fifo_tail; 520238855Sadrian int m_fifo_depth; 521238855Sadrian}; 522238855Sadrian 523238710Sadrianstruct ath_tx_methods { 524238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 525238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 526238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 527238931Sadrian 528238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 529238931Sadrian struct ath_txq *txq); 530238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 531238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 532239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 533239204Sadrian ATH_RESET_TYPE reset_type); 534238710Sadrian}; 535238710Sadrian 536116743Ssamstruct ath_softc { 537147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 538138570Ssam struct ath_stats sc_stats; /* interface statistics */ 539227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 540234090Sadrian struct ath_intr_stats sc_intr_stats; 541235491Sadrian uint64_t sc_debug; 542240899Sadrian uint64_t sc_ktrdebug; 543178354Ssam int sc_nvaps; /* # vaps */ 544178354Ssam int sc_nstavaps; /* # station vaps */ 545195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 546178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 547178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 548178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 549178354Ssam 550238055Sadrian struct ath_rx_methods sc_rx; 551238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 552249565Sadrian ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 553238710Sadrian struct ath_tx_methods sc_tx; 554238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 555238710Sadrian 556245465Sadrian /* 557245465Sadrian * This is (currently) protected by the TX queue lock; 558245465Sadrian * it should migrate to a separate lock later 559245465Sadrian * so as to minimise contention. 560245465Sadrian */ 561245465Sadrian ath_bufhead sc_txbuf_list; 562245465Sadrian 563238284Sadrian int sc_rx_statuslen; 564238284Sadrian int sc_tx_desclen; 565238284Sadrian int sc_tx_statuslen; 566238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 567238284Sadrian int sc_edma_bufsize; 568238055Sadrian 569227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 570138570Ssam void (*sc_node_free)(struct ieee80211_node *); 571116743Ssam device_t sc_dev; 572159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 573159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 574116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 575116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 576227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 577227328Sadrian char sc_pcu_mtx_name[32]; 578238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 579238433Sadrian char sc_rx_mtx_name[32]; 580246453Sadrian struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 581242391Sadrian char sc_tx_mtx_name[32]; 582246453Sadrian struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 583246453Sadrian char sc_tx_ic_mtx_name[32]; 584155491Ssam struct taskqueue *sc_tq; /* private task queue */ 585116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 586138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 587155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 588138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 589242527Sadrian 590242527Sadrian /* 591242527Sadrian * First set of flags. 592242527Sadrian */ 593242527Sadrian uint32_t sc_invalid : 1,/* disable hardware accesses */ 594178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 595238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 596178354Ssam sc_softled : 1,/* enable LED gpio status */ 597228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 598178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 599178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 600178354Ssam sc_diversity: 1,/* enable rx diversity */ 601178354Ssam sc_hasveol : 1,/* tx VEOL support */ 602178354Ssam sc_ledstate : 1,/* LED on/off state */ 603178354Ssam sc_blinking : 1,/* LED blink operation active */ 604178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 605178354Ssam sc_scanning : 1,/* scanning active */ 606155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 607178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 608165571Ssam sc_xchanmode: 1,/* extended channel mode */ 609170530Ssam sc_outdoor : 1,/* outdoor operation */ 610178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 611178354Ssam sc_hasbmask : 1,/* bssid mask support */ 612195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 613178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 614178354Ssam sc_beacons : 1,/* beacons running */ 615178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 616178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 617179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 618185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 619186904Ssam sc_tdma : 1,/* TDMA in use */ 620189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 621220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 622224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 623238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 624238284Sadrian sc_isedma : 1;/* supports EDMA */ 625242527Sadrian 626242527Sadrian /* 627242527Sadrian * Second set of flags. 628242527Sadrian */ 629247366Sadrian u_int32_t sc_use_ent : 1, 630247366Sadrian sc_rx_stbc : 1, 631250865Sadrian sc_tx_stbc : 1, 632251401Sadrian sc_hasenforcetxop : 1, /* support enforce TxOP */ 633251401Sadrian sc_rx_lnamixer : 1; /* RX using LNA mixing */ 634242527Sadrian 635248671Sadrian int sc_cabq_enable; /* Enable cabq transmission */ 636248671Sadrian 637242527Sadrian /* 638242527Sadrian * Enterprise mode configuration for AR9380 and later chipsets. 639242527Sadrian */ 640242527Sadrian uint32_t sc_ent_cfg; 641242527Sadrian 642178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 643178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 644116743Ssam /* rate tables */ 645188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 646116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 647116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 648155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 649138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 650170530Ssam u_int16_t sc_curaid; /* current association id */ 651187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 652170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 653116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 654140432Ssam struct { 655140432Ssam u_int8_t ieeerate; /* IEEE rate */ 656140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 657140761Ssam u_int8_t txflags; /* radiotap tx flags */ 658140432Ssam u_int16_t ledon; /* softled on time */ 659140432Ssam u_int16_t ledoff; /* softled off time */ 660140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 661138570Ssam u_int8_t sc_protrix; /* protection rate index */ 662170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 663155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 664170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 665170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 666138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 667227346Sadrian 668116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 669227651Sadrian 670227346Sadrian /* 671227346Sadrian * These are modified in the interrupt handler as well as 672227346Sadrian * the task queues and other contexts. Thus these must be 673227346Sadrian * protected by a mutex, or they could clash. 674227346Sadrian * 675227346Sadrian * For now, access to these is behind the ATH_LOCK, 676227346Sadrian * just to save time. 677227346Sadrian */ 678227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 679227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 680227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 681227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 682227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 683227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 684227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 685227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 686227346Sadrian 687138570Ssam u_int sc_keymax; /* size of key cache */ 688147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 689116743Ssam 690228891Sadrian /* 691228891Sadrian * Software based LED blinking 692228891Sadrian */ 693140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 694140432Ssam u_int sc_ledon; /* pin setting for LED on */ 695140432Ssam u_int sc_ledidle; /* idle polling interval */ 696140432Ssam int sc_ledevent; /* time of last LED event */ 697184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 698140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 699140432Ssam struct callout sc_ledtimer; /* led off timer */ 700138570Ssam 701228891Sadrian /* 702228891Sadrian * Hardware based LED blinking 703228891Sadrian */ 704228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 705228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 706228891Sadrian 707155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 708155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 709155515Ssam 710178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 711138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 712116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 713116743Ssam struct task sc_rxtask; /* rx int processing */ 714138570Ssam u_int8_t sc_defant; /* current default antenna */ 715138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 716155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 717192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 718192468Ssam struct ath_rx_radiotap_header sc_rx_th; 719192468Ssam int sc_rx_th_len; 720192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 721116743Ssam 722138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 723239282Sadrian uint16_t sc_txbuf_descid; 724138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 725237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 726237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 727237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 728238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 729138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 730155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 731138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 732138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 733138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 734138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 735116743Ssam struct task sc_txtask; /* tx int processing */ 736233673Sadrian struct task sc_txqtask; /* tx proc processing */ 737238709Sadrian 738238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 739238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 740238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 741238709Sadrian 742189605Ssam int sc_wd_timer; /* count down for wd timer */ 743189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 744192468Ssam struct ath_tx_radiotap_header sc_tx_th; 745192468Ssam int sc_tx_th_len; 746116743Ssam 747138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 748138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 749116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 750138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 751138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 752138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 753116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 754138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 755232163Sadrian struct task sc_resettask; /* interface reset task */ 756234369Sadrian struct task sc_fataltask; /* fatal task */ 757138570Ssam enum { 758138570Ssam OK, /* no change needed */ 759138570Ssam UPDATE, /* update pending */ 760138570Ssam COMMIT /* beacon sent, commit change */ 761138570Ssam } sc_updateslot; /* slot time update fsm */ 762178354Ssam int sc_slotupdate; /* slot to advance fsm */ 763178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 764178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 765116743Ssam 766116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 767185744Ssam int sc_lastlongcal; /* last long cal completed */ 768185744Ssam int sc_lastcalreset;/* last cal reset done */ 769217684Sadrian int sc_lastani; /* last ANI poll */ 770217684Sadrian int sc_lastshortcal; /* last short calibration */ 771217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 772155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 773186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 774186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 775186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 776186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 777186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 778186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 779186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 780186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 781217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 782249639Sadrian uint32_t sc_txchainmask; /* hardware TX chainmask */ 783249639Sadrian uint32_t sc_rxchainmask; /* hardware RX chainmask */ 784249639Sadrian uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 785249639Sadrian uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 786249639Sadrian uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 787247085Sadrian int sc_aggr_limit; /* TX limit on all aggregates */ 788247087Sadrian int sc_delim_min_pad; /* Minimum delimiter count */ 789222585Sadrian 790232764Sadrian /* Queue limits */ 791232764Sadrian 792227328Sadrian /* 793232764Sadrian * To avoid queue starvation in congested conditions, 794232764Sadrian * these parameters tune the maximum number of frames 795232764Sadrian * queued to the data/mcastq before they're dropped. 796232764Sadrian * 797232764Sadrian * This is to prevent: 798232764Sadrian * + a single destination overwhelming everything, including 799232764Sadrian * management/multicast frames; 800232764Sadrian * + multicast frames overwhelming everything (when the 801232764Sadrian * air is sufficiently busy that cabq can't drain.) 802250665Sadrian * + A node in powersave shouldn't be allowed to exhaust 803250665Sadrian * all available mbufs; 804232764Sadrian * 805232764Sadrian * These implement: 806232764Sadrian * + data_minfree is the maximum number of free buffers 807232764Sadrian * overall to successfully allow a data frame. 808232764Sadrian * 809232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 810232764Sadrian */ 811250326Sadrian int sc_txq_node_maxdepth; 812232764Sadrian int sc_txq_data_minfree; 813232764Sadrian int sc_txq_mcastq_maxdepth; 814250665Sadrian int sc_txq_node_psq_maxdepth; 815232764Sadrian 816232764Sadrian /* 817250866Sadrian * Software queue twiddles 818227328Sadrian * 819250866Sadrian * hwq_limit_nonaggr: 820250866Sadrian * when to begin limiting non-aggregate frames to the 821250866Sadrian * hardware queue, regardless of the TID. 822250866Sadrian * hwq_limit_aggr: 823250866Sadrian * when to begin limiting A-MPDU frames to the 824250866Sadrian * hardware queue, regardless of the TID. 825227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 826227328Sadrian * TID will be scheduled again 827227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 828227328Sadrian * stops being scheduled. 829227328Sadrian */ 830250866Sadrian int sc_hwq_limit_nonaggr; 831250866Sadrian int sc_hwq_limit_aggr; 832227328Sadrian int sc_tid_hwq_lo; 833227328Sadrian int sc_tid_hwq_hi; 834227328Sadrian 835222585Sadrian /* DFS related state */ 836222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 837222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 838222585Sadrian struct task sc_dfstask; /* DFS processing task */ 839227328Sadrian 840244951Sadrian /* Spectral related state */ 841244951Sadrian void *sc_spectral; 842244951Sadrian int sc_dospectral; 843244951Sadrian 844242782Sadrian /* ALQ */ 845242853Skevlo#ifdef ATH_DEBUG_ALQ 846242782Sadrian struct if_ath_alq sc_alq; 847242782Sadrian#endif 848242782Sadrian 849227328Sadrian /* TX AMPDU handling */ 850227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 851227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 852227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 853227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 854227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 855227328Sadrian struct ieee80211_tx_ampdu *); 856227328Sadrian void (*sc_addba_response_timeout) 857227328Sadrian (struct ieee80211_node *, 858227328Sadrian struct ieee80211_tx_ampdu *); 859227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 860227328Sadrian struct ieee80211_tx_ampdu *tap, 861227328Sadrian int status); 862116743Ssam}; 863116743Ssam 864121100Ssam#define ATH_LOCK_INIT(_sc) \ 865121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 866167252Ssam NULL, MTX_DEF | MTX_RECURSE) 867121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 868121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 869121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 870121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 871227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 872121100Ssam 873227328Sadrian/* 874246453Sadrian * The TX lock is non-reentrant and serialises the TX frame send 875246453Sadrian * and completion operations. 876242391Sadrian */ 877242391Sadrian#define ATH_TX_LOCK_INIT(_sc) do {\ 878242391Sadrian snprintf((_sc)->sc_tx_mtx_name, \ 879242391Sadrian sizeof((_sc)->sc_tx_mtx_name), \ 880242391Sadrian "%s TX lock", \ 881242391Sadrian device_get_nameunit((_sc)->sc_dev)); \ 882242391Sadrian mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 883242391Sadrian NULL, MTX_DEF); \ 884242391Sadrian } while (0) 885242391Sadrian#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 886242391Sadrian#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 887242391Sadrian#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 888242391Sadrian#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 889242391Sadrian MA_OWNED) 890242391Sadrian#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 891242391Sadrian MA_NOTOWNED) 892246745Sadrian#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 893246745Sadrian mtx_trylock(&(_sc)->sc_tx_mtx)) 894242391Sadrian 895242391Sadrian/* 896246453Sadrian * The IC TX lock is non-reentrant and serialises packet queuing from 897246453Sadrian * the upper layers. 898246453Sadrian */ 899246453Sadrian#define ATH_TX_IC_LOCK_INIT(_sc) do {\ 900246453Sadrian snprintf((_sc)->sc_tx_ic_mtx_name, \ 901246453Sadrian sizeof((_sc)->sc_tx_ic_mtx_name), \ 902246453Sadrian "%s IC TX lock", \ 903246453Sadrian device_get_nameunit((_sc)->sc_dev)); \ 904246453Sadrian mtx_init(&(_sc)->sc_tx_ic_mtx, (_sc)->sc_tx_ic_mtx_name, \ 905246453Sadrian NULL, MTX_DEF); \ 906246453Sadrian } while (0) 907246453Sadrian#define ATH_TX_IC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_ic_mtx) 908246453Sadrian#define ATH_TX_IC_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_ic_mtx) 909246453Sadrian#define ATH_TX_IC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_ic_mtx) 910246453Sadrian#define ATH_TX_IC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 911246453Sadrian MA_OWNED) 912246453Sadrian#define ATH_TX_IC_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 913246453Sadrian MA_NOTOWNED) 914246453Sadrian 915246453Sadrian/* 916227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 917227328Sadrian * Although currently the interrupt code is run in netisr context and 918227328Sadrian * doesn't require this, this may change in the future. 919227328Sadrian * Please keep this in mind when protecting certain code paths 920227328Sadrian * with the PCU lock. 921227328Sadrian * 922227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 923227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 924227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 925227328Sadrian * 926227328Sadrian * Although the current single-thread taskqueue mechanism protects the 927227328Sadrian * majority of these situations by simply serialising them, there are 928227328Sadrian * a few others which occur at the same time. These include the TX path 929227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 930227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 931227328Sadrian */ 932227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 933227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 934227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 935227328Sadrian "%s PCU lock", \ 936227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 937227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 938227328Sadrian NULL, MTX_DEF); \ 939227328Sadrian } while (0) 940227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 941227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 942227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 943227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 944227328Sadrian MA_OWNED) 945227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 946227651Sadrian MA_NOTOWNED) 947227328Sadrian 948238433Sadrian/* 949238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 950238433Sadrian * RX FIFO/list isn't modified by various execution paths. 951238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 952238433Sadrian * RX path can be executed via various reset/channel change paths. 953238433Sadrian */ 954238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 955238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 956238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 957238433Sadrian "%s RX lock", \ 958238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 959238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 960238433Sadrian NULL, MTX_DEF); \ 961238433Sadrian } while (0) 962238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 963238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 964238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 965238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 966238433Sadrian MA_OWNED) 967238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 968238433Sadrian MA_NOTOWNED) 969238433Sadrian 970138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 971138570Ssam 972155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 973155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 974155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 975167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 976155482Ssam} while (0) 977121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 978121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 979121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 980121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 981121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 982250391Sadrian#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 983250391Sadrian mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 984121100Ssam 985238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 986238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 987238709Sadrian "%s_buf", \ 988238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 989238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 990238709Sadrian MTX_DEF); \ 991238709Sadrian} while (0) 992238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 993238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 994238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 995238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 996238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 997238709Sadrian 998116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 999116743Ssamint ath_detach(struct ath_softc *); 1000116743Ssamvoid ath_resume(struct ath_softc *); 1001116743Ssamvoid ath_suspend(struct ath_softc *); 1002116743Ssamvoid ath_shutdown(struct ath_softc *); 1003116743Ssamvoid ath_intr(void *); 1004116743Ssam 1005116743Ssam/* 1006116743Ssam * HAL definitions to comply with local coding convention. 1007116743Ssam */ 1008138570Ssam#define ath_hal_detach(_ah) \ 1009138570Ssam ((*(_ah)->ah_detach)((_ah))) 1010116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 1011116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1012186904Ssam#define ath_hal_macversion(_ah) \ 1013186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1014116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 1015116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1016116743Ssam#define ath_hal_getmac(_ah, _mac) \ 1017116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1018138570Ssam#define ath_hal_setmac(_ah, _mac) \ 1019138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1020178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 1021178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1022178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 1023178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1024116743Ssam#define ath_hal_intrset(_ah, _mask) \ 1025116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1026116743Ssam#define ath_hal_intrget(_ah) \ 1027116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 1028116743Ssam#define ath_hal_intrpend(_ah) \ 1029116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 1030116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 1031116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1032116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 1033116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1034155515Ssam#define ath_hal_setpower(_ah, _mode) \ 1035155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1036138570Ssam#define ath_hal_keycachesize(_ah) \ 1037138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1038116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 1039116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1040138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1041138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1042116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 1043116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1044116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 1045116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1046116743Ssam#define ath_hal_getrxfilter(_ah) \ 1047116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 1048116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 1049116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1050116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1051116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1052116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 1053116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1054238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1055238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1056186904Ssam/* NB: common across all chips */ 1057186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1058116743Ssam#define ath_hal_gettsf32(_ah) \ 1059186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 1060116743Ssam#define ath_hal_gettsf64(_ah) \ 1061116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 1062243425Sadrian#define ath_hal_settsf64(_ah, _val) \ 1063243425Sadrian ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1064116743Ssam#define ath_hal_resettsf(_ah) \ 1065116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 1066116743Ssam#define ath_hal_rxena(_ah) \ 1067116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 1068116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1069116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1070116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 1071116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1072138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 1073138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1074238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 1075238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1076116743Ssam#define ath_hal_txstart(_ah, _q) \ 1077116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1078116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 1079116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1080155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1081155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1082185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1083185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1084185744Ssam#define ath_hal_calreset(_ah, _chan) \ 1085185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1086116743Ssam#define ath_hal_setledstate(_ah, _state) \ 1087116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 1088138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1089138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1090116743Ssam#define ath_hal_beaconreset(_ah) \ 1091116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1092186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 1093186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1094138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 1095138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1096225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 1097225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 1098116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 1099138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1100138570Ssam#define ath_hal_phydisable(_ah) \ 1101138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 1102138570Ssam#define ath_hal_setopmode(_ah) \ 1103138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 1104116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 1105116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1106116743Ssam#define ath_hal_stoppcurecv(_ah) \ 1107116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 1108116743Ssam#define ath_hal_startpcurecv(_ah) \ 1109116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 1110116743Ssam#define ath_hal_stopdmarecv(_ah) \ 1111116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 1112138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1113138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1114138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 1115155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1116170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1117116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1118116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1119116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 1120116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1121116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 1122116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1123138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1124138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1125138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1126138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1127186904Ssam/* NB: common across all chips */ 1128186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1129186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 1130186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1131116743Ssam#define ath_hal_getrfgain(_ah) \ 1132116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 1133138570Ssam#define ath_hal_getdefantenna(_ah) \ 1134138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 1135138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 1136138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1137155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1138155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1139217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 1140217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1141138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 1142138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1143138570Ssam#define ath_hal_setslottime(_ah, _us) \ 1144138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1145138570Ssam#define ath_hal_getslottime(_ah) \ 1146138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 1147138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 1148138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1149138570Ssam#define ath_hal_getacktimeout(_ah) \ 1150138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 1151138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 1152138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1153138570Ssam#define ath_hal_getctstimeout(_ah) \ 1154138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 1155138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1156138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1157138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1158138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1159138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 1160138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1161138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 1162155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1163155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 1164184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1165138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 1166138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 1167178354Ssam#define ath_hal_gettkipmic(_ah) \ 1168178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1169178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 1170178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1171162410Ssam#define ath_hal_hastkipsplit(_ah) \ 1172138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1173162410Ssam#define ath_hal_gettkipsplit(_ah) \ 1174162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1175162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 1176162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1177178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 1178178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1179138570Ssam#define ath_hal_hwphycounters(_ah) \ 1180138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1181138570Ssam#define ath_hal_hasdiversity(_ah) \ 1182138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1183138570Ssam#define ath_hal_getdiversity(_ah) \ 1184138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1185138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 1186138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1187166954Ssam#define ath_hal_getantennaswitch(_ah) \ 1188166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1189166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 1190166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1191138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 1192138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1193138570Ssam#define ath_hal_setdiag(_ah, _v) \ 1194138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1195138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 1196138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1197138570Ssam#define ath_hal_hasveol(_ah) \ 1198138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1199138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 1200138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1201138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 1202138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1203138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1204138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1205138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1206138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1207138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 1208138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1209138570Ssam#define ath_hal_settpscale(_ah, _v) \ 1210138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1211138570Ssam#define ath_hal_hastpc(_ah) \ 1212138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1213138570Ssam#define ath_hal_gettpc(_ah) \ 1214138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1215138570Ssam#define ath_hal_settpc(_ah, _v) \ 1216138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1217138570Ssam#define ath_hal_hasbursting(_ah) \ 1218138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1219203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1220203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1221147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1222147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1223147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1224147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1225170530Ssam#define ath_hal_hasfastframes(_ah) \ 1226170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1227178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1228178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1229195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1230195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1231178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1232178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1233178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1234178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1235178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1236178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1237155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1238155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1239155515Ssam#define ath_hal_getrfkill(_ah) \ 1240155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1241155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1242155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1243155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1244155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1245155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1246155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1247155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1248155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1249155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1250155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1251155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1252155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1253155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1254155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1255184354Ssam#define ath_hal_hasintmit(_ah) \ 1256230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1257230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1258184354Ssam#define ath_hal_getintmit(_ah) \ 1259230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1260230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1261184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1262230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1263230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1264238280Sadrian 1265250865Sadrian#define ath_hal_hasenforcetxop(_ah) \ 1266250865Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1267250865Sadrian#define ath_hal_getenforcetxop(_ah) \ 1268250865Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1269250865Sadrian#define ath_hal_setenforcetxop(_ah, _v) \ 1270250865Sadrian ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1271250865Sadrian 1272251401Sadrian#define ath_hal_hasrxlnamixer(_ah) \ 1273251401Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1274250865Sadrian 1275238280Sadrian/* EDMA definitions */ 1276237953Sadrian#define ath_hal_hasedma(_ah) \ 1277237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1278237953Sadrian 0, NULL) == HAL_OK) 1279238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1280238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1281238280Sadrian == HAL_OK) 1282238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1283238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1284238280Sadrian == HAL_OK) 1285238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1286238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1287238280Sadrian == HAL_OK) 1288238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1289238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1290238280Sadrian == HAL_OK) 1291238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1292238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1293238280Sadrian == HAL_OK) 1294238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1295238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1296238280Sadrian == HAL_OK) 1297238280Sadrian 1298154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1299154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1300238280Sadrian 1301238280Sadrian/* 802.11n HAL methods */ 1302218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1303218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1304218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1305218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1306231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1307231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1308231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1309231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1310218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1311230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1312230493Sadrian 0, NULL) == HAL_OK) 1313220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1314230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1315230493Sadrian 0, NULL) == HAL_OK) 1316220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1317220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1318225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1319230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1320230493Sadrian 0, NULL) == HAL_OK) 1321116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1322116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1323165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1324165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1325116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1326116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1327116743Ssam _rtsrate, _rtsdura) \ 1328116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1329116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1330155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1331138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1332116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1333138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1334116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1335239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1336239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1337239051Sadrian (_first), (_last), (_ds0))) 1338165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1339165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1340155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1341155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1342217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1343217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1344238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1345238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1346238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1347238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1348238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1349238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1350238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1351238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1352238731Sadrian (_size))) 1353242510Sadrian#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1354242510Sadrian ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1355116743Ssam 1356218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1357218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1358218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1359218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1360239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1361239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1362239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1363239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1364233895Sadrian (_first), (_last), (_lastaggr))) 1365218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1366218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1367227328Sadrian 1368218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1369218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1370218067Sadrian (_series), (_ns), (_flags))) 1371227328Sadrian 1372227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1373242510Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1374242510Sadrian#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1375227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1376227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1377227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1378227328Sadrian 1379218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1380218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1381227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1382227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1383247774Sadrian#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1384247774Sadrian ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1385218066Sadrian 1386230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1387230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1388230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1389230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1390230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1391230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1392230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1393230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1394230493Sadrian 1395222585Sadrian/* 1396235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1397235957Sadrian */ 1398235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1399235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1400235957Sadrian#define ath_hal_disablepcie(_ah) \ 1401235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1402235957Sadrian 1403235957Sadrian/* 1404222585Sadrian * This is badly-named; you need to set the correct parameters 1405222585Sadrian * to begin to receive useful radar events; and even then 1406222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1407222585Sadrian * more information. 1408222585Sadrian */ 1409222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1410222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1411222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1412222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1413239656Sadrian#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1414239656Sadrian ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1415222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1416230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1417230493Sadrian (_buf), (_event))) 1418224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1419224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1420230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1421155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1422234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1423234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1424230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1425230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1426247286Sadrian#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1427247286Sadrian ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1428155515Ssam 1429245002Sadrian#define ath_hal_spectral_supported(_ah) \ 1430245002Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1431244947Sadrian#define ath_hal_spectral_get_config(_ah, _p) \ 1432244947Sadrian ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1433244947Sadrian#define ath_hal_spectral_configure(_ah, _p) \ 1434244947Sadrian ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1435244947Sadrian#define ath_hal_spectral_start(_ah) \ 1436244947Sadrian ((*(_ah)->ah_spectralStart)((_ah))) 1437244947Sadrian#define ath_hal_spectral_stop(_ah) \ 1438244947Sadrian ((*(_ah)->ah_spectralStop)((_ah))) 1439244947Sadrian 1440251484Sadrian#define ath_hal_btcoex_supported(_ah) \ 1441251484Sadrian (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1442251484Sadrian#define ath_hal_btcoex_set_info(_ah, _info) \ 1443251484Sadrian ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1444251484Sadrian#define ath_hal_btcoex_set_config(_ah, _cfg) \ 1445251484Sadrian ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1446251484Sadrian#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1447251484Sadrian ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1448251484Sadrian#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1449251484Sadrian ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1450251484Sadrian#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1451251484Sadrian ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1452251484Sadrian#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1453251484Sadrian ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1454251484Sadrian#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1455251484Sadrian ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1456251484Sadrian#define ath_hal_btcoex_enable(_ah) \ 1457251484Sadrian ((*(_ah)->ah_btCoexEnable)((_ah))) 1458251484Sadrian#define ath_hal_btcoex_disable(_ah) \ 1459251484Sadrian ((*(_ah)->ah_btCoexDisable)((_ah))) 1460251484Sadrian 1461116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1462