if_athvar.h revision 244951
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 244951 2013-01-02 03:59:02Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38241567Sadrian#include <machine/atomic.h> 39241567Sadrian 40185522Ssam#include <dev/ath/ath_hal/ah.h> 41185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 42119783Ssam#include <net80211/ieee80211_radiotap.h> 43116743Ssam#include <dev/ath/if_athioctl.h> 44138570Ssam#include <dev/ath/if_athrate.h> 45242782Sadrian#ifdef ATH_DEBUG_ALQ 46242782Sadrian#include <dev/ath/if_ath_alq.h> 47242782Sadrian#endif 48116743Ssam 49116743Ssam#define ATH_TIMEOUT 1000 50116743Ssam 51220033Sadrian/* 52237000Sadrian * There is a separate TX ath_buf pool for management frames. 53237000Sadrian * This ensures that management frames such as probe responses 54237000Sadrian * and BAR frames can be transmitted during periods of high 55237000Sadrian * TX activity. 56237000Sadrian */ 57237000Sadrian#define ATH_MGMT_TXBUF 32 58237000Sadrian 59237000Sadrian/* 60220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 61220033Sadrian */ 62220053Sadrian#ifdef ATH_ENABLE_11N 63235804Sadrian#define ATH_TXBUF 512 64220033Sadrian#define ATH_RXBUF 512 65220033Sadrian#endif 66220033Sadrian 67155481Ssam#ifndef ATH_RXBUF 68116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 69155481Ssam#endif 70155481Ssam#ifndef ATH_TXBUF 71170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 72155481Ssam#endif 73178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 74178354Ssam 75140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 76138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79116743Ssam 80225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83147067Ssam 84147057Ssam/* 85147057Ssam * The key cache is used for h/w cipher state and also for 86147057Ssam * tracking station state such as the current tx antenna. 87147057Ssam * We also setup a mapping table between key cache slot indices 88147057Ssam * and station state to short-circuit node lookups on rx. 89147057Ssam * Different parts have different size key caches. We handle 90147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 91147057Ssam */ 92147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 93147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 94147057Ssam 95170530Ssamstruct taskqueue; 96170530Ssamstruct kthread; 97170530Ssamstruct ath_buf; 98170530Ssam 99227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 100227328Sadrian 101227328Sadrian/* 102227328Sadrian * Per-TID state 103227328Sadrian * 104227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 105227328Sadrian */ 106227328Sadrianstruct ath_tid { 107241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 108227328Sadrian struct ath_node *an; /* pointer to parent */ 109227328Sadrian int tid; /* tid */ 110227328Sadrian int ac; /* which AC gets this trafic */ 111227328Sadrian int hwq_depth; /* how many buffers are on HW */ 112243786Sadrian u_int axq_depth; /* SW queue depth */ 113227328Sadrian 114240585Sadrian struct { 115241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 116240585Sadrian u_int axq_depth; /* SW queue depth */ 117240585Sadrian } filtq; 118240585Sadrian 119227328Sadrian /* 120227328Sadrian * Entry on the ath_txq; when there's traffic 121227328Sadrian * to send 122227328Sadrian */ 123227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 124227328Sadrian int sched; 125227328Sadrian int paused; /* >0 if the TID has been paused */ 126240585Sadrian 127240585Sadrian /* 128240585Sadrian * These are flags - perhaps later collapse 129240585Sadrian * down to a single uint32_t ? 130240585Sadrian */ 131235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 132233908Sadrian int bar_wait; /* waiting for BAR */ 133233908Sadrian int bar_tx; /* BAR TXed */ 134240585Sadrian int isfiltered; /* is this node currently filtered */ 135240585Sadrian int clrdmask; /* has clrdmask been set */ 136227328Sadrian 137227328Sadrian /* 138227328Sadrian * Is the TID being cleaned up after a transition 139227328Sadrian * from aggregation to non-aggregation? 140227328Sadrian * When this is set to 1, this TID will be paused 141227328Sadrian * and no further traffic will be queued until all 142227328Sadrian * the hardware packets pending for this TID have been 143227328Sadrian * TXed/completed; at which point (non-aggregation) 144227328Sadrian * traffic will resume being TXed. 145227328Sadrian */ 146227328Sadrian int cleanup_inprogress; 147227328Sadrian /* 148227328Sadrian * How many hardware-queued packets are 149227328Sadrian * waiting to be cleaned up. 150227328Sadrian * This is only valid if cleanup_inprogress is 1. 151227328Sadrian */ 152227328Sadrian int incomp; 153227328Sadrian 154227328Sadrian /* 155227328Sadrian * The following implements a ring representing 156227328Sadrian * the frames in the current BAW. 157227328Sadrian * To avoid copying the array content each time 158227328Sadrian * the BAW is moved, the baw_head/baw_tail point 159227328Sadrian * to the current BAW begin/end; when the BAW is 160227328Sadrian * shifted the head/tail of the array are also 161227328Sadrian * appropriately shifted. 162227328Sadrian */ 163227328Sadrian /* active tx buffers, beginning at current BAW */ 164227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 165227328Sadrian /* where the baw head is in the array */ 166227328Sadrian int baw_head; 167227328Sadrian /* where the BAW tail is in the array */ 168227328Sadrian int baw_tail; 169227328Sadrian}; 170227328Sadrian 171138570Ssam/* driver-specific node state */ 172116743Ssamstruct ath_node { 173119150Ssam struct ieee80211_node an_node; /* base class */ 174178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 175178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 176241170Sadrian uint32_t an_is_powersave; /* node is sleeping */ 177242271Sadrian uint32_t an_stack_psq; /* net80211 psq isn't empty */ 178242271Sadrian uint32_t an_tim_set; /* TIM has been set */ 179170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 180227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 181227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 182227328Sadrian struct mtx an_mtx; /* protecting the ath_node state */ 183241567Sadrian uint32_t an_swq_depth; /* how many SWQ packets for this 184241567Sadrian node */ 185138570Ssam /* variable-length rate control state follows */ 186116743Ssam}; 187138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 188138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 189116743Ssam 190138570Ssam#define ATH_RSSI_LPF_LEN 10 191138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 192138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 193138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 194138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 195138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 196138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 197138570Ssam if ((y) >= -20) \ 198138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 199138570Ssam} while (0) 200184358Ssam#define ATH_EP_RND(x,mul) \ 201184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 202184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 203138570Ssam 204237000Sadriantypedef enum { 205237000Sadrian ATH_BUFTYPE_NORMAL = 0, 206237000Sadrian ATH_BUFTYPE_MGMT = 1, 207237000Sadrian} ath_buf_type_t; 208237000Sadrian 209116743Ssamstruct ath_buf { 210227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 211227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 212116743Ssam int bf_nseg; 213238436Sadrian HAL_STATUS bf_rxstatus; 214186904Ssam uint16_t bf_flags; /* status flags (below) */ 215239282Sadrian uint16_t bf_descid; /* 16 bit descriptor ID */ 216116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 217165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 218116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 219138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 220116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 221116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 222227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 223227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 224116743Ssam bus_size_t bf_mapsize; 225140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 226116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 227227328Sadrian 228227328Sadrian /* Completion function to call on TX complete (fail or not) */ 229227328Sadrian /* 230227328Sadrian * "fail" here is set to 1 if the queue entries were removed 231227328Sadrian * through a call to ath_tx_draintxq(). 232227328Sadrian */ 233227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 234227328Sadrian 235227328Sadrian /* This state is kept to support software retries and aggregation */ 236227328Sadrian struct { 237237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 238227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 239227328Sadrian 240237046Sadrian uint8_t bfs_retries; /* retry count */ 241237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 242237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 243237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 244244109Sadrian uint8_t bfs_tx_queue; /* destination hardware TX queue */ 245237046Sadrian 246234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 247234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 248234109Sadrian bfs_isretried:1, /* retried frame? */ 249234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 250234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 251234109Sadrian bfs_shpream:1, /* use short preamble */ 252234109Sadrian bfs_istxfrag:1, /* is fragmented */ 253234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 254234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 255236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 256234109Sadrian 257227328Sadrian /* 258227328Sadrian * These fields are passed into the 259227328Sadrian * descriptor setup functions. 260227328Sadrian */ 261237153Sadrian 262237153Sadrian /* Make this an 8 bit value? */ 263227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 264237153Sadrian 265237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 266237153Sadrian 267237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 268227328Sadrian uint16_t bfs_al; /* length of aggregate */ 269237153Sadrian 270237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 271237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 272237153Sadrian uint8_t bfs_try0; /* first try count */ 273237153Sadrian 274237153Sadrian uint16_t bfs_txpower; /* tx power */ 275227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 276237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 277237153Sadrian 278237153Sadrian /* 16 bit? */ 279237153Sadrian int32_t bfs_keyix; /* crypto key index */ 280237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 281237153Sadrian 282237153Sadrian /* Make this an 8 bit value? */ 283227328Sadrian enum ieee80211_protmode bfs_protmode; 284237153Sadrian 285237153Sadrian /* 16 bit? */ 286237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 287227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 288227328Sadrian } bf_state; 289116743Ssam}; 290227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 291116743Ssam 292237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 293186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 294186904Ssam 295138570Ssam/* 296138570Ssam * DMA state for tx/rx descriptors. 297138570Ssam */ 298138570Ssamstruct ath_descdma { 299138570Ssam const char* dd_name; 300138570Ssam struct ath_desc *dd_desc; /* descriptors */ 301238708Sadrian int dd_descsize; /* size of single descriptor */ 302138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 303158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 304138570Ssam bus_dma_segment_t dd_dseg; 305138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 306138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 307138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 308138570Ssam}; 309138570Ssam 310138570Ssam/* 311138570Ssam * Data transmit queue state. One of these exists for each 312138570Ssam * hardware transmit queue. Packets sent to us from above 313138570Ssam * are assigned to queues based on their priority. Not all 314138570Ssam * devices support a complete set of hardware transmit queues. 315138570Ssam * For those devices the array sc_ac2q will map multiple 316138570Ssam * priorities to fewer hardware queues (typically all to one 317138570Ssam * hardware queue). 318138570Ssam */ 319138570Ssamstruct ath_txq { 320227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 321138570Ssam u_int axq_qnum; /* hardware q number */ 322178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 323190579Ssam u_int axq_ac; /* WME AC */ 324186904Ssam u_int axq_flags; 325186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 326156073Ssam u_int axq_depth; /* queue depth (stat only) */ 327227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 328239197Sadrian u_int axq_fifo_depth; /* depth of FIFO frames */ 329138570Ssam u_int axq_intrcnt; /* interrupt count */ 330138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 331227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 332155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 333227344Sadrian 334227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 335227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 336138570Ssam}; 337138570Ssam 338227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 339227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 340227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 341241170Sadrian#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 342241170Sadrian MA_NOTOWNED) 343227328Sadrian 344241336Sadrian/* 345241336Sadrian * These are for the hardware queue. 346241336Sadrian */ 347227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 348227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 349227344Sadrian (_tq)->axq_depth++; \ 350227344Sadrian} while (0) 351138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 352227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 353138570Ssam (_tq)->axq_depth++; \ 354138570Ssam} while (0) 355227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 356227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 357138570Ssam (_tq)->axq_depth--; \ 358138570Ssam} while (0) 359239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 360227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 361138570Ssam 362241336Sadrian/* 363241566Sadrian * These are for the TID software queue. 364241336Sadrian */ 365241336Sadrian#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 366241336Sadrian TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 367241336Sadrian (_tq)->axq_depth++; \ 368241567Sadrian atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 369241336Sadrian} while (0) 370241336Sadrian#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 371241336Sadrian TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 372241336Sadrian (_tq)->axq_depth++; \ 373241567Sadrian atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 374241336Sadrian} while (0) 375241336Sadrian#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 376241336Sadrian TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 377241336Sadrian (_tq)->axq_depth--; \ 378241567Sadrian atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 379241336Sadrian} while (0) 380241336Sadrian#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 381241336Sadrian#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 382241336Sadrian 383241566Sadrian/* 384241566Sadrian * These are for the TID filtered frame queue 385241566Sadrian */ 386241566Sadrian#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 387241566Sadrian TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 388241566Sadrian (_tq)->axq_depth++; \ 389241567Sadrian atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 390241566Sadrian} while (0) 391241566Sadrian#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 392241566Sadrian TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 393241566Sadrian (_tq)->axq_depth++; \ 394241567Sadrian atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 395241566Sadrian} while (0) 396241566Sadrian#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 397241566Sadrian TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 398241566Sadrian (_tq)->axq_depth--; \ 399241567Sadrian atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 400241566Sadrian} while (0) 401241566Sadrian#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 402241566Sadrian#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 403241566Sadrian 404178354Ssamstruct ath_vap { 405178354Ssam struct ieee80211vap av_vap; /* base class */ 406178354Ssam int av_bslot; /* beacon slot index */ 407178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 408178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 409178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 410178354Ssam 411178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 412192468Ssam struct mbuf *, int, int, int); 413178354Ssam int (*av_newstate)(struct ieee80211vap *, 414178354Ssam enum ieee80211_state, int); 415178354Ssam void (*av_bmiss)(struct ieee80211vap *); 416241170Sadrian void (*av_node_ps)(struct ieee80211_node *, int); 417242271Sadrian int (*av_set_tim)(struct ieee80211_node *, int); 418178354Ssam}; 419178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 420178354Ssam 421155491Ssamstruct taskqueue; 422155486Ssamstruct ath_tx99; 423155486Ssam 424227328Sadrian/* 425227328Sadrian * Whether to reset the TX/RX queue with or without 426227328Sadrian * a queue flush. 427227328Sadrian */ 428227328Sadriantypedef enum { 429227328Sadrian ATH_RESET_DEFAULT = 0, 430227328Sadrian ATH_RESET_NOLOSS = 1, 431227328Sadrian ATH_RESET_FULL = 2, 432227328Sadrian} ATH_RESET_TYPE; 433227328Sadrian 434238055Sadrianstruct ath_rx_methods { 435238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 436238055Sadrian int (*recv_start)(struct ath_softc *sc); 437238055Sadrian void (*recv_flush)(struct ath_softc *sc); 438238055Sadrian void (*recv_tasklet)(void *arg, int npending); 439238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 440238055Sadrian struct ath_buf *bf); 441238284Sadrian int (*recv_setup)(struct ath_softc *sc); 442238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 443238055Sadrian}; 444238055Sadrian 445238284Sadrian/* 446238284Sadrian * Represent the current state of the RX FIFO. 447238284Sadrian */ 448238284Sadrianstruct ath_rx_edma { 449238284Sadrian struct ath_buf **m_fifo; 450238284Sadrian int m_fifolen; 451238284Sadrian int m_fifo_head; 452238284Sadrian int m_fifo_tail; 453238284Sadrian int m_fifo_depth; 454238284Sadrian struct mbuf *m_rxpending; 455238284Sadrian}; 456238284Sadrian 457238855Sadrianstruct ath_tx_edma_fifo { 458238855Sadrian struct ath_buf **m_fifo; 459238855Sadrian int m_fifolen; 460238855Sadrian int m_fifo_head; 461238855Sadrian int m_fifo_tail; 462238855Sadrian int m_fifo_depth; 463238855Sadrian}; 464238855Sadrian 465238710Sadrianstruct ath_tx_methods { 466238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 467238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 468238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 469238931Sadrian 470238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 471238931Sadrian struct ath_txq *txq); 472238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 473238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 474239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 475239204Sadrian ATH_RESET_TYPE reset_type); 476238710Sadrian}; 477238710Sadrian 478116743Ssamstruct ath_softc { 479147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 480138570Ssam struct ath_stats sc_stats; /* interface statistics */ 481227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 482234090Sadrian struct ath_intr_stats sc_intr_stats; 483235491Sadrian uint64_t sc_debug; 484240899Sadrian uint64_t sc_ktrdebug; 485178354Ssam int sc_nvaps; /* # vaps */ 486178354Ssam int sc_nstavaps; /* # station vaps */ 487195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 488178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 489178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 490178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 491178354Ssam 492238055Sadrian struct ath_rx_methods sc_rx; 493238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 494238710Sadrian struct ath_tx_methods sc_tx; 495238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 496238710Sadrian 497238284Sadrian int sc_rx_statuslen; 498238284Sadrian int sc_tx_desclen; 499238284Sadrian int sc_tx_statuslen; 500238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 501238284Sadrian int sc_edma_bufsize; 502238055Sadrian 503227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 504138570Ssam void (*sc_node_free)(struct ieee80211_node *); 505116743Ssam device_t sc_dev; 506159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 507159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 508116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 509116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 510227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 511227328Sadrian char sc_pcu_mtx_name[32]; 512238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 513238433Sadrian char sc_rx_mtx_name[32]; 514242391Sadrian struct mtx sc_tx_mtx; /* TX access mutex */ 515242391Sadrian char sc_tx_mtx_name[32]; 516155491Ssam struct taskqueue *sc_tq; /* private task queue */ 517116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 518138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 519155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 520138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 521242527Sadrian 522242527Sadrian /* 523242527Sadrian * First set of flags. 524242527Sadrian */ 525242527Sadrian uint32_t sc_invalid : 1,/* disable hardware accesses */ 526178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 527238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 528178354Ssam sc_softled : 1,/* enable LED gpio status */ 529228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 530178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 531178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 532178354Ssam sc_diversity: 1,/* enable rx diversity */ 533178354Ssam sc_hasveol : 1,/* tx VEOL support */ 534178354Ssam sc_ledstate : 1,/* LED on/off state */ 535178354Ssam sc_blinking : 1,/* LED blink operation active */ 536178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 537178354Ssam sc_scanning : 1,/* scanning active */ 538155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 539178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 540165571Ssam sc_xchanmode: 1,/* extended channel mode */ 541170530Ssam sc_outdoor : 1,/* outdoor operation */ 542178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 543178354Ssam sc_hasbmask : 1,/* bssid mask support */ 544195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 545178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 546178354Ssam sc_beacons : 1,/* beacons running */ 547178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 548178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 549179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 550185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 551186904Ssam sc_tdma : 1,/* TDMA in use */ 552189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 553220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 554224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 555238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 556238284Sadrian sc_isedma : 1;/* supports EDMA */ 557242527Sadrian 558242527Sadrian /* 559242527Sadrian * Second set of flags. 560242527Sadrian */ 561242527Sadrian u_int32_t sc_use_ent : 1; 562242527Sadrian 563242527Sadrian /* 564242527Sadrian * Enterprise mode configuration for AR9380 and later chipsets. 565242527Sadrian */ 566242527Sadrian uint32_t sc_ent_cfg; 567242527Sadrian 568178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 569178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 570116743Ssam /* rate tables */ 571188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 572116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 573116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 574155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 575138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 576170530Ssam u_int16_t sc_curaid; /* current association id */ 577187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 578170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 579116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 580140432Ssam struct { 581140432Ssam u_int8_t ieeerate; /* IEEE rate */ 582140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 583140761Ssam u_int8_t txflags; /* radiotap tx flags */ 584140432Ssam u_int16_t ledon; /* softled on time */ 585140432Ssam u_int16_t ledoff; /* softled off time */ 586140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 587138570Ssam u_int8_t sc_protrix; /* protection rate index */ 588170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 589155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 590170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 591170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 592138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 593227346Sadrian 594116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 595227651Sadrian 596227346Sadrian /* 597227346Sadrian * These are modified in the interrupt handler as well as 598227346Sadrian * the task queues and other contexts. Thus these must be 599227346Sadrian * protected by a mutex, or they could clash. 600227346Sadrian * 601227346Sadrian * For now, access to these is behind the ATH_LOCK, 602227346Sadrian * just to save time. 603227346Sadrian */ 604227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 605227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 606227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 607227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 608227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 609227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 610227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 611227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 612227346Sadrian 613138570Ssam u_int sc_keymax; /* size of key cache */ 614147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 615116743Ssam 616228891Sadrian /* 617228891Sadrian * Software based LED blinking 618228891Sadrian */ 619140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 620140432Ssam u_int sc_ledon; /* pin setting for LED on */ 621140432Ssam u_int sc_ledidle; /* idle polling interval */ 622140432Ssam int sc_ledevent; /* time of last LED event */ 623184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 624140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 625140432Ssam struct callout sc_ledtimer; /* led off timer */ 626138570Ssam 627228891Sadrian /* 628228891Sadrian * Hardware based LED blinking 629228891Sadrian */ 630228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 631228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 632228891Sadrian 633155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 634155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 635155515Ssam 636178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 637138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 638116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 639116743Ssam struct task sc_rxtask; /* rx int processing */ 640138570Ssam u_int8_t sc_defant; /* current default antenna */ 641138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 642155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 643192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 644192468Ssam struct ath_rx_radiotap_header sc_rx_th; 645192468Ssam int sc_rx_th_len; 646192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 647116743Ssam 648138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 649239282Sadrian uint16_t sc_txbuf_descid; 650138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 651237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 652237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 653237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 654238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 655138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 656155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 657138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 658138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 659138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 660138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 661116743Ssam struct task sc_txtask; /* tx int processing */ 662233673Sadrian struct task sc_txqtask; /* tx proc processing */ 663238709Sadrian 664238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 665238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 666238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 667238709Sadrian 668189605Ssam int sc_wd_timer; /* count down for wd timer */ 669189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 670192468Ssam struct ath_tx_radiotap_header sc_tx_th; 671192468Ssam int sc_tx_th_len; 672116743Ssam 673138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 674138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 675116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 676138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 677138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 678138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 679116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 680138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 681232163Sadrian struct task sc_resettask; /* interface reset task */ 682234369Sadrian struct task sc_fataltask; /* fatal task */ 683138570Ssam enum { 684138570Ssam OK, /* no change needed */ 685138570Ssam UPDATE, /* update pending */ 686138570Ssam COMMIT /* beacon sent, commit change */ 687138570Ssam } sc_updateslot; /* slot time update fsm */ 688178354Ssam int sc_slotupdate; /* slot to advance fsm */ 689178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 690178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 691116743Ssam 692116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 693185744Ssam int sc_lastlongcal; /* last long cal completed */ 694185744Ssam int sc_lastcalreset;/* last cal reset done */ 695217684Sadrian int sc_lastani; /* last ANI poll */ 696217684Sadrian int sc_lastshortcal; /* last short calibration */ 697217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 698155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 699186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 700186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 701186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 702186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 703186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 704186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 705186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 706186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 707217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 708218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 709218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 710233967Sadrian int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 711222585Sadrian 712232764Sadrian /* Queue limits */ 713232764Sadrian 714227328Sadrian /* 715232764Sadrian * To avoid queue starvation in congested conditions, 716232764Sadrian * these parameters tune the maximum number of frames 717232764Sadrian * queued to the data/mcastq before they're dropped. 718232764Sadrian * 719232764Sadrian * This is to prevent: 720232764Sadrian * + a single destination overwhelming everything, including 721232764Sadrian * management/multicast frames; 722232764Sadrian * + multicast frames overwhelming everything (when the 723232764Sadrian * air is sufficiently busy that cabq can't drain.) 724232764Sadrian * 725232764Sadrian * These implement: 726232764Sadrian * + data_minfree is the maximum number of free buffers 727232764Sadrian * overall to successfully allow a data frame. 728232764Sadrian * 729232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 730232764Sadrian */ 731232764Sadrian int sc_txq_data_minfree; 732232764Sadrian int sc_txq_mcastq_maxdepth; 733232764Sadrian 734232764Sadrian /* 735227328Sadrian * Aggregation twiddles 736227328Sadrian * 737227328Sadrian * hwq_limit: how busy to keep the hardware queue - don't schedule 738227328Sadrian * further packets to the hardware, regardless of the TID 739227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 740227328Sadrian * TID will be scheduled again 741227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 742227328Sadrian * stops being scheduled. 743227328Sadrian */ 744227328Sadrian int sc_hwq_limit; 745227328Sadrian int sc_tid_hwq_lo; 746227328Sadrian int sc_tid_hwq_hi; 747227328Sadrian 748222585Sadrian /* DFS related state */ 749222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 750222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 751222585Sadrian struct task sc_dfstask; /* DFS processing task */ 752227328Sadrian 753244951Sadrian /* Spectral related state */ 754244951Sadrian void *sc_spectral; 755244951Sadrian int sc_dospectral; 756244951Sadrian 757242782Sadrian /* ALQ */ 758242853Skevlo#ifdef ATH_DEBUG_ALQ 759242782Sadrian struct if_ath_alq sc_alq; 760242782Sadrian#endif 761242782Sadrian 762227328Sadrian /* TX AMPDU handling */ 763227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 764227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 765227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 766227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 767227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 768227328Sadrian struct ieee80211_tx_ampdu *); 769227328Sadrian void (*sc_addba_response_timeout) 770227328Sadrian (struct ieee80211_node *, 771227328Sadrian struct ieee80211_tx_ampdu *); 772227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 773227328Sadrian struct ieee80211_tx_ampdu *tap, 774227328Sadrian int status); 775116743Ssam}; 776116743Ssam 777121100Ssam#define ATH_LOCK_INIT(_sc) \ 778121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 779167252Ssam NULL, MTX_DEF | MTX_RECURSE) 780121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 781121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 782121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 783121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 784227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 785121100Ssam 786227328Sadrian/* 787242391Sadrian * The TX lock is non-reentrant and serialises the TX send operations. 788242391Sadrian * (ath_start(), ath_raw_xmit().) It doesn't yet serialise the TX 789242391Sadrian * completion operations; thus it can't be used (yet!) to protect 790242391Sadrian * hardware / software TXQ operations. 791242391Sadrian */ 792242391Sadrian#define ATH_TX_LOCK_INIT(_sc) do {\ 793242391Sadrian snprintf((_sc)->sc_tx_mtx_name, \ 794242391Sadrian sizeof((_sc)->sc_tx_mtx_name), \ 795242391Sadrian "%s TX lock", \ 796242391Sadrian device_get_nameunit((_sc)->sc_dev)); \ 797242391Sadrian mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 798242391Sadrian NULL, MTX_DEF); \ 799242391Sadrian } while (0) 800242391Sadrian#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 801242391Sadrian#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 802242391Sadrian#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 803242391Sadrian#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 804242391Sadrian MA_OWNED) 805242391Sadrian#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 806242391Sadrian MA_NOTOWNED) 807242391Sadrian 808242391Sadrian/* 809227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 810227328Sadrian * Although currently the interrupt code is run in netisr context and 811227328Sadrian * doesn't require this, this may change in the future. 812227328Sadrian * Please keep this in mind when protecting certain code paths 813227328Sadrian * with the PCU lock. 814227328Sadrian * 815227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 816227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 817227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 818227328Sadrian * 819227328Sadrian * Although the current single-thread taskqueue mechanism protects the 820227328Sadrian * majority of these situations by simply serialising them, there are 821227328Sadrian * a few others which occur at the same time. These include the TX path 822227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 823227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 824227328Sadrian */ 825227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 826227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 827227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 828227328Sadrian "%s PCU lock", \ 829227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 830227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 831227328Sadrian NULL, MTX_DEF); \ 832227328Sadrian } while (0) 833227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 834227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 835227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 836227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 837227328Sadrian MA_OWNED) 838227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 839227651Sadrian MA_NOTOWNED) 840227328Sadrian 841238433Sadrian/* 842238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 843238433Sadrian * RX FIFO/list isn't modified by various execution paths. 844238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 845238433Sadrian * RX path can be executed via various reset/channel change paths. 846238433Sadrian */ 847238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 848238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 849238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 850238433Sadrian "%s RX lock", \ 851238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 852238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 853238433Sadrian NULL, MTX_DEF); \ 854238433Sadrian } while (0) 855238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 856238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 857238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 858238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 859238433Sadrian MA_OWNED) 860238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 861238433Sadrian MA_NOTOWNED) 862238433Sadrian 863138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 864138570Ssam 865155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 866155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 867155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 868167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 869155482Ssam} while (0) 870121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 871121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 872121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 873121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 874121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 875121100Ssam 876238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 877238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 878238709Sadrian "%s_buf", \ 879238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 880238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 881238709Sadrian MTX_DEF); \ 882238709Sadrian} while (0) 883238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 884238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 885238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 886238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 887238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 888238709Sadrian 889116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 890116743Ssamint ath_detach(struct ath_softc *); 891116743Ssamvoid ath_resume(struct ath_softc *); 892116743Ssamvoid ath_suspend(struct ath_softc *); 893116743Ssamvoid ath_shutdown(struct ath_softc *); 894116743Ssamvoid ath_intr(void *); 895116743Ssam 896116743Ssam/* 897116743Ssam * HAL definitions to comply with local coding convention. 898116743Ssam */ 899138570Ssam#define ath_hal_detach(_ah) \ 900138570Ssam ((*(_ah)->ah_detach)((_ah))) 901116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 902116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 903186904Ssam#define ath_hal_macversion(_ah) \ 904186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 905116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 906116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 907116743Ssam#define ath_hal_getmac(_ah, _mac) \ 908116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 909138570Ssam#define ath_hal_setmac(_ah, _mac) \ 910138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 911178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 912178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 913178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 914178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 915116743Ssam#define ath_hal_intrset(_ah, _mask) \ 916116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 917116743Ssam#define ath_hal_intrget(_ah) \ 918116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 919116743Ssam#define ath_hal_intrpend(_ah) \ 920116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 921116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 922116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 923116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 924116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 925155515Ssam#define ath_hal_setpower(_ah, _mode) \ 926155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 927138570Ssam#define ath_hal_keycachesize(_ah) \ 928138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 929116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 930116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 931138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 932138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 933116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 934116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 935116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 936116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 937116743Ssam#define ath_hal_getrxfilter(_ah) \ 938116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 939116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 940116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 941116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 942116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 943116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 944116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 945238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 946238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 947186904Ssam/* NB: common across all chips */ 948186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 949116743Ssam#define ath_hal_gettsf32(_ah) \ 950186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 951116743Ssam#define ath_hal_gettsf64(_ah) \ 952116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 953243425Sadrian#define ath_hal_settsf64(_ah, _val) \ 954243425Sadrian ((*(_ah)->ah_setTsf64)((_ah), (_val))) 955116743Ssam#define ath_hal_resettsf(_ah) \ 956116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 957116743Ssam#define ath_hal_rxena(_ah) \ 958116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 959116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 960116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 961116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 962116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 963138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 964138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 965238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 966238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 967116743Ssam#define ath_hal_txstart(_ah, _q) \ 968116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 969116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 970116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 971155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 972155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 973185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 974185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 975185744Ssam#define ath_hal_calreset(_ah, _chan) \ 976185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 977116743Ssam#define ath_hal_setledstate(_ah, _state) \ 978116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 979138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 980138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 981116743Ssam#define ath_hal_beaconreset(_ah) \ 982116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 983186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 984186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 985138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 986138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 987225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 988225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 989116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 990138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 991138570Ssam#define ath_hal_phydisable(_ah) \ 992138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 993138570Ssam#define ath_hal_setopmode(_ah) \ 994138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 995116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 996116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 997116743Ssam#define ath_hal_stoppcurecv(_ah) \ 998116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 999116743Ssam#define ath_hal_startpcurecv(_ah) \ 1000116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 1001116743Ssam#define ath_hal_stopdmarecv(_ah) \ 1002116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 1003138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1004138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1005138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 1006155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1007170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1008116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1009116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1010116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 1011116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1012116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 1013116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1014138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1015138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1016138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1017138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1018186904Ssam/* NB: common across all chips */ 1019186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1020186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 1021186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1022116743Ssam#define ath_hal_getrfgain(_ah) \ 1023116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 1024138570Ssam#define ath_hal_getdefantenna(_ah) \ 1025138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 1026138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 1027138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1028155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1029155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1030217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 1031217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1032138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 1033138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1034138570Ssam#define ath_hal_setslottime(_ah, _us) \ 1035138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1036138570Ssam#define ath_hal_getslottime(_ah) \ 1037138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 1038138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 1039138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1040138570Ssam#define ath_hal_getacktimeout(_ah) \ 1041138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 1042138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 1043138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1044138570Ssam#define ath_hal_getctstimeout(_ah) \ 1045138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 1046138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1047138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1048138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1049138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1050138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 1051138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1052138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 1053155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1054155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 1055184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1056138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 1057138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 1058178354Ssam#define ath_hal_gettkipmic(_ah) \ 1059178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1060178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 1061178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1062162410Ssam#define ath_hal_hastkipsplit(_ah) \ 1063138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1064162410Ssam#define ath_hal_gettkipsplit(_ah) \ 1065162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1066162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 1067162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1068178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 1069178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1070138570Ssam#define ath_hal_hwphycounters(_ah) \ 1071138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1072138570Ssam#define ath_hal_hasdiversity(_ah) \ 1073138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1074138570Ssam#define ath_hal_getdiversity(_ah) \ 1075138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1076138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 1077138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1078166954Ssam#define ath_hal_getantennaswitch(_ah) \ 1079166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1080166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 1081166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1082138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 1083138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1084138570Ssam#define ath_hal_setdiag(_ah, _v) \ 1085138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1086138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 1087138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1088138570Ssam#define ath_hal_hasveol(_ah) \ 1089138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1090138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 1091138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1092138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 1093138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1094138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1095138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1096138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1097138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1098138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 1099138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1100138570Ssam#define ath_hal_settpscale(_ah, _v) \ 1101138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1102138570Ssam#define ath_hal_hastpc(_ah) \ 1103138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1104138570Ssam#define ath_hal_gettpc(_ah) \ 1105138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1106138570Ssam#define ath_hal_settpc(_ah, _v) \ 1107138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1108138570Ssam#define ath_hal_hasbursting(_ah) \ 1109138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1110203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1111203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1112147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1113147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1114147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1115147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1116170530Ssam#define ath_hal_hasfastframes(_ah) \ 1117170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1118178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1119178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1120195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1121195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1122178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1123178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1124178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1125178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1126178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1127178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1128155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1129155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1130155515Ssam#define ath_hal_getrfkill(_ah) \ 1131155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1132155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1133155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1134155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1135155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1136155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1137155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1138155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1139155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1140155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1141155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1142155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1143155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1144155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1145155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1146184354Ssam#define ath_hal_hasintmit(_ah) \ 1147230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1148230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1149184354Ssam#define ath_hal_getintmit(_ah) \ 1150230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1151230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1152184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1153230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1154230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1155238280Sadrian 1156238280Sadrian/* EDMA definitions */ 1157237953Sadrian#define ath_hal_hasedma(_ah) \ 1158237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1159237953Sadrian 0, NULL) == HAL_OK) 1160238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1161238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1162238280Sadrian == HAL_OK) 1163238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1164238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1165238280Sadrian == HAL_OK) 1166238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1167238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1168238280Sadrian == HAL_OK) 1169238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1170238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1171238280Sadrian == HAL_OK) 1172238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1173238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1174238280Sadrian == HAL_OK) 1175238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1176238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1177238280Sadrian == HAL_OK) 1178238280Sadrian 1179154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1180154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1181238280Sadrian 1182238280Sadrian/* 802.11n HAL methods */ 1183218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1184218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1185218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1186218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1187231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1188231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1189231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1190231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1191218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1192230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1193230493Sadrian 0, NULL) == HAL_OK) 1194220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1195230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1196230493Sadrian 0, NULL) == HAL_OK) 1197220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1198220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1199225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1200230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1201230493Sadrian 0, NULL) == HAL_OK) 1202116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1203116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1204165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1205165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1206116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1207116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1208116743Ssam _rtsrate, _rtsdura) \ 1209116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1210116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1211155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1212138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1213116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1214138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1215116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1216239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1217239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1218239051Sadrian (_first), (_last), (_ds0))) 1219165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1220165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1221155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1222155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1223217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1224217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1225238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1226238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1227238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1228238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1229238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1230238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1231238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1232238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1233238731Sadrian (_size))) 1234242510Sadrian#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1235242510Sadrian ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1236116743Ssam 1237218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1238218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1239218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1240218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1241239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1242239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1243239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1244239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1245233895Sadrian (_first), (_last), (_lastaggr))) 1246218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1247218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1248227328Sadrian 1249218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1250218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1251218067Sadrian (_series), (_ns), (_flags))) 1252227328Sadrian 1253227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1254242510Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1255242510Sadrian#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1256227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1257227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1258227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1259227328Sadrian 1260218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1261218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1262227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1263227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1264218066Sadrian 1265230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1266230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1267230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1268230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1269230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1270230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1271230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1272230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1273230493Sadrian 1274222585Sadrian/* 1275235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1276235957Sadrian */ 1277235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1278235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1279235957Sadrian#define ath_hal_disablepcie(_ah) \ 1280235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1281235957Sadrian 1282235957Sadrian/* 1283222585Sadrian * This is badly-named; you need to set the correct parameters 1284222585Sadrian * to begin to receive useful radar events; and even then 1285222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1286222585Sadrian * more information. 1287222585Sadrian */ 1288222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1289222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1290222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1291222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1292239656Sadrian#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1293239656Sadrian ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1294222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1295230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1296230493Sadrian (_buf), (_event))) 1297224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1298224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1299230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1300155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1301234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1302234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1303230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1304230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1305155515Ssam 1306244947Sadrian#define ath_hal_spectral_get_config(_ah, _p) \ 1307244947Sadrian ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1308244947Sadrian#define ath_hal_spectral_configure(_ah, _p) \ 1309244947Sadrian ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1310244947Sadrian#define ath_hal_spectral_start(_ah) \ 1311244947Sadrian ((*(_ah)->ah_spectralStart)((_ah))) 1312244947Sadrian#define ath_hal_spectral_stop(_ah) \ 1313244947Sadrian ((*(_ah)->ah_spectralStop)((_ah))) 1314244947Sadrian 1315116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1316