if_athvar.h revision 240899
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 240899 2012-09-24 20:35:56Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46220033Sadrian/* 47237000Sadrian * There is a separate TX ath_buf pool for management frames. 48237000Sadrian * This ensures that management frames such as probe responses 49237000Sadrian * and BAR frames can be transmitted during periods of high 50237000Sadrian * TX activity. 51237000Sadrian */ 52237000Sadrian#define ATH_MGMT_TXBUF 32 53237000Sadrian 54237000Sadrian/* 55220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 56220033Sadrian */ 57220053Sadrian#ifdef ATH_ENABLE_11N 58235804Sadrian#define ATH_TXBUF 512 59220033Sadrian#define ATH_RXBUF 512 60220033Sadrian#endif 61220033Sadrian 62155481Ssam#ifndef ATH_RXBUF 63116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 64155481Ssam#endif 65155481Ssam#ifndef ATH_TXBUF 66170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 67155481Ssam#endif 68178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 69178354Ssam 70140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74116743Ssam 75225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78147067Ssam 79147057Ssam/* 80147057Ssam * The key cache is used for h/w cipher state and also for 81147057Ssam * tracking station state such as the current tx antenna. 82147057Ssam * We also setup a mapping table between key cache slot indices 83147057Ssam * and station state to short-circuit node lookups on rx. 84147057Ssam * Different parts have different size key caches. We handle 85147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 86147057Ssam */ 87147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 88147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89147057Ssam 90170530Ssamstruct taskqueue; 91170530Ssamstruct kthread; 92170530Ssamstruct ath_buf; 93170530Ssam 94227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95227328Sadrian 96227328Sadrian/* 97227328Sadrian * Per-TID state 98227328Sadrian * 99227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100227328Sadrian */ 101227328Sadrianstruct ath_tid { 102227328Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103227328Sadrian u_int axq_depth; /* SW queue depth */ 104227328Sadrian char axq_name[48]; /* lock name */ 105227328Sadrian struct ath_node *an; /* pointer to parent */ 106227328Sadrian int tid; /* tid */ 107227328Sadrian int ac; /* which AC gets this trafic */ 108227328Sadrian int hwq_depth; /* how many buffers are on HW */ 109227328Sadrian 110240585Sadrian struct { 111240585Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* filtered queue */ 112240585Sadrian u_int axq_depth; /* SW queue depth */ 113240585Sadrian char axq_name[48]; /* lock name */ 114240585Sadrian } filtq; 115240585Sadrian 116227328Sadrian /* 117227328Sadrian * Entry on the ath_txq; when there's traffic 118227328Sadrian * to send 119227328Sadrian */ 120227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 121227328Sadrian int sched; 122227328Sadrian int paused; /* >0 if the TID has been paused */ 123240585Sadrian 124240585Sadrian /* 125240585Sadrian * These are flags - perhaps later collapse 126240585Sadrian * down to a single uint32_t ? 127240585Sadrian */ 128235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 129233908Sadrian int bar_wait; /* waiting for BAR */ 130233908Sadrian int bar_tx; /* BAR TXed */ 131240585Sadrian int isfiltered; /* is this node currently filtered */ 132240585Sadrian int clrdmask; /* has clrdmask been set */ 133227328Sadrian 134227328Sadrian /* 135227328Sadrian * Is the TID being cleaned up after a transition 136227328Sadrian * from aggregation to non-aggregation? 137227328Sadrian * When this is set to 1, this TID will be paused 138227328Sadrian * and no further traffic will be queued until all 139227328Sadrian * the hardware packets pending for this TID have been 140227328Sadrian * TXed/completed; at which point (non-aggregation) 141227328Sadrian * traffic will resume being TXed. 142227328Sadrian */ 143227328Sadrian int cleanup_inprogress; 144227328Sadrian /* 145227328Sadrian * How many hardware-queued packets are 146227328Sadrian * waiting to be cleaned up. 147227328Sadrian * This is only valid if cleanup_inprogress is 1. 148227328Sadrian */ 149227328Sadrian int incomp; 150227328Sadrian 151227328Sadrian /* 152227328Sadrian * The following implements a ring representing 153227328Sadrian * the frames in the current BAW. 154227328Sadrian * To avoid copying the array content each time 155227328Sadrian * the BAW is moved, the baw_head/baw_tail point 156227328Sadrian * to the current BAW begin/end; when the BAW is 157227328Sadrian * shifted the head/tail of the array are also 158227328Sadrian * appropriately shifted. 159227328Sadrian */ 160227328Sadrian /* active tx buffers, beginning at current BAW */ 161227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 162227328Sadrian /* where the baw head is in the array */ 163227328Sadrian int baw_head; 164227328Sadrian /* where the BAW tail is in the array */ 165227328Sadrian int baw_tail; 166227328Sadrian}; 167227328Sadrian 168138570Ssam/* driver-specific node state */ 169116743Ssamstruct ath_node { 170119150Ssam struct ieee80211_node an_node; /* base class */ 171178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 172178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 173170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 174227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 175227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 176227328Sadrian struct mtx an_mtx; /* protecting the ath_node state */ 177138570Ssam /* variable-length rate control state follows */ 178116743Ssam}; 179138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 180138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 181116743Ssam 182138570Ssam#define ATH_RSSI_LPF_LEN 10 183138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 184138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 185138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 186138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 187138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 188138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 189138570Ssam if ((y) >= -20) \ 190138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 191138570Ssam} while (0) 192184358Ssam#define ATH_EP_RND(x,mul) \ 193184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 194184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 195138570Ssam 196237000Sadriantypedef enum { 197237000Sadrian ATH_BUFTYPE_NORMAL = 0, 198237000Sadrian ATH_BUFTYPE_MGMT = 1, 199237000Sadrian} ath_buf_type_t; 200237000Sadrian 201116743Ssamstruct ath_buf { 202227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 203227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 204116743Ssam int bf_nseg; 205238436Sadrian HAL_STATUS bf_rxstatus; 206186904Ssam uint16_t bf_flags; /* status flags (below) */ 207239282Sadrian uint16_t bf_descid; /* 16 bit descriptor ID */ 208116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 209165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 210116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 211138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 212116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 213116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 214227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 215227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 216116743Ssam bus_size_t bf_mapsize; 217140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 218116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 219227328Sadrian 220227328Sadrian /* Completion function to call on TX complete (fail or not) */ 221227328Sadrian /* 222227328Sadrian * "fail" here is set to 1 if the queue entries were removed 223227328Sadrian * through a call to ath_tx_draintxq(). 224227328Sadrian */ 225227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 226227328Sadrian 227227328Sadrian /* This state is kept to support software retries and aggregation */ 228227328Sadrian struct { 229237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 230227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 231227328Sadrian 232237046Sadrian uint8_t bfs_retries; /* retry count */ 233237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 234237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 235237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 236237046Sadrian 237237046Sadrian struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 238237046Sadrian 239234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 240234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 241234109Sadrian bfs_isretried:1, /* retried frame? */ 242234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 243234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 244234109Sadrian bfs_shpream:1, /* use short preamble */ 245234109Sadrian bfs_istxfrag:1, /* is fragmented */ 246234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 247234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 248236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 249234109Sadrian 250227328Sadrian /* 251227328Sadrian * These fields are passed into the 252227328Sadrian * descriptor setup functions. 253227328Sadrian */ 254237153Sadrian 255237153Sadrian /* Make this an 8 bit value? */ 256227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 257237153Sadrian 258237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 259237153Sadrian 260237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 261227328Sadrian uint16_t bfs_al; /* length of aggregate */ 262237153Sadrian 263237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 264237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 265237153Sadrian uint8_t bfs_try0; /* first try count */ 266237153Sadrian 267237153Sadrian uint16_t bfs_txpower; /* tx power */ 268227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 269237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 270237153Sadrian 271237153Sadrian /* 16 bit? */ 272237153Sadrian int32_t bfs_keyix; /* crypto key index */ 273237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 274237153Sadrian 275237153Sadrian /* Make this an 8 bit value? */ 276227328Sadrian enum ieee80211_protmode bfs_protmode; 277237153Sadrian 278237153Sadrian /* 16 bit? */ 279237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 280227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 281227328Sadrian } bf_state; 282116743Ssam}; 283227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 284116743Ssam 285237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 286186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 287186904Ssam 288138570Ssam/* 289138570Ssam * DMA state for tx/rx descriptors. 290138570Ssam */ 291138570Ssamstruct ath_descdma { 292138570Ssam const char* dd_name; 293138570Ssam struct ath_desc *dd_desc; /* descriptors */ 294238708Sadrian int dd_descsize; /* size of single descriptor */ 295138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 296158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 297138570Ssam bus_dma_segment_t dd_dseg; 298138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 299138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 300138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 301138570Ssam}; 302138570Ssam 303138570Ssam/* 304138570Ssam * Data transmit queue state. One of these exists for each 305138570Ssam * hardware transmit queue. Packets sent to us from above 306138570Ssam * are assigned to queues based on their priority. Not all 307138570Ssam * devices support a complete set of hardware transmit queues. 308138570Ssam * For those devices the array sc_ac2q will map multiple 309138570Ssam * priorities to fewer hardware queues (typically all to one 310138570Ssam * hardware queue). 311138570Ssam */ 312138570Ssamstruct ath_txq { 313227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 314138570Ssam u_int axq_qnum; /* hardware q number */ 315178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 316190579Ssam u_int axq_ac; /* WME AC */ 317186904Ssam u_int axq_flags; 318186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 319156073Ssam u_int axq_depth; /* queue depth (stat only) */ 320227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 321239197Sadrian u_int axq_fifo_depth; /* depth of FIFO frames */ 322138570Ssam u_int axq_intrcnt; /* interrupt count */ 323138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 324227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 325138570Ssam struct mtx axq_lock; /* lock on q and link */ 326155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 327227344Sadrian 328227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 329227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 330138570Ssam}; 331138570Ssam 332227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 333227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 334227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 335227328Sadrian 336155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 337155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 338155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 339167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 340161425Simp} while (0) 341138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 342138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 343138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 344239261Sadrian#define ATH_TXQ_LOCK_ASSERT(_tq) \ 345239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_OWNED) 346239261Sadrian#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 347239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 348227328Sadrian#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 349138570Ssam 350236873Sadrian#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 351236873Sadrian ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 352240585Sadrian#define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 353240585Sadrian ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 354236873Sadrian 355227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 356227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 357227344Sadrian (_tq)->axq_depth++; \ 358227344Sadrian} while (0) 359138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 360227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 361138570Ssam (_tq)->axq_depth++; \ 362138570Ssam} while (0) 363227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 364227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 365138570Ssam (_tq)->axq_depth--; \ 366138570Ssam} while (0) 367239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 368227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 369138570Ssam 370178354Ssamstruct ath_vap { 371178354Ssam struct ieee80211vap av_vap; /* base class */ 372178354Ssam int av_bslot; /* beacon slot index */ 373178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 374178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 375178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 376178354Ssam 377178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 378192468Ssam struct mbuf *, int, int, int); 379178354Ssam int (*av_newstate)(struct ieee80211vap *, 380178354Ssam enum ieee80211_state, int); 381178354Ssam void (*av_bmiss)(struct ieee80211vap *); 382178354Ssam}; 383178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 384178354Ssam 385155491Ssamstruct taskqueue; 386155486Ssamstruct ath_tx99; 387155486Ssam 388227328Sadrian/* 389227328Sadrian * Whether to reset the TX/RX queue with or without 390227328Sadrian * a queue flush. 391227328Sadrian */ 392227328Sadriantypedef enum { 393227328Sadrian ATH_RESET_DEFAULT = 0, 394227328Sadrian ATH_RESET_NOLOSS = 1, 395227328Sadrian ATH_RESET_FULL = 2, 396227328Sadrian} ATH_RESET_TYPE; 397227328Sadrian 398238055Sadrianstruct ath_rx_methods { 399238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 400238055Sadrian int (*recv_start)(struct ath_softc *sc); 401238055Sadrian void (*recv_flush)(struct ath_softc *sc); 402238055Sadrian void (*recv_tasklet)(void *arg, int npending); 403238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 404238055Sadrian struct ath_buf *bf); 405238284Sadrian int (*recv_setup)(struct ath_softc *sc); 406238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 407238055Sadrian}; 408238055Sadrian 409238284Sadrian/* 410238284Sadrian * Represent the current state of the RX FIFO. 411238284Sadrian */ 412238284Sadrianstruct ath_rx_edma { 413238284Sadrian struct ath_buf **m_fifo; 414238284Sadrian int m_fifolen; 415238284Sadrian int m_fifo_head; 416238284Sadrian int m_fifo_tail; 417238284Sadrian int m_fifo_depth; 418238284Sadrian struct mbuf *m_rxpending; 419238284Sadrian}; 420238284Sadrian 421238855Sadrianstruct ath_tx_edma_fifo { 422238855Sadrian struct ath_buf **m_fifo; 423238855Sadrian int m_fifolen; 424238855Sadrian int m_fifo_head; 425238855Sadrian int m_fifo_tail; 426238855Sadrian int m_fifo_depth; 427238855Sadrian}; 428238855Sadrian 429238710Sadrianstruct ath_tx_methods { 430238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 431238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 432238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 433238931Sadrian 434238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 435238931Sadrian struct ath_txq *txq); 436238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 437238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 438239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 439239204Sadrian ATH_RESET_TYPE reset_type); 440238710Sadrian}; 441238710Sadrian 442116743Ssamstruct ath_softc { 443147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 444138570Ssam struct ath_stats sc_stats; /* interface statistics */ 445227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 446234090Sadrian struct ath_intr_stats sc_intr_stats; 447235491Sadrian uint64_t sc_debug; 448240899Sadrian uint64_t sc_ktrdebug; 449178354Ssam int sc_nvaps; /* # vaps */ 450178354Ssam int sc_nstavaps; /* # station vaps */ 451195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 452178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 453178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 454178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 455178354Ssam 456238055Sadrian struct ath_rx_methods sc_rx; 457238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 458238710Sadrian struct ath_tx_methods sc_tx; 459238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 460238710Sadrian 461238284Sadrian int sc_rx_statuslen; 462238284Sadrian int sc_tx_desclen; 463238284Sadrian int sc_tx_statuslen; 464238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 465238284Sadrian int sc_edma_bufsize; 466238055Sadrian 467227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 468138570Ssam void (*sc_node_free)(struct ieee80211_node *); 469116743Ssam device_t sc_dev; 470159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 471159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 472116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 473116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 474227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 475227328Sadrian char sc_pcu_mtx_name[32]; 476238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 477238433Sadrian char sc_rx_mtx_name[32]; 478155491Ssam struct taskqueue *sc_tq; /* private task queue */ 479116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 480138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 481155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 482138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 483178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 484178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 485238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 486178354Ssam sc_softled : 1,/* enable LED gpio status */ 487228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 488178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 489178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 490178354Ssam sc_diversity: 1,/* enable rx diversity */ 491178354Ssam sc_hasveol : 1,/* tx VEOL support */ 492178354Ssam sc_ledstate : 1,/* LED on/off state */ 493178354Ssam sc_blinking : 1,/* LED blink operation active */ 494178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 495178354Ssam sc_scanning : 1,/* scanning active */ 496155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 497178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 498165571Ssam sc_xchanmode: 1,/* extended channel mode */ 499170530Ssam sc_outdoor : 1,/* outdoor operation */ 500178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 501178354Ssam sc_hasbmask : 1,/* bssid mask support */ 502195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 503178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 504178354Ssam sc_beacons : 1,/* beacons running */ 505178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 506178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 507179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 508185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 509186904Ssam sc_tdma : 1,/* TDMA in use */ 510189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 511220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 512224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 513238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 514238284Sadrian sc_isedma : 1;/* supports EDMA */ 515178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 516178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 517116743Ssam /* rate tables */ 518188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 519116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 520116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 521155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 522138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 523170530Ssam u_int16_t sc_curaid; /* current association id */ 524187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 525170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 526116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 527140432Ssam struct { 528140432Ssam u_int8_t ieeerate; /* IEEE rate */ 529140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 530140761Ssam u_int8_t txflags; /* radiotap tx flags */ 531140432Ssam u_int16_t ledon; /* softled on time */ 532140432Ssam u_int16_t ledoff; /* softled off time */ 533140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 534138570Ssam u_int8_t sc_protrix; /* protection rate index */ 535170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 536155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 537170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 538170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 539138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 540227346Sadrian 541116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 542227651Sadrian 543227346Sadrian /* 544227346Sadrian * These are modified in the interrupt handler as well as 545227346Sadrian * the task queues and other contexts. Thus these must be 546227346Sadrian * protected by a mutex, or they could clash. 547227346Sadrian * 548227346Sadrian * For now, access to these is behind the ATH_LOCK, 549227346Sadrian * just to save time. 550227346Sadrian */ 551227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 552227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 553227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 554227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 555227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 556227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 557227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 558227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 559227346Sadrian 560138570Ssam u_int sc_keymax; /* size of key cache */ 561147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 562116743Ssam 563228891Sadrian /* 564228891Sadrian * Software based LED blinking 565228891Sadrian */ 566140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 567140432Ssam u_int sc_ledon; /* pin setting for LED on */ 568140432Ssam u_int sc_ledidle; /* idle polling interval */ 569140432Ssam int sc_ledevent; /* time of last LED event */ 570184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 571140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 572140432Ssam struct callout sc_ledtimer; /* led off timer */ 573138570Ssam 574228891Sadrian /* 575228891Sadrian * Hardware based LED blinking 576228891Sadrian */ 577228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 578228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 579228891Sadrian 580155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 581155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 582155515Ssam 583178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 584138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 585116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 586116743Ssam struct task sc_rxtask; /* rx int processing */ 587138570Ssam u_int8_t sc_defant; /* current default antenna */ 588138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 589155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 590192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 591192468Ssam struct ath_rx_radiotap_header sc_rx_th; 592192468Ssam int sc_rx_th_len; 593192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 594116743Ssam 595138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 596239282Sadrian uint16_t sc_txbuf_descid; 597138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 598237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 599237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 600237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 601238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 602138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 603155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 604138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 605138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 606138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 607138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 608116743Ssam struct task sc_txtask; /* tx int processing */ 609233673Sadrian struct task sc_txqtask; /* tx proc processing */ 610238709Sadrian 611238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 612238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 613238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 614238709Sadrian 615189605Ssam int sc_wd_timer; /* count down for wd timer */ 616189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 617192468Ssam struct ath_tx_radiotap_header sc_tx_th; 618192468Ssam int sc_tx_th_len; 619116743Ssam 620138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 621138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 622116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 623138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 624138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 625138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 626116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 627138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 628232163Sadrian struct task sc_resettask; /* interface reset task */ 629234369Sadrian struct task sc_fataltask; /* fatal task */ 630138570Ssam enum { 631138570Ssam OK, /* no change needed */ 632138570Ssam UPDATE, /* update pending */ 633138570Ssam COMMIT /* beacon sent, commit change */ 634138570Ssam } sc_updateslot; /* slot time update fsm */ 635178354Ssam int sc_slotupdate; /* slot to advance fsm */ 636178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 637178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 638116743Ssam 639116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 640185744Ssam int sc_lastlongcal; /* last long cal completed */ 641185744Ssam int sc_lastcalreset;/* last cal reset done */ 642217684Sadrian int sc_lastani; /* last ANI poll */ 643217684Sadrian int sc_lastshortcal; /* last short calibration */ 644217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 645155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 646186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 647186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 648186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 649186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 650186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 651186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 652186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 653186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 654217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 655218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 656218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 657233967Sadrian int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 658222585Sadrian 659232764Sadrian /* Queue limits */ 660232764Sadrian 661227328Sadrian /* 662232764Sadrian * To avoid queue starvation in congested conditions, 663232764Sadrian * these parameters tune the maximum number of frames 664232764Sadrian * queued to the data/mcastq before they're dropped. 665232764Sadrian * 666232764Sadrian * This is to prevent: 667232764Sadrian * + a single destination overwhelming everything, including 668232764Sadrian * management/multicast frames; 669232764Sadrian * + multicast frames overwhelming everything (when the 670232764Sadrian * air is sufficiently busy that cabq can't drain.) 671232764Sadrian * 672232764Sadrian * These implement: 673232764Sadrian * + data_minfree is the maximum number of free buffers 674232764Sadrian * overall to successfully allow a data frame. 675232764Sadrian * 676232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 677232764Sadrian */ 678232764Sadrian int sc_txq_data_minfree; 679232764Sadrian int sc_txq_mcastq_maxdepth; 680232764Sadrian 681232764Sadrian /* 682227328Sadrian * Aggregation twiddles 683227328Sadrian * 684227328Sadrian * hwq_limit: how busy to keep the hardware queue - don't schedule 685227328Sadrian * further packets to the hardware, regardless of the TID 686227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 687227328Sadrian * TID will be scheduled again 688227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 689227328Sadrian * stops being scheduled. 690227328Sadrian */ 691227328Sadrian int sc_hwq_limit; 692227328Sadrian int sc_tid_hwq_lo; 693227328Sadrian int sc_tid_hwq_hi; 694227328Sadrian 695222585Sadrian /* DFS related state */ 696222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 697222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 698222585Sadrian struct task sc_dfstask; /* DFS processing task */ 699227328Sadrian 700227328Sadrian /* TX AMPDU handling */ 701227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 702227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 703227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 704227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 705227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 706227328Sadrian struct ieee80211_tx_ampdu *); 707227328Sadrian void (*sc_addba_response_timeout) 708227328Sadrian (struct ieee80211_node *, 709227328Sadrian struct ieee80211_tx_ampdu *); 710227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 711227328Sadrian struct ieee80211_tx_ampdu *tap, 712227328Sadrian int status); 713116743Ssam}; 714116743Ssam 715121100Ssam#define ATH_LOCK_INIT(_sc) \ 716121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 717167252Ssam NULL, MTX_DEF | MTX_RECURSE) 718121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 719121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 720121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 721121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 722227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 723121100Ssam 724227328Sadrian/* 725227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 726227328Sadrian * Although currently the interrupt code is run in netisr context and 727227328Sadrian * doesn't require this, this may change in the future. 728227328Sadrian * Please keep this in mind when protecting certain code paths 729227328Sadrian * with the PCU lock. 730227328Sadrian * 731227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 732227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 733227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 734227328Sadrian * 735227328Sadrian * Although the current single-thread taskqueue mechanism protects the 736227328Sadrian * majority of these situations by simply serialising them, there are 737227328Sadrian * a few others which occur at the same time. These include the TX path 738227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 739227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 740227328Sadrian */ 741227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 742227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 743227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 744227328Sadrian "%s PCU lock", \ 745227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 746227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 747227328Sadrian NULL, MTX_DEF); \ 748227328Sadrian } while (0) 749227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 750227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 751227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 752227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 753227328Sadrian MA_OWNED) 754227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 755227651Sadrian MA_NOTOWNED) 756227328Sadrian 757238433Sadrian/* 758238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 759238433Sadrian * RX FIFO/list isn't modified by various execution paths. 760238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 761238433Sadrian * RX path can be executed via various reset/channel change paths. 762238433Sadrian */ 763238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 764238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 765238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 766238433Sadrian "%s RX lock", \ 767238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 768238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 769238433Sadrian NULL, MTX_DEF); \ 770238433Sadrian } while (0) 771238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 772238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 773238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 774238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 775238433Sadrian MA_OWNED) 776238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 777238433Sadrian MA_NOTOWNED) 778238433Sadrian 779138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 780138570Ssam 781155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 782155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 783155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 784167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 785155482Ssam} while (0) 786121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 787121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 788121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 789121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 790121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 791121100Ssam 792238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 793238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 794238709Sadrian "%s_buf", \ 795238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 796238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 797238709Sadrian MTX_DEF); \ 798238709Sadrian} while (0) 799238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 800238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 801238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 802238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 803238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 804238709Sadrian 805116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 806116743Ssamint ath_detach(struct ath_softc *); 807116743Ssamvoid ath_resume(struct ath_softc *); 808116743Ssamvoid ath_suspend(struct ath_softc *); 809116743Ssamvoid ath_shutdown(struct ath_softc *); 810116743Ssamvoid ath_intr(void *); 811116743Ssam 812116743Ssam/* 813116743Ssam * HAL definitions to comply with local coding convention. 814116743Ssam */ 815138570Ssam#define ath_hal_detach(_ah) \ 816138570Ssam ((*(_ah)->ah_detach)((_ah))) 817116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 818116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 819186904Ssam#define ath_hal_macversion(_ah) \ 820186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 821116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 822116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 823116743Ssam#define ath_hal_getmac(_ah, _mac) \ 824116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 825138570Ssam#define ath_hal_setmac(_ah, _mac) \ 826138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 827178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 828178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 829178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 830178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 831116743Ssam#define ath_hal_intrset(_ah, _mask) \ 832116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 833116743Ssam#define ath_hal_intrget(_ah) \ 834116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 835116743Ssam#define ath_hal_intrpend(_ah) \ 836116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 837116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 838116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 839116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 840116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 841155515Ssam#define ath_hal_setpower(_ah, _mode) \ 842155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 843138570Ssam#define ath_hal_keycachesize(_ah) \ 844138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 845116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 846116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 847138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 848138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 849116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 850116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 851116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 852116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 853116743Ssam#define ath_hal_getrxfilter(_ah) \ 854116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 855116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 856116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 857116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 858116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 859116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 860116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 861238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 862238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 863186904Ssam/* NB: common across all chips */ 864186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 865116743Ssam#define ath_hal_gettsf32(_ah) \ 866186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 867116743Ssam#define ath_hal_gettsf64(_ah) \ 868116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 869116743Ssam#define ath_hal_resettsf(_ah) \ 870116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 871116743Ssam#define ath_hal_rxena(_ah) \ 872116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 873116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 874116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 875116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 876116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 877138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 878138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 879238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 880238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 881116743Ssam#define ath_hal_txstart(_ah, _q) \ 882116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 883116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 884116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 885155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 886155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 887185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 888185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 889185744Ssam#define ath_hal_calreset(_ah, _chan) \ 890185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 891116743Ssam#define ath_hal_setledstate(_ah, _state) \ 892116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 893138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 894138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 895116743Ssam#define ath_hal_beaconreset(_ah) \ 896116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 897186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 898186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 899138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 900138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 901225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 902225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 903116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 904138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 905138570Ssam#define ath_hal_phydisable(_ah) \ 906138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 907138570Ssam#define ath_hal_setopmode(_ah) \ 908138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 909116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 910116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 911116743Ssam#define ath_hal_stoppcurecv(_ah) \ 912116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 913116743Ssam#define ath_hal_startpcurecv(_ah) \ 914116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 915116743Ssam#define ath_hal_stopdmarecv(_ah) \ 916116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 917138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 918138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 919138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 920155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 921170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 922116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 923116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 924116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 925116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 926116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 927116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 928138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 929138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 930138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 931138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 932186904Ssam/* NB: common across all chips */ 933186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 934186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 935186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 936116743Ssam#define ath_hal_getrfgain(_ah) \ 937116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 938138570Ssam#define ath_hal_getdefantenna(_ah) \ 939138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 940138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 941138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 942155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 943155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 944217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 945217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 946138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 947138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 948138570Ssam#define ath_hal_setslottime(_ah, _us) \ 949138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 950138570Ssam#define ath_hal_getslottime(_ah) \ 951138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 952138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 953138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 954138570Ssam#define ath_hal_getacktimeout(_ah) \ 955138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 956138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 957138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 958138570Ssam#define ath_hal_getctstimeout(_ah) \ 959138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 960138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 961138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 962138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 963138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 964138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 965138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 966138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 967155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 968155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 969184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 970138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 971138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 972178354Ssam#define ath_hal_gettkipmic(_ah) \ 973178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 974178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 975178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 976162410Ssam#define ath_hal_hastkipsplit(_ah) \ 977138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 978162410Ssam#define ath_hal_gettkipsplit(_ah) \ 979162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 980162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 981162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 982178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 983178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 984138570Ssam#define ath_hal_hwphycounters(_ah) \ 985138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 986138570Ssam#define ath_hal_hasdiversity(_ah) \ 987138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 988138570Ssam#define ath_hal_getdiversity(_ah) \ 989138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 990138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 991138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 992166954Ssam#define ath_hal_getantennaswitch(_ah) \ 993166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 994166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 995166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 996138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 997138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 998138570Ssam#define ath_hal_setdiag(_ah, _v) \ 999138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1000138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 1001138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1002138570Ssam#define ath_hal_hasveol(_ah) \ 1003138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1004138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 1005138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1006138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 1007138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1008138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1009138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1010138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1011138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1012138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 1013138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1014138570Ssam#define ath_hal_settpscale(_ah, _v) \ 1015138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1016138570Ssam#define ath_hal_hastpc(_ah) \ 1017138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1018138570Ssam#define ath_hal_gettpc(_ah) \ 1019138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1020138570Ssam#define ath_hal_settpc(_ah, _v) \ 1021138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1022138570Ssam#define ath_hal_hasbursting(_ah) \ 1023138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1024203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1025203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1026147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1027147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1028147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1029147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1030170530Ssam#define ath_hal_hasfastframes(_ah) \ 1031170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1032178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1033178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1034195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1035195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1036178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1037178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1038178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1039178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1040178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1041178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1042155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1043155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1044155515Ssam#define ath_hal_getrfkill(_ah) \ 1045155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1046155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1047155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1048155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1049155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1050155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1051155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1052155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1053155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1054155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1055155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1056155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1057155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1058155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1059155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1060184354Ssam#define ath_hal_hasintmit(_ah) \ 1061230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1062230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1063184354Ssam#define ath_hal_getintmit(_ah) \ 1064230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1065230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1066184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1067230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1068230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1069238280Sadrian 1070238280Sadrian/* EDMA definitions */ 1071237953Sadrian#define ath_hal_hasedma(_ah) \ 1072237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1073237953Sadrian 0, NULL) == HAL_OK) 1074238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1075238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1076238280Sadrian == HAL_OK) 1077238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1078238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1079238280Sadrian == HAL_OK) 1080238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1081238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1082238280Sadrian == HAL_OK) 1083238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1084238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1085238280Sadrian == HAL_OK) 1086238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1087238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1088238280Sadrian == HAL_OK) 1089238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1090238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1091238280Sadrian == HAL_OK) 1092238280Sadrian 1093154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1094154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1095238280Sadrian 1096238280Sadrian/* 802.11n HAL methods */ 1097218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1098218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1099218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1100218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1101231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1102231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1103231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1104231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1105218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1106230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1107230493Sadrian 0, NULL) == HAL_OK) 1108220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1109230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1110230493Sadrian 0, NULL) == HAL_OK) 1111220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1112220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1113225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1114230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1115230493Sadrian 0, NULL) == HAL_OK) 1116116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1117116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1118165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1119165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1120116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1121116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1122116743Ssam _rtsrate, _rtsdura) \ 1123116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1124116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1125155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1126138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1127116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1128138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1129116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1130239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1131239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1132239051Sadrian (_first), (_last), (_ds0))) 1133165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1134165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1135155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1136155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1137217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1138217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1139238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1140238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1141238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1142238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1143238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1144238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1145238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1146238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1147238731Sadrian (_size))) 1148116743Ssam 1149218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1150218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1151218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1152218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1153239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1154239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1155239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1156239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1157233895Sadrian (_first), (_last), (_lastaggr))) 1158218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1159218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1160227328Sadrian 1161218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1162218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1163218067Sadrian (_series), (_ns), (_flags))) 1164227328Sadrian 1165227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1166238838Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1167218066Sadrian#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1168227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1169227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1170227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1171227328Sadrian 1172218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1173218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1174227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1175227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1176218066Sadrian 1177230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1178230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1179230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1180230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1181230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1182230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1183230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1184230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1185230493Sadrian 1186222585Sadrian/* 1187235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1188235957Sadrian */ 1189235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1190235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1191235957Sadrian#define ath_hal_disablepcie(_ah) \ 1192235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1193235957Sadrian 1194235957Sadrian/* 1195222585Sadrian * This is badly-named; you need to set the correct parameters 1196222585Sadrian * to begin to receive useful radar events; and even then 1197222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1198222585Sadrian * more information. 1199222585Sadrian */ 1200222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1201222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1202222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1203222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1204239656Sadrian#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1205239656Sadrian ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1206222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1207230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1208230493Sadrian (_buf), (_event))) 1209224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1210224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1211230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1212155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1213234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1214234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1215230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1216230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1217155515Ssam 1218116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1219