if_athvar.h revision 240585
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 240585 2012-09-17 01:21:55Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52#define ATH_MGMT_TXBUF 32 53 54/* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57#ifdef ATH_ENABLE_11N 58#define ATH_TXBUF 512 59#define ATH_RXBUF 512 60#endif 61 62#ifndef ATH_RXBUF 63#define ATH_RXBUF 40 /* number of RX buffers */ 64#endif 65#ifndef ATH_TXBUF 66#define ATH_TXBUF 200 /* number of TX buffers */ 67#endif 68#define ATH_BCBUF 4 /* number of beacon buffers */ 69 70#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79/* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87#define ATH_KEYMAX 128 /* max key cache size we handle */ 88#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90struct taskqueue; 91struct kthread; 92struct ath_buf; 93 94#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96/* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 struct { 111 TAILQ_HEAD(,ath_buf) axq_q; /* filtered queue */ 112 u_int axq_depth; /* SW queue depth */ 113 char axq_name[48]; /* lock name */ 114 } filtq; 115 116 /* 117 * Entry on the ath_txq; when there's traffic 118 * to send 119 */ 120 TAILQ_ENTRY(ath_tid) axq_qelem; 121 int sched; 122 int paused; /* >0 if the TID has been paused */ 123 124 /* 125 * These are flags - perhaps later collapse 126 * down to a single uint32_t ? 127 */ 128 int addba_tx_pending; /* TX ADDBA pending */ 129 int bar_wait; /* waiting for BAR */ 130 int bar_tx; /* BAR TXed */ 131 int isfiltered; /* is this node currently filtered */ 132 int clrdmask; /* has clrdmask been set */ 133 134 /* 135 * Is the TID being cleaned up after a transition 136 * from aggregation to non-aggregation? 137 * When this is set to 1, this TID will be paused 138 * and no further traffic will be queued until all 139 * the hardware packets pending for this TID have been 140 * TXed/completed; at which point (non-aggregation) 141 * traffic will resume being TXed. 142 */ 143 int cleanup_inprogress; 144 /* 145 * How many hardware-queued packets are 146 * waiting to be cleaned up. 147 * This is only valid if cleanup_inprogress is 1. 148 */ 149 int incomp; 150 151 /* 152 * The following implements a ring representing 153 * the frames in the current BAW. 154 * To avoid copying the array content each time 155 * the BAW is moved, the baw_head/baw_tail point 156 * to the current BAW begin/end; when the BAW is 157 * shifted the head/tail of the array are also 158 * appropriately shifted. 159 */ 160 /* active tx buffers, beginning at current BAW */ 161 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 162 /* where the baw head is in the array */ 163 int baw_head; 164 /* where the BAW tail is in the array */ 165 int baw_tail; 166}; 167 168/* driver-specific node state */ 169struct ath_node { 170 struct ieee80211_node an_node; /* base class */ 171 u_int8_t an_mgmtrix; /* min h/w rate index */ 172 u_int8_t an_mcastrix; /* mcast h/w rate index */ 173 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 174 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 175 char an_name[32]; /* eg "wlan0_a1" */ 176 struct mtx an_mtx; /* protecting the ath_node state */ 177 /* variable-length rate control state follows */ 178}; 179#define ATH_NODE(ni) ((struct ath_node *)(ni)) 180#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 181 182#define ATH_RSSI_LPF_LEN 10 183#define ATH_RSSI_DUMMY_MARKER 0x127 184#define ATH_EP_MUL(x, mul) ((x) * (mul)) 185#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 186#define ATH_LPF_RSSI(x, y, len) \ 187 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 188#define ATH_RSSI_LPF(x, y) do { \ 189 if ((y) >= -20) \ 190 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 191} while (0) 192#define ATH_EP_RND(x,mul) \ 193 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 194#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 195 196typedef enum { 197 ATH_BUFTYPE_NORMAL = 0, 198 ATH_BUFTYPE_MGMT = 1, 199} ath_buf_type_t; 200 201struct ath_buf { 202 TAILQ_ENTRY(ath_buf) bf_list; 203 struct ath_buf * bf_next; /* next buffer in the aggregate */ 204 int bf_nseg; 205 HAL_STATUS bf_rxstatus; 206 uint16_t bf_flags; /* status flags (below) */ 207 uint16_t bf_descid; /* 16 bit descriptor ID */ 208 struct ath_desc *bf_desc; /* virtual addr of desc */ 209 struct ath_desc_status bf_status; /* tx/rx status */ 210 bus_addr_t bf_daddr; /* physical addr of desc */ 211 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 212 struct mbuf *bf_m; /* mbuf for buf */ 213 struct ieee80211_node *bf_node; /* pointer to the node */ 214 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 215 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 216 bus_size_t bf_mapsize; 217#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 218 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 219 220 /* Completion function to call on TX complete (fail or not) */ 221 /* 222 * "fail" here is set to 1 if the queue entries were removed 223 * through a call to ath_tx_draintxq(). 224 */ 225 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 226 227 /* This state is kept to support software retries and aggregation */ 228 struct { 229 uint16_t bfs_seqno; /* sequence number of this packet */ 230 uint16_t bfs_ndelim; /* number of delims for padding */ 231 232 uint8_t bfs_retries; /* retry count */ 233 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 234 uint8_t bfs_nframes; /* number of frames in aggregate */ 235 uint8_t bfs_pri; /* packet AC priority */ 236 237 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 238 239 u_int32_t bfs_aggr:1, /* part of aggregate? */ 240 bfs_aggrburst:1, /* part of aggregate burst? */ 241 bfs_isretried:1, /* retried frame? */ 242 bfs_dobaw:1, /* actually check against BAW? */ 243 bfs_addedbaw:1, /* has been added to the BAW */ 244 bfs_shpream:1, /* use short preamble */ 245 bfs_istxfrag:1, /* is fragmented */ 246 bfs_ismrr:1, /* do multi-rate TX retry */ 247 bfs_doprot:1, /* do RTS/CTS based protection */ 248 bfs_doratelookup:1; /* do rate lookup before each TX */ 249 250 /* 251 * These fields are passed into the 252 * descriptor setup functions. 253 */ 254 255 /* Make this an 8 bit value? */ 256 HAL_PKT_TYPE bfs_atype; /* packet type */ 257 258 uint32_t bfs_pktlen; /* length of this packet */ 259 260 uint16_t bfs_hdrlen; /* length of this packet header */ 261 uint16_t bfs_al; /* length of aggregate */ 262 263 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 264 uint8_t bfs_txrate0; /* first TX rate */ 265 uint8_t bfs_try0; /* first try count */ 266 267 uint16_t bfs_txpower; /* tx power */ 268 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 269 uint8_t bfs_ctsrate; /* CTS rate */ 270 271 /* 16 bit? */ 272 int32_t bfs_keyix; /* crypto key index */ 273 int32_t bfs_txantenna; /* TX antenna config */ 274 275 /* Make this an 8 bit value? */ 276 enum ieee80211_protmode bfs_protmode; 277 278 /* 16 bit? */ 279 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 280 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 281 } bf_state; 282}; 283typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 284 285#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 286#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 287 288/* 289 * DMA state for tx/rx descriptors. 290 */ 291struct ath_descdma { 292 const char* dd_name; 293 struct ath_desc *dd_desc; /* descriptors */ 294 int dd_descsize; /* size of single descriptor */ 295 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 296 bus_size_t dd_desc_len; /* size of dd_desc */ 297 bus_dma_segment_t dd_dseg; 298 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 299 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 300 struct ath_buf *dd_bufptr; /* associated buffers */ 301}; 302 303/* 304 * Data transmit queue state. One of these exists for each 305 * hardware transmit queue. Packets sent to us from above 306 * are assigned to queues based on their priority. Not all 307 * devices support a complete set of hardware transmit queues. 308 * For those devices the array sc_ac2q will map multiple 309 * priorities to fewer hardware queues (typically all to one 310 * hardware queue). 311 */ 312struct ath_txq { 313 struct ath_softc *axq_softc; /* Needed for scheduling */ 314 u_int axq_qnum; /* hardware q number */ 315#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 316 u_int axq_ac; /* WME AC */ 317 u_int axq_flags; 318#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 319 u_int axq_depth; /* queue depth (stat only) */ 320 u_int axq_aggr_depth; /* how many aggregates are queued */ 321 u_int axq_fifo_depth; /* depth of FIFO frames */ 322 u_int axq_intrcnt; /* interrupt count */ 323 u_int32_t *axq_link; /* link ptr in last TX desc */ 324 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 325 struct mtx axq_lock; /* lock on q and link */ 326 char axq_name[12]; /* e.g. "ath0_txq4" */ 327 328 /* Per-TID traffic queue for software -> hardware TX */ 329 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 330}; 331 332#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 333#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 334#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 335 336#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 337 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 338 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 339 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 340} while (0) 341#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 342#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 343#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 344#define ATH_TXQ_LOCK_ASSERT(_tq) \ 345 mtx_assert(&(_tq)->axq_lock, MA_OWNED) 346#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 347 mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 348#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 349 350#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 351 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 352#define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 353 ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 354 355#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 356 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 357 (_tq)->axq_depth++; \ 358} while (0) 359#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 360 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 361 (_tq)->axq_depth++; \ 362} while (0) 363#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 364 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 365 (_tq)->axq_depth--; \ 366} while (0) 367#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 368#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 369 370struct ath_vap { 371 struct ieee80211vap av_vap; /* base class */ 372 int av_bslot; /* beacon slot index */ 373 struct ath_buf *av_bcbuf; /* beacon buffer */ 374 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 375 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 376 377 void (*av_recv_mgmt)(struct ieee80211_node *, 378 struct mbuf *, int, int, int); 379 int (*av_newstate)(struct ieee80211vap *, 380 enum ieee80211_state, int); 381 void (*av_bmiss)(struct ieee80211vap *); 382}; 383#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 384 385struct taskqueue; 386struct ath_tx99; 387 388/* 389 * Whether to reset the TX/RX queue with or without 390 * a queue flush. 391 */ 392typedef enum { 393 ATH_RESET_DEFAULT = 0, 394 ATH_RESET_NOLOSS = 1, 395 ATH_RESET_FULL = 2, 396} ATH_RESET_TYPE; 397 398struct ath_rx_methods { 399 void (*recv_stop)(struct ath_softc *sc, int dodelay); 400 int (*recv_start)(struct ath_softc *sc); 401 void (*recv_flush)(struct ath_softc *sc); 402 void (*recv_tasklet)(void *arg, int npending); 403 int (*recv_rxbuf_init)(struct ath_softc *sc, 404 struct ath_buf *bf); 405 int (*recv_setup)(struct ath_softc *sc); 406 int (*recv_teardown)(struct ath_softc *sc); 407}; 408 409/* 410 * Represent the current state of the RX FIFO. 411 */ 412struct ath_rx_edma { 413 struct ath_buf **m_fifo; 414 int m_fifolen; 415 int m_fifo_head; 416 int m_fifo_tail; 417 int m_fifo_depth; 418 struct mbuf *m_rxpending; 419}; 420 421struct ath_tx_edma_fifo { 422 struct ath_buf **m_fifo; 423 int m_fifolen; 424 int m_fifo_head; 425 int m_fifo_tail; 426 int m_fifo_depth; 427}; 428 429struct ath_tx_methods { 430 int (*xmit_setup)(struct ath_softc *sc); 431 int (*xmit_teardown)(struct ath_softc *sc); 432 void (*xmit_attach_comp_func)(struct ath_softc *sc); 433 434 void (*xmit_dma_restart)(struct ath_softc *sc, 435 struct ath_txq *txq); 436 void (*xmit_handoff)(struct ath_softc *sc, 437 struct ath_txq *txq, struct ath_buf *bf); 438 void (*xmit_drain)(struct ath_softc *sc, 439 ATH_RESET_TYPE reset_type); 440}; 441 442struct ath_softc { 443 struct ifnet *sc_ifp; /* interface common */ 444 struct ath_stats sc_stats; /* interface statistics */ 445 struct ath_tx_aggr_stats sc_aggr_stats; 446 struct ath_intr_stats sc_intr_stats; 447 uint64_t sc_debug; 448 int sc_nvaps; /* # vaps */ 449 int sc_nstavaps; /* # station vaps */ 450 int sc_nmeshvaps; /* # mbss vaps */ 451 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 452 u_int8_t sc_nbssid0; /* # vap's using base mac */ 453 uint32_t sc_bssidmask; /* bssid mask */ 454 455 struct ath_rx_methods sc_rx; 456 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 457 struct ath_tx_methods sc_tx; 458 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 459 460 int sc_rx_statuslen; 461 int sc_tx_desclen; 462 int sc_tx_statuslen; 463 int sc_tx_nmaps; /* Number of TX maps */ 464 int sc_edma_bufsize; 465 466 void (*sc_node_cleanup)(struct ieee80211_node *); 467 void (*sc_node_free)(struct ieee80211_node *); 468 device_t sc_dev; 469 HAL_BUS_TAG sc_st; /* bus space tag */ 470 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 471 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 472 struct mtx sc_mtx; /* master lock (recursive) */ 473 struct mtx sc_pcu_mtx; /* PCU access mutex */ 474 char sc_pcu_mtx_name[32]; 475 struct mtx sc_rx_mtx; /* RX access mutex */ 476 char sc_rx_mtx_name[32]; 477 struct taskqueue *sc_tq; /* private task queue */ 478 struct ath_hal *sc_ah; /* Atheros HAL */ 479 struct ath_ratectrl *sc_rc; /* tx rate control support */ 480 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 481 void (*sc_setdefantenna)(struct ath_softc *, u_int); 482 unsigned int sc_invalid : 1,/* disable hardware accesses */ 483 sc_mrretry : 1,/* multi-rate retry support */ 484 sc_mrrprot : 1,/* MRR + protection support */ 485 sc_softled : 1,/* enable LED gpio status */ 486 sc_hardled : 1,/* enable MAC LED status */ 487 sc_splitmic : 1,/* split TKIP MIC keys */ 488 sc_needmib : 1,/* enable MIB stats intr */ 489 sc_diversity: 1,/* enable rx diversity */ 490 sc_hasveol : 1,/* tx VEOL support */ 491 sc_ledstate : 1,/* LED on/off state */ 492 sc_blinking : 1,/* LED blink operation active */ 493 sc_mcastkey : 1,/* mcast key cache search */ 494 sc_scanning : 1,/* scanning active */ 495 sc_syncbeacon:1,/* sync/resync beacon timers */ 496 sc_hasclrkey: 1,/* CLR key supported */ 497 sc_xchanmode: 1,/* extended channel mode */ 498 sc_outdoor : 1,/* outdoor operation */ 499 sc_dturbo : 1,/* dynamic turbo in use */ 500 sc_hasbmask : 1,/* bssid mask support */ 501 sc_hasbmatch: 1,/* bssid match disable support*/ 502 sc_hastsfadd: 1,/* tsf adjust support */ 503 sc_beacons : 1,/* beacons running */ 504 sc_swbmiss : 1,/* sta mode using sw bmiss */ 505 sc_stagbeacons:1,/* use staggered beacons */ 506 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 507 sc_resume_up: 1,/* on resume, start all vaps */ 508 sc_tdma : 1,/* TDMA in use */ 509 sc_setcca : 1,/* set/clr CCA with TDMA */ 510 sc_resetcal : 1,/* reset cal state next trip */ 511 sc_rxslink : 1,/* do self-linked final descriptor */ 512 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 513 sc_isedma : 1;/* supports EDMA */ 514 uint32_t sc_eerd; /* regdomain from EEPROM */ 515 uint32_t sc_eecc; /* country code from EEPROM */ 516 /* rate tables */ 517 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 518 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 519 enum ieee80211_phymode sc_curmode; /* current phy mode */ 520 HAL_OPMODE sc_opmode; /* current operating mode */ 521 u_int16_t sc_curtxpow; /* current tx power limit */ 522 u_int16_t sc_curaid; /* current association id */ 523 struct ieee80211_channel *sc_curchan; /* current installed channel */ 524 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 525 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 526 struct { 527 u_int8_t ieeerate; /* IEEE rate */ 528 u_int8_t rxflags; /* radiotap rx flags */ 529 u_int8_t txflags; /* radiotap tx flags */ 530 u_int16_t ledon; /* softled on time */ 531 u_int16_t ledoff; /* softled off time */ 532 } sc_hwmap[32]; /* h/w rate ix mappings */ 533 u_int8_t sc_protrix; /* protection rate index */ 534 u_int8_t sc_lastdatarix; /* last data frame rate index */ 535 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 536 u_int sc_fftxqmin; /* min frames before staging */ 537 u_int sc_fftxqmax; /* max frames before drop */ 538 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 539 540 HAL_INT sc_imask; /* interrupt mask copy */ 541 542 /* 543 * These are modified in the interrupt handler as well as 544 * the task queues and other contexts. Thus these must be 545 * protected by a mutex, or they could clash. 546 * 547 * For now, access to these is behind the ATH_LOCK, 548 * just to save time. 549 */ 550 uint32_t sc_txq_active; /* bitmap of active TXQs */ 551 uint32_t sc_kickpcu; /* whether to kick the PCU */ 552 uint32_t sc_rxproc_cnt; /* In RX processing */ 553 uint32_t sc_txproc_cnt; /* In TX processing */ 554 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 555 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 556 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 557 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 558 559 u_int sc_keymax; /* size of key cache */ 560 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 561 562 /* 563 * Software based LED blinking 564 */ 565 u_int sc_ledpin; /* GPIO pin for driving LED */ 566 u_int sc_ledon; /* pin setting for LED on */ 567 u_int sc_ledidle; /* idle polling interval */ 568 int sc_ledevent; /* time of last LED event */ 569 u_int8_t sc_txrix; /* current tx rate for LED */ 570 u_int16_t sc_ledoff; /* off time for current blink */ 571 struct callout sc_ledtimer; /* led off timer */ 572 573 /* 574 * Hardware based LED blinking 575 */ 576 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 577 int sc_led_net_pin; /* MAC network LED GPIO pin */ 578 579 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 580 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 581 582 struct ath_descdma sc_rxdma; /* RX descriptors */ 583 ath_bufhead sc_rxbuf; /* receive buffer */ 584 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 585 struct task sc_rxtask; /* rx int processing */ 586 u_int8_t sc_defant; /* current default antenna */ 587 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 588 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 589 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 590 struct ath_rx_radiotap_header sc_rx_th; 591 int sc_rx_th_len; 592 u_int sc_monpass; /* frames to pass in mon.mode */ 593 594 struct ath_descdma sc_txdma; /* TX descriptors */ 595 uint16_t sc_txbuf_descid; 596 ath_bufhead sc_txbuf; /* transmit buffer */ 597 int sc_txbuf_cnt; /* how many buffers avail */ 598 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 599 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 600 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 601 struct mtx sc_txbuflock; /* txbuf lock */ 602 char sc_txname[12]; /* e.g. "ath0_buf" */ 603 u_int sc_txqsetup; /* h/w queues setup */ 604 u_int sc_txintrperiod;/* tx interrupt batching */ 605 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 606 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 607 struct task sc_txtask; /* tx int processing */ 608 struct task sc_txqtask; /* tx proc processing */ 609 610 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 611 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 612 char sc_txcompname[12]; /* eg ath0_txcomp */ 613 614 int sc_wd_timer; /* count down for wd timer */ 615 struct callout sc_wd_ch; /* tx watchdog timer */ 616 struct ath_tx_radiotap_header sc_tx_th; 617 int sc_tx_th_len; 618 619 struct ath_descdma sc_bdma; /* beacon descriptors */ 620 ath_bufhead sc_bbuf; /* beacon buffers */ 621 u_int sc_bhalq; /* HAL q for outgoing beacons */ 622 u_int sc_bmisscount; /* missed beacon transmits */ 623 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 624 struct ath_txq *sc_cabq; /* tx q for cab frames */ 625 struct task sc_bmisstask; /* bmiss int processing */ 626 struct task sc_bstucktask; /* stuck beacon processing */ 627 struct task sc_resettask; /* interface reset task */ 628 struct task sc_fataltask; /* fatal task */ 629 enum { 630 OK, /* no change needed */ 631 UPDATE, /* update pending */ 632 COMMIT /* beacon sent, commit change */ 633 } sc_updateslot; /* slot time update fsm */ 634 int sc_slotupdate; /* slot to advance fsm */ 635 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 636 int sc_nbcnvaps; /* # vaps with beacons */ 637 638 struct callout sc_cal_ch; /* callout handle for cals */ 639 int sc_lastlongcal; /* last long cal completed */ 640 int sc_lastcalreset;/* last cal reset done */ 641 int sc_lastani; /* last ANI poll */ 642 int sc_lastshortcal; /* last short calibration */ 643 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 644 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 645 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 646 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 647 u_int sc_tdmaswba; /* TDMA SWBA counter */ 648 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 649 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 650 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 651 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 652 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 653 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 654 int sc_txchainmask; /* currently configured TX chainmask */ 655 int sc_rxchainmask; /* currently configured RX chainmask */ 656 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 657 658 /* Queue limits */ 659 660 /* 661 * To avoid queue starvation in congested conditions, 662 * these parameters tune the maximum number of frames 663 * queued to the data/mcastq before they're dropped. 664 * 665 * This is to prevent: 666 * + a single destination overwhelming everything, including 667 * management/multicast frames; 668 * + multicast frames overwhelming everything (when the 669 * air is sufficiently busy that cabq can't drain.) 670 * 671 * These implement: 672 * + data_minfree is the maximum number of free buffers 673 * overall to successfully allow a data frame. 674 * 675 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 676 */ 677 int sc_txq_data_minfree; 678 int sc_txq_mcastq_maxdepth; 679 680 /* 681 * Aggregation twiddles 682 * 683 * hwq_limit: how busy to keep the hardware queue - don't schedule 684 * further packets to the hardware, regardless of the TID 685 * tid_hwq_lo: how low the per-TID hwq count has to be before the 686 * TID will be scheduled again 687 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 688 * stops being scheduled. 689 */ 690 int sc_hwq_limit; 691 int sc_tid_hwq_lo; 692 int sc_tid_hwq_hi; 693 694 /* DFS related state */ 695 void *sc_dfs; /* Used by an optional DFS module */ 696 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 697 struct task sc_dfstask; /* DFS processing task */ 698 699 /* TX AMPDU handling */ 700 int (*sc_addba_request)(struct ieee80211_node *, 701 struct ieee80211_tx_ampdu *, int, int, int); 702 int (*sc_addba_response)(struct ieee80211_node *, 703 struct ieee80211_tx_ampdu *, int, int, int); 704 void (*sc_addba_stop)(struct ieee80211_node *, 705 struct ieee80211_tx_ampdu *); 706 void (*sc_addba_response_timeout) 707 (struct ieee80211_node *, 708 struct ieee80211_tx_ampdu *); 709 void (*sc_bar_response)(struct ieee80211_node *ni, 710 struct ieee80211_tx_ampdu *tap, 711 int status); 712}; 713 714#define ATH_LOCK_INIT(_sc) \ 715 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 716 NULL, MTX_DEF | MTX_RECURSE) 717#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 718#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 719#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 720#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 721#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 722 723/* 724 * The PCU lock is non-recursive and should be treated as a spinlock. 725 * Although currently the interrupt code is run in netisr context and 726 * doesn't require this, this may change in the future. 727 * Please keep this in mind when protecting certain code paths 728 * with the PCU lock. 729 * 730 * The PCU lock is used to serialise access to the PCU so things such 731 * as TX, RX, state change (eg channel change), channel reset and updates 732 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 733 * 734 * Although the current single-thread taskqueue mechanism protects the 735 * majority of these situations by simply serialising them, there are 736 * a few others which occur at the same time. These include the TX path 737 * (which only acquires ATH_LOCK when recycling buffers to the free list), 738 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 739 */ 740#define ATH_PCU_LOCK_INIT(_sc) do {\ 741 snprintf((_sc)->sc_pcu_mtx_name, \ 742 sizeof((_sc)->sc_pcu_mtx_name), \ 743 "%s PCU lock", \ 744 device_get_nameunit((_sc)->sc_dev)); \ 745 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 746 NULL, MTX_DEF); \ 747 } while (0) 748#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 749#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 750#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 751#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 752 MA_OWNED) 753#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 754 MA_NOTOWNED) 755 756/* 757 * The RX lock is primarily a(nother) workaround to ensure that the 758 * RX FIFO/list isn't modified by various execution paths. 759 * Even though RX occurs in a single context (the ath taskqueue), the 760 * RX path can be executed via various reset/channel change paths. 761 */ 762#define ATH_RX_LOCK_INIT(_sc) do {\ 763 snprintf((_sc)->sc_rx_mtx_name, \ 764 sizeof((_sc)->sc_rx_mtx_name), \ 765 "%s RX lock", \ 766 device_get_nameunit((_sc)->sc_dev)); \ 767 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 768 NULL, MTX_DEF); \ 769 } while (0) 770#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 771#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 772#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 773#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 774 MA_OWNED) 775#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 776 MA_NOTOWNED) 777 778#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 779 780#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 781 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 782 device_get_nameunit((_sc)->sc_dev)); \ 783 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 784} while (0) 785#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 786#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 787#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 788#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 789 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 790 791#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 792 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 793 "%s_buf", \ 794 device_get_nameunit((_sc)->sc_dev)); \ 795 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 796 MTX_DEF); \ 797} while (0) 798#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 799#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 800#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 801#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 802 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 803 804int ath_attach(u_int16_t, struct ath_softc *); 805int ath_detach(struct ath_softc *); 806void ath_resume(struct ath_softc *); 807void ath_suspend(struct ath_softc *); 808void ath_shutdown(struct ath_softc *); 809void ath_intr(void *); 810 811/* 812 * HAL definitions to comply with local coding convention. 813 */ 814#define ath_hal_detach(_ah) \ 815 ((*(_ah)->ah_detach)((_ah))) 816#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 817 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 818#define ath_hal_macversion(_ah) \ 819 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 820#define ath_hal_getratetable(_ah, _mode) \ 821 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 822#define ath_hal_getmac(_ah, _mac) \ 823 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 824#define ath_hal_setmac(_ah, _mac) \ 825 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 826#define ath_hal_getbssidmask(_ah, _mask) \ 827 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 828#define ath_hal_setbssidmask(_ah, _mask) \ 829 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 830#define ath_hal_intrset(_ah, _mask) \ 831 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 832#define ath_hal_intrget(_ah) \ 833 ((*(_ah)->ah_getInterrupts)((_ah))) 834#define ath_hal_intrpend(_ah) \ 835 ((*(_ah)->ah_isInterruptPending)((_ah))) 836#define ath_hal_getisr(_ah, _pmask) \ 837 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 838#define ath_hal_updatetxtriglevel(_ah, _inc) \ 839 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 840#define ath_hal_setpower(_ah, _mode) \ 841 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 842#define ath_hal_keycachesize(_ah) \ 843 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 844#define ath_hal_keyreset(_ah, _ix) \ 845 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 846#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 847 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 848#define ath_hal_keyisvalid(_ah, _ix) \ 849 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 850#define ath_hal_keysetmac(_ah, _ix, _mac) \ 851 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 852#define ath_hal_getrxfilter(_ah) \ 853 ((*(_ah)->ah_getRxFilter)((_ah))) 854#define ath_hal_setrxfilter(_ah, _filter) \ 855 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 856#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 857 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 858#define ath_hal_waitforbeacon(_ah, _bf) \ 859 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 860#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 861 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 862/* NB: common across all chips */ 863#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 864#define ath_hal_gettsf32(_ah) \ 865 OS_REG_READ(_ah, AR_TSF_L32) 866#define ath_hal_gettsf64(_ah) \ 867 ((*(_ah)->ah_getTsf64)((_ah))) 868#define ath_hal_resettsf(_ah) \ 869 ((*(_ah)->ah_resetTsf)((_ah))) 870#define ath_hal_rxena(_ah) \ 871 ((*(_ah)->ah_enableReceive)((_ah))) 872#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 873 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 874#define ath_hal_gettxbuf(_ah, _q) \ 875 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 876#define ath_hal_numtxpending(_ah, _q) \ 877 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 878#define ath_hal_getrxbuf(_ah, _rxq) \ 879 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 880#define ath_hal_txstart(_ah, _q) \ 881 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 882#define ath_hal_setchannel(_ah, _chan) \ 883 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 884#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 885 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 886#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 887 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 888#define ath_hal_calreset(_ah, _chan) \ 889 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 890#define ath_hal_setledstate(_ah, _state) \ 891 ((*(_ah)->ah_setLedState)((_ah), (_state))) 892#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 893 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 894#define ath_hal_beaconreset(_ah) \ 895 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 896#define ath_hal_beaconsettimers(_ah, _bt) \ 897 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 898#define ath_hal_beacontimers(_ah, _bs) \ 899 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 900#define ath_hal_getnexttbtt(_ah) \ 901 ((*(_ah)->ah_getNextTBTT)((_ah))) 902#define ath_hal_setassocid(_ah, _bss, _associd) \ 903 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 904#define ath_hal_phydisable(_ah) \ 905 ((*(_ah)->ah_phyDisable)((_ah))) 906#define ath_hal_setopmode(_ah) \ 907 ((*(_ah)->ah_setPCUConfig)((_ah))) 908#define ath_hal_stoptxdma(_ah, _qnum) \ 909 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 910#define ath_hal_stoppcurecv(_ah) \ 911 ((*(_ah)->ah_stopPcuReceive)((_ah))) 912#define ath_hal_startpcurecv(_ah) \ 913 ((*(_ah)->ah_startPcuReceive)((_ah))) 914#define ath_hal_stopdmarecv(_ah) \ 915 ((*(_ah)->ah_stopDmaReceive)((_ah))) 916#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 917 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 918 (_indata), (_insize), (_outdata), (_outsize))) 919#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 920 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 921#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 922 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 923#define ath_hal_resettxqueue(_ah, _q) \ 924 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 925#define ath_hal_releasetxqueue(_ah, _q) \ 926 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 927#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 928 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 929#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 930 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 931/* NB: common across all chips */ 932#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 933#define ath_hal_txqenabled(_ah, _qnum) \ 934 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 935#define ath_hal_getrfgain(_ah) \ 936 ((*(_ah)->ah_getRfGain)((_ah))) 937#define ath_hal_getdefantenna(_ah) \ 938 ((*(_ah)->ah_getDefAntenna)((_ah))) 939#define ath_hal_setdefantenna(_ah, _ant) \ 940 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 941#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 942 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 943#define ath_hal_ani_poll(_ah, _chan) \ 944 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 945#define ath_hal_mibevent(_ah, _stats) \ 946 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 947#define ath_hal_setslottime(_ah, _us) \ 948 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 949#define ath_hal_getslottime(_ah) \ 950 ((*(_ah)->ah_getSlotTime)((_ah))) 951#define ath_hal_setacktimeout(_ah, _us) \ 952 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 953#define ath_hal_getacktimeout(_ah) \ 954 ((*(_ah)->ah_getAckTimeout)((_ah))) 955#define ath_hal_setctstimeout(_ah, _us) \ 956 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 957#define ath_hal_getctstimeout(_ah) \ 958 ((*(_ah)->ah_getCTSTimeout)((_ah))) 959#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 960 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 961#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 962 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 963#define ath_hal_ciphersupported(_ah, _cipher) \ 964 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 965#define ath_hal_getregdomain(_ah, _prd) \ 966 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 967#define ath_hal_setregdomain(_ah, _rd) \ 968 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 969#define ath_hal_getcountrycode(_ah, _pcc) \ 970 (*(_pcc) = (_ah)->ah_countryCode) 971#define ath_hal_gettkipmic(_ah) \ 972 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 973#define ath_hal_settkipmic(_ah, _v) \ 974 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 975#define ath_hal_hastkipsplit(_ah) \ 976 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 977#define ath_hal_gettkipsplit(_ah) \ 978 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 979#define ath_hal_settkipsplit(_ah, _v) \ 980 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 981#define ath_hal_haswmetkipmic(_ah) \ 982 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 983#define ath_hal_hwphycounters(_ah) \ 984 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 985#define ath_hal_hasdiversity(_ah) \ 986 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 987#define ath_hal_getdiversity(_ah) \ 988 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 989#define ath_hal_setdiversity(_ah, _v) \ 990 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 991#define ath_hal_getantennaswitch(_ah) \ 992 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 993#define ath_hal_setantennaswitch(_ah, _v) \ 994 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 995#define ath_hal_getdiag(_ah, _pv) \ 996 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 997#define ath_hal_setdiag(_ah, _v) \ 998 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 999#define ath_hal_getnumtxqueues(_ah, _pv) \ 1000 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1001#define ath_hal_hasveol(_ah) \ 1002 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1003#define ath_hal_hastxpowlimit(_ah) \ 1004 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1005#define ath_hal_settxpowlimit(_ah, _pow) \ 1006 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1007#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1008 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1009#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1010 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1011#define ath_hal_gettpscale(_ah, _scale) \ 1012 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1013#define ath_hal_settpscale(_ah, _v) \ 1014 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1015#define ath_hal_hastpc(_ah) \ 1016 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1017#define ath_hal_gettpc(_ah) \ 1018 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1019#define ath_hal_settpc(_ah, _v) \ 1020 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1021#define ath_hal_hasbursting(_ah) \ 1022 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1023#define ath_hal_setmcastkeysearch(_ah, _v) \ 1024 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1025#define ath_hal_hasmcastkeysearch(_ah) \ 1026 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1027#define ath_hal_getmcastkeysearch(_ah) \ 1028 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1029#define ath_hal_hasfastframes(_ah) \ 1030 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1031#define ath_hal_hasbssidmask(_ah) \ 1032 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1033#define ath_hal_hasbssidmatch(_ah) \ 1034 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1035#define ath_hal_hastsfadjust(_ah) \ 1036 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1037#define ath_hal_gettsfadjust(_ah) \ 1038 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1039#define ath_hal_settsfadjust(_ah, _onoff) \ 1040 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1041#define ath_hal_hasrfsilent(_ah) \ 1042 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1043#define ath_hal_getrfkill(_ah) \ 1044 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1045#define ath_hal_setrfkill(_ah, _onoff) \ 1046 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1047#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1048 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1049#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1050 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1051#define ath_hal_gettpack(_ah, _ptpack) \ 1052 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1053#define ath_hal_settpack(_ah, _tpack) \ 1054 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1055#define ath_hal_gettpcts(_ah, _ptpcts) \ 1056 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1057#define ath_hal_settpcts(_ah, _tpcts) \ 1058 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1059#define ath_hal_hasintmit(_ah) \ 1060 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1061 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1062#define ath_hal_getintmit(_ah) \ 1063 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1064 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1065#define ath_hal_setintmit(_ah, _v) \ 1066 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1067 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1068 1069/* EDMA definitions */ 1070#define ath_hal_hasedma(_ah) \ 1071 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1072 0, NULL) == HAL_OK) 1073#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1074 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1075 == HAL_OK) 1076#define ath_hal_getntxmaps(_ah, _req) \ 1077 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1078 == HAL_OK) 1079#define ath_hal_gettxdesclen(_ah, _req) \ 1080 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1081 == HAL_OK) 1082#define ath_hal_gettxstatuslen(_ah, _req) \ 1083 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1084 == HAL_OK) 1085#define ath_hal_getrxstatuslen(_ah, _req) \ 1086 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1087 == HAL_OK) 1088#define ath_hal_setrxbufsize(_ah, _req) \ 1089 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1090 == HAL_OK) 1091 1092#define ath_hal_getchannoise(_ah, _c) \ 1093 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1094 1095/* 802.11n HAL methods */ 1096#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1097 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1098#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1099 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1100#define ath_hal_setrxchainmask(_ah, _rx) \ 1101 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1102#define ath_hal_settxchainmask(_ah, _tx) \ 1103 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1104#define ath_hal_split4ktrans(_ah) \ 1105 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1106 0, NULL) == HAL_OK) 1107#define ath_hal_self_linked_final_rxdesc(_ah) \ 1108 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1109 0, NULL) == HAL_OK) 1110#define ath_hal_gtxto_supported(_ah) \ 1111 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1112#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1113 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1114 0, NULL) == HAL_OK) 1115#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1116 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1117#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1118 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1119#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1120 _txr0, _txtr0, _keyix, _ant, _flags, \ 1121 _rtsrate, _rtsdura) \ 1122 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1123 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1124 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1125#define ath_hal_setupxtxdesc(_ah, _ds, \ 1126 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1127 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1128 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1129#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1130 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1131 (_first), (_last), (_ds0))) 1132#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1133 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1134#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1135 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1136#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1137 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1138#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1139 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1140#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1141 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1142#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1143 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1144#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1145 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1146 (_size))) 1147 1148#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1149 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1150 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1151 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1152#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1153 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1154 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1155 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1156 (_first), (_last), (_lastaggr))) 1157#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1158 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1159 1160#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1161 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1162 (_series), (_ns), (_flags))) 1163 1164#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1165 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1166#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1167 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1168#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1169 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1170 1171#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1172 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1173#define ath_hal_clr11n_aggr(_ah, _ds) \ 1174 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1175 1176#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1177 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1178#define ath_hal_gpioset(_ah, _gpio, _b) \ 1179 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1180#define ath_hal_gpioget(_ah, _gpio) \ 1181 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1182#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1183 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1184 1185/* 1186 * PCIe suspend/resume/poweron/poweroff related macros 1187 */ 1188#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1189 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1190#define ath_hal_disablepcie(_ah) \ 1191 ((*(_ah)->ah_disablePCIE)((_ah))) 1192 1193/* 1194 * This is badly-named; you need to set the correct parameters 1195 * to begin to receive useful radar events; and even then 1196 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1197 * more information. 1198 */ 1199#define ath_hal_enabledfs(_ah, _param) \ 1200 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1201#define ath_hal_getdfsthresh(_ah, _param) \ 1202 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1203#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1204 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1205#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1206 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1207 (_buf), (_event))) 1208#define ath_hal_is_fast_clock_enabled(_ah) \ 1209 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1210#define ath_hal_radar_wait(_ah, _chan) \ 1211 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1212#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1213 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1214#define ath_hal_get_chan_ext_busy(_ah) \ 1215 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1216 1217#endif /* _DEV_ATH_ATHVAR_H */ 1218