if_athvar.h revision 239261
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 239261 2012-08-14 22:30:17Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46220033Sadrian/* 47237000Sadrian * There is a separate TX ath_buf pool for management frames. 48237000Sadrian * This ensures that management frames such as probe responses 49237000Sadrian * and BAR frames can be transmitted during periods of high 50237000Sadrian * TX activity. 51237000Sadrian */ 52237000Sadrian#define ATH_MGMT_TXBUF 32 53237000Sadrian 54237000Sadrian/* 55220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 56220033Sadrian */ 57220053Sadrian#ifdef ATH_ENABLE_11N 58235804Sadrian#define ATH_TXBUF 512 59220033Sadrian#define ATH_RXBUF 512 60220033Sadrian#endif 61220033Sadrian 62155481Ssam#ifndef ATH_RXBUF 63116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 64155481Ssam#endif 65155481Ssam#ifndef ATH_TXBUF 66170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 67155481Ssam#endif 68178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 69178354Ssam 70140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74116743Ssam 75225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78147067Ssam 79147057Ssam/* 80147057Ssam * The key cache is used for h/w cipher state and also for 81147057Ssam * tracking station state such as the current tx antenna. 82147057Ssam * We also setup a mapping table between key cache slot indices 83147057Ssam * and station state to short-circuit node lookups on rx. 84147057Ssam * Different parts have different size key caches. We handle 85147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 86147057Ssam */ 87147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 88147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89147057Ssam 90170530Ssamstruct taskqueue; 91170530Ssamstruct kthread; 92170530Ssamstruct ath_buf; 93170530Ssam 94227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95227328Sadrian 96227328Sadrian/* 97227328Sadrian * Per-TID state 98227328Sadrian * 99227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100227328Sadrian */ 101227328Sadrianstruct ath_tid { 102227328Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103227328Sadrian u_int axq_depth; /* SW queue depth */ 104227328Sadrian char axq_name[48]; /* lock name */ 105227328Sadrian struct ath_node *an; /* pointer to parent */ 106227328Sadrian int tid; /* tid */ 107227328Sadrian int ac; /* which AC gets this trafic */ 108227328Sadrian int hwq_depth; /* how many buffers are on HW */ 109227328Sadrian 110227328Sadrian /* 111227328Sadrian * Entry on the ath_txq; when there's traffic 112227328Sadrian * to send 113227328Sadrian */ 114227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 115227328Sadrian int sched; 116227328Sadrian int paused; /* >0 if the TID has been paused */ 117235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 118233908Sadrian int bar_wait; /* waiting for BAR */ 119233908Sadrian int bar_tx; /* BAR TXed */ 120227328Sadrian 121227328Sadrian /* 122227328Sadrian * Is the TID being cleaned up after a transition 123227328Sadrian * from aggregation to non-aggregation? 124227328Sadrian * When this is set to 1, this TID will be paused 125227328Sadrian * and no further traffic will be queued until all 126227328Sadrian * the hardware packets pending for this TID have been 127227328Sadrian * TXed/completed; at which point (non-aggregation) 128227328Sadrian * traffic will resume being TXed. 129227328Sadrian */ 130227328Sadrian int cleanup_inprogress; 131227328Sadrian /* 132227328Sadrian * How many hardware-queued packets are 133227328Sadrian * waiting to be cleaned up. 134227328Sadrian * This is only valid if cleanup_inprogress is 1. 135227328Sadrian */ 136227328Sadrian int incomp; 137227328Sadrian 138227328Sadrian /* 139227328Sadrian * The following implements a ring representing 140227328Sadrian * the frames in the current BAW. 141227328Sadrian * To avoid copying the array content each time 142227328Sadrian * the BAW is moved, the baw_head/baw_tail point 143227328Sadrian * to the current BAW begin/end; when the BAW is 144227328Sadrian * shifted the head/tail of the array are also 145227328Sadrian * appropriately shifted. 146227328Sadrian */ 147227328Sadrian /* active tx buffers, beginning at current BAW */ 148227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149227328Sadrian /* where the baw head is in the array */ 150227328Sadrian int baw_head; 151227328Sadrian /* where the BAW tail is in the array */ 152227328Sadrian int baw_tail; 153227328Sadrian}; 154227328Sadrian 155138570Ssam/* driver-specific node state */ 156116743Ssamstruct ath_node { 157119150Ssam struct ieee80211_node an_node; /* base class */ 158178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 159178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 160170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 163227328Sadrian struct mtx an_mtx; /* protecting the ath_node state */ 164138570Ssam /* variable-length rate control state follows */ 165116743Ssam}; 166138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 167138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168116743Ssam 169138570Ssam#define ATH_RSSI_LPF_LEN 10 170138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 171138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 172138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 174138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 176138570Ssam if ((y) >= -20) \ 177138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178138570Ssam} while (0) 179184358Ssam#define ATH_EP_RND(x,mul) \ 180184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182138570Ssam 183237000Sadriantypedef enum { 184237000Sadrian ATH_BUFTYPE_NORMAL = 0, 185237000Sadrian ATH_BUFTYPE_MGMT = 1, 186237000Sadrian} ath_buf_type_t; 187237000Sadrian 188116743Ssamstruct ath_buf { 189227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 190227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 191116743Ssam int bf_nseg; 192238436Sadrian HAL_STATUS bf_rxstatus; 193186904Ssam uint16_t bf_flags; /* status flags (below) */ 194116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 195165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 196116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 197138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 198116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 199116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 200227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 201227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 202116743Ssam bus_size_t bf_mapsize; 203140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 204116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 205227328Sadrian 206227328Sadrian /* Completion function to call on TX complete (fail or not) */ 207227328Sadrian /* 208227328Sadrian * "fail" here is set to 1 if the queue entries were removed 209227328Sadrian * through a call to ath_tx_draintxq(). 210227328Sadrian */ 211227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 212227328Sadrian 213227328Sadrian /* This state is kept to support software retries and aggregation */ 214227328Sadrian struct { 215237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 216227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 217227328Sadrian 218237046Sadrian uint8_t bfs_retries; /* retry count */ 219237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 220237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 221237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 222237046Sadrian 223237046Sadrian struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 224237046Sadrian 225234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 226234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 227234109Sadrian bfs_isretried:1, /* retried frame? */ 228234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 229234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 230234109Sadrian bfs_shpream:1, /* use short preamble */ 231234109Sadrian bfs_istxfrag:1, /* is fragmented */ 232234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 233234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 234236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 235234109Sadrian 236227328Sadrian /* 237227328Sadrian * These fields are passed into the 238227328Sadrian * descriptor setup functions. 239227328Sadrian */ 240237153Sadrian 241237153Sadrian /* Make this an 8 bit value? */ 242227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 243237153Sadrian 244237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 245237153Sadrian 246237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 247227328Sadrian uint16_t bfs_al; /* length of aggregate */ 248237153Sadrian 249237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 250237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 251237153Sadrian uint8_t bfs_try0; /* first try count */ 252237153Sadrian 253237153Sadrian uint16_t bfs_txpower; /* tx power */ 254227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 255237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 256237153Sadrian 257237153Sadrian /* 16 bit? */ 258237153Sadrian int32_t bfs_keyix; /* crypto key index */ 259237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 260237153Sadrian 261237153Sadrian /* Make this an 8 bit value? */ 262227328Sadrian enum ieee80211_protmode bfs_protmode; 263237153Sadrian 264237153Sadrian /* 16 bit? */ 265237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 266227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 267227328Sadrian } bf_state; 268116743Ssam}; 269227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 270116743Ssam 271237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 272186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 273186904Ssam 274138570Ssam/* 275138570Ssam * DMA state for tx/rx descriptors. 276138570Ssam */ 277138570Ssamstruct ath_descdma { 278138570Ssam const char* dd_name; 279138570Ssam struct ath_desc *dd_desc; /* descriptors */ 280238708Sadrian int dd_descsize; /* size of single descriptor */ 281138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 282158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 283138570Ssam bus_dma_segment_t dd_dseg; 284138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 285138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 286138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 287138570Ssam}; 288138570Ssam 289138570Ssam/* 290138570Ssam * Data transmit queue state. One of these exists for each 291138570Ssam * hardware transmit queue. Packets sent to us from above 292138570Ssam * are assigned to queues based on their priority. Not all 293138570Ssam * devices support a complete set of hardware transmit queues. 294138570Ssam * For those devices the array sc_ac2q will map multiple 295138570Ssam * priorities to fewer hardware queues (typically all to one 296138570Ssam * hardware queue). 297138570Ssam */ 298138570Ssamstruct ath_txq { 299227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 300138570Ssam u_int axq_qnum; /* hardware q number */ 301178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 302190579Ssam u_int axq_ac; /* WME AC */ 303186904Ssam u_int axq_flags; 304186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 305156073Ssam u_int axq_depth; /* queue depth (stat only) */ 306227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 307239197Sadrian u_int axq_fifo_depth; /* depth of FIFO frames */ 308138570Ssam u_int axq_intrcnt; /* interrupt count */ 309138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 310227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 311138570Ssam struct mtx axq_lock; /* lock on q and link */ 312155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 313227344Sadrian 314227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 315227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 316138570Ssam}; 317138570Ssam 318227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 319227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 320227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 321227328Sadrian 322155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 323155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 324155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 325167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 326161425Simp} while (0) 327138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 328138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 329138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 330239261Sadrian#define ATH_TXQ_LOCK_ASSERT(_tq) \ 331239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_OWNED) 332239261Sadrian#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 333239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 334227328Sadrian#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 335138570Ssam 336236873Sadrian#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 337236873Sadrian ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 338236873Sadrian 339227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 340227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 341227344Sadrian (_tq)->axq_depth++; \ 342227344Sadrian} while (0) 343138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 344227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 345138570Ssam (_tq)->axq_depth++; \ 346138570Ssam} while (0) 347227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 348227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 349138570Ssam (_tq)->axq_depth--; \ 350138570Ssam} while (0) 351239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 352227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 353138570Ssam 354178354Ssamstruct ath_vap { 355178354Ssam struct ieee80211vap av_vap; /* base class */ 356178354Ssam int av_bslot; /* beacon slot index */ 357178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 358178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 359178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 360178354Ssam 361178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 362192468Ssam struct mbuf *, int, int, int); 363178354Ssam int (*av_newstate)(struct ieee80211vap *, 364178354Ssam enum ieee80211_state, int); 365178354Ssam void (*av_bmiss)(struct ieee80211vap *); 366178354Ssam}; 367178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 368178354Ssam 369155491Ssamstruct taskqueue; 370155486Ssamstruct ath_tx99; 371155486Ssam 372227328Sadrian/* 373227328Sadrian * Whether to reset the TX/RX queue with or without 374227328Sadrian * a queue flush. 375227328Sadrian */ 376227328Sadriantypedef enum { 377227328Sadrian ATH_RESET_DEFAULT = 0, 378227328Sadrian ATH_RESET_NOLOSS = 1, 379227328Sadrian ATH_RESET_FULL = 2, 380227328Sadrian} ATH_RESET_TYPE; 381227328Sadrian 382238055Sadrianstruct ath_rx_methods { 383238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 384238055Sadrian int (*recv_start)(struct ath_softc *sc); 385238055Sadrian void (*recv_flush)(struct ath_softc *sc); 386238055Sadrian void (*recv_tasklet)(void *arg, int npending); 387238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 388238055Sadrian struct ath_buf *bf); 389238284Sadrian int (*recv_setup)(struct ath_softc *sc); 390238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 391238055Sadrian}; 392238055Sadrian 393238284Sadrian/* 394238284Sadrian * Represent the current state of the RX FIFO. 395238284Sadrian */ 396238284Sadrianstruct ath_rx_edma { 397238284Sadrian struct ath_buf **m_fifo; 398238284Sadrian int m_fifolen; 399238284Sadrian int m_fifo_head; 400238284Sadrian int m_fifo_tail; 401238284Sadrian int m_fifo_depth; 402238284Sadrian struct mbuf *m_rxpending; 403238284Sadrian}; 404238284Sadrian 405238855Sadrianstruct ath_tx_edma_fifo { 406238855Sadrian struct ath_buf **m_fifo; 407238855Sadrian int m_fifolen; 408238855Sadrian int m_fifo_head; 409238855Sadrian int m_fifo_tail; 410238855Sadrian int m_fifo_depth; 411238855Sadrian}; 412238855Sadrian 413238710Sadrianstruct ath_tx_methods { 414238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 415238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 416238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 417238931Sadrian 418238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 419238931Sadrian struct ath_txq *txq); 420238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 421238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 422239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 423239204Sadrian ATH_RESET_TYPE reset_type); 424238710Sadrian}; 425238710Sadrian 426116743Ssamstruct ath_softc { 427147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 428138570Ssam struct ath_stats sc_stats; /* interface statistics */ 429227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 430234090Sadrian struct ath_intr_stats sc_intr_stats; 431235491Sadrian uint64_t sc_debug; 432178354Ssam int sc_nvaps; /* # vaps */ 433178354Ssam int sc_nstavaps; /* # station vaps */ 434195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 435178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 436178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 437178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 438178354Ssam 439238055Sadrian struct ath_rx_methods sc_rx; 440238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 441238710Sadrian struct ath_tx_methods sc_tx; 442238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 443238710Sadrian 444238284Sadrian int sc_rx_statuslen; 445238284Sadrian int sc_tx_desclen; 446238284Sadrian int sc_tx_statuslen; 447238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 448238284Sadrian int sc_edma_bufsize; 449238055Sadrian 450227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 451138570Ssam void (*sc_node_free)(struct ieee80211_node *); 452116743Ssam device_t sc_dev; 453159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 454159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 455116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 456116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 457227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 458227328Sadrian char sc_pcu_mtx_name[32]; 459238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 460238433Sadrian char sc_rx_mtx_name[32]; 461155491Ssam struct taskqueue *sc_tq; /* private task queue */ 462116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 463138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 464155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 465138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 466178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 467178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 468238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 469178354Ssam sc_softled : 1,/* enable LED gpio status */ 470228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 471178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 472178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 473178354Ssam sc_diversity: 1,/* enable rx diversity */ 474178354Ssam sc_hasveol : 1,/* tx VEOL support */ 475178354Ssam sc_ledstate : 1,/* LED on/off state */ 476178354Ssam sc_blinking : 1,/* LED blink operation active */ 477178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 478178354Ssam sc_scanning : 1,/* scanning active */ 479155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 480178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 481165571Ssam sc_xchanmode: 1,/* extended channel mode */ 482170530Ssam sc_outdoor : 1,/* outdoor operation */ 483178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 484178354Ssam sc_hasbmask : 1,/* bssid mask support */ 485195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 486178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 487178354Ssam sc_beacons : 1,/* beacons running */ 488178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 489178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 490179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 491185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 492186904Ssam sc_tdma : 1,/* TDMA in use */ 493189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 494220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 495224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 496238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 497238284Sadrian sc_isedma : 1;/* supports EDMA */ 498178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 499178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 500116743Ssam /* rate tables */ 501188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 502116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 503116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 504155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 505138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 506170530Ssam u_int16_t sc_curaid; /* current association id */ 507187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 508170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 509116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 510140432Ssam struct { 511140432Ssam u_int8_t ieeerate; /* IEEE rate */ 512140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 513140761Ssam u_int8_t txflags; /* radiotap tx flags */ 514140432Ssam u_int16_t ledon; /* softled on time */ 515140432Ssam u_int16_t ledoff; /* softled off time */ 516140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 517138570Ssam u_int8_t sc_protrix; /* protection rate index */ 518170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 519155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 520170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 521170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 522138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 523227346Sadrian 524116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 525227651Sadrian 526227346Sadrian /* 527227346Sadrian * These are modified in the interrupt handler as well as 528227346Sadrian * the task queues and other contexts. Thus these must be 529227346Sadrian * protected by a mutex, or they could clash. 530227346Sadrian * 531227346Sadrian * For now, access to these is behind the ATH_LOCK, 532227346Sadrian * just to save time. 533227346Sadrian */ 534227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 535227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 536227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 537227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 538227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 539227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 540227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 541227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 542227346Sadrian 543138570Ssam u_int sc_keymax; /* size of key cache */ 544147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 545116743Ssam 546228891Sadrian /* 547228891Sadrian * Software based LED blinking 548228891Sadrian */ 549140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 550140432Ssam u_int sc_ledon; /* pin setting for LED on */ 551140432Ssam u_int sc_ledidle; /* idle polling interval */ 552140432Ssam int sc_ledevent; /* time of last LED event */ 553184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 554140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 555140432Ssam struct callout sc_ledtimer; /* led off timer */ 556138570Ssam 557228891Sadrian /* 558228891Sadrian * Hardware based LED blinking 559228891Sadrian */ 560228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 561228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 562228891Sadrian 563155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 564155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 565155515Ssam 566178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 567138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 568116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 569116743Ssam struct task sc_rxtask; /* rx int processing */ 570138570Ssam u_int8_t sc_defant; /* current default antenna */ 571138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 572155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 573192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 574192468Ssam struct ath_rx_radiotap_header sc_rx_th; 575192468Ssam int sc_rx_th_len; 576192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 577116743Ssam 578138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 579138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 580237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 581237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 582237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 583238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 584138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 585155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 586138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 587138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 588138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 589138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 590116743Ssam struct task sc_txtask; /* tx int processing */ 591233673Sadrian struct task sc_txqtask; /* tx proc processing */ 592238709Sadrian 593238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 594238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 595238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 596238709Sadrian 597189605Ssam int sc_wd_timer; /* count down for wd timer */ 598189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 599192468Ssam struct ath_tx_radiotap_header sc_tx_th; 600192468Ssam int sc_tx_th_len; 601116743Ssam 602138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 603138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 604116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 605138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 606138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 607138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 608116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 609138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 610232163Sadrian struct task sc_resettask; /* interface reset task */ 611234369Sadrian struct task sc_fataltask; /* fatal task */ 612138570Ssam enum { 613138570Ssam OK, /* no change needed */ 614138570Ssam UPDATE, /* update pending */ 615138570Ssam COMMIT /* beacon sent, commit change */ 616138570Ssam } sc_updateslot; /* slot time update fsm */ 617178354Ssam int sc_slotupdate; /* slot to advance fsm */ 618178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 619178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 620116743Ssam 621116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 622185744Ssam int sc_lastlongcal; /* last long cal completed */ 623185744Ssam int sc_lastcalreset;/* last cal reset done */ 624217684Sadrian int sc_lastani; /* last ANI poll */ 625217684Sadrian int sc_lastshortcal; /* last short calibration */ 626217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 627155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 628186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 629186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 630186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 631186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 632186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 633186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 634186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 635186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 636217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 637218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 638218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 639233967Sadrian int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 640222585Sadrian 641232764Sadrian /* Queue limits */ 642232764Sadrian 643227328Sadrian /* 644232764Sadrian * To avoid queue starvation in congested conditions, 645232764Sadrian * these parameters tune the maximum number of frames 646232764Sadrian * queued to the data/mcastq before they're dropped. 647232764Sadrian * 648232764Sadrian * This is to prevent: 649232764Sadrian * + a single destination overwhelming everything, including 650232764Sadrian * management/multicast frames; 651232764Sadrian * + multicast frames overwhelming everything (when the 652232764Sadrian * air is sufficiently busy that cabq can't drain.) 653232764Sadrian * 654232764Sadrian * These implement: 655232764Sadrian * + data_minfree is the maximum number of free buffers 656232764Sadrian * overall to successfully allow a data frame. 657232764Sadrian * 658232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 659232764Sadrian */ 660232764Sadrian int sc_txq_data_minfree; 661232764Sadrian int sc_txq_mcastq_maxdepth; 662232764Sadrian 663232764Sadrian /* 664227328Sadrian * Aggregation twiddles 665227328Sadrian * 666227328Sadrian * hwq_limit: how busy to keep the hardware queue - don't schedule 667227328Sadrian * further packets to the hardware, regardless of the TID 668227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 669227328Sadrian * TID will be scheduled again 670227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 671227328Sadrian * stops being scheduled. 672227328Sadrian */ 673227328Sadrian int sc_hwq_limit; 674227328Sadrian int sc_tid_hwq_lo; 675227328Sadrian int sc_tid_hwq_hi; 676227328Sadrian 677222585Sadrian /* DFS related state */ 678222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 679222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 680222585Sadrian struct task sc_dfstask; /* DFS processing task */ 681227328Sadrian 682227328Sadrian /* TX AMPDU handling */ 683227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 684227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 685227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 686227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 687227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 688227328Sadrian struct ieee80211_tx_ampdu *); 689227328Sadrian void (*sc_addba_response_timeout) 690227328Sadrian (struct ieee80211_node *, 691227328Sadrian struct ieee80211_tx_ampdu *); 692227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 693227328Sadrian struct ieee80211_tx_ampdu *tap, 694227328Sadrian int status); 695116743Ssam}; 696116743Ssam 697121100Ssam#define ATH_LOCK_INIT(_sc) \ 698121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 699167252Ssam NULL, MTX_DEF | MTX_RECURSE) 700121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 701121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 702121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 703121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 704227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 705121100Ssam 706227328Sadrian/* 707227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 708227328Sadrian * Although currently the interrupt code is run in netisr context and 709227328Sadrian * doesn't require this, this may change in the future. 710227328Sadrian * Please keep this in mind when protecting certain code paths 711227328Sadrian * with the PCU lock. 712227328Sadrian * 713227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 714227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 715227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 716227328Sadrian * 717227328Sadrian * Although the current single-thread taskqueue mechanism protects the 718227328Sadrian * majority of these situations by simply serialising them, there are 719227328Sadrian * a few others which occur at the same time. These include the TX path 720227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 721227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 722227328Sadrian */ 723227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 724227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 725227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 726227328Sadrian "%s PCU lock", \ 727227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 728227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 729227328Sadrian NULL, MTX_DEF); \ 730227328Sadrian } while (0) 731227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 732227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 733227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 734227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 735227328Sadrian MA_OWNED) 736227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 737227651Sadrian MA_NOTOWNED) 738227328Sadrian 739238433Sadrian/* 740238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 741238433Sadrian * RX FIFO/list isn't modified by various execution paths. 742238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 743238433Sadrian * RX path can be executed via various reset/channel change paths. 744238433Sadrian */ 745238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 746238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 747238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 748238433Sadrian "%s RX lock", \ 749238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 750238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 751238433Sadrian NULL, MTX_DEF); \ 752238433Sadrian } while (0) 753238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 754238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 755238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 756238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 757238433Sadrian MA_OWNED) 758238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 759238433Sadrian MA_NOTOWNED) 760238433Sadrian 761138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 762138570Ssam 763155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 764155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 765155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 766167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 767155482Ssam} while (0) 768121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 769121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 770121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 771121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 772121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 773121100Ssam 774238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 775238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 776238709Sadrian "%s_buf", \ 777238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 778238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 779238709Sadrian MTX_DEF); \ 780238709Sadrian} while (0) 781238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 782238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 783238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 784238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 785238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 786238709Sadrian 787116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 788116743Ssamint ath_detach(struct ath_softc *); 789116743Ssamvoid ath_resume(struct ath_softc *); 790116743Ssamvoid ath_suspend(struct ath_softc *); 791116743Ssamvoid ath_shutdown(struct ath_softc *); 792116743Ssamvoid ath_intr(void *); 793116743Ssam 794116743Ssam/* 795116743Ssam * HAL definitions to comply with local coding convention. 796116743Ssam */ 797138570Ssam#define ath_hal_detach(_ah) \ 798138570Ssam ((*(_ah)->ah_detach)((_ah))) 799116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 800116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 801186904Ssam#define ath_hal_macversion(_ah) \ 802186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 803116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 804116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 805116743Ssam#define ath_hal_getmac(_ah, _mac) \ 806116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 807138570Ssam#define ath_hal_setmac(_ah, _mac) \ 808138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 809178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 810178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 811178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 812178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 813116743Ssam#define ath_hal_intrset(_ah, _mask) \ 814116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 815116743Ssam#define ath_hal_intrget(_ah) \ 816116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 817116743Ssam#define ath_hal_intrpend(_ah) \ 818116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 819116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 820116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 821116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 822116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 823155515Ssam#define ath_hal_setpower(_ah, _mode) \ 824155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 825138570Ssam#define ath_hal_keycachesize(_ah) \ 826138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 827116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 828116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 829138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 830138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 831116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 832116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 833116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 834116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 835116743Ssam#define ath_hal_getrxfilter(_ah) \ 836116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 837116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 838116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 839116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 840116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 841116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 842116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 843238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 844238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 845186904Ssam/* NB: common across all chips */ 846186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 847116743Ssam#define ath_hal_gettsf32(_ah) \ 848186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 849116743Ssam#define ath_hal_gettsf64(_ah) \ 850116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 851116743Ssam#define ath_hal_resettsf(_ah) \ 852116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 853116743Ssam#define ath_hal_rxena(_ah) \ 854116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 855116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 856116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 857116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 858116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 859138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 860138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 861238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 862238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 863116743Ssam#define ath_hal_txstart(_ah, _q) \ 864116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 865116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 866116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 867155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 868155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 869185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 870185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 871185744Ssam#define ath_hal_calreset(_ah, _chan) \ 872185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 873116743Ssam#define ath_hal_setledstate(_ah, _state) \ 874116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 875138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 876138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 877116743Ssam#define ath_hal_beaconreset(_ah) \ 878116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 879186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 880186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 881138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 882138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 883225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 884225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 885116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 886138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 887138570Ssam#define ath_hal_phydisable(_ah) \ 888138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 889138570Ssam#define ath_hal_setopmode(_ah) \ 890138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 891116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 892116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 893116743Ssam#define ath_hal_stoppcurecv(_ah) \ 894116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 895116743Ssam#define ath_hal_startpcurecv(_ah) \ 896116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 897116743Ssam#define ath_hal_stopdmarecv(_ah) \ 898116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 899138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 900138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 901138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 902155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 903170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 904116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 905116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 906116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 907116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 908116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 909116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 910138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 911138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 912138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 913138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 914186904Ssam/* NB: common across all chips */ 915186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 916186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 917186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 918116743Ssam#define ath_hal_getrfgain(_ah) \ 919116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 920138570Ssam#define ath_hal_getdefantenna(_ah) \ 921138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 922138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 923138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 924155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 925155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 926217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 927217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 928138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 929138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 930138570Ssam#define ath_hal_setslottime(_ah, _us) \ 931138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 932138570Ssam#define ath_hal_getslottime(_ah) \ 933138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 934138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 935138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 936138570Ssam#define ath_hal_getacktimeout(_ah) \ 937138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 938138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 939138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 940138570Ssam#define ath_hal_getctstimeout(_ah) \ 941138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 942138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 943138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 944138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 945138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 946138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 947138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 948138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 949155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 950155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 951184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 952138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 953138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 954178354Ssam#define ath_hal_gettkipmic(_ah) \ 955178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 956178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 957178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 958162410Ssam#define ath_hal_hastkipsplit(_ah) \ 959138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 960162410Ssam#define ath_hal_gettkipsplit(_ah) \ 961162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 962162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 963162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 964178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 965178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 966138570Ssam#define ath_hal_hwphycounters(_ah) \ 967138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 968138570Ssam#define ath_hal_hasdiversity(_ah) \ 969138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 970138570Ssam#define ath_hal_getdiversity(_ah) \ 971138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 972138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 973138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 974166954Ssam#define ath_hal_getantennaswitch(_ah) \ 975166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 976166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 977166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 978138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 979138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 980138570Ssam#define ath_hal_setdiag(_ah, _v) \ 981138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 982138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 983138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 984138570Ssam#define ath_hal_hasveol(_ah) \ 985138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 986138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 987138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 988138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 989138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 990138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 991138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 992138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 993138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 994138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 995138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 996138570Ssam#define ath_hal_settpscale(_ah, _v) \ 997138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 998138570Ssam#define ath_hal_hastpc(_ah) \ 999138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1000138570Ssam#define ath_hal_gettpc(_ah) \ 1001138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1002138570Ssam#define ath_hal_settpc(_ah, _v) \ 1003138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1004138570Ssam#define ath_hal_hasbursting(_ah) \ 1005138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1006203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1007203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1008147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1009147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1010147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1011147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1012170530Ssam#define ath_hal_hasfastframes(_ah) \ 1013170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1014178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1015178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1016195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1017195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1018178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1019178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1020178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1021178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1022178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1023178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1024155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1025155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1026155515Ssam#define ath_hal_getrfkill(_ah) \ 1027155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1028155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1029155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1030155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1031155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1032155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1033155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1034155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1035155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1036155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1037155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1038155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1039155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1040155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1041155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1042184354Ssam#define ath_hal_hasintmit(_ah) \ 1043230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1044230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1045184354Ssam#define ath_hal_getintmit(_ah) \ 1046230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1047230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1048184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1049230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1050230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1051238280Sadrian 1052238280Sadrian/* EDMA definitions */ 1053237953Sadrian#define ath_hal_hasedma(_ah) \ 1054237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1055237953Sadrian 0, NULL) == HAL_OK) 1056238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1057238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1058238280Sadrian == HAL_OK) 1059238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1060238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1061238280Sadrian == HAL_OK) 1062238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1063238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1064238280Sadrian == HAL_OK) 1065238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1066238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1067238280Sadrian == HAL_OK) 1068238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1069238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1070238280Sadrian == HAL_OK) 1071238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1072238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1073238280Sadrian == HAL_OK) 1074238280Sadrian 1075154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1076154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1077238280Sadrian 1078238280Sadrian/* 802.11n HAL methods */ 1079218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1080218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1081218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1082218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1083231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1084231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1085231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1086231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1087218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1088230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1089230493Sadrian 0, NULL) == HAL_OK) 1090220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1091230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1092230493Sadrian 0, NULL) == HAL_OK) 1093220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1094220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1095225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1096230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1097230493Sadrian 0, NULL) == HAL_OK) 1098116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1099116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1100165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1101165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1102116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1103116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1104116743Ssam _rtsrate, _rtsdura) \ 1105116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1106116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1107155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1108138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1109116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1110138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1111116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1112239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1113239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1114239051Sadrian (_first), (_last), (_ds0))) 1115165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1116165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1117155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1118155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1119217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1120217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1121238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1122238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1123238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1124238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1125238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1126238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1127238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1128238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1129238731Sadrian (_size))) 1130116743Ssam 1131218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1132218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1133218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1134218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1135239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1136239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1137239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1138239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1139233895Sadrian (_first), (_last), (_lastaggr))) 1140218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1141218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1142227328Sadrian 1143218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1144218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1145218067Sadrian (_series), (_ns), (_flags))) 1146227328Sadrian 1147227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1148238838Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1149218066Sadrian#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1150227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1151227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1152227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1153227328Sadrian 1154218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1155218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1156227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1157227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1158218066Sadrian 1159230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1160230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1161230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1162230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1163230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1164230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1165230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1166230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1167230493Sadrian 1168222585Sadrian/* 1169235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1170235957Sadrian */ 1171235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1172235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1173235957Sadrian#define ath_hal_disablepcie(_ah) \ 1174235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1175235957Sadrian 1176235957Sadrian/* 1177222585Sadrian * This is badly-named; you need to set the correct parameters 1178222585Sadrian * to begin to receive useful radar events; and even then 1179222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1180222585Sadrian * more information. 1181222585Sadrian */ 1182222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1183222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1184222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1185222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1186222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1187230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1188230493Sadrian (_buf), (_event))) 1189224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1190224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1191230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1192155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1193234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1194234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1195230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1196230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1197155515Ssam 1198116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1199