if_athvar.h revision 237953
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 237953 2012-07-02 06:02:12Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52#define ATH_MGMT_TXBUF 32 53 54/* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57#ifdef ATH_ENABLE_11N 58#define ATH_TXBUF 512 59#define ATH_RXBUF 512 60#endif 61 62#ifndef ATH_RXBUF 63#define ATH_RXBUF 40 /* number of RX buffers */ 64#endif 65#ifndef ATH_TXBUF 66#define ATH_TXBUF 200 /* number of TX buffers */ 67#endif 68#define ATH_BCBUF 4 /* number of beacon buffers */ 69 70#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79/* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87#define ATH_KEYMAX 128 /* max key cache size we handle */ 88#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90struct taskqueue; 91struct kthread; 92struct ath_buf; 93 94#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96/* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 /* 111 * Entry on the ath_txq; when there's traffic 112 * to send 113 */ 114 TAILQ_ENTRY(ath_tid) axq_qelem; 115 int sched; 116 int paused; /* >0 if the TID has been paused */ 117 int addba_tx_pending; /* TX ADDBA pending */ 118 int bar_wait; /* waiting for BAR */ 119 int bar_tx; /* BAR TXed */ 120 121 /* 122 * Is the TID being cleaned up after a transition 123 * from aggregation to non-aggregation? 124 * When this is set to 1, this TID will be paused 125 * and no further traffic will be queued until all 126 * the hardware packets pending for this TID have been 127 * TXed/completed; at which point (non-aggregation) 128 * traffic will resume being TXed. 129 */ 130 int cleanup_inprogress; 131 /* 132 * How many hardware-queued packets are 133 * waiting to be cleaned up. 134 * This is only valid if cleanup_inprogress is 1. 135 */ 136 int incomp; 137 138 /* 139 * The following implements a ring representing 140 * the frames in the current BAW. 141 * To avoid copying the array content each time 142 * the BAW is moved, the baw_head/baw_tail point 143 * to the current BAW begin/end; when the BAW is 144 * shifted the head/tail of the array are also 145 * appropriately shifted. 146 */ 147 /* active tx buffers, beginning at current BAW */ 148 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149 /* where the baw head is in the array */ 150 int baw_head; 151 /* where the BAW tail is in the array */ 152 int baw_tail; 153}; 154 155/* driver-specific node state */ 156struct ath_node { 157 struct ieee80211_node an_node; /* base class */ 158 u_int8_t an_mgmtrix; /* min h/w rate index */ 159 u_int8_t an_mcastrix; /* mcast h/w rate index */ 160 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162 char an_name[32]; /* eg "wlan0_a1" */ 163 struct mtx an_mtx; /* protecting the ath_node state */ 164 /* variable-length rate control state follows */ 165}; 166#define ATH_NODE(ni) ((struct ath_node *)(ni)) 167#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168 169#define ATH_RSSI_LPF_LEN 10 170#define ATH_RSSI_DUMMY_MARKER 0x127 171#define ATH_EP_MUL(x, mul) ((x) * (mul)) 172#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173#define ATH_LPF_RSSI(x, y, len) \ 174 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175#define ATH_RSSI_LPF(x, y) do { \ 176 if ((y) >= -20) \ 177 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178} while (0) 179#define ATH_EP_RND(x,mul) \ 180 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182 183typedef enum { 184 ATH_BUFTYPE_NORMAL = 0, 185 ATH_BUFTYPE_MGMT = 1, 186} ath_buf_type_t; 187 188struct ath_buf { 189 TAILQ_ENTRY(ath_buf) bf_list; 190 struct ath_buf * bf_next; /* next buffer in the aggregate */ 191 int bf_nseg; 192 uint16_t bf_flags; /* status flags (below) */ 193 struct ath_desc *bf_desc; /* virtual addr of desc */ 194 struct ath_desc_status bf_status; /* tx/rx status */ 195 bus_addr_t bf_daddr; /* physical addr of desc */ 196 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 197 struct mbuf *bf_m; /* mbuf for buf */ 198 struct ieee80211_node *bf_node; /* pointer to the node */ 199 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 200 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 201 bus_size_t bf_mapsize; 202#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 203 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 204 205 /* Completion function to call on TX complete (fail or not) */ 206 /* 207 * "fail" here is set to 1 if the queue entries were removed 208 * through a call to ath_tx_draintxq(). 209 */ 210 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 211 212 /* This state is kept to support software retries and aggregation */ 213 struct { 214 uint16_t bfs_seqno; /* sequence number of this packet */ 215 uint16_t bfs_ndelim; /* number of delims for padding */ 216 217 uint8_t bfs_retries; /* retry count */ 218 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 219 uint8_t bfs_nframes; /* number of frames in aggregate */ 220 uint8_t bfs_pri; /* packet AC priority */ 221 222 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 223 224 u_int32_t bfs_aggr:1, /* part of aggregate? */ 225 bfs_aggrburst:1, /* part of aggregate burst? */ 226 bfs_isretried:1, /* retried frame? */ 227 bfs_dobaw:1, /* actually check against BAW? */ 228 bfs_addedbaw:1, /* has been added to the BAW */ 229 bfs_shpream:1, /* use short preamble */ 230 bfs_istxfrag:1, /* is fragmented */ 231 bfs_ismrr:1, /* do multi-rate TX retry */ 232 bfs_doprot:1, /* do RTS/CTS based protection */ 233 bfs_doratelookup:1; /* do rate lookup before each TX */ 234 235 /* 236 * These fields are passed into the 237 * descriptor setup functions. 238 */ 239 240 /* Make this an 8 bit value? */ 241 HAL_PKT_TYPE bfs_atype; /* packet type */ 242 243 uint32_t bfs_pktlen; /* length of this packet */ 244 245 uint16_t bfs_hdrlen; /* length of this packet header */ 246 uint16_t bfs_al; /* length of aggregate */ 247 248 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 249 uint8_t bfs_txrate0; /* first TX rate */ 250 uint8_t bfs_try0; /* first try count */ 251 252 uint16_t bfs_txpower; /* tx power */ 253 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 254 uint8_t bfs_ctsrate; /* CTS rate */ 255 256 /* 16 bit? */ 257 int32_t bfs_keyix; /* crypto key index */ 258 int32_t bfs_txantenna; /* TX antenna config */ 259 260 /* Make this an 8 bit value? */ 261 enum ieee80211_protmode bfs_protmode; 262 263 /* 16 bit? */ 264 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 265 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 266 } bf_state; 267}; 268typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 269 270#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 271#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 272 273/* 274 * DMA state for tx/rx descriptors. 275 */ 276struct ath_descdma { 277 const char* dd_name; 278 struct ath_desc *dd_desc; /* descriptors */ 279 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 280 bus_size_t dd_desc_len; /* size of dd_desc */ 281 bus_dma_segment_t dd_dseg; 282 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 283 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 284 struct ath_buf *dd_bufptr; /* associated buffers */ 285}; 286 287/* 288 * Data transmit queue state. One of these exists for each 289 * hardware transmit queue. Packets sent to us from above 290 * are assigned to queues based on their priority. Not all 291 * devices support a complete set of hardware transmit queues. 292 * For those devices the array sc_ac2q will map multiple 293 * priorities to fewer hardware queues (typically all to one 294 * hardware queue). 295 */ 296struct ath_txq { 297 struct ath_softc *axq_softc; /* Needed for scheduling */ 298 u_int axq_qnum; /* hardware q number */ 299#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 300 u_int axq_ac; /* WME AC */ 301 u_int axq_flags; 302#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 303 u_int axq_depth; /* queue depth (stat only) */ 304 u_int axq_aggr_depth; /* how many aggregates are queued */ 305 u_int axq_intrcnt; /* interrupt count */ 306 u_int32_t *axq_link; /* link ptr in last TX desc */ 307 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 308 struct mtx axq_lock; /* lock on q and link */ 309 char axq_name[12]; /* e.g. "ath0_txq4" */ 310 311 /* Per-TID traffic queue for software -> hardware TX */ 312 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 313}; 314 315#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 316#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 317#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 318 319#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 320 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 321 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 322 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 323} while (0) 324#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 325#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 326#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 327#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 328#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 329 330#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 331 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 332 333#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 334 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 335 (_tq)->axq_depth++; \ 336} while (0) 337#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 338 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 339 (_tq)->axq_depth++; \ 340} while (0) 341#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 342 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 343 (_tq)->axq_depth--; \ 344} while (0) 345#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 346 347struct ath_vap { 348 struct ieee80211vap av_vap; /* base class */ 349 int av_bslot; /* beacon slot index */ 350 struct ath_buf *av_bcbuf; /* beacon buffer */ 351 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 352 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 353 354 void (*av_recv_mgmt)(struct ieee80211_node *, 355 struct mbuf *, int, int, int); 356 int (*av_newstate)(struct ieee80211vap *, 357 enum ieee80211_state, int); 358 void (*av_bmiss)(struct ieee80211vap *); 359}; 360#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 361 362struct taskqueue; 363struct ath_tx99; 364 365/* 366 * Whether to reset the TX/RX queue with or without 367 * a queue flush. 368 */ 369typedef enum { 370 ATH_RESET_DEFAULT = 0, 371 ATH_RESET_NOLOSS = 1, 372 ATH_RESET_FULL = 2, 373} ATH_RESET_TYPE; 374 375struct ath_softc { 376 struct ifnet *sc_ifp; /* interface common */ 377 struct ath_stats sc_stats; /* interface statistics */ 378 struct ath_tx_aggr_stats sc_aggr_stats; 379 struct ath_intr_stats sc_intr_stats; 380 uint64_t sc_debug; 381 int sc_nvaps; /* # vaps */ 382 int sc_nstavaps; /* # station vaps */ 383 int sc_nmeshvaps; /* # mbss vaps */ 384 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 385 u_int8_t sc_nbssid0; /* # vap's using base mac */ 386 uint32_t sc_bssidmask; /* bssid mask */ 387 388 void (*sc_node_cleanup)(struct ieee80211_node *); 389 void (*sc_node_free)(struct ieee80211_node *); 390 device_t sc_dev; 391 HAL_BUS_TAG sc_st; /* bus space tag */ 392 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 393 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 394 struct mtx sc_mtx; /* master lock (recursive) */ 395 struct mtx sc_pcu_mtx; /* PCU access mutex */ 396 char sc_pcu_mtx_name[32]; 397 struct taskqueue *sc_tq; /* private task queue */ 398 struct ath_hal *sc_ah; /* Atheros HAL */ 399 struct ath_ratectrl *sc_rc; /* tx rate control support */ 400 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 401 void (*sc_setdefantenna)(struct ath_softc *, u_int); 402 unsigned int sc_invalid : 1,/* disable hardware accesses */ 403 sc_mrretry : 1,/* multi-rate retry support */ 404 sc_softled : 1,/* enable LED gpio status */ 405 sc_hardled : 1,/* enable MAC LED status */ 406 sc_splitmic : 1,/* split TKIP MIC keys */ 407 sc_needmib : 1,/* enable MIB stats intr */ 408 sc_diversity: 1,/* enable rx diversity */ 409 sc_hasveol : 1,/* tx VEOL support */ 410 sc_ledstate : 1,/* LED on/off state */ 411 sc_blinking : 1,/* LED blink operation active */ 412 sc_mcastkey : 1,/* mcast key cache search */ 413 sc_scanning : 1,/* scanning active */ 414 sc_syncbeacon:1,/* sync/resync beacon timers */ 415 sc_hasclrkey: 1,/* CLR key supported */ 416 sc_xchanmode: 1,/* extended channel mode */ 417 sc_outdoor : 1,/* outdoor operation */ 418 sc_dturbo : 1,/* dynamic turbo in use */ 419 sc_hasbmask : 1,/* bssid mask support */ 420 sc_hasbmatch: 1,/* bssid match disable support*/ 421 sc_hastsfadd: 1,/* tsf adjust support */ 422 sc_beacons : 1,/* beacons running */ 423 sc_swbmiss : 1,/* sta mode using sw bmiss */ 424 sc_stagbeacons:1,/* use staggered beacons */ 425 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 426 sc_resume_up: 1,/* on resume, start all vaps */ 427 sc_tdma : 1,/* TDMA in use */ 428 sc_setcca : 1,/* set/clr CCA with TDMA */ 429 sc_resetcal : 1,/* reset cal state next trip */ 430 sc_rxslink : 1,/* do self-linked final descriptor */ 431 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 432 uint32_t sc_eerd; /* regdomain from EEPROM */ 433 uint32_t sc_eecc; /* country code from EEPROM */ 434 /* rate tables */ 435 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 436 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 437 enum ieee80211_phymode sc_curmode; /* current phy mode */ 438 HAL_OPMODE sc_opmode; /* current operating mode */ 439 u_int16_t sc_curtxpow; /* current tx power limit */ 440 u_int16_t sc_curaid; /* current association id */ 441 struct ieee80211_channel *sc_curchan; /* current installed channel */ 442 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 443 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 444 struct { 445 u_int8_t ieeerate; /* IEEE rate */ 446 u_int8_t rxflags; /* radiotap rx flags */ 447 u_int8_t txflags; /* radiotap tx flags */ 448 u_int16_t ledon; /* softled on time */ 449 u_int16_t ledoff; /* softled off time */ 450 } sc_hwmap[32]; /* h/w rate ix mappings */ 451 u_int8_t sc_protrix; /* protection rate index */ 452 u_int8_t sc_lastdatarix; /* last data frame rate index */ 453 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 454 u_int sc_fftxqmin; /* min frames before staging */ 455 u_int sc_fftxqmax; /* max frames before drop */ 456 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 457 458 HAL_INT sc_imask; /* interrupt mask copy */ 459 460 /* 461 * These are modified in the interrupt handler as well as 462 * the task queues and other contexts. Thus these must be 463 * protected by a mutex, or they could clash. 464 * 465 * For now, access to these is behind the ATH_LOCK, 466 * just to save time. 467 */ 468 uint32_t sc_txq_active; /* bitmap of active TXQs */ 469 uint32_t sc_kickpcu; /* whether to kick the PCU */ 470 uint32_t sc_rxproc_cnt; /* In RX processing */ 471 uint32_t sc_txproc_cnt; /* In TX processing */ 472 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 473 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 474 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 475 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 476 477 u_int sc_keymax; /* size of key cache */ 478 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 479 480 /* 481 * Software based LED blinking 482 */ 483 u_int sc_ledpin; /* GPIO pin for driving LED */ 484 u_int sc_ledon; /* pin setting for LED on */ 485 u_int sc_ledidle; /* idle polling interval */ 486 int sc_ledevent; /* time of last LED event */ 487 u_int8_t sc_txrix; /* current tx rate for LED */ 488 u_int16_t sc_ledoff; /* off time for current blink */ 489 struct callout sc_ledtimer; /* led off timer */ 490 491 /* 492 * Hardware based LED blinking 493 */ 494 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 495 int sc_led_net_pin; /* MAC network LED GPIO pin */ 496 497 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 498 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 499 500 struct ath_descdma sc_rxdma; /* RX descriptors */ 501 ath_bufhead sc_rxbuf; /* receive buffer */ 502 struct mbuf *sc_rxpending; /* pending receive data */ 503 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 504 struct task sc_rxtask; /* rx int processing */ 505 u_int8_t sc_defant; /* current default antenna */ 506 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 507 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 508 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 509 struct ath_rx_radiotap_header sc_rx_th; 510 int sc_rx_th_len; 511 u_int sc_monpass; /* frames to pass in mon.mode */ 512 513 struct ath_descdma sc_txdma; /* TX descriptors */ 514 ath_bufhead sc_txbuf; /* transmit buffer */ 515 int sc_txbuf_cnt; /* how many buffers avail */ 516 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 517 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 518 struct mtx sc_txbuflock; /* txbuf lock */ 519 char sc_txname[12]; /* e.g. "ath0_buf" */ 520 u_int sc_txqsetup; /* h/w queues setup */ 521 u_int sc_txintrperiod;/* tx interrupt batching */ 522 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 523 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 524 struct task sc_txtask; /* tx int processing */ 525 struct task sc_txqtask; /* tx proc processing */ 526 int sc_wd_timer; /* count down for wd timer */ 527 struct callout sc_wd_ch; /* tx watchdog timer */ 528 struct ath_tx_radiotap_header sc_tx_th; 529 int sc_tx_th_len; 530 531 struct ath_descdma sc_bdma; /* beacon descriptors */ 532 ath_bufhead sc_bbuf; /* beacon buffers */ 533 u_int sc_bhalq; /* HAL q for outgoing beacons */ 534 u_int sc_bmisscount; /* missed beacon transmits */ 535 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 536 struct ath_txq *sc_cabq; /* tx q for cab frames */ 537 struct task sc_bmisstask; /* bmiss int processing */ 538 struct task sc_bstucktask; /* stuck beacon processing */ 539 struct task sc_resettask; /* interface reset task */ 540 struct task sc_fataltask; /* fatal task */ 541 enum { 542 OK, /* no change needed */ 543 UPDATE, /* update pending */ 544 COMMIT /* beacon sent, commit change */ 545 } sc_updateslot; /* slot time update fsm */ 546 int sc_slotupdate; /* slot to advance fsm */ 547 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 548 int sc_nbcnvaps; /* # vaps with beacons */ 549 550 struct callout sc_cal_ch; /* callout handle for cals */ 551 int sc_lastlongcal; /* last long cal completed */ 552 int sc_lastcalreset;/* last cal reset done */ 553 int sc_lastani; /* last ANI poll */ 554 int sc_lastshortcal; /* last short calibration */ 555 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 556 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 557 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 558 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 559 u_int sc_tdmaswba; /* TDMA SWBA counter */ 560 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 561 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 562 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 563 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 564 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 565 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 566 int sc_txchainmask; /* currently configured TX chainmask */ 567 int sc_rxchainmask; /* currently configured RX chainmask */ 568 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 569 570 /* Queue limits */ 571 572 /* 573 * To avoid queue starvation in congested conditions, 574 * these parameters tune the maximum number of frames 575 * queued to the data/mcastq before they're dropped. 576 * 577 * This is to prevent: 578 * + a single destination overwhelming everything, including 579 * management/multicast frames; 580 * + multicast frames overwhelming everything (when the 581 * air is sufficiently busy that cabq can't drain.) 582 * 583 * These implement: 584 * + data_minfree is the maximum number of free buffers 585 * overall to successfully allow a data frame. 586 * 587 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 588 */ 589 int sc_txq_data_minfree; 590 int sc_txq_mcastq_maxdepth; 591 592 /* 593 * Aggregation twiddles 594 * 595 * hwq_limit: how busy to keep the hardware queue - don't schedule 596 * further packets to the hardware, regardless of the TID 597 * tid_hwq_lo: how low the per-TID hwq count has to be before the 598 * TID will be scheduled again 599 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 600 * stops being scheduled. 601 */ 602 int sc_hwq_limit; 603 int sc_tid_hwq_lo; 604 int sc_tid_hwq_hi; 605 606 /* DFS related state */ 607 void *sc_dfs; /* Used by an optional DFS module */ 608 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 609 struct task sc_dfstask; /* DFS processing task */ 610 611 /* TX AMPDU handling */ 612 int (*sc_addba_request)(struct ieee80211_node *, 613 struct ieee80211_tx_ampdu *, int, int, int); 614 int (*sc_addba_response)(struct ieee80211_node *, 615 struct ieee80211_tx_ampdu *, int, int, int); 616 void (*sc_addba_stop)(struct ieee80211_node *, 617 struct ieee80211_tx_ampdu *); 618 void (*sc_addba_response_timeout) 619 (struct ieee80211_node *, 620 struct ieee80211_tx_ampdu *); 621 void (*sc_bar_response)(struct ieee80211_node *ni, 622 struct ieee80211_tx_ampdu *tap, 623 int status); 624}; 625 626#define ATH_LOCK_INIT(_sc) \ 627 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 628 NULL, MTX_DEF | MTX_RECURSE) 629#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 630#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 631#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 632#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 633#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 634 635/* 636 * The PCU lock is non-recursive and should be treated as a spinlock. 637 * Although currently the interrupt code is run in netisr context and 638 * doesn't require this, this may change in the future. 639 * Please keep this in mind when protecting certain code paths 640 * with the PCU lock. 641 * 642 * The PCU lock is used to serialise access to the PCU so things such 643 * as TX, RX, state change (eg channel change), channel reset and updates 644 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 645 * 646 * Although the current single-thread taskqueue mechanism protects the 647 * majority of these situations by simply serialising them, there are 648 * a few others which occur at the same time. These include the TX path 649 * (which only acquires ATH_LOCK when recycling buffers to the free list), 650 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 651 */ 652#define ATH_PCU_LOCK_INIT(_sc) do {\ 653 snprintf((_sc)->sc_pcu_mtx_name, \ 654 sizeof((_sc)->sc_pcu_mtx_name), \ 655 "%s PCU lock", \ 656 device_get_nameunit((_sc)->sc_dev)); \ 657 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 658 NULL, MTX_DEF); \ 659 } while (0) 660#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 661#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 662#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 663#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 664 MA_OWNED) 665#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 666 MA_NOTOWNED) 667 668#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 669 670#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 671 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 672 device_get_nameunit((_sc)->sc_dev)); \ 673 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 674} while (0) 675#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 676#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 677#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 678#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 679 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 680 681int ath_attach(u_int16_t, struct ath_softc *); 682int ath_detach(struct ath_softc *); 683void ath_resume(struct ath_softc *); 684void ath_suspend(struct ath_softc *); 685void ath_shutdown(struct ath_softc *); 686void ath_intr(void *); 687 688/* 689 * HAL definitions to comply with local coding convention. 690 */ 691#define ath_hal_detach(_ah) \ 692 ((*(_ah)->ah_detach)((_ah))) 693#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 694 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 695#define ath_hal_macversion(_ah) \ 696 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 697#define ath_hal_getratetable(_ah, _mode) \ 698 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 699#define ath_hal_getmac(_ah, _mac) \ 700 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 701#define ath_hal_setmac(_ah, _mac) \ 702 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 703#define ath_hal_getbssidmask(_ah, _mask) \ 704 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 705#define ath_hal_setbssidmask(_ah, _mask) \ 706 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 707#define ath_hal_intrset(_ah, _mask) \ 708 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 709#define ath_hal_intrget(_ah) \ 710 ((*(_ah)->ah_getInterrupts)((_ah))) 711#define ath_hal_intrpend(_ah) \ 712 ((*(_ah)->ah_isInterruptPending)((_ah))) 713#define ath_hal_getisr(_ah, _pmask) \ 714 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 715#define ath_hal_updatetxtriglevel(_ah, _inc) \ 716 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 717#define ath_hal_setpower(_ah, _mode) \ 718 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 719#define ath_hal_keycachesize(_ah) \ 720 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 721#define ath_hal_keyreset(_ah, _ix) \ 722 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 723#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 724 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 725#define ath_hal_keyisvalid(_ah, _ix) \ 726 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 727#define ath_hal_keysetmac(_ah, _ix, _mac) \ 728 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 729#define ath_hal_getrxfilter(_ah) \ 730 ((*(_ah)->ah_getRxFilter)((_ah))) 731#define ath_hal_setrxfilter(_ah, _filter) \ 732 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 733#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 734 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 735#define ath_hal_waitforbeacon(_ah, _bf) \ 736 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 737#define ath_hal_putrxbuf(_ah, _bufaddr) \ 738 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 739/* NB: common across all chips */ 740#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 741#define ath_hal_gettsf32(_ah) \ 742 OS_REG_READ(_ah, AR_TSF_L32) 743#define ath_hal_gettsf64(_ah) \ 744 ((*(_ah)->ah_getTsf64)((_ah))) 745#define ath_hal_resettsf(_ah) \ 746 ((*(_ah)->ah_resetTsf)((_ah))) 747#define ath_hal_rxena(_ah) \ 748 ((*(_ah)->ah_enableReceive)((_ah))) 749#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 750 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 751#define ath_hal_gettxbuf(_ah, _q) \ 752 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 753#define ath_hal_numtxpending(_ah, _q) \ 754 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 755#define ath_hal_getrxbuf(_ah) \ 756 ((*(_ah)->ah_getRxDP)((_ah))) 757#define ath_hal_txstart(_ah, _q) \ 758 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 759#define ath_hal_setchannel(_ah, _chan) \ 760 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 761#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 762 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 763#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 764 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 765#define ath_hal_calreset(_ah, _chan) \ 766 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 767#define ath_hal_setledstate(_ah, _state) \ 768 ((*(_ah)->ah_setLedState)((_ah), (_state))) 769#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 770 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 771#define ath_hal_beaconreset(_ah) \ 772 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 773#define ath_hal_beaconsettimers(_ah, _bt) \ 774 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 775#define ath_hal_beacontimers(_ah, _bs) \ 776 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 777#define ath_hal_getnexttbtt(_ah) \ 778 ((*(_ah)->ah_getNextTBTT)((_ah))) 779#define ath_hal_setassocid(_ah, _bss, _associd) \ 780 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 781#define ath_hal_phydisable(_ah) \ 782 ((*(_ah)->ah_phyDisable)((_ah))) 783#define ath_hal_setopmode(_ah) \ 784 ((*(_ah)->ah_setPCUConfig)((_ah))) 785#define ath_hal_stoptxdma(_ah, _qnum) \ 786 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 787#define ath_hal_stoppcurecv(_ah) \ 788 ((*(_ah)->ah_stopPcuReceive)((_ah))) 789#define ath_hal_startpcurecv(_ah) \ 790 ((*(_ah)->ah_startPcuReceive)((_ah))) 791#define ath_hal_stopdmarecv(_ah) \ 792 ((*(_ah)->ah_stopDmaReceive)((_ah))) 793#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 794 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 795 (_indata), (_insize), (_outdata), (_outsize))) 796#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 797 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 798#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 799 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 800#define ath_hal_resettxqueue(_ah, _q) \ 801 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 802#define ath_hal_releasetxqueue(_ah, _q) \ 803 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 804#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 805 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 806#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 807 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 808/* NB: common across all chips */ 809#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 810#define ath_hal_txqenabled(_ah, _qnum) \ 811 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 812#define ath_hal_getrfgain(_ah) \ 813 ((*(_ah)->ah_getRfGain)((_ah))) 814#define ath_hal_getdefantenna(_ah) \ 815 ((*(_ah)->ah_getDefAntenna)((_ah))) 816#define ath_hal_setdefantenna(_ah, _ant) \ 817 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 818#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 819 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 820#define ath_hal_ani_poll(_ah, _chan) \ 821 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 822#define ath_hal_mibevent(_ah, _stats) \ 823 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 824#define ath_hal_setslottime(_ah, _us) \ 825 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 826#define ath_hal_getslottime(_ah) \ 827 ((*(_ah)->ah_getSlotTime)((_ah))) 828#define ath_hal_setacktimeout(_ah, _us) \ 829 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 830#define ath_hal_getacktimeout(_ah) \ 831 ((*(_ah)->ah_getAckTimeout)((_ah))) 832#define ath_hal_setctstimeout(_ah, _us) \ 833 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 834#define ath_hal_getctstimeout(_ah) \ 835 ((*(_ah)->ah_getCTSTimeout)((_ah))) 836#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 837 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 838#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 839 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 840#define ath_hal_ciphersupported(_ah, _cipher) \ 841 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 842#define ath_hal_getregdomain(_ah, _prd) \ 843 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 844#define ath_hal_setregdomain(_ah, _rd) \ 845 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 846#define ath_hal_getcountrycode(_ah, _pcc) \ 847 (*(_pcc) = (_ah)->ah_countryCode) 848#define ath_hal_gettkipmic(_ah) \ 849 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 850#define ath_hal_settkipmic(_ah, _v) \ 851 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 852#define ath_hal_hastkipsplit(_ah) \ 853 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 854#define ath_hal_gettkipsplit(_ah) \ 855 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 856#define ath_hal_settkipsplit(_ah, _v) \ 857 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 858#define ath_hal_haswmetkipmic(_ah) \ 859 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 860#define ath_hal_hwphycounters(_ah) \ 861 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 862#define ath_hal_hasdiversity(_ah) \ 863 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 864#define ath_hal_getdiversity(_ah) \ 865 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 866#define ath_hal_setdiversity(_ah, _v) \ 867 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 868#define ath_hal_getantennaswitch(_ah) \ 869 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 870#define ath_hal_setantennaswitch(_ah, _v) \ 871 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 872#define ath_hal_getdiag(_ah, _pv) \ 873 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 874#define ath_hal_setdiag(_ah, _v) \ 875 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 876#define ath_hal_getnumtxqueues(_ah, _pv) \ 877 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 878#define ath_hal_hasveol(_ah) \ 879 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 880#define ath_hal_hastxpowlimit(_ah) \ 881 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 882#define ath_hal_settxpowlimit(_ah, _pow) \ 883 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 884#define ath_hal_gettxpowlimit(_ah, _ppow) \ 885 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 886#define ath_hal_getmaxtxpow(_ah, _ppow) \ 887 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 888#define ath_hal_gettpscale(_ah, _scale) \ 889 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 890#define ath_hal_settpscale(_ah, _v) \ 891 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 892#define ath_hal_hastpc(_ah) \ 893 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 894#define ath_hal_gettpc(_ah) \ 895 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 896#define ath_hal_settpc(_ah, _v) \ 897 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 898#define ath_hal_hasbursting(_ah) \ 899 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 900#define ath_hal_setmcastkeysearch(_ah, _v) \ 901 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 902#define ath_hal_hasmcastkeysearch(_ah) \ 903 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 904#define ath_hal_getmcastkeysearch(_ah) \ 905 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 906#define ath_hal_hasfastframes(_ah) \ 907 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 908#define ath_hal_hasbssidmask(_ah) \ 909 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 910#define ath_hal_hasbssidmatch(_ah) \ 911 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 912#define ath_hal_hastsfadjust(_ah) \ 913 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 914#define ath_hal_gettsfadjust(_ah) \ 915 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 916#define ath_hal_settsfadjust(_ah, _onoff) \ 917 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 918#define ath_hal_hasrfsilent(_ah) \ 919 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 920#define ath_hal_getrfkill(_ah) \ 921 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 922#define ath_hal_setrfkill(_ah, _onoff) \ 923 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 924#define ath_hal_getrfsilent(_ah, _prfsilent) \ 925 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 926#define ath_hal_setrfsilent(_ah, _rfsilent) \ 927 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 928#define ath_hal_gettpack(_ah, _ptpack) \ 929 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 930#define ath_hal_settpack(_ah, _tpack) \ 931 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 932#define ath_hal_gettpcts(_ah, _ptpcts) \ 933 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 934#define ath_hal_settpcts(_ah, _tpcts) \ 935 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 936#define ath_hal_hasintmit(_ah) \ 937 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 938 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 939#define ath_hal_getintmit(_ah) \ 940 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 941 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 942#define ath_hal_setintmit(_ah, _v) \ 943 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 944 HAL_CAP_INTMIT_ENABLE, _v, NULL) 945#define ath_hal_hasedma(_ah) \ 946 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 947 0, NULL) == HAL_OK) 948#define ath_hal_getchannoise(_ah, _c) \ 949 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 950#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 951 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 952#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 953 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 954#define ath_hal_setrxchainmask(_ah, _rx) \ 955 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 956#define ath_hal_settxchainmask(_ah, _tx) \ 957 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 958#define ath_hal_split4ktrans(_ah) \ 959 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 960 0, NULL) == HAL_OK) 961#define ath_hal_self_linked_final_rxdesc(_ah) \ 962 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 963 0, NULL) == HAL_OK) 964#define ath_hal_gtxto_supported(_ah) \ 965 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 966#define ath_hal_has_long_rxdesc_tsf(_ah) \ 967 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 968 0, NULL) == HAL_OK) 969#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 970 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 971#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 972 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 973#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 974 _txr0, _txtr0, _keyix, _ant, _flags, \ 975 _rtsrate, _rtsdura) \ 976 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 977 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 978 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 979#define ath_hal_setupxtxdesc(_ah, _ds, \ 980 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 981 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 982 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 983#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 984 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 985#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 986 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 987#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 988 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 989#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 990 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 991 992#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 993 _txr0, _txtr0, _antm, _rcr, _rcd) \ 994 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 995 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 996#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 997 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 998 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 999 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 1000 (_first), (_last), (_lastaggr))) 1001#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1002 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1003 1004#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1005 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1006 (_series), (_ns), (_flags))) 1007 1008#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1009 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1010#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1011 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1012#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1013 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1014 1015#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1016 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1017#define ath_hal_clr11n_aggr(_ah, _ds) \ 1018 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1019 1020#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1021 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1022#define ath_hal_gpioset(_ah, _gpio, _b) \ 1023 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1024#define ath_hal_gpioget(_ah, _gpio) \ 1025 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1026#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1027 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1028 1029/* 1030 * PCIe suspend/resume/poweron/poweroff related macros 1031 */ 1032#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1033 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1034#define ath_hal_disablepcie(_ah) \ 1035 ((*(_ah)->ah_disablePCIE)((_ah))) 1036 1037/* 1038 * This is badly-named; you need to set the correct parameters 1039 * to begin to receive useful radar events; and even then 1040 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1041 * more information. 1042 */ 1043#define ath_hal_enabledfs(_ah, _param) \ 1044 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1045#define ath_hal_getdfsthresh(_ah, _param) \ 1046 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1047#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1048 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1049 (_buf), (_event))) 1050#define ath_hal_is_fast_clock_enabled(_ah) \ 1051 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1052#define ath_hal_radar_wait(_ah, _chan) \ 1053 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1054#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1055 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1056#define ath_hal_get_chan_ext_busy(_ah) \ 1057 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1058 1059#endif /* _DEV_ATH_ATHVAR_H */ 1060