if_athvar.h revision 237000
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 237000 2012-06-13 06:57:55Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46220033Sadrian/* 47237000Sadrian * There is a separate TX ath_buf pool for management frames. 48237000Sadrian * This ensures that management frames such as probe responses 49237000Sadrian * and BAR frames can be transmitted during periods of high 50237000Sadrian * TX activity. 51237000Sadrian */ 52237000Sadrian#define ATH_MGMT_TXBUF 32 53237000Sadrian 54237000Sadrian/* 55220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 56220033Sadrian */ 57220053Sadrian#ifdef ATH_ENABLE_11N 58235804Sadrian#define ATH_TXBUF 512 59220033Sadrian#define ATH_RXBUF 512 60220033Sadrian#endif 61220033Sadrian 62155481Ssam#ifndef ATH_RXBUF 63116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 64155481Ssam#endif 65155481Ssam#ifndef ATH_TXBUF 66170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 67155481Ssam#endif 68178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 69178354Ssam 70140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74116743Ssam 75225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78147067Ssam 79147057Ssam/* 80147057Ssam * The key cache is used for h/w cipher state and also for 81147057Ssam * tracking station state such as the current tx antenna. 82147057Ssam * We also setup a mapping table between key cache slot indices 83147057Ssam * and station state to short-circuit node lookups on rx. 84147057Ssam * Different parts have different size key caches. We handle 85147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 86147057Ssam */ 87147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 88147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89147057Ssam 90170530Ssamstruct taskqueue; 91170530Ssamstruct kthread; 92170530Ssamstruct ath_buf; 93170530Ssam 94227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95227328Sadrian 96227328Sadrian/* 97227328Sadrian * Per-TID state 98227328Sadrian * 99227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100227328Sadrian */ 101227328Sadrianstruct ath_tid { 102227328Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103227328Sadrian u_int axq_depth; /* SW queue depth */ 104227328Sadrian char axq_name[48]; /* lock name */ 105227328Sadrian struct ath_node *an; /* pointer to parent */ 106227328Sadrian int tid; /* tid */ 107227328Sadrian int ac; /* which AC gets this trafic */ 108227328Sadrian int hwq_depth; /* how many buffers are on HW */ 109227328Sadrian 110227328Sadrian /* 111227328Sadrian * Entry on the ath_txq; when there's traffic 112227328Sadrian * to send 113227328Sadrian */ 114227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 115227328Sadrian int sched; 116227328Sadrian int paused; /* >0 if the TID has been paused */ 117235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 118233908Sadrian int bar_wait; /* waiting for BAR */ 119233908Sadrian int bar_tx; /* BAR TXed */ 120227328Sadrian 121227328Sadrian /* 122227328Sadrian * Is the TID being cleaned up after a transition 123227328Sadrian * from aggregation to non-aggregation? 124227328Sadrian * When this is set to 1, this TID will be paused 125227328Sadrian * and no further traffic will be queued until all 126227328Sadrian * the hardware packets pending for this TID have been 127227328Sadrian * TXed/completed; at which point (non-aggregation) 128227328Sadrian * traffic will resume being TXed. 129227328Sadrian */ 130227328Sadrian int cleanup_inprogress; 131227328Sadrian /* 132227328Sadrian * How many hardware-queued packets are 133227328Sadrian * waiting to be cleaned up. 134227328Sadrian * This is only valid if cleanup_inprogress is 1. 135227328Sadrian */ 136227328Sadrian int incomp; 137227328Sadrian 138227328Sadrian /* 139227328Sadrian * The following implements a ring representing 140227328Sadrian * the frames in the current BAW. 141227328Sadrian * To avoid copying the array content each time 142227328Sadrian * the BAW is moved, the baw_head/baw_tail point 143227328Sadrian * to the current BAW begin/end; when the BAW is 144227328Sadrian * shifted the head/tail of the array are also 145227328Sadrian * appropriately shifted. 146227328Sadrian */ 147227328Sadrian /* active tx buffers, beginning at current BAW */ 148227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149227328Sadrian /* where the baw head is in the array */ 150227328Sadrian int baw_head; 151227328Sadrian /* where the BAW tail is in the array */ 152227328Sadrian int baw_tail; 153227328Sadrian}; 154227328Sadrian 155138570Ssam/* driver-specific node state */ 156116743Ssamstruct ath_node { 157119150Ssam struct ieee80211_node an_node; /* base class */ 158178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 159178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 160170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 163227328Sadrian struct mtx an_mtx; /* protecting the ath_node state */ 164138570Ssam /* variable-length rate control state follows */ 165116743Ssam}; 166138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 167138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168116743Ssam 169138570Ssam#define ATH_RSSI_LPF_LEN 10 170138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 171138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 172138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 174138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 176138570Ssam if ((y) >= -20) \ 177138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178138570Ssam} while (0) 179184358Ssam#define ATH_EP_RND(x,mul) \ 180184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182138570Ssam 183237000Sadriantypedef enum { 184237000Sadrian ATH_BUFTYPE_NORMAL = 0, 185237000Sadrian ATH_BUFTYPE_MGMT = 1, 186237000Sadrian} ath_buf_type_t; 187237000Sadrian 188116743Ssamstruct ath_buf { 189227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 190227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 191116743Ssam int bf_nseg; 192186904Ssam uint16_t bf_flags; /* status flags (below) */ 193116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 194165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 195116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 196138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 197116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 198116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 199227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 200227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 201116743Ssam bus_size_t bf_mapsize; 202140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 203116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 204227328Sadrian 205227328Sadrian /* Completion function to call on TX complete (fail or not) */ 206227328Sadrian /* 207227328Sadrian * "fail" here is set to 1 if the queue entries were removed 208227328Sadrian * through a call to ath_tx_draintxq(). 209227328Sadrian */ 210227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 211227328Sadrian 212227328Sadrian /* This state is kept to support software retries and aggregation */ 213227328Sadrian struct { 214227328Sadrian int bfs_seqno; /* sequence number of this packet */ 215227328Sadrian int bfs_retries; /* retry count */ 216227328Sadrian uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 217227328Sadrian uint16_t bfs_pri; /* packet AC priority */ 218227328Sadrian struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 219227328Sadrian uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 220227328Sadrian uint16_t bfs_nframes; /* number of frames in aggregate */ 221227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 222227328Sadrian 223234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 224234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 225234109Sadrian bfs_isretried:1, /* retried frame? */ 226234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 227234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 228234109Sadrian bfs_shpream:1, /* use short preamble */ 229234109Sadrian bfs_istxfrag:1, /* is fragmented */ 230234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 231234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 232236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 233234109Sadrian 234227328Sadrian int bfs_nfl; /* next fragment length */ 235227328Sadrian 236227328Sadrian /* 237227328Sadrian * These fields are passed into the 238227328Sadrian * descriptor setup functions. 239227328Sadrian */ 240227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 241227328Sadrian int bfs_pktlen; /* length of this packet */ 242227328Sadrian int bfs_hdrlen; /* length of this packet header */ 243227328Sadrian uint16_t bfs_al; /* length of aggregate */ 244233966Sadrian int bfs_txflags; /* HAL (tx) descriptor flags */ 245227328Sadrian int bfs_txrate0; /* first TX rate */ 246227328Sadrian int bfs_try0; /* first try count */ 247227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 248227328Sadrian int bfs_keyix; /* crypto key index */ 249227328Sadrian int bfs_txpower; /* tx power */ 250227328Sadrian int bfs_txantenna; /* TX antenna config */ 251227328Sadrian enum ieee80211_protmode bfs_protmode; 252227328Sadrian int bfs_ctsrate; /* CTS rate */ 253227328Sadrian int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 254227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 255227328Sadrian } bf_state; 256116743Ssam}; 257227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 258116743Ssam 259237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 260186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 261186904Ssam 262138570Ssam/* 263138570Ssam * DMA state for tx/rx descriptors. 264138570Ssam */ 265138570Ssamstruct ath_descdma { 266138570Ssam const char* dd_name; 267138570Ssam struct ath_desc *dd_desc; /* descriptors */ 268138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 269158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 270138570Ssam bus_dma_segment_t dd_dseg; 271138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 272138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 273138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 274138570Ssam}; 275138570Ssam 276138570Ssam/* 277138570Ssam * Data transmit queue state. One of these exists for each 278138570Ssam * hardware transmit queue. Packets sent to us from above 279138570Ssam * are assigned to queues based on their priority. Not all 280138570Ssam * devices support a complete set of hardware transmit queues. 281138570Ssam * For those devices the array sc_ac2q will map multiple 282138570Ssam * priorities to fewer hardware queues (typically all to one 283138570Ssam * hardware queue). 284138570Ssam */ 285138570Ssamstruct ath_txq { 286227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 287138570Ssam u_int axq_qnum; /* hardware q number */ 288178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 289190579Ssam u_int axq_ac; /* WME AC */ 290186904Ssam u_int axq_flags; 291186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 292156073Ssam u_int axq_depth; /* queue depth (stat only) */ 293227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 294138570Ssam u_int axq_intrcnt; /* interrupt count */ 295138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 296227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 297138570Ssam struct mtx axq_lock; /* lock on q and link */ 298155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 299227344Sadrian 300227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 301227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 302138570Ssam}; 303138570Ssam 304227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 305227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 306227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 307227328Sadrian 308155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 309155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 310155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 311167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 312161425Simp} while (0) 313138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 314138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 315138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 316138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 317227328Sadrian#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 318138570Ssam 319236873Sadrian#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 320236873Sadrian ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 321236873Sadrian 322227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 323227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 324227344Sadrian (_tq)->axq_depth++; \ 325227344Sadrian} while (0) 326138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 327227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 328138570Ssam (_tq)->axq_depth++; \ 329138570Ssam} while (0) 330227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 331227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 332138570Ssam (_tq)->axq_depth--; \ 333138570Ssam} while (0) 334227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 335138570Ssam 336178354Ssamstruct ath_vap { 337178354Ssam struct ieee80211vap av_vap; /* base class */ 338178354Ssam int av_bslot; /* beacon slot index */ 339178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 340178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 341178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 342178354Ssam 343178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 344192468Ssam struct mbuf *, int, int, int); 345178354Ssam int (*av_newstate)(struct ieee80211vap *, 346178354Ssam enum ieee80211_state, int); 347178354Ssam void (*av_bmiss)(struct ieee80211vap *); 348178354Ssam}; 349178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 350178354Ssam 351155491Ssamstruct taskqueue; 352155486Ssamstruct ath_tx99; 353155486Ssam 354227328Sadrian/* 355227328Sadrian * Whether to reset the TX/RX queue with or without 356227328Sadrian * a queue flush. 357227328Sadrian */ 358227328Sadriantypedef enum { 359227328Sadrian ATH_RESET_DEFAULT = 0, 360227328Sadrian ATH_RESET_NOLOSS = 1, 361227328Sadrian ATH_RESET_FULL = 2, 362227328Sadrian} ATH_RESET_TYPE; 363227328Sadrian 364116743Ssamstruct ath_softc { 365147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 366138570Ssam struct ath_stats sc_stats; /* interface statistics */ 367227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 368234090Sadrian struct ath_intr_stats sc_intr_stats; 369235491Sadrian uint64_t sc_debug; 370178354Ssam int sc_nvaps; /* # vaps */ 371178354Ssam int sc_nstavaps; /* # station vaps */ 372195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 373178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 374178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 375178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 376178354Ssam 377227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 378138570Ssam void (*sc_node_free)(struct ieee80211_node *); 379116743Ssam device_t sc_dev; 380159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 381159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 382116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 383116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 384227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 385227328Sadrian char sc_pcu_mtx_name[32]; 386155491Ssam struct taskqueue *sc_tq; /* private task queue */ 387116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 388138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 389155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 390138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 391178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 392178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 393178354Ssam sc_softled : 1,/* enable LED gpio status */ 394228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 395178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 396178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 397178354Ssam sc_diversity: 1,/* enable rx diversity */ 398178354Ssam sc_hasveol : 1,/* tx VEOL support */ 399178354Ssam sc_ledstate : 1,/* LED on/off state */ 400178354Ssam sc_blinking : 1,/* LED blink operation active */ 401178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 402178354Ssam sc_scanning : 1,/* scanning active */ 403155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 404178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 405165571Ssam sc_xchanmode: 1,/* extended channel mode */ 406170530Ssam sc_outdoor : 1,/* outdoor operation */ 407178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 408178354Ssam sc_hasbmask : 1,/* bssid mask support */ 409195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 410178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 411178354Ssam sc_beacons : 1,/* beacons running */ 412178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 413178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 414179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 415185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 416186904Ssam sc_tdma : 1,/* TDMA in use */ 417189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 418220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 419224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 420225444Sadrian sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 421178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 422178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 423116743Ssam /* rate tables */ 424188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 425116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 426116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 427155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 428138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 429170530Ssam u_int16_t sc_curaid; /* current association id */ 430187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 431170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 432116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 433140432Ssam struct { 434140432Ssam u_int8_t ieeerate; /* IEEE rate */ 435140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 436140761Ssam u_int8_t txflags; /* radiotap tx flags */ 437140432Ssam u_int16_t ledon; /* softled on time */ 438140432Ssam u_int16_t ledoff; /* softled off time */ 439140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 440138570Ssam u_int8_t sc_protrix; /* protection rate index */ 441170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 442155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 443170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 444170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 445138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 446227346Sadrian 447116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 448227651Sadrian 449227346Sadrian /* 450227346Sadrian * These are modified in the interrupt handler as well as 451227346Sadrian * the task queues and other contexts. Thus these must be 452227346Sadrian * protected by a mutex, or they could clash. 453227346Sadrian * 454227346Sadrian * For now, access to these is behind the ATH_LOCK, 455227346Sadrian * just to save time. 456227346Sadrian */ 457227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 458227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 459227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 460227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 461227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 462227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 463227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 464227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 465227346Sadrian 466138570Ssam u_int sc_keymax; /* size of key cache */ 467147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 468116743Ssam 469228891Sadrian /* 470228891Sadrian * Software based LED blinking 471228891Sadrian */ 472140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 473140432Ssam u_int sc_ledon; /* pin setting for LED on */ 474140432Ssam u_int sc_ledidle; /* idle polling interval */ 475140432Ssam int sc_ledevent; /* time of last LED event */ 476184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 477140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 478140432Ssam struct callout sc_ledtimer; /* led off timer */ 479138570Ssam 480228891Sadrian /* 481228891Sadrian * Hardware based LED blinking 482228891Sadrian */ 483228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 484228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 485228891Sadrian 486155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 487155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 488155515Ssam 489178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 490138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 491170530Ssam struct mbuf *sc_rxpending; /* pending receive data */ 492116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 493116743Ssam struct task sc_rxtask; /* rx int processing */ 494138570Ssam u_int8_t sc_defant; /* current default antenna */ 495138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 496155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 497192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 498192468Ssam struct ath_rx_radiotap_header sc_rx_th; 499192468Ssam int sc_rx_th_len; 500192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 501116743Ssam 502138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 503138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 504237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 505237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 506138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 507155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 508138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 509138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 510138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 511138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 512116743Ssam struct task sc_txtask; /* tx int processing */ 513233673Sadrian struct task sc_txqtask; /* tx proc processing */ 514189605Ssam int sc_wd_timer; /* count down for wd timer */ 515189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 516192468Ssam struct ath_tx_radiotap_header sc_tx_th; 517192468Ssam int sc_tx_th_len; 518116743Ssam 519138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 520138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 521116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 522138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 523138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 524138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 525116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 526138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 527232163Sadrian struct task sc_resettask; /* interface reset task */ 528234369Sadrian struct task sc_fataltask; /* fatal task */ 529138570Ssam enum { 530138570Ssam OK, /* no change needed */ 531138570Ssam UPDATE, /* update pending */ 532138570Ssam COMMIT /* beacon sent, commit change */ 533138570Ssam } sc_updateslot; /* slot time update fsm */ 534178354Ssam int sc_slotupdate; /* slot to advance fsm */ 535178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 536178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 537116743Ssam 538116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 539185744Ssam int sc_lastlongcal; /* last long cal completed */ 540185744Ssam int sc_lastcalreset;/* last cal reset done */ 541217684Sadrian int sc_lastani; /* last ANI poll */ 542217684Sadrian int sc_lastshortcal; /* last short calibration */ 543217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 544155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 545186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 546186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 547186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 548186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 549186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 550186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 551186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 552186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 553217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 554218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 555218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 556233967Sadrian int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 557222585Sadrian 558232764Sadrian /* Queue limits */ 559232764Sadrian 560227328Sadrian /* 561232764Sadrian * To avoid queue starvation in congested conditions, 562232764Sadrian * these parameters tune the maximum number of frames 563232764Sadrian * queued to the data/mcastq before they're dropped. 564232764Sadrian * 565232764Sadrian * This is to prevent: 566232764Sadrian * + a single destination overwhelming everything, including 567232764Sadrian * management/multicast frames; 568232764Sadrian * + multicast frames overwhelming everything (when the 569232764Sadrian * air is sufficiently busy that cabq can't drain.) 570232764Sadrian * 571232764Sadrian * These implement: 572232764Sadrian * + data_minfree is the maximum number of free buffers 573232764Sadrian * overall to successfully allow a data frame. 574232764Sadrian * 575232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 576232764Sadrian */ 577232764Sadrian int sc_txq_data_minfree; 578232764Sadrian int sc_txq_mcastq_maxdepth; 579232764Sadrian 580232764Sadrian /* 581227328Sadrian * Aggregation twiddles 582227328Sadrian * 583227328Sadrian * hwq_limit: how busy to keep the hardware queue - don't schedule 584227328Sadrian * further packets to the hardware, regardless of the TID 585227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 586227328Sadrian * TID will be scheduled again 587227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 588227328Sadrian * stops being scheduled. 589227328Sadrian */ 590227328Sadrian int sc_hwq_limit; 591227328Sadrian int sc_tid_hwq_lo; 592227328Sadrian int sc_tid_hwq_hi; 593227328Sadrian 594222585Sadrian /* DFS related state */ 595222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 596222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 597222585Sadrian struct task sc_dfstask; /* DFS processing task */ 598227328Sadrian 599227328Sadrian /* TX AMPDU handling */ 600227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 601227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 602227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 603227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 604227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 605227328Sadrian struct ieee80211_tx_ampdu *); 606227328Sadrian void (*sc_addba_response_timeout) 607227328Sadrian (struct ieee80211_node *, 608227328Sadrian struct ieee80211_tx_ampdu *); 609227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 610227328Sadrian struct ieee80211_tx_ampdu *tap, 611227328Sadrian int status); 612116743Ssam}; 613116743Ssam 614121100Ssam#define ATH_LOCK_INIT(_sc) \ 615121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 616167252Ssam NULL, MTX_DEF | MTX_RECURSE) 617121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 618121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 619121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 620121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 621227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 622121100Ssam 623227328Sadrian/* 624227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 625227328Sadrian * Although currently the interrupt code is run in netisr context and 626227328Sadrian * doesn't require this, this may change in the future. 627227328Sadrian * Please keep this in mind when protecting certain code paths 628227328Sadrian * with the PCU lock. 629227328Sadrian * 630227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 631227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 632227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 633227328Sadrian * 634227328Sadrian * Although the current single-thread taskqueue mechanism protects the 635227328Sadrian * majority of these situations by simply serialising them, there are 636227328Sadrian * a few others which occur at the same time. These include the TX path 637227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 638227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 639227328Sadrian */ 640227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 641227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 642227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 643227328Sadrian "%s PCU lock", \ 644227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 645227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 646227328Sadrian NULL, MTX_DEF); \ 647227328Sadrian } while (0) 648227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 649227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 650227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 651227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 652227328Sadrian MA_OWNED) 653227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 654227651Sadrian MA_NOTOWNED) 655227328Sadrian 656138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 657138570Ssam 658155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 659155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 660155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 661167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 662155482Ssam} while (0) 663121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 664121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 665121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 666121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 667121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 668121100Ssam 669116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 670116743Ssamint ath_detach(struct ath_softc *); 671116743Ssamvoid ath_resume(struct ath_softc *); 672116743Ssamvoid ath_suspend(struct ath_softc *); 673116743Ssamvoid ath_shutdown(struct ath_softc *); 674116743Ssamvoid ath_intr(void *); 675116743Ssam 676116743Ssam/* 677116743Ssam * HAL definitions to comply with local coding convention. 678116743Ssam */ 679138570Ssam#define ath_hal_detach(_ah) \ 680138570Ssam ((*(_ah)->ah_detach)((_ah))) 681116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 682116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 683186904Ssam#define ath_hal_macversion(_ah) \ 684186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 685116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 686116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 687116743Ssam#define ath_hal_getmac(_ah, _mac) \ 688116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 689138570Ssam#define ath_hal_setmac(_ah, _mac) \ 690138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 691178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 692178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 693178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 694178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 695116743Ssam#define ath_hal_intrset(_ah, _mask) \ 696116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 697116743Ssam#define ath_hal_intrget(_ah) \ 698116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 699116743Ssam#define ath_hal_intrpend(_ah) \ 700116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 701116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 702116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 703116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 704116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 705155515Ssam#define ath_hal_setpower(_ah, _mode) \ 706155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 707138570Ssam#define ath_hal_keycachesize(_ah) \ 708138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 709116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 710116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 711138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 712138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 713116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 714116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 715116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 716116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 717116743Ssam#define ath_hal_getrxfilter(_ah) \ 718116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 719116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 720116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 721116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 722116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 723116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 724116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 725116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 726116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 727186904Ssam/* NB: common across all chips */ 728186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 729116743Ssam#define ath_hal_gettsf32(_ah) \ 730186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 731116743Ssam#define ath_hal_gettsf64(_ah) \ 732116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 733116743Ssam#define ath_hal_resettsf(_ah) \ 734116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 735116743Ssam#define ath_hal_rxena(_ah) \ 736116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 737116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 738116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 739116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 740116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 741138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 742138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 743116743Ssam#define ath_hal_getrxbuf(_ah) \ 744116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 745116743Ssam#define ath_hal_txstart(_ah, _q) \ 746116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 747116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 748116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 749155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 750155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 751185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 752185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 753185744Ssam#define ath_hal_calreset(_ah, _chan) \ 754185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 755116743Ssam#define ath_hal_setledstate(_ah, _state) \ 756116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 757138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 758138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 759116743Ssam#define ath_hal_beaconreset(_ah) \ 760116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 761186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 762186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 763138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 764138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 765225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 766225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 767116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 768138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 769138570Ssam#define ath_hal_phydisable(_ah) \ 770138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 771138570Ssam#define ath_hal_setopmode(_ah) \ 772138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 773116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 774116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 775116743Ssam#define ath_hal_stoppcurecv(_ah) \ 776116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 777116743Ssam#define ath_hal_startpcurecv(_ah) \ 778116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 779116743Ssam#define ath_hal_stopdmarecv(_ah) \ 780116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 781138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 782138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 783138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 784155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 785170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 786116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 787116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 788116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 789116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 790116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 791116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 792138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 793138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 794138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 795138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 796186904Ssam/* NB: common across all chips */ 797186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 798186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 799186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 800116743Ssam#define ath_hal_getrfgain(_ah) \ 801116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 802138570Ssam#define ath_hal_getdefantenna(_ah) \ 803138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 804138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 805138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 806155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 807155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 808217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 809217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 810138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 811138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 812138570Ssam#define ath_hal_setslottime(_ah, _us) \ 813138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 814138570Ssam#define ath_hal_getslottime(_ah) \ 815138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 816138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 817138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 818138570Ssam#define ath_hal_getacktimeout(_ah) \ 819138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 820138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 821138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 822138570Ssam#define ath_hal_getctstimeout(_ah) \ 823138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 824138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 825138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 826138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 827138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 828138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 829138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 830138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 831155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 832155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 833184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 834138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 835138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 836178354Ssam#define ath_hal_gettkipmic(_ah) \ 837178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 838178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 839178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 840162410Ssam#define ath_hal_hastkipsplit(_ah) \ 841138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 842162410Ssam#define ath_hal_gettkipsplit(_ah) \ 843162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 844162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 845162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 846178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 847178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 848138570Ssam#define ath_hal_hwphycounters(_ah) \ 849138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 850138570Ssam#define ath_hal_hasdiversity(_ah) \ 851138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 852138570Ssam#define ath_hal_getdiversity(_ah) \ 853138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 854138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 855138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 856166954Ssam#define ath_hal_getantennaswitch(_ah) \ 857166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 858166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 859166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 860138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 861138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 862138570Ssam#define ath_hal_setdiag(_ah, _v) \ 863138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 864138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 865138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 866138570Ssam#define ath_hal_hasveol(_ah) \ 867138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 868138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 869138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 870138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 871138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 872138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 873138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 874138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 875138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 876138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 877138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 878138570Ssam#define ath_hal_settpscale(_ah, _v) \ 879138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 880138570Ssam#define ath_hal_hastpc(_ah) \ 881138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 882138570Ssam#define ath_hal_gettpc(_ah) \ 883138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 884138570Ssam#define ath_hal_settpc(_ah, _v) \ 885138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 886138570Ssam#define ath_hal_hasbursting(_ah) \ 887138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 888203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 889203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 890147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 891147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 892147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 893147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 894170530Ssam#define ath_hal_hasfastframes(_ah) \ 895170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 896178354Ssam#define ath_hal_hasbssidmask(_ah) \ 897178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 898195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 899195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 900178354Ssam#define ath_hal_hastsfadjust(_ah) \ 901178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 902178354Ssam#define ath_hal_gettsfadjust(_ah) \ 903178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 904178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 905178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 906155515Ssam#define ath_hal_hasrfsilent(_ah) \ 907155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 908155515Ssam#define ath_hal_getrfkill(_ah) \ 909155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 910155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 911155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 912155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 913155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 914155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 915155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 916155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 917155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 918155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 919155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 920155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 921155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 922155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 923155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 924184354Ssam#define ath_hal_hasintmit(_ah) \ 925230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 926230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 927184354Ssam#define ath_hal_getintmit(_ah) \ 928230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 929230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 930184354Ssam#define ath_hal_setintmit(_ah, _v) \ 931230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 932230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 933154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 934154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 935218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 936218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 937218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 938218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 939231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 940231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 941231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 942231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 943218490Sadrian#define ath_hal_split4ktrans(_ah) \ 944230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 945230493Sadrian 0, NULL) == HAL_OK) 946220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 947230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 948230493Sadrian 0, NULL) == HAL_OK) 949220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 950220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 951225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 952230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 953230493Sadrian 0, NULL) == HAL_OK) 954116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 955116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 956165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 957165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 958116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 959116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 960116743Ssam _rtsrate, _rtsdura) \ 961116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 962116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 963155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 964138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 965116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 966138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 967116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 968138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 969138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 970165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 971165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 972155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 973155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 974217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 975217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 976116743Ssam 977218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 978218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 979218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 980218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 981227328Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 982233895Sadrian _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 983227328Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 984227328Sadrian (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 985233895Sadrian (_first), (_last), (_lastaggr))) 986218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 987218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 988227328Sadrian 989218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 990218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 991218067Sadrian (_series), (_ns), (_flags))) 992227328Sadrian 993227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 994227328Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 995218066Sadrian#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 996227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 997227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 998227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 999227328Sadrian 1000218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1001218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1002227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1003227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1004218066Sadrian 1005230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1006230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1007230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1008230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1009230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1010230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1011230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1012230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1013230493Sadrian 1014222585Sadrian/* 1015235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1016235957Sadrian */ 1017235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1018235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1019235957Sadrian#define ath_hal_disablepcie(_ah) \ 1020235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1021235957Sadrian 1022235957Sadrian/* 1023222585Sadrian * This is badly-named; you need to set the correct parameters 1024222585Sadrian * to begin to receive useful radar events; and even then 1025222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1026222585Sadrian * more information. 1027222585Sadrian */ 1028222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1029222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1030222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1031222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1032222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1033230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1034230493Sadrian (_buf), (_event))) 1035224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1036224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1037230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1038155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1039234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1040234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1041230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1042230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1043155515Ssam 1044116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1045