if_athvar.h revision 224720
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 224720 2011-08-08 19:03:26Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49#ifdef ATH_ENABLE_11N 50#define ATH_TXBUF 512 51#define ATH_RXBUF 512 52#endif 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 200 /* number of TX buffers */ 59#endif 60#define ATH_BCBUF 4 /* number of beacon buffers */ 61 62#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 68#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71/* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79#define ATH_KEYMAX 128 /* max key cache size we handle */ 80#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82struct taskqueue; 83struct kthread; 84struct ath_buf; 85 86/* driver-specific node state */ 87struct ath_node { 88 struct ieee80211_node an_node; /* base class */ 89 u_int8_t an_mgmtrix; /* min h/w rate index */ 90 u_int8_t an_mcastrix; /* mcast h/w rate index */ 91 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 92 /* variable-length rate control state follows */ 93}; 94#define ATH_NODE(ni) ((struct ath_node *)(ni)) 95#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 96 97#define ATH_RSSI_LPF_LEN 10 98#define ATH_RSSI_DUMMY_MARKER 0x127 99#define ATH_EP_MUL(x, mul) ((x) * (mul)) 100#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 101#define ATH_LPF_RSSI(x, y, len) \ 102 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 103#define ATH_RSSI_LPF(x, y) do { \ 104 if ((y) >= -20) \ 105 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 106} while (0) 107#define ATH_EP_RND(x,mul) \ 108 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 109#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 110 111struct ath_buf { 112 STAILQ_ENTRY(ath_buf) bf_list; 113 int bf_nseg; 114 uint16_t bf_txflags; /* tx descriptor flags */ 115 uint16_t bf_flags; /* status flags (below) */ 116 struct ath_desc *bf_desc; /* virtual addr of desc */ 117 struct ath_desc_status bf_status; /* tx/rx status */ 118 bus_addr_t bf_daddr; /* physical addr of desc */ 119 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 120 struct mbuf *bf_m; /* mbuf for buf */ 121 struct ieee80211_node *bf_node; /* pointer to the node */ 122 bus_size_t bf_mapsize; 123#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 124 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 125}; 126typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 127 128#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 129 130/* 131 * DMA state for tx/rx descriptors. 132 */ 133struct ath_descdma { 134 const char* dd_name; 135 struct ath_desc *dd_desc; /* descriptors */ 136 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 137 bus_size_t dd_desc_len; /* size of dd_desc */ 138 bus_dma_segment_t dd_dseg; 139 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 140 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 141 struct ath_buf *dd_bufptr; /* associated buffers */ 142}; 143 144/* 145 * Data transmit queue state. One of these exists for each 146 * hardware transmit queue. Packets sent to us from above 147 * are assigned to queues based on their priority. Not all 148 * devices support a complete set of hardware transmit queues. 149 * For those devices the array sc_ac2q will map multiple 150 * priorities to fewer hardware queues (typically all to one 151 * hardware queue). 152 */ 153struct ath_txq { 154 u_int axq_qnum; /* hardware q number */ 155#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 156 u_int axq_ac; /* WME AC */ 157 u_int axq_flags; 158#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 159 u_int axq_depth; /* queue depth (stat only) */ 160 u_int axq_intrcnt; /* interrupt count */ 161 u_int32_t *axq_link; /* link ptr in last TX desc */ 162 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 163 struct mtx axq_lock; /* lock on q and link */ 164 char axq_name[12]; /* e.g. "ath0_txq4" */ 165}; 166 167#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 168 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 169 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 170 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 171} while (0) 172#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 173#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 174#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 175#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 176 177#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 178 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 179 (_tq)->axq_depth++; \ 180} while (0) 181#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 182 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 183 (_tq)->axq_depth--; \ 184} while (0) 185/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 186#define ATH_TXQ_LAST(_tq) \ 187 ((struct ath_buf *)(void *) \ 188 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 189 190struct ath_vap { 191 struct ieee80211vap av_vap; /* base class */ 192 int av_bslot; /* beacon slot index */ 193 struct ath_buf *av_bcbuf; /* beacon buffer */ 194 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 195 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 196 197 void (*av_recv_mgmt)(struct ieee80211_node *, 198 struct mbuf *, int, int, int); 199 int (*av_newstate)(struct ieee80211vap *, 200 enum ieee80211_state, int); 201 void (*av_bmiss)(struct ieee80211vap *); 202}; 203#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 204 205struct taskqueue; 206struct ath_tx99; 207 208struct ath_softc { 209 struct ifnet *sc_ifp; /* interface common */ 210 struct ath_stats sc_stats; /* interface statistics */ 211 int sc_debug; 212 int sc_nvaps; /* # vaps */ 213 int sc_nstavaps; /* # station vaps */ 214 int sc_nmeshvaps; /* # mbss vaps */ 215 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 216 u_int8_t sc_nbssid0; /* # vap's using base mac */ 217 uint32_t sc_bssidmask; /* bssid mask */ 218 219 void (*sc_node_free)(struct ieee80211_node *); 220 device_t sc_dev; 221 HAL_BUS_TAG sc_st; /* bus space tag */ 222 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 223 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 224 struct mtx sc_mtx; /* master lock (recursive) */ 225 struct taskqueue *sc_tq; /* private task queue */ 226 struct ath_hal *sc_ah; /* Atheros HAL */ 227 struct ath_ratectrl *sc_rc; /* tx rate control support */ 228 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 229 void (*sc_setdefantenna)(struct ath_softc *, u_int); 230 unsigned int sc_invalid : 1,/* disable hardware accesses */ 231 sc_mrretry : 1,/* multi-rate retry support */ 232 sc_softled : 1,/* enable LED gpio status */ 233 sc_splitmic : 1,/* split TKIP MIC keys */ 234 sc_needmib : 1,/* enable MIB stats intr */ 235 sc_diversity: 1,/* enable rx diversity */ 236 sc_hasveol : 1,/* tx VEOL support */ 237 sc_ledstate : 1,/* LED on/off state */ 238 sc_blinking : 1,/* LED blink operation active */ 239 sc_mcastkey : 1,/* mcast key cache search */ 240 sc_scanning : 1,/* scanning active */ 241 sc_syncbeacon:1,/* sync/resync beacon timers */ 242 sc_hasclrkey: 1,/* CLR key supported */ 243 sc_xchanmode: 1,/* extended channel mode */ 244 sc_outdoor : 1,/* outdoor operation */ 245 sc_dturbo : 1,/* dynamic turbo in use */ 246 sc_hasbmask : 1,/* bssid mask support */ 247 sc_hasbmatch: 1,/* bssid match disable support*/ 248 sc_hastsfadd: 1,/* tsf adjust support */ 249 sc_beacons : 1,/* beacons running */ 250 sc_swbmiss : 1,/* sta mode using sw bmiss */ 251 sc_stagbeacons:1,/* use staggered beacons */ 252 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 253 sc_resume_up: 1,/* on resume, start all vaps */ 254 sc_tdma : 1,/* TDMA in use */ 255 sc_setcca : 1,/* set/clr CCA with TDMA */ 256 sc_resetcal : 1,/* reset cal state next trip */ 257 sc_rxslink : 1,/* do self-linked final descriptor */ 258 sc_kickpcu : 1;/* kick PCU RX on next RX proc */ 259 uint32_t sc_eerd; /* regdomain from EEPROM */ 260 uint32_t sc_eecc; /* country code from EEPROM */ 261 /* rate tables */ 262 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 263 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 264 enum ieee80211_phymode sc_curmode; /* current phy mode */ 265 HAL_OPMODE sc_opmode; /* current operating mode */ 266 u_int16_t sc_curtxpow; /* current tx power limit */ 267 u_int16_t sc_curaid; /* current association id */ 268 struct ieee80211_channel *sc_curchan; /* current installed channel */ 269 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 270 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 271 struct { 272 u_int8_t ieeerate; /* IEEE rate */ 273 u_int8_t rxflags; /* radiotap rx flags */ 274 u_int8_t txflags; /* radiotap tx flags */ 275 u_int16_t ledon; /* softled on time */ 276 u_int16_t ledoff; /* softled off time */ 277 } sc_hwmap[32]; /* h/w rate ix mappings */ 278 u_int8_t sc_protrix; /* protection rate index */ 279 u_int8_t sc_lastdatarix; /* last data frame rate index */ 280 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 281 u_int sc_fftxqmin; /* min frames before staging */ 282 u_int sc_fftxqmax; /* max frames before drop */ 283 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 284 HAL_INT sc_imask; /* interrupt mask copy */ 285 u_int sc_keymax; /* size of key cache */ 286 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 287 288 u_int sc_ledpin; /* GPIO pin for driving LED */ 289 u_int sc_ledon; /* pin setting for LED on */ 290 u_int sc_ledidle; /* idle polling interval */ 291 int sc_ledevent; /* time of last LED event */ 292 u_int8_t sc_txrix; /* current tx rate for LED */ 293 u_int16_t sc_ledoff; /* off time for current blink */ 294 struct callout sc_ledtimer; /* led off timer */ 295 296 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 297 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 298 299 struct ath_descdma sc_rxdma; /* RX descriptors */ 300 ath_bufhead sc_rxbuf; /* receive buffer */ 301 struct mbuf *sc_rxpending; /* pending receive data */ 302 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 303 struct task sc_rxtask; /* rx int processing */ 304 u_int8_t sc_defant; /* current default antenna */ 305 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 306 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 307 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 308 struct ath_rx_radiotap_header sc_rx_th; 309 int sc_rx_th_len; 310 u_int sc_monpass; /* frames to pass in mon.mode */ 311 312 struct ath_descdma sc_txdma; /* TX descriptors */ 313 ath_bufhead sc_txbuf; /* transmit buffer */ 314 struct mtx sc_txbuflock; /* txbuf lock */ 315 char sc_txname[12]; /* e.g. "ath0_buf" */ 316 u_int sc_txqsetup; /* h/w queues setup */ 317 u_int sc_txintrperiod;/* tx interrupt batching */ 318 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 319 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 320 struct task sc_txtask; /* tx int processing */ 321 int sc_wd_timer; /* count down for wd timer */ 322 struct callout sc_wd_ch; /* tx watchdog timer */ 323 struct ath_tx_radiotap_header sc_tx_th; 324 int sc_tx_th_len; 325 326 struct ath_descdma sc_bdma; /* beacon descriptors */ 327 ath_bufhead sc_bbuf; /* beacon buffers */ 328 u_int sc_bhalq; /* HAL q for outgoing beacons */ 329 u_int sc_bmisscount; /* missed beacon transmits */ 330 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 331 struct ath_txq *sc_cabq; /* tx q for cab frames */ 332 struct task sc_bmisstask; /* bmiss int processing */ 333 struct task sc_bstucktask; /* stuck beacon processing */ 334 enum { 335 OK, /* no change needed */ 336 UPDATE, /* update pending */ 337 COMMIT /* beacon sent, commit change */ 338 } sc_updateslot; /* slot time update fsm */ 339 int sc_slotupdate; /* slot to advance fsm */ 340 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 341 int sc_nbcnvaps; /* # vaps with beacons */ 342 343 struct callout sc_cal_ch; /* callout handle for cals */ 344 int sc_lastlongcal; /* last long cal completed */ 345 int sc_lastcalreset;/* last cal reset done */ 346 int sc_lastani; /* last ANI poll */ 347 int sc_lastshortcal; /* last short calibration */ 348 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 349 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 350 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 351 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 352 u_int sc_tdmaswba; /* TDMA SWBA counter */ 353 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 354 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 355 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 356 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 357 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 358 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 359 int sc_txchainmask; /* currently configured TX chainmask */ 360 int sc_rxchainmask; /* currently configured RX chainmask */ 361 362 /* DFS related state */ 363 void *sc_dfs; /* Used by an optional DFS module */ 364 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 365 struct task sc_dfstask; /* DFS processing task */ 366}; 367 368#define ATH_LOCK_INIT(_sc) \ 369 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 370 NULL, MTX_DEF | MTX_RECURSE) 371#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 372#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 373#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 374#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 375 376#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 377 378#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 379 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 380 device_get_nameunit((_sc)->sc_dev)); \ 381 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 382} while (0) 383#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 384#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 385#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 386#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 387 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 388 389int ath_attach(u_int16_t, struct ath_softc *); 390int ath_detach(struct ath_softc *); 391void ath_resume(struct ath_softc *); 392void ath_suspend(struct ath_softc *); 393void ath_shutdown(struct ath_softc *); 394void ath_intr(void *); 395 396/* 397 * HAL definitions to comply with local coding convention. 398 */ 399#define ath_hal_detach(_ah) \ 400 ((*(_ah)->ah_detach)((_ah))) 401#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 402 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 403#define ath_hal_macversion(_ah) \ 404 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 405#define ath_hal_getratetable(_ah, _mode) \ 406 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 407#define ath_hal_getmac(_ah, _mac) \ 408 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 409#define ath_hal_setmac(_ah, _mac) \ 410 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 411#define ath_hal_getbssidmask(_ah, _mask) \ 412 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 413#define ath_hal_setbssidmask(_ah, _mask) \ 414 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 415#define ath_hal_intrset(_ah, _mask) \ 416 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 417#define ath_hal_intrget(_ah) \ 418 ((*(_ah)->ah_getInterrupts)((_ah))) 419#define ath_hal_intrpend(_ah) \ 420 ((*(_ah)->ah_isInterruptPending)((_ah))) 421#define ath_hal_getisr(_ah, _pmask) \ 422 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 423#define ath_hal_updatetxtriglevel(_ah, _inc) \ 424 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 425#define ath_hal_setpower(_ah, _mode) \ 426 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 427#define ath_hal_keycachesize(_ah) \ 428 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 429#define ath_hal_keyreset(_ah, _ix) \ 430 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 431#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 432 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 433#define ath_hal_keyisvalid(_ah, _ix) \ 434 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 435#define ath_hal_keysetmac(_ah, _ix, _mac) \ 436 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 437#define ath_hal_getrxfilter(_ah) \ 438 ((*(_ah)->ah_getRxFilter)((_ah))) 439#define ath_hal_setrxfilter(_ah, _filter) \ 440 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 441#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 442 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 443#define ath_hal_waitforbeacon(_ah, _bf) \ 444 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 445#define ath_hal_putrxbuf(_ah, _bufaddr) \ 446 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 447/* NB: common across all chips */ 448#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 449#define ath_hal_gettsf32(_ah) \ 450 OS_REG_READ(_ah, AR_TSF_L32) 451#define ath_hal_gettsf64(_ah) \ 452 ((*(_ah)->ah_getTsf64)((_ah))) 453#define ath_hal_resettsf(_ah) \ 454 ((*(_ah)->ah_resetTsf)((_ah))) 455#define ath_hal_rxena(_ah) \ 456 ((*(_ah)->ah_enableReceive)((_ah))) 457#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 458 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 459#define ath_hal_gettxbuf(_ah, _q) \ 460 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 461#define ath_hal_numtxpending(_ah, _q) \ 462 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 463#define ath_hal_getrxbuf(_ah) \ 464 ((*(_ah)->ah_getRxDP)((_ah))) 465#define ath_hal_txstart(_ah, _q) \ 466 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 467#define ath_hal_setchannel(_ah, _chan) \ 468 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 469#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 470 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 471#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 472 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 473#define ath_hal_calreset(_ah, _chan) \ 474 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 475#define ath_hal_setledstate(_ah, _state) \ 476 ((*(_ah)->ah_setLedState)((_ah), (_state))) 477#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 478 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 479#define ath_hal_beaconreset(_ah) \ 480 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 481#define ath_hal_beaconsettimers(_ah, _bt) \ 482 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 483#define ath_hal_beacontimers(_ah, _bs) \ 484 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 485#define ath_hal_setassocid(_ah, _bss, _associd) \ 486 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 487#define ath_hal_phydisable(_ah) \ 488 ((*(_ah)->ah_phyDisable)((_ah))) 489#define ath_hal_setopmode(_ah) \ 490 ((*(_ah)->ah_setPCUConfig)((_ah))) 491#define ath_hal_stoptxdma(_ah, _qnum) \ 492 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 493#define ath_hal_stoppcurecv(_ah) \ 494 ((*(_ah)->ah_stopPcuReceive)((_ah))) 495#define ath_hal_startpcurecv(_ah) \ 496 ((*(_ah)->ah_startPcuReceive)((_ah))) 497#define ath_hal_stopdmarecv(_ah) \ 498 ((*(_ah)->ah_stopDmaReceive)((_ah))) 499#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 500 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 501 (_indata), (_insize), (_outdata), (_outsize))) 502#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 503 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 504#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 505 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 506#define ath_hal_resettxqueue(_ah, _q) \ 507 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 508#define ath_hal_releasetxqueue(_ah, _q) \ 509 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 510#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 511 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 512#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 513 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 514/* NB: common across all chips */ 515#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 516#define ath_hal_txqenabled(_ah, _qnum) \ 517 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 518#define ath_hal_getrfgain(_ah) \ 519 ((*(_ah)->ah_getRfGain)((_ah))) 520#define ath_hal_getdefantenna(_ah) \ 521 ((*(_ah)->ah_getDefAntenna)((_ah))) 522#define ath_hal_setdefantenna(_ah, _ant) \ 523 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 524#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 525 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 526#define ath_hal_ani_poll(_ah, _chan) \ 527 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 528#define ath_hal_mibevent(_ah, _stats) \ 529 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 530#define ath_hal_setslottime(_ah, _us) \ 531 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 532#define ath_hal_getslottime(_ah) \ 533 ((*(_ah)->ah_getSlotTime)((_ah))) 534#define ath_hal_setacktimeout(_ah, _us) \ 535 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 536#define ath_hal_getacktimeout(_ah) \ 537 ((*(_ah)->ah_getAckTimeout)((_ah))) 538#define ath_hal_setctstimeout(_ah, _us) \ 539 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 540#define ath_hal_getctstimeout(_ah) \ 541 ((*(_ah)->ah_getCTSTimeout)((_ah))) 542#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 543 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 544#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 545 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 546#define ath_hal_ciphersupported(_ah, _cipher) \ 547 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 548#define ath_hal_getregdomain(_ah, _prd) \ 549 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 550#define ath_hal_setregdomain(_ah, _rd) \ 551 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 552#define ath_hal_getcountrycode(_ah, _pcc) \ 553 (*(_pcc) = (_ah)->ah_countryCode) 554#define ath_hal_gettkipmic(_ah) \ 555 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 556#define ath_hal_settkipmic(_ah, _v) \ 557 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 558#define ath_hal_hastkipsplit(_ah) \ 559 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 560#define ath_hal_gettkipsplit(_ah) \ 561 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 562#define ath_hal_settkipsplit(_ah, _v) \ 563 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 564#define ath_hal_haswmetkipmic(_ah) \ 565 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 566#define ath_hal_hwphycounters(_ah) \ 567 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 568#define ath_hal_hasdiversity(_ah) \ 569 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 570#define ath_hal_getdiversity(_ah) \ 571 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 572#define ath_hal_setdiversity(_ah, _v) \ 573 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 574#define ath_hal_getantennaswitch(_ah) \ 575 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 576#define ath_hal_setantennaswitch(_ah, _v) \ 577 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 578#define ath_hal_getdiag(_ah, _pv) \ 579 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 580#define ath_hal_setdiag(_ah, _v) \ 581 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 582#define ath_hal_getnumtxqueues(_ah, _pv) \ 583 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 584#define ath_hal_hasveol(_ah) \ 585 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 586#define ath_hal_hastxpowlimit(_ah) \ 587 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 588#define ath_hal_settxpowlimit(_ah, _pow) \ 589 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 590#define ath_hal_gettxpowlimit(_ah, _ppow) \ 591 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 592#define ath_hal_getmaxtxpow(_ah, _ppow) \ 593 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 594#define ath_hal_gettpscale(_ah, _scale) \ 595 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 596#define ath_hal_settpscale(_ah, _v) \ 597 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 598#define ath_hal_hastpc(_ah) \ 599 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 600#define ath_hal_gettpc(_ah) \ 601 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 602#define ath_hal_settpc(_ah, _v) \ 603 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 604#define ath_hal_hasbursting(_ah) \ 605 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 606#define ath_hal_setmcastkeysearch(_ah, _v) \ 607 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 608#define ath_hal_hasmcastkeysearch(_ah) \ 609 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 610#define ath_hal_getmcastkeysearch(_ah) \ 611 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 612#define ath_hal_hasfastframes(_ah) \ 613 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 614#define ath_hal_hasbssidmask(_ah) \ 615 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 616#define ath_hal_hasbssidmatch(_ah) \ 617 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 618#define ath_hal_hastsfadjust(_ah) \ 619 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 620#define ath_hal_gettsfadjust(_ah) \ 621 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 622#define ath_hal_settsfadjust(_ah, _onoff) \ 623 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 624#define ath_hal_hasrfsilent(_ah) \ 625 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 626#define ath_hal_getrfkill(_ah) \ 627 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 628#define ath_hal_setrfkill(_ah, _onoff) \ 629 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 630#define ath_hal_getrfsilent(_ah, _prfsilent) \ 631 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 632#define ath_hal_setrfsilent(_ah, _rfsilent) \ 633 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 634#define ath_hal_gettpack(_ah, _ptpack) \ 635 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 636#define ath_hal_settpack(_ah, _tpack) \ 637 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 638#define ath_hal_gettpcts(_ah, _ptpcts) \ 639 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 640#define ath_hal_settpcts(_ah, _tpcts) \ 641 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 642#define ath_hal_hasintmit(_ah) \ 643 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 644#define ath_hal_getintmit(_ah) \ 645 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 646#define ath_hal_setintmit(_ah, _v) \ 647 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, _v, NULL) 648#define ath_hal_getchannoise(_ah, _c) \ 649 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 650#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 651 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 652#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 653 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 654#define ath_hal_split4ktrans(_ah) \ 655 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, 0, NULL) == HAL_OK) 656#define ath_hal_self_linked_final_rxdesc(_ah) \ 657 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, 0, NULL) == HAL_OK) 658#define ath_hal_gtxto_supported(_ah) \ 659 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 660 661#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 662 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 663#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 664 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 665#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 666 _txr0, _txtr0, _keyix, _ant, _flags, \ 667 _rtsrate, _rtsdura) \ 668 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 669 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 670 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 671#define ath_hal_setupxtxdesc(_ah, _ds, \ 672 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 673 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 674 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 675#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 676 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 677#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 678 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 679#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 680 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 681#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 682 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 683 684#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 685 _cipher, _delims, _seglen, _first, _last) \ 686 ((*(_ah)->ah_chainTxDesc((_ah), (_ds), (_pktlen), (_hdrlen), \ 687 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 688 (_first), (_last)))) 689#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 690 _txr0, _txtr0, _antm, _rcr, _rcd) \ 691 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 692 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 693#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 694 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 695#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 696 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 697 (_series), (_ns), (_flags))) 698#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 699 ((*(_ah)->ah_set11nAggrMiddle((_ah), (_ds), (_num)))) 700#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 701 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 702 703/* 704 * This is badly-named; you need to set the correct parameters 705 * to begin to receive useful radar events; and even then 706 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 707 * more information. 708 */ 709#define ath_hal_enabledfs(_ah, _param) \ 710 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 711#define ath_hal_getdfsthresh(_ah, _param) \ 712 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 713#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 714 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), (_buf), (_event))) 715#define ath_hal_is_fast_clock_enabled(_ah) \ 716 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 717 718#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 719 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 720#define ath_hal_gpioset(_ah, _gpio, _b) \ 721 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 722#define ath_hal_gpioget(_ah, _gpio) \ 723 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 724#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 725 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 726 727#define ath_hal_radar_wait(_ah, _chan) \ 728 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 729 730#endif /* _DEV_ATH_ATHVAR_H */ 731