if_athvar.h revision 192468
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 192468 2009-05-20 20:00:40Z sam $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46155481Ssam#ifndef ATH_RXBUF 47116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 48155481Ssam#endif 49155481Ssam#ifndef ATH_TXBUF 50170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 51155481Ssam#endif 52178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 53178354Ssam 54140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 55138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 56155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 57138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 58116743Ssam 59147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 60147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 61147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 62147067Ssam 63147057Ssam/* 64147057Ssam * The key cache is used for h/w cipher state and also for 65147057Ssam * tracking station state such as the current tx antenna. 66147057Ssam * We also setup a mapping table between key cache slot indices 67147057Ssam * and station state to short-circuit node lookups on rx. 68147057Ssam * Different parts have different size key caches. We handle 69147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 70147057Ssam */ 71147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 72147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 73147057Ssam 74170530Ssamstruct taskqueue; 75170530Ssamstruct kthread; 76170530Ssamstruct ath_buf; 77170530Ssam 78138570Ssam/* driver-specific node state */ 79116743Ssamstruct ath_node { 80119150Ssam struct ieee80211_node an_node; /* base class */ 81178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 82178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 83170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 84138570Ssam /* variable-length rate control state follows */ 85116743Ssam}; 86138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 87138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 88116743Ssam 89138570Ssam#define ATH_RSSI_LPF_LEN 10 90138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 91138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 92138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 93138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 94138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 95138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 96138570Ssam if ((y) >= -20) \ 97138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 98138570Ssam} while (0) 99184358Ssam#define ATH_EP_RND(x,mul) \ 100184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 101184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 102138570Ssam 103116743Ssamstruct ath_buf { 104138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 105116743Ssam int bf_nseg; 106186904Ssam uint16_t bf_txflags; /* tx descriptor flags */ 107186904Ssam uint16_t bf_flags; /* status flags (below) */ 108116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 109165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 110116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 111138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 112116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 113116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 114116743Ssam bus_size_t bf_mapsize; 115140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 116116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 117116743Ssam}; 118138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 119116743Ssam 120186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 121186904Ssam 122138570Ssam/* 123138570Ssam * DMA state for tx/rx descriptors. 124138570Ssam */ 125138570Ssamstruct ath_descdma { 126138570Ssam const char* dd_name; 127138570Ssam struct ath_desc *dd_desc; /* descriptors */ 128138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 129158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 130138570Ssam bus_dma_segment_t dd_dseg; 131138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 132138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 133138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 134138570Ssam}; 135138570Ssam 136138570Ssam/* 137138570Ssam * Data transmit queue state. One of these exists for each 138138570Ssam * hardware transmit queue. Packets sent to us from above 139138570Ssam * are assigned to queues based on their priority. Not all 140138570Ssam * devices support a complete set of hardware transmit queues. 141138570Ssam * For those devices the array sc_ac2q will map multiple 142138570Ssam * priorities to fewer hardware queues (typically all to one 143138570Ssam * hardware queue). 144138570Ssam */ 145138570Ssamstruct ath_txq { 146138570Ssam u_int axq_qnum; /* hardware q number */ 147178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 148190579Ssam u_int axq_ac; /* WME AC */ 149186904Ssam u_int axq_flags; 150186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 151156073Ssam u_int axq_depth; /* queue depth (stat only) */ 152138570Ssam u_int axq_intrcnt; /* interrupt count */ 153138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 154138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 155138570Ssam struct mtx axq_lock; /* lock on q and link */ 156155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 157138570Ssam}; 158138570Ssam 159155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 160155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 161155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 162167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 163161425Simp} while (0) 164138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 165138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 166138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 167138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 168138570Ssam 169138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 170138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 171138570Ssam (_tq)->axq_depth++; \ 172138570Ssam} while (0) 173138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 174138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 175138570Ssam (_tq)->axq_depth--; \ 176138570Ssam} while (0) 177178354Ssam/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 178178354Ssam#define ATH_TXQ_LAST(_tq) \ 179178354Ssam ((struct ath_buf *)(void *) \ 180178354Ssam ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 181138570Ssam 182178354Ssamstruct ath_vap { 183178354Ssam struct ieee80211vap av_vap; /* base class */ 184178354Ssam int av_bslot; /* beacon slot index */ 185178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 186178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 187178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 188178354Ssam 189178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 190192468Ssam struct mbuf *, int, int, int); 191178354Ssam int (*av_newstate)(struct ieee80211vap *, 192178354Ssam enum ieee80211_state, int); 193178354Ssam void (*av_bmiss)(struct ieee80211vap *); 194178354Ssam}; 195178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 196178354Ssam 197155491Ssamstruct taskqueue; 198155486Ssamstruct ath_tx99; 199155486Ssam 200116743Ssamstruct ath_softc { 201147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 202138570Ssam struct ath_stats sc_stats; /* interface statistics */ 203138570Ssam int sc_debug; 204178354Ssam int sc_nvaps; /* # vaps */ 205178354Ssam int sc_nstavaps; /* # station vaps */ 206178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 207178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 208178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 209178354Ssam 210138570Ssam void (*sc_node_free)(struct ieee80211_node *); 211116743Ssam device_t sc_dev; 212159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 213159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 214116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 215116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 216155491Ssam struct taskqueue *sc_tq; /* private task queue */ 217116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 218138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 219155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 220138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 221178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 222178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 223178354Ssam sc_softled : 1,/* enable LED gpio status */ 224178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 225178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 226178354Ssam sc_diversity: 1,/* enable rx diversity */ 227178354Ssam sc_hasveol : 1,/* tx VEOL support */ 228178354Ssam sc_ledstate : 1,/* LED on/off state */ 229178354Ssam sc_blinking : 1,/* LED blink operation active */ 230178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 231178354Ssam sc_scanning : 1,/* scanning active */ 232155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 233178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 234165571Ssam sc_xchanmode: 1,/* extended channel mode */ 235170530Ssam sc_outdoor : 1,/* outdoor operation */ 236178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 237178354Ssam sc_hasbmask : 1,/* bssid mask support */ 238178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 239178354Ssam sc_beacons : 1,/* beacons running */ 240178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 241178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 242179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 243185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 244186904Ssam sc_tdma : 1,/* TDMA in use */ 245189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 246185744Ssam sc_resetcal : 1;/* reset cal state next trip */ 247178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 248178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 249116743Ssam /* rate tables */ 250188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 251116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 252116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 253155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 254138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 255170530Ssam u_int16_t sc_curaid; /* current association id */ 256187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 257170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 258116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 259140432Ssam struct { 260140432Ssam u_int8_t ieeerate; /* IEEE rate */ 261140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 262140761Ssam u_int8_t txflags; /* radiotap tx flags */ 263140432Ssam u_int16_t ledon; /* softled on time */ 264140432Ssam u_int16_t ledoff; /* softled off time */ 265140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 266138570Ssam u_int8_t sc_protrix; /* protection rate index */ 267170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 268155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 269170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 270170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 271138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 272116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 273138570Ssam u_int sc_keymax; /* size of key cache */ 274147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 275116743Ssam 276140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 277140432Ssam u_int sc_ledon; /* pin setting for LED on */ 278140432Ssam u_int sc_ledidle; /* idle polling interval */ 279140432Ssam int sc_ledevent; /* time of last LED event */ 280184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 281140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 282140432Ssam struct callout sc_ledtimer; /* led off timer */ 283138570Ssam 284155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 285155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 286155515Ssam 287178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 288138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 289170530Ssam struct mbuf *sc_rxpending; /* pending receive data */ 290116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 291116743Ssam struct task sc_rxtask; /* rx int processing */ 292138570Ssam u_int8_t sc_defant; /* current default antenna */ 293138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 294155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 295192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 296192468Ssam struct ath_rx_radiotap_header sc_rx_th; 297192468Ssam int sc_rx_th_len; 298192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 299116743Ssam 300138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 301138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 302138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 303155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 304138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 305138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 306138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 307138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 308116743Ssam struct task sc_txtask; /* tx int processing */ 309189605Ssam int sc_wd_timer; /* count down for wd timer */ 310189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 311192468Ssam struct ath_tx_radiotap_header sc_tx_th; 312192468Ssam int sc_tx_th_len; 313116743Ssam 314138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 315138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 316116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 317138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 318138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 319138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 320116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 321138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 322138570Ssam enum { 323138570Ssam OK, /* no change needed */ 324138570Ssam UPDATE, /* update pending */ 325138570Ssam COMMIT /* beacon sent, commit change */ 326138570Ssam } sc_updateslot; /* slot time update fsm */ 327178354Ssam int sc_slotupdate; /* slot to advance fsm */ 328178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 329178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 330116743Ssam 331116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 332185744Ssam int sc_lastlongcal; /* last long cal completed */ 333185744Ssam int sc_lastcalreset;/* last cal reset done */ 334155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 335186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 336186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 337186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 338186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 339186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 340186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 341186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 342186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 343116743Ssam}; 344116743Ssam 345121100Ssam#define ATH_LOCK_INIT(_sc) \ 346121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 347167252Ssam NULL, MTX_DEF | MTX_RECURSE) 348121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 349121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 350121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 351121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 352121100Ssam 353138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 354138570Ssam 355155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 356155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 357155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 358167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 359155482Ssam} while (0) 360121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 361121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 362121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 363121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 364121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 365121100Ssam 366116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 367116743Ssamint ath_detach(struct ath_softc *); 368116743Ssamvoid ath_resume(struct ath_softc *); 369116743Ssamvoid ath_suspend(struct ath_softc *); 370116743Ssamvoid ath_shutdown(struct ath_softc *); 371116743Ssamvoid ath_intr(void *); 372116743Ssam 373116743Ssam/* 374116743Ssam * HAL definitions to comply with local coding convention. 375116743Ssam */ 376138570Ssam#define ath_hal_detach(_ah) \ 377138570Ssam ((*(_ah)->ah_detach)((_ah))) 378116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 379116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 380186904Ssam#define ath_hal_macversion(_ah) \ 381186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 382116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 383116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 384116743Ssam#define ath_hal_getmac(_ah, _mac) \ 385116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 386138570Ssam#define ath_hal_setmac(_ah, _mac) \ 387138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 388178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 389178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 390178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 391178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 392116743Ssam#define ath_hal_intrset(_ah, _mask) \ 393116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 394116743Ssam#define ath_hal_intrget(_ah) \ 395116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 396116743Ssam#define ath_hal_intrpend(_ah) \ 397116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 398116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 399116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 400116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 401116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 402155515Ssam#define ath_hal_setpower(_ah, _mode) \ 403155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 404138570Ssam#define ath_hal_keycachesize(_ah) \ 405138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 406116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 407116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 408138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 409138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 410116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 411116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 412116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 413116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 414116743Ssam#define ath_hal_getrxfilter(_ah) \ 415116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 416116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 417116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 418116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 419116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 420116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 421116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 422116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 423116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 424186904Ssam/* NB: common across all chips */ 425186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 426116743Ssam#define ath_hal_gettsf32(_ah) \ 427186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 428116743Ssam#define ath_hal_gettsf64(_ah) \ 429116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 430116743Ssam#define ath_hal_resettsf(_ah) \ 431116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 432116743Ssam#define ath_hal_rxena(_ah) \ 433116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 434116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 435116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 436116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 437116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 438138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 439138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 440116743Ssam#define ath_hal_getrxbuf(_ah) \ 441116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 442116743Ssam#define ath_hal_txstart(_ah, _q) \ 443116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 444116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 445116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 446155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 447155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 448185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 449185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 450185744Ssam#define ath_hal_calreset(_ah, _chan) \ 451185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 452116743Ssam#define ath_hal_setledstate(_ah, _state) \ 453116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 454138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 455138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 456116743Ssam#define ath_hal_beaconreset(_ah) \ 457116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 458186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 459186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 460138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 461138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 462116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 463138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 464138570Ssam#define ath_hal_phydisable(_ah) \ 465138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 466138570Ssam#define ath_hal_setopmode(_ah) \ 467138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 468116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 469116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 470116743Ssam#define ath_hal_stoppcurecv(_ah) \ 471116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 472116743Ssam#define ath_hal_startpcurecv(_ah) \ 473116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 474116743Ssam#define ath_hal_stopdmarecv(_ah) \ 475116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 476138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 477138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 478138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 479155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 480170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 481116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 482116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 483116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 484116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 485116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 486116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 487138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 488138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 489138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 490138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 491186904Ssam/* NB: common across all chips */ 492186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 493186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 494186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 495116743Ssam#define ath_hal_getrfgain(_ah) \ 496116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 497138570Ssam#define ath_hal_getdefantenna(_ah) \ 498138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 499138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 500138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 501155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 502155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 503138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 504138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 505138570Ssam#define ath_hal_setslottime(_ah, _us) \ 506138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 507138570Ssam#define ath_hal_getslottime(_ah) \ 508138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 509138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 510138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 511138570Ssam#define ath_hal_getacktimeout(_ah) \ 512138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 513138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 514138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 515138570Ssam#define ath_hal_getctstimeout(_ah) \ 516138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 517138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 518138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 519138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 520138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 521138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 522138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 523138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 524155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 525155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 526184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 527138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 528138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 529178354Ssam#define ath_hal_gettkipmic(_ah) \ 530178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 531178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 532178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 533162410Ssam#define ath_hal_hastkipsplit(_ah) \ 534138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 535162410Ssam#define ath_hal_gettkipsplit(_ah) \ 536162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 537162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 538162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 539178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 540178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 541138570Ssam#define ath_hal_hwphycounters(_ah) \ 542138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 543138570Ssam#define ath_hal_hasdiversity(_ah) \ 544138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 545138570Ssam#define ath_hal_getdiversity(_ah) \ 546138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 547138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 548138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 549166954Ssam#define ath_hal_getantennaswitch(_ah) \ 550166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 551166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 552166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 553138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 554138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 555138570Ssam#define ath_hal_setdiag(_ah, _v) \ 556138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 557138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 558138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 559138570Ssam#define ath_hal_hasveol(_ah) \ 560138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 561138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 562138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 563138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 564138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 565138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 566138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 567138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 568138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 569138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 570138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 571138570Ssam#define ath_hal_settpscale(_ah, _v) \ 572138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 573138570Ssam#define ath_hal_hastpc(_ah) \ 574138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 575138570Ssam#define ath_hal_gettpc(_ah) \ 576138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 577138570Ssam#define ath_hal_settpc(_ah, _v) \ 578138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 579138570Ssam#define ath_hal_hasbursting(_ah) \ 580138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 581147057Ssam#ifdef notyet 582147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 583147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 584147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 585147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 586147057Ssam#else 587147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 588147057Ssam#endif 589170530Ssam#define ath_hal_hasfastframes(_ah) \ 590170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 591178354Ssam#define ath_hal_hasbssidmask(_ah) \ 592178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 593178354Ssam#define ath_hal_hastsfadjust(_ah) \ 594178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 595178354Ssam#define ath_hal_gettsfadjust(_ah) \ 596178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 597178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 598178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 599155515Ssam#define ath_hal_hasrfsilent(_ah) \ 600155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 601155515Ssam#define ath_hal_getrfkill(_ah) \ 602155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 603155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 604155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 605155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 606155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 607155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 608155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 609155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 610155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 611155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 612155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 613155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 614155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 615155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 616155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 617184354Ssam#define ath_hal_hasintmit(_ah) \ 618184354Ssam (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK) 619184354Ssam#define ath_hal_getintmit(_ah) \ 620184354Ssam (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK) 621184354Ssam#define ath_hal_setintmit(_ah, _v) \ 622184354Ssam ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL) 623154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 624154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 625116743Ssam 626116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 627116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 628165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 629165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 630116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 631116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 632116743Ssam _rtsrate, _rtsdura) \ 633116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 634116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 635155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 636138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 637116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 638138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 639116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 640138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 641138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 642165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 643165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 644155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 645155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 646116743Ssam 647188974Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 648188974Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 649138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 650138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 651155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 652155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 653155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 654155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 655138570Ssam 656155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 657155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 658155515Ssam 659116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 660