if_athvar.h revision 189380
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 189380 2009-03-05 00:15:43Z sam $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46155481Ssam#ifndef ATH_RXBUF 47116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 48155481Ssam#endif 49155481Ssam#ifndef ATH_TXBUF 50170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 51155481Ssam#endif 52178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 53178354Ssam 54140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 55138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 56155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 57138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 58116743Ssam 59147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 60147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 61147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 62147067Ssam 63147057Ssam/* 64147057Ssam * The key cache is used for h/w cipher state and also for 65147057Ssam * tracking station state such as the current tx antenna. 66147057Ssam * We also setup a mapping table between key cache slot indices 67147057Ssam * and station state to short-circuit node lookups on rx. 68147057Ssam * Different parts have different size key caches. We handle 69147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 70147057Ssam */ 71147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 72147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 73147057Ssam 74170530Ssam#define ATH_FF_TXQMIN 2 /* min txq depth for staging */ 75170530Ssam#define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */ 76170530Ssam#define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/ 77170530Ssam 78170530Ssamstruct taskqueue; 79170530Ssamstruct kthread; 80170530Ssamstruct ath_buf; 81170530Ssam 82138570Ssam/* driver-specific node state */ 83116743Ssamstruct ath_node { 84119150Ssam struct ieee80211_node an_node; /* base class */ 85178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 86178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 87170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 88138570Ssam /* variable-length rate control state follows */ 89116743Ssam}; 90138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 91138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 92116743Ssam 93138570Ssam#define ATH_RSSI_LPF_LEN 10 94138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 95138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 96138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 97138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 98138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 99138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 100138570Ssam if ((y) >= -20) \ 101138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 102138570Ssam} while (0) 103184358Ssam#define ATH_EP_RND(x,mul) \ 104184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 105184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 106138570Ssam 107116743Ssamstruct ath_buf { 108138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 109170530Ssam TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */ 110170530Ssam u_int32_t bf_age; /* age when placed on stageq */ 111116743Ssam int bf_nseg; 112186904Ssam uint16_t bf_txflags; /* tx descriptor flags */ 113186904Ssam uint16_t bf_flags; /* status flags (below) */ 114116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 115165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 116116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 117138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 118116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 119116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 120116743Ssam bus_size_t bf_mapsize; 121140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 122116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 123116743Ssam}; 124138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 125116743Ssam 126186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 127186904Ssam 128138570Ssam/* 129138570Ssam * DMA state for tx/rx descriptors. 130138570Ssam */ 131138570Ssamstruct ath_descdma { 132138570Ssam const char* dd_name; 133138570Ssam struct ath_desc *dd_desc; /* descriptors */ 134138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 135158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 136138570Ssam bus_dma_segment_t dd_dseg; 137138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 138138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 139138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 140138570Ssam}; 141138570Ssam 142138570Ssam/* 143138570Ssam * Data transmit queue state. One of these exists for each 144138570Ssam * hardware transmit queue. Packets sent to us from above 145138570Ssam * are assigned to queues based on their priority. Not all 146138570Ssam * devices support a complete set of hardware transmit queues. 147138570Ssam * For those devices the array sc_ac2q will map multiple 148138570Ssam * priorities to fewer hardware queues (typically all to one 149138570Ssam * hardware queue). 150138570Ssam */ 151138570Ssamstruct ath_txq { 152138570Ssam u_int axq_qnum; /* hardware q number */ 153178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 154186904Ssam u_int axq_flags; 155186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 156156073Ssam u_int axq_depth; /* queue depth (stat only) */ 157138570Ssam u_int axq_intrcnt; /* interrupt count */ 158138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 159138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 160138570Ssam struct mtx axq_lock; /* lock on q and link */ 161155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 162170530Ssam /* 163170530Ssam * Fast-frame state. The staging queue holds awaiting 164170530Ssam * a fast-frame pairing. Buffers on this queue are 165170530Ssam * assigned an ``age'' and flushed when they wait too long. 166170530Ssam */ 167170530Ssam TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; 168170530Ssam u_int32_t axq_curage; /* queue age */ 169138570Ssam}; 170138570Ssam 171155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 172155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 173155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 174167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 175161425Simp} while (0) 176138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 177138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 178138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 179138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 180138570Ssam 181138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 182138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 183138570Ssam (_tq)->axq_depth++; \ 184170530Ssam (_tq)->axq_curage++; \ 185138570Ssam} while (0) 186138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 187138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 188138570Ssam (_tq)->axq_depth--; \ 189138570Ssam} while (0) 190178354Ssam/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 191178354Ssam#define ATH_TXQ_LAST(_tq) \ 192178354Ssam ((struct ath_buf *)(void *) \ 193178354Ssam ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 194138570Ssam 195178354Ssamstruct ath_vap { 196178354Ssam struct ieee80211vap av_vap; /* base class */ 197178354Ssam int av_bslot; /* beacon slot index */ 198178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 199178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 200178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 201178354Ssam 202178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 203178354Ssam struct mbuf *, int, int, int, u_int32_t); 204178354Ssam int (*av_newstate)(struct ieee80211vap *, 205178354Ssam enum ieee80211_state, int); 206178354Ssam void (*av_bmiss)(struct ieee80211vap *); 207178354Ssam}; 208178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 209178354Ssam 210155491Ssamstruct taskqueue; 211155486Ssamstruct ath_tx99; 212155486Ssam 213116743Ssamstruct ath_softc { 214147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 215138570Ssam struct ath_stats sc_stats; /* interface statistics */ 216138570Ssam int sc_debug; 217178354Ssam int sc_nvaps; /* # vaps */ 218178354Ssam int sc_nstavaps; /* # station vaps */ 219178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 220178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 221178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 222178354Ssam 223138570Ssam void (*sc_node_free)(struct ieee80211_node *); 224116743Ssam device_t sc_dev; 225159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 226159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 227116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 229155491Ssam struct taskqueue *sc_tq; /* private task queue */ 230116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 231138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 232155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 233138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 234178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 235178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 236178354Ssam sc_softled : 1,/* enable LED gpio status */ 237178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 238178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 239178354Ssam sc_diversity: 1,/* enable rx diversity */ 240178354Ssam sc_hasveol : 1,/* tx VEOL support */ 241178354Ssam sc_ledstate : 1,/* LED on/off state */ 242178354Ssam sc_blinking : 1,/* LED blink operation active */ 243178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 244178354Ssam sc_scanning : 1,/* scanning active */ 245155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 246178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 247165571Ssam sc_xchanmode: 1,/* extended channel mode */ 248170530Ssam sc_outdoor : 1,/* outdoor operation */ 249178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 250178354Ssam sc_hasbmask : 1,/* bssid mask support */ 251178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 252178354Ssam sc_beacons : 1,/* beacons running */ 253178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 254178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 255179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 256185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 257186904Ssam sc_tdma : 1,/* TDMA in use */ 258189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 259185744Ssam sc_resetcal : 1;/* reset cal state next trip */ 260178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 261178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 262116743Ssam /* rate tables */ 263188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 264116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 265116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 266155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 267138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 268170530Ssam u_int16_t sc_curaid; /* current association id */ 269187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 270170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 271116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 272140432Ssam struct { 273140432Ssam u_int8_t ieeerate; /* IEEE rate */ 274140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 275140761Ssam u_int8_t txflags; /* radiotap tx flags */ 276140432Ssam u_int16_t ledon; /* softled on time */ 277140432Ssam u_int16_t ledoff; /* softled off time */ 278140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 279138570Ssam u_int8_t sc_protrix; /* protection rate index */ 280170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 281155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 282170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 283170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 284138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 285116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 286138570Ssam u_int sc_keymax; /* size of key cache */ 287147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 288116743Ssam 289140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 290140432Ssam u_int sc_ledon; /* pin setting for LED on */ 291140432Ssam u_int sc_ledidle; /* idle polling interval */ 292140432Ssam int sc_ledevent; /* time of last LED event */ 293184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 294140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 295140432Ssam struct callout sc_ledtimer; /* led off timer */ 296138570Ssam 297155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 298155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 299155515Ssam 300178354Ssam struct ath_tx_radiotap_header sc_tx_th; 301127698Ssam int sc_tx_th_len; 302178354Ssam struct ath_rx_radiotap_header sc_rx_th; 303140761Ssam int sc_rx_th_len; 304154140Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 305119783Ssam 306178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 307138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 308170530Ssam struct mbuf *sc_rxpending; /* pending receive data */ 309116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 310116743Ssam struct task sc_rxtask; /* rx int processing */ 311138570Ssam u_int8_t sc_defant; /* current default antenna */ 312138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 313155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 314116743Ssam 315138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 316138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 317138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 318155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 319138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 320138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 321138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 322138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 323116743Ssam struct task sc_txtask; /* tx int processing */ 324116743Ssam 325138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 326138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 327116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 328138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 329138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 330138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 331116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 332138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 333138570Ssam enum { 334138570Ssam OK, /* no change needed */ 335138570Ssam UPDATE, /* update pending */ 336138570Ssam COMMIT /* beacon sent, commit change */ 337138570Ssam } sc_updateslot; /* slot time update fsm */ 338178354Ssam int sc_slotupdate; /* slot to advance fsm */ 339178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 340178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 341116743Ssam 342116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 343185744Ssam int sc_lastlongcal; /* last long cal completed */ 344185744Ssam int sc_lastcalreset;/* last cal reset done */ 345155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 346186904Ssam#ifdef ATH_SUPPORT_TDMA 347186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 348186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 349186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 350186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 351186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 352186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 353186904Ssam u_int sc_tdmabintcnt; /* TDMA beacon intvl (slots) */ 354186904Ssam struct ath_rx_status *sc_tdmars; /* TDMA status of last rx */ 355186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 356186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 357186904Ssam#endif 358116743Ssam}; 359116743Ssam 360121100Ssam#define ATH_LOCK_INIT(_sc) \ 361121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 362167252Ssam NULL, MTX_DEF | MTX_RECURSE) 363121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 364121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 365121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 366121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 367121100Ssam 368138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 369138570Ssam 370155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 371155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 372155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 373167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 374155482Ssam} while (0) 375121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 376121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 377121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 378121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 379121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 380121100Ssam 381116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 382116743Ssamint ath_detach(struct ath_softc *); 383116743Ssamvoid ath_resume(struct ath_softc *); 384116743Ssamvoid ath_suspend(struct ath_softc *); 385116743Ssamvoid ath_shutdown(struct ath_softc *); 386116743Ssamvoid ath_intr(void *); 387116743Ssam 388116743Ssam/* 389116743Ssam * HAL definitions to comply with local coding convention. 390116743Ssam */ 391138570Ssam#define ath_hal_detach(_ah) \ 392138570Ssam ((*(_ah)->ah_detach)((_ah))) 393116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 394116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 395186904Ssam#define ath_hal_macversion(_ah) \ 396186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 397116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 398116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 399116743Ssam#define ath_hal_getmac(_ah, _mac) \ 400116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 401138570Ssam#define ath_hal_setmac(_ah, _mac) \ 402138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 403178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 404178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 405178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 406178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 407116743Ssam#define ath_hal_intrset(_ah, _mask) \ 408116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 409116743Ssam#define ath_hal_intrget(_ah) \ 410116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 411116743Ssam#define ath_hal_intrpend(_ah) \ 412116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 413116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 414116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 415116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 416116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 417155515Ssam#define ath_hal_setpower(_ah, _mode) \ 418155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 419138570Ssam#define ath_hal_keycachesize(_ah) \ 420138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 421116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 422116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 423138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 424138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 425116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 426116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 427116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 428116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 429116743Ssam#define ath_hal_getrxfilter(_ah) \ 430116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 431116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 432116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 433116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 434116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 435116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 436116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 437116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 438116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 439186904Ssam/* NB: common across all chips */ 440186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 441116743Ssam#define ath_hal_gettsf32(_ah) \ 442186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 443116743Ssam#define ath_hal_gettsf64(_ah) \ 444116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 445116743Ssam#define ath_hal_resettsf(_ah) \ 446116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 447116743Ssam#define ath_hal_rxena(_ah) \ 448116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 449116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 450116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 451116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 452116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 453138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 454138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 455116743Ssam#define ath_hal_getrxbuf(_ah) \ 456116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 457116743Ssam#define ath_hal_txstart(_ah, _q) \ 458116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 459116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 460116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 461155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 462155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 463185744Ssam#if HAL_ABI_VERSION >= 0x08111000 464185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 465185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 466185744Ssam#define ath_hal_calreset(_ah, _chan) \ 467185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 468185744Ssam#else 469185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 470185744Ssam ath_hal_calibrate(_ah, _chan, _isdone) 471185744Ssam#define ath_hal_calreset(_ah, _chan) (0) 472185744Ssam#endif 473116743Ssam#define ath_hal_setledstate(_ah, _state) \ 474116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 475138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 476138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 477116743Ssam#define ath_hal_beaconreset(_ah) \ 478116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 479186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 480186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 481138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 482138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 483116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 484138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 485138570Ssam#define ath_hal_phydisable(_ah) \ 486138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 487138570Ssam#define ath_hal_setopmode(_ah) \ 488138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 489116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 490116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 491116743Ssam#define ath_hal_stoppcurecv(_ah) \ 492116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 493116743Ssam#define ath_hal_startpcurecv(_ah) \ 494116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 495116743Ssam#define ath_hal_stopdmarecv(_ah) \ 496116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 497138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 498138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 499138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 500155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 501170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 502116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 503116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 504116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 505116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 506116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 507116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 508138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 509138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 510138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 511138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 512186904Ssam/* NB: common across all chips */ 513186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 514186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 515186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 516116743Ssam#define ath_hal_getrfgain(_ah) \ 517116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 518138570Ssam#define ath_hal_getdefantenna(_ah) \ 519138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 520138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 521138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 522155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 523155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 524138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 525138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 526138570Ssam#define ath_hal_setslottime(_ah, _us) \ 527138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 528138570Ssam#define ath_hal_getslottime(_ah) \ 529138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 530138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 531138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 532138570Ssam#define ath_hal_getacktimeout(_ah) \ 533138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 534138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 535138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 536138570Ssam#define ath_hal_getctstimeout(_ah) \ 537138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 538138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 539138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 540138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 541138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 542138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 543138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 544138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 545155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 546184369Ssam#if HAL_ABI_VERSION < 0x08090100 547184369Ssam/* XXX wrong for anything but amd64 and i386 */ 548183221Ssam#if defined(__LP64__) 549155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 550183221Ssam (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 176) = (_rd)) 551183221Ssam#else 552183221Ssam#define ath_hal_setregdomain(_ah, _rd) \ 553182893Srpaulo (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 128) = (_rd)) 554183221Ssam#endif 555184369Ssam#else 556184369Ssam#define ath_hal_setregdomain(_ah, _rd) \ 557184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 558184369Ssam#endif 559138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 560138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 561178354Ssam#define ath_hal_gettkipmic(_ah) \ 562178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 563178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 564178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 565162410Ssam#define ath_hal_hastkipsplit(_ah) \ 566138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 567162410Ssam#define ath_hal_gettkipsplit(_ah) \ 568162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 569162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 570162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 571178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 572178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 573138570Ssam#define ath_hal_hwphycounters(_ah) \ 574138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 575138570Ssam#define ath_hal_hasdiversity(_ah) \ 576138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 577138570Ssam#define ath_hal_getdiversity(_ah) \ 578138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 579138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 580138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 581166954Ssam#define ath_hal_getantennaswitch(_ah) \ 582166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 583166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 584166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 585138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 586138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 587138570Ssam#define ath_hal_setdiag(_ah, _v) \ 588138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 589138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 590138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 591138570Ssam#define ath_hal_hasveol(_ah) \ 592138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 593138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 594138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 595138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 596138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 597138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 598138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 599138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 600138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 601138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 602138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 603138570Ssam#define ath_hal_settpscale(_ah, _v) \ 604138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 605138570Ssam#define ath_hal_hastpc(_ah) \ 606138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 607138570Ssam#define ath_hal_gettpc(_ah) \ 608138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 609138570Ssam#define ath_hal_settpc(_ah, _v) \ 610138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 611138570Ssam#define ath_hal_hasbursting(_ah) \ 612138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 613147057Ssam#ifdef notyet 614147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 615147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 616147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 617147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 618147057Ssam#else 619147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 620147057Ssam#endif 621170530Ssam#define ath_hal_hasfastframes(_ah) \ 622170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 623178354Ssam#define ath_hal_hasbssidmask(_ah) \ 624178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 625178354Ssam#define ath_hal_hastsfadjust(_ah) \ 626178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 627178354Ssam#define ath_hal_gettsfadjust(_ah) \ 628178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 629178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 630178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 631155515Ssam#define ath_hal_hasrfsilent(_ah) \ 632155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 633155515Ssam#define ath_hal_getrfkill(_ah) \ 634155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 635155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 636155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 637155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 638155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 639155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 640155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 641155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 642155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 643155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 644155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 645155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 646155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 647155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 648155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 649184354Ssam#define ath_hal_hasintmit(_ah) \ 650184354Ssam (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK) 651184354Ssam#define ath_hal_getintmit(_ah) \ 652184354Ssam (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK) 653184354Ssam#define ath_hal_setintmit(_ah, _v) \ 654184354Ssam ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL) 655154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 656154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 657155515Ssam#if HAL_ABI_VERSION < 0x05122200 658155515Ssam#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 659155515Ssam#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 660155515Ssam#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 661155515Ssam#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 662155515Ssam#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 663155515Ssam#endif 664165571Ssam#if HAL_ABI_VERSION < 0x06102501 665165571Ssam#define ath_hal_ispublicsafetysku(ah) \ 666165571Ssam (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 667165571Ssam (ah)->ah_regdomain == 0x12) 668165571Ssam#endif 669166016Ssam#if HAL_ABI_VERSION < 0x06122400 670166016Ssam/* XXX yech, can't get to regdomain so just hack a compat shim */ 671166016Ssam#define ath_hal_isgsmsku(ah) \ 672166016Ssam ((ah)->ah_countryCode == 843) 673166016Ssam#endif 674170530Ssam#if HAL_ABI_VERSION < 0x07050400 675170530Ssam/* compat shims so code compilers--it won't work though */ 676170530Ssam#define CHANNEL_HT20 0x10000 677170530Ssam#define CHANNEL_HT40PLUS 0x20000 678170530Ssam#define CHANNEL_HT40MINUS 0x40000 679170530Ssam#define HAL_MODE_11NG_HT20 0x008000 680170530Ssam#define HAL_MODE_11NA_HT20 0x010000 681170530Ssam#endif 682116743Ssam 683116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 684116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 685165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 686165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 687116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 688116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 689116743Ssam _rtsrate, _rtsdura) \ 690116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 691116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 692155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 693138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 694116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 695138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 696116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 697138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 698138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 699165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 700165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 701155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 702155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 703116743Ssam 704188974Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 705188974Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 706138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 707138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 708155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 709155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 710155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 711155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 712138570Ssam 713155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 714155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 715155515Ssam 716116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 717