if_athvar.h revision 183221
1116743Ssam/*- 2178354Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 183221 2008-09-21 00:28:54Z sam $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38116743Ssam#include <contrib/dev/ath/ah.h> 39165185Ssam#include <contrib/dev/ath/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46155481Ssam#ifndef ATH_RXBUF 47116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 48155481Ssam#endif 49155481Ssam#ifndef ATH_TXBUF 50170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 51155481Ssam#endif 52178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 53178354Ssam 54140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 55138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 56155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 57138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 58116743Ssam 59147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 60147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 61147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 62147067Ssam 63147057Ssam/* 64147057Ssam * The key cache is used for h/w cipher state and also for 65147057Ssam * tracking station state such as the current tx antenna. 66147057Ssam * We also setup a mapping table between key cache slot indices 67147057Ssam * and station state to short-circuit node lookups on rx. 68147057Ssam * Different parts have different size key caches. We handle 69147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 70147057Ssam */ 71147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 72147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 73147057Ssam 74170530Ssam#define ATH_FF_TXQMIN 2 /* min txq depth for staging */ 75170530Ssam#define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */ 76170530Ssam#define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/ 77170530Ssam 78170530Ssamstruct taskqueue; 79170530Ssamstruct kthread; 80170530Ssamstruct ath_buf; 81170530Ssam 82138570Ssam/* driver-specific node state */ 83116743Ssamstruct ath_node { 84119150Ssam struct ieee80211_node an_node; /* base class */ 85178354Ssam const struct ieee80211_txparam *an_tp; 86178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 87178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 88170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 89138570Ssam /* variable-length rate control state follows */ 90116743Ssam}; 91138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 92138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 93116743Ssam 94138570Ssam#define ATH_RSSI_LPF_LEN 10 95138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 96138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 97138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 98138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 99138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 100138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 101138570Ssam if ((y) >= -20) \ 102138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 103138570Ssam} while (0) 104138570Ssam 105116743Ssamstruct ath_buf { 106138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 107170530Ssam TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */ 108170530Ssam u_int32_t bf_age; /* age when placed on stageq */ 109116743Ssam int bf_nseg; 110156073Ssam int bf_flags; /* tx descriptor flags */ 111116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 112165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 113116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 114138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 115116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 116116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 117116743Ssam bus_size_t bf_mapsize; 118140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 119116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 120116743Ssam}; 121138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 122116743Ssam 123138570Ssam/* 124138570Ssam * DMA state for tx/rx descriptors. 125138570Ssam */ 126138570Ssamstruct ath_descdma { 127138570Ssam const char* dd_name; 128138570Ssam struct ath_desc *dd_desc; /* descriptors */ 129138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 130158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 131138570Ssam bus_dma_segment_t dd_dseg; 132138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 133138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 134138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 135138570Ssam}; 136138570Ssam 137138570Ssam/* 138138570Ssam * Data transmit queue state. One of these exists for each 139138570Ssam * hardware transmit queue. Packets sent to us from above 140138570Ssam * are assigned to queues based on their priority. Not all 141138570Ssam * devices support a complete set of hardware transmit queues. 142138570Ssam * For those devices the array sc_ac2q will map multiple 143138570Ssam * priorities to fewer hardware queues (typically all to one 144138570Ssam * hardware queue). 145138570Ssam */ 146138570Ssamstruct ath_txq { 147138570Ssam u_int axq_qnum; /* hardware q number */ 148178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 149156073Ssam u_int axq_depth; /* queue depth (stat only) */ 150138570Ssam u_int axq_intrcnt; /* interrupt count */ 151138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 152138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 153138570Ssam struct mtx axq_lock; /* lock on q and link */ 154155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 155170530Ssam /* 156170530Ssam * Fast-frame state. The staging queue holds awaiting 157170530Ssam * a fast-frame pairing. Buffers on this queue are 158170530Ssam * assigned an ``age'' and flushed when they wait too long. 159170530Ssam */ 160170530Ssam TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; 161170530Ssam u_int32_t axq_curage; /* queue age */ 162138570Ssam}; 163138570Ssam 164155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 165155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 166155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 167167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 168161425Simp} while (0) 169138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 170138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 171138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 172138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 173138570Ssam 174138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 175138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 176138570Ssam (_tq)->axq_depth++; \ 177170530Ssam (_tq)->axq_curage++; \ 178138570Ssam} while (0) 179138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 180138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 181138570Ssam (_tq)->axq_depth--; \ 182138570Ssam} while (0) 183178354Ssam/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 184178354Ssam#define ATH_TXQ_LAST(_tq) \ 185178354Ssam ((struct ath_buf *)(void *) \ 186178354Ssam ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 187138570Ssam 188178354Ssamstruct ath_vap { 189178354Ssam struct ieee80211vap av_vap; /* base class */ 190178354Ssam int av_bslot; /* beacon slot index */ 191178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 192178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 193178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 194178354Ssam 195178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 196178354Ssam struct mbuf *, int, int, int, u_int32_t); 197178354Ssam int (*av_newstate)(struct ieee80211vap *, 198178354Ssam enum ieee80211_state, int); 199178354Ssam void (*av_bmiss)(struct ieee80211vap *); 200178354Ssam}; 201178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 202178354Ssam 203155491Ssamstruct taskqueue; 204155486Ssamstruct ath_tx99; 205155486Ssam 206116743Ssamstruct ath_softc { 207147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 208138570Ssam struct ath_stats sc_stats; /* interface statistics */ 209138570Ssam int sc_debug; 210178354Ssam int sc_nvaps; /* # vaps */ 211178354Ssam int sc_nstavaps; /* # station vaps */ 212178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 213178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 214178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 215178354Ssam 216138570Ssam void (*sc_node_free)(struct ieee80211_node *); 217116743Ssam device_t sc_dev; 218159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 219159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 220116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 222155491Ssam struct taskqueue *sc_tq; /* private task queue */ 223116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 224138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 225155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 226138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 227178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 228178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 229178354Ssam sc_softled : 1,/* enable LED gpio status */ 230178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 231178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 232178354Ssam sc_diversity: 1,/* enable rx diversity */ 233178354Ssam sc_hasveol : 1,/* tx VEOL support */ 234178354Ssam sc_ledstate : 1,/* LED on/off state */ 235178354Ssam sc_blinking : 1,/* LED blink operation active */ 236178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 237178354Ssam sc_scanning : 1,/* scanning active */ 238155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 239178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 240165571Ssam sc_xchanmode: 1,/* extended channel mode */ 241170530Ssam sc_outdoor : 1,/* outdoor operation */ 242178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 243178354Ssam sc_hasbmask : 1,/* bssid mask support */ 244178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 245178354Ssam sc_beacons : 1,/* beacons running */ 246178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 247178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 248179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 249179401Ssam sc_resume_up: 1;/* on resume, start all vaps */ 250178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 251178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 252116743Ssam /* rate tables */ 253166013Ssam#define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0) 254166013Ssam#define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1) 255165571Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2]; 256116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 257116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 258155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 259138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 260170530Ssam u_int16_t sc_curaid; /* current association id */ 261138570Ssam HAL_CHANNEL sc_curchan; /* current h/w channel */ 262170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 263116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 264140432Ssam struct { 265140432Ssam u_int8_t ieeerate; /* IEEE rate */ 266140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 267140761Ssam u_int8_t txflags; /* radiotap tx flags */ 268140432Ssam u_int16_t ledon; /* softled on time */ 269140432Ssam u_int16_t ledoff; /* softled off time */ 270140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 271138570Ssam u_int8_t sc_protrix; /* protection rate index */ 272170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 273155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 274170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 275170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 276138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 277116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 278138570Ssam u_int sc_keymax; /* size of key cache */ 279147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 280116743Ssam 281140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 282140432Ssam u_int sc_ledon; /* pin setting for LED on */ 283140432Ssam u_int sc_ledidle; /* idle polling interval */ 284140432Ssam int sc_ledevent; /* time of last LED event */ 285140432Ssam u_int8_t sc_rxrate; /* current rx rate for LED */ 286140432Ssam u_int8_t sc_txrate; /* current tx rate for LED */ 287140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 288140432Ssam struct callout sc_ledtimer; /* led off timer */ 289138570Ssam 290155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 291155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 292155515Ssam 293178354Ssam struct ath_tx_radiotap_header sc_tx_th; 294127698Ssam int sc_tx_th_len; 295178354Ssam struct ath_rx_radiotap_header sc_rx_th; 296140761Ssam int sc_rx_th_len; 297154140Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 298119783Ssam 299178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 300138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 301170530Ssam struct mbuf *sc_rxpending; /* pending receive data */ 302116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 303116743Ssam struct task sc_rxtask; /* rx int processing */ 304138570Ssam struct task sc_rxorntask; /* rxorn int processing */ 305138570Ssam u_int8_t sc_defant; /* current default antenna */ 306138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 307155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 308116743Ssam 309138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 310138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 311138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 312155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 313138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 314138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 315138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 316138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 317116743Ssam struct task sc_txtask; /* tx int processing */ 318116743Ssam 319138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 320138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 321116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 322138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 323138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 324138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 325116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 326138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 327138570Ssam enum { 328138570Ssam OK, /* no change needed */ 329138570Ssam UPDATE, /* update pending */ 330138570Ssam COMMIT /* beacon sent, commit change */ 331138570Ssam } sc_updateslot; /* slot time update fsm */ 332178354Ssam int sc_slotupdate; /* slot to advance fsm */ 333178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 334178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 335116743Ssam 336116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 337155515Ssam int sc_calinterval; /* current polling interval */ 338155515Ssam int sc_caltries; /* cals at current interval */ 339155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 340116743Ssam}; 341116743Ssam 342121100Ssam#define ATH_LOCK_INIT(_sc) \ 343121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 344167252Ssam NULL, MTX_DEF | MTX_RECURSE) 345121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 346121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 347121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 348121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 349121100Ssam 350138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 351138570Ssam 352155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 353155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 354155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 355167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 356155482Ssam} while (0) 357121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 358121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 359121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 360121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 361121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 362121100Ssam 363116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 364116743Ssamint ath_detach(struct ath_softc *); 365116743Ssamvoid ath_resume(struct ath_softc *); 366116743Ssamvoid ath_suspend(struct ath_softc *); 367116743Ssamvoid ath_shutdown(struct ath_softc *); 368116743Ssamvoid ath_intr(void *); 369116743Ssam 370116743Ssam/* 371116743Ssam * HAL definitions to comply with local coding convention. 372116743Ssam */ 373138570Ssam#define ath_hal_detach(_ah) \ 374138570Ssam ((*(_ah)->ah_detach)((_ah))) 375116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 376116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 377116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 378116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 379116743Ssam#define ath_hal_getmac(_ah, _mac) \ 380116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 381138570Ssam#define ath_hal_setmac(_ah, _mac) \ 382138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 383178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 384178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 385178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 386178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 387116743Ssam#define ath_hal_intrset(_ah, _mask) \ 388116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 389116743Ssam#define ath_hal_intrget(_ah) \ 390116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 391116743Ssam#define ath_hal_intrpend(_ah) \ 392116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 393116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 394116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 395116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 396116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 397155515Ssam#define ath_hal_setpower(_ah, _mode) \ 398155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 399138570Ssam#define ath_hal_keycachesize(_ah) \ 400138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 401116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 402116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 403138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 404138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 405116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 406116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 407116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 408116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 409116743Ssam#define ath_hal_getrxfilter(_ah) \ 410116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 411116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 412116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 413116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 414116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 415116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 416116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 417116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 418116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 419116743Ssam#define ath_hal_gettsf32(_ah) \ 420116743Ssam ((*(_ah)->ah_getTsf32)((_ah))) 421116743Ssam#define ath_hal_gettsf64(_ah) \ 422116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 423116743Ssam#define ath_hal_resettsf(_ah) \ 424116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 425116743Ssam#define ath_hal_rxena(_ah) \ 426116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 427116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 428116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 429116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 430116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 431138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 432138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 433116743Ssam#define ath_hal_getrxbuf(_ah) \ 434116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 435116743Ssam#define ath_hal_txstart(_ah, _q) \ 436116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 437116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 438116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 439155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 440155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 441116743Ssam#define ath_hal_setledstate(_ah, _state) \ 442116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 443138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 444138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 445116743Ssam#define ath_hal_beaconreset(_ah) \ 446116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 447138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 448138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 449116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 450138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 451138570Ssam#define ath_hal_phydisable(_ah) \ 452138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 453138570Ssam#define ath_hal_setopmode(_ah) \ 454138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 455116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 456116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 457116743Ssam#define ath_hal_stoppcurecv(_ah) \ 458116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 459116743Ssam#define ath_hal_startpcurecv(_ah) \ 460116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 461116743Ssam#define ath_hal_stopdmarecv(_ah) \ 462116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 463138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 464138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 465138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 466155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 467170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 468116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 469116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 470116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 471116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 472116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 473116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 474138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 475138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 476138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 477138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 478116743Ssam#define ath_hal_getrfgain(_ah) \ 479116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 480138570Ssam#define ath_hal_getdefantenna(_ah) \ 481138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 482138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 483138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 484155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 485155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 486138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 487138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 488138570Ssam#define ath_hal_setslottime(_ah, _us) \ 489138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 490138570Ssam#define ath_hal_getslottime(_ah) \ 491138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 492138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 493138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 494138570Ssam#define ath_hal_getacktimeout(_ah) \ 495138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 496138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 497138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 498138570Ssam#define ath_hal_getctstimeout(_ah) \ 499138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 500138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 501138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 502138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 503138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 504138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 505138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 506138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 507155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 508183221Ssam#if defined(__LP64__) 509155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 510183221Ssam (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 176) = (_rd)) 511183221Ssam#else 512183221Ssam#define ath_hal_setregdomain(_ah, _rd) \ 513182893Srpaulo (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 128) = (_rd)) 514183221Ssam#endif 515138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 516138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 517178354Ssam#define ath_hal_gettkipmic(_ah) \ 518178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 519178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 520178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 521162410Ssam#define ath_hal_hastkipsplit(_ah) \ 522138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 523162410Ssam#define ath_hal_gettkipsplit(_ah) \ 524162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 525162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 526162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 527178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 528178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 529138570Ssam#define ath_hal_hwphycounters(_ah) \ 530138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 531138570Ssam#define ath_hal_hasdiversity(_ah) \ 532138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 533138570Ssam#define ath_hal_getdiversity(_ah) \ 534138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 535138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 536138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 537166954Ssam#define ath_hal_getantennaswitch(_ah) \ 538166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 539166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 540166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 541138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 542138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 543138570Ssam#define ath_hal_setdiag(_ah, _v) \ 544138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 545138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 546138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 547138570Ssam#define ath_hal_hasveol(_ah) \ 548138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 549138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 550138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 551138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 552138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 553138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 554138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 555138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 556138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 557138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 558138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 559138570Ssam#define ath_hal_settpscale(_ah, _v) \ 560138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 561138570Ssam#define ath_hal_hastpc(_ah) \ 562138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 563138570Ssam#define ath_hal_gettpc(_ah) \ 564138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 565138570Ssam#define ath_hal_settpc(_ah, _v) \ 566138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 567138570Ssam#define ath_hal_hasbursting(_ah) \ 568138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 569147057Ssam#ifdef notyet 570147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 571147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 572147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 573147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 574147057Ssam#else 575147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 576147057Ssam#endif 577170530Ssam#define ath_hal_hasfastframes(_ah) \ 578170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 579178354Ssam#define ath_hal_hasbssidmask(_ah) \ 580178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 581178354Ssam#define ath_hal_hastsfadjust(_ah) \ 582178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 583178354Ssam#define ath_hal_gettsfadjust(_ah) \ 584178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 585178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 586178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 587155515Ssam#define ath_hal_hasrfsilent(_ah) \ 588155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 589155515Ssam#define ath_hal_getrfkill(_ah) \ 590155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 591155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 592155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 593155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 594155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 595155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 596155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 597155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 598155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 599155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 600155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 601155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 602155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 603155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 604155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 605154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 606154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 607155515Ssam#if HAL_ABI_VERSION < 0x05122200 608155515Ssam#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 609155515Ssam#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 610155515Ssam#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 611155515Ssam#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 612155515Ssam#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 613155515Ssam#endif 614165571Ssam#if HAL_ABI_VERSION < 0x06102501 615165571Ssam#define ath_hal_ispublicsafetysku(ah) \ 616165571Ssam (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 617165571Ssam (ah)->ah_regdomain == 0x12) 618165571Ssam#endif 619166016Ssam#if HAL_ABI_VERSION < 0x06122400 620166016Ssam/* XXX yech, can't get to regdomain so just hack a compat shim */ 621166016Ssam#define ath_hal_isgsmsku(ah) \ 622166016Ssam ((ah)->ah_countryCode == 843) 623166016Ssam#endif 624170530Ssam#if HAL_ABI_VERSION < 0x07050400 625170530Ssam/* compat shims so code compilers--it won't work though */ 626170530Ssam#define CHANNEL_HT20 0x10000 627170530Ssam#define CHANNEL_HT40PLUS 0x20000 628170530Ssam#define CHANNEL_HT40MINUS 0x40000 629170530Ssam#define HAL_MODE_11NG_HT20 0x008000 630170530Ssam#define HAL_MODE_11NA_HT20 0x010000 631170530Ssam#endif 632116743Ssam 633116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 634116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 635165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 636165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 637116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 638116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 639116743Ssam _rtsrate, _rtsdura) \ 640116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 641116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 642155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 643138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 644116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 645138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 646116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 647138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 648138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 649165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 650165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 651155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 652155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 653116743Ssam 654138570Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 655138570Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 656138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 657138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 658155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 659155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 660155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 661155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 662138570Ssam 663155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 664155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 665155515Ssam 666116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 667