if_athvar.h revision 166016
1116743Ssam/*- 2159938Ssam * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 3. Neither the names of the above-listed copyright holders nor the names 16116743Ssam * of any contributors may be used to endorse or promote products derived 17116743Ssam * from this software without specific prior written permission. 18116743Ssam * 19116743Ssam * Alternatively, this software may be distributed under the terms of the 20116743Ssam * GNU General Public License ("GPL") version 2 as published by the Free 21116743Ssam * Software Foundation. 22116743Ssam * 23116743Ssam * NO WARRANTY 24116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 35116743Ssam * 36116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 166016 2007-01-15 04:26:19Z sam $ 37116743Ssam */ 38116743Ssam 39116743Ssam/* 40116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 41116743Ssam */ 42116743Ssam#ifndef _DEV_ATH_ATHVAR_H 43116743Ssam#define _DEV_ATH_ATHVAR_H 44116743Ssam 45116743Ssam#include <sys/taskqueue.h> 46116743Ssam 47116743Ssam#include <contrib/dev/ath/ah.h> 48165185Ssam#include <contrib/dev/ath/ah_desc.h> 49119783Ssam#include <net80211/ieee80211_radiotap.h> 50116743Ssam#include <dev/ath/if_athioctl.h> 51138570Ssam#include <dev/ath/if_athrate.h> 52116743Ssam 53116743Ssam#define ATH_TIMEOUT 1000 54116743Ssam 55155481Ssam#ifndef ATH_RXBUF 56116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 57155481Ssam#endif 58155481Ssam#ifndef ATH_TXBUF 59140438Ssam#define ATH_TXBUF 100 /* number of TX buffers */ 60155481Ssam#endif 61140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 62138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 63155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 64138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 65116743Ssam 66147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 67147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 68147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 69147067Ssam 70147057Ssam/* 71147057Ssam * The key cache is used for h/w cipher state and also for 72147057Ssam * tracking station state such as the current tx antenna. 73147057Ssam * We also setup a mapping table between key cache slot indices 74147057Ssam * and station state to short-circuit node lookups on rx. 75147057Ssam * Different parts have different size key caches. We handle 76147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 77147057Ssam */ 78147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 79147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 80147057Ssam 81138570Ssam/* driver-specific node state */ 82116743Ssamstruct ath_node { 83119150Ssam struct ieee80211_node an_node; /* base class */ 84138570Ssam u_int32_t an_avgrssi; /* average rssi over all rx frames */ 85138570Ssam /* variable-length rate control state follows */ 86116743Ssam}; 87138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 88138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 89116743Ssam 90138570Ssam#define ATH_RSSI_LPF_LEN 10 91138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 92138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 93138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 94138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 95138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 96138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 97138570Ssam if ((y) >= -20) \ 98138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 99138570Ssam} while (0) 100138570Ssam 101116743Ssamstruct ath_buf { 102138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 103116743Ssam int bf_nseg; 104156073Ssam int bf_flags; /* tx descriptor flags */ 105116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 106165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 107116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 108138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 109116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 110116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 111116743Ssam bus_size_t bf_mapsize; 112140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 113116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 114116743Ssam}; 115138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 116116743Ssam 117138570Ssam/* 118138570Ssam * DMA state for tx/rx descriptors. 119138570Ssam */ 120138570Ssamstruct ath_descdma { 121138570Ssam const char* dd_name; 122138570Ssam struct ath_desc *dd_desc; /* descriptors */ 123138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 124158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 125138570Ssam bus_dma_segment_t dd_dseg; 126138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 127138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 128138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 129138570Ssam}; 130138570Ssam 131138570Ssam/* 132138570Ssam * Data transmit queue state. One of these exists for each 133138570Ssam * hardware transmit queue. Packets sent to us from above 134138570Ssam * are assigned to queues based on their priority. Not all 135138570Ssam * devices support a complete set of hardware transmit queues. 136138570Ssam * For those devices the array sc_ac2q will map multiple 137138570Ssam * priorities to fewer hardware queues (typically all to one 138138570Ssam * hardware queue). 139138570Ssam */ 140138570Ssamstruct ath_txq { 141138570Ssam u_int axq_qnum; /* hardware q number */ 142156073Ssam u_int axq_depth; /* queue depth (stat only) */ 143138570Ssam u_int axq_intrcnt; /* interrupt count */ 144138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 145138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 146138570Ssam struct mtx axq_lock; /* lock on q and link */ 147155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 148138570Ssam}; 149138570Ssam 150155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 151155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 152155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 153155482Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \ 154161425Simp} while (0) 155138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 156138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 157138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 158138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 159138570Ssam 160138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 161138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 162138570Ssam (_tq)->axq_depth++; \ 163138570Ssam} while (0) 164138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 165138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 166138570Ssam (_tq)->axq_depth--; \ 167138570Ssam} while (0) 168138570Ssam 169155491Ssamstruct taskqueue; 170155486Ssamstruct ath_tx99; 171155486Ssam 172116743Ssamstruct ath_softc { 173147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 174138570Ssam struct ath_stats sc_stats; /* interface statistics */ 175116743Ssam struct ieee80211com sc_ic; /* IEEE 802.11 common */ 176138570Ssam int sc_debug; 177165571Ssam u_int32_t sc_countrycode; 178165571Ssam u_int32_t sc_regdomain; 179138570Ssam void (*sc_recv_mgmt)(struct ieee80211com *, 180138570Ssam struct mbuf *, 181138570Ssam struct ieee80211_node *, 182138570Ssam int, int, u_int32_t); 183117812Ssam int (*sc_newstate)(struct ieee80211com *, 184117812Ssam enum ieee80211_state, int); 185138570Ssam void (*sc_node_free)(struct ieee80211_node *); 186116743Ssam device_t sc_dev; 187159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 188159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 189116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 190116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 191155491Ssam struct taskqueue *sc_tq; /* private task queue */ 192116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 193138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 194155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 195138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 196147057Ssam unsigned int sc_invalid : 1, /* disable hardware accesses */ 197138570Ssam sc_mrretry : 1, /* multi-rate retry support */ 198138570Ssam sc_softled : 1, /* enable LED gpio status */ 199138570Ssam sc_splitmic: 1, /* split TKIP MIC keys */ 200138570Ssam sc_needmib : 1, /* enable MIB stats intr */ 201138570Ssam sc_diversity : 1,/* enable rx diversity */ 202138570Ssam sc_hasveol : 1, /* tx VEOL support */ 203140432Ssam sc_ledstate: 1, /* LED on/off state */ 204144961Ssam sc_blinking: 1, /* LED blink operation active */ 205147057Ssam sc_mcastkey: 1, /* mcast key cache search */ 206155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 207165571Ssam sc_hasclrkey:1, /* CLR key supported */ 208165571Ssam sc_xchanmode: 1,/* extended channel mode */ 209165571Ssam sc_outdoor : 1;/* outdoor operation */ 210116743Ssam /* rate tables */ 211166013Ssam#define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0) 212166013Ssam#define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1) 213165571Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2]; 214116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 215116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 216155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 217138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 218138570Ssam HAL_CHANNEL sc_curchan; /* current h/w channel */ 219116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 220140432Ssam struct { 221140432Ssam u_int8_t ieeerate; /* IEEE rate */ 222140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 223140761Ssam u_int8_t txflags; /* radiotap tx flags */ 224140432Ssam u_int16_t ledon; /* softled on time */ 225140432Ssam u_int16_t ledoff; /* softled off time */ 226140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 227155477Ssam u_int8_t sc_minrateix; /* min h/w rate index */ 228155483Ssam u_int8_t sc_mcastrix; /* mcast h/w rate index */ 229138570Ssam u_int8_t sc_protrix; /* protection rate index */ 230155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 231138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 232116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 233138570Ssam u_int sc_keymax; /* size of key cache */ 234147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 235116743Ssam 236140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 237140432Ssam u_int sc_ledon; /* pin setting for LED on */ 238140432Ssam u_int sc_ledidle; /* idle polling interval */ 239140432Ssam int sc_ledevent; /* time of last LED event */ 240140432Ssam u_int8_t sc_rxrate; /* current rx rate for LED */ 241140432Ssam u_int8_t sc_txrate; /* current tx rate for LED */ 242140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 243140432Ssam struct callout sc_ledtimer; /* led off timer */ 244138570Ssam 245155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 246155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 247155515Ssam 248119783Ssam struct bpf_if *sc_drvbpf; 249119783Ssam union { 250119783Ssam struct ath_tx_radiotap_header th; 251119783Ssam u_int8_t pad[64]; 252119783Ssam } u_tx_rt; 253127698Ssam int sc_tx_th_len; 254119783Ssam union { 255140761Ssam struct ath_rx_radiotap_header th; 256119783Ssam u_int8_t pad[64]; 257119783Ssam } u_rx_rt; 258140761Ssam int sc_rx_th_len; 259154140Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 260119783Ssam 261138570Ssam struct ath_descdma sc_rxdma; /* RX descriptos */ 262138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 263116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 264116743Ssam struct task sc_rxtask; /* rx int processing */ 265138570Ssam struct task sc_rxorntask; /* rxorn int processing */ 266138570Ssam u_int8_t sc_defant; /* current default antenna */ 267138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 268155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 269116743Ssam 270138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 271138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 272138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 273155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 274116743Ssam int sc_tx_timer; /* transmit timeout */ 275138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 276138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 277138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 278138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 279116743Ssam struct task sc_txtask; /* tx int processing */ 280116743Ssam 281138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 282138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 283116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 284138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 285138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 286138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 287138570Ssam struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 288116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 289138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 290138570Ssam enum { 291138570Ssam OK, /* no change needed */ 292138570Ssam UPDATE, /* update pending */ 293138570Ssam COMMIT /* beacon sent, commit change */ 294138570Ssam } sc_updateslot; /* slot time update fsm */ 295159938Ssam struct ath_txq sc_mcastq; /* mcast xmits w/ ps sta's */ 296116743Ssam 297116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 298155515Ssam int sc_calinterval; /* current polling interval */ 299155515Ssam int sc_caltries; /* cals at current interval */ 300155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 301116743Ssam struct callout sc_scan_ch; /* callout handle for scan */ 302155515Ssam struct callout sc_dfs_ch; /* callout handle for dfs */ 303116743Ssam}; 304119783Ssam#define sc_tx_th u_tx_rt.th 305140761Ssam#define sc_rx_th u_rx_rt.th 306116743Ssam 307121100Ssam#define ATH_LOCK_INIT(_sc) \ 308121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 309121100Ssam MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 310121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 311121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 312121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 313121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 314121100Ssam 315138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 316138570Ssam 317155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 318155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 319155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 320155482Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \ 321155482Ssam} while (0) 322121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 323121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 324121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 325121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 326121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 327121100Ssam 328116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 329116743Ssamint ath_detach(struct ath_softc *); 330116743Ssamvoid ath_resume(struct ath_softc *); 331116743Ssamvoid ath_suspend(struct ath_softc *); 332116743Ssamvoid ath_shutdown(struct ath_softc *); 333116743Ssamvoid ath_intr(void *); 334116743Ssam 335116743Ssam/* 336116743Ssam * HAL definitions to comply with local coding convention. 337116743Ssam */ 338138570Ssam#define ath_hal_detach(_ah) \ 339138570Ssam ((*(_ah)->ah_detach)((_ah))) 340116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 341116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 342116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 343116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 344116743Ssam#define ath_hal_getmac(_ah, _mac) \ 345116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 346138570Ssam#define ath_hal_setmac(_ah, _mac) \ 347138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 348116743Ssam#define ath_hal_intrset(_ah, _mask) \ 349116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 350116743Ssam#define ath_hal_intrget(_ah) \ 351116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 352116743Ssam#define ath_hal_intrpend(_ah) \ 353116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 354116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 355116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 356116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 357116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 358155515Ssam#define ath_hal_setpower(_ah, _mode) \ 359155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 360138570Ssam#define ath_hal_keycachesize(_ah) \ 361138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 362116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 363116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 364138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 365138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 366116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 367116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 368116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 369116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 370116743Ssam#define ath_hal_getrxfilter(_ah) \ 371116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 372116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 373116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 374116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 375116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 376116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 377116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 378116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 379116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 380116743Ssam#define ath_hal_gettsf32(_ah) \ 381116743Ssam ((*(_ah)->ah_getTsf32)((_ah))) 382116743Ssam#define ath_hal_gettsf64(_ah) \ 383116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 384116743Ssam#define ath_hal_resettsf(_ah) \ 385116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 386116743Ssam#define ath_hal_rxena(_ah) \ 387116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 388116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 389116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 390116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 391116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 392138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 393138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 394116743Ssam#define ath_hal_getrxbuf(_ah) \ 395116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 396116743Ssam#define ath_hal_txstart(_ah, _q) \ 397116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 398116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 399116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 400155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 401155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 402116743Ssam#define ath_hal_setledstate(_ah, _state) \ 403116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 404138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 405138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 406116743Ssam#define ath_hal_beaconreset(_ah) \ 407116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 408138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 409138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 410116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 411138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 412138570Ssam#define ath_hal_phydisable(_ah) \ 413138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 414138570Ssam#define ath_hal_setopmode(_ah) \ 415138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 416116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 417116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 418116743Ssam#define ath_hal_stoppcurecv(_ah) \ 419116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 420116743Ssam#define ath_hal_startpcurecv(_ah) \ 421116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 422116743Ssam#define ath_hal_stopdmarecv(_ah) \ 423116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 424138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 425138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 426138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 427155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 428163187Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (void **)(_outdata), _outsize) 429116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 430116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 431116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 432116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 433116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 434116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 435138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 436138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 437138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 438138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 439116743Ssam#define ath_hal_getrfgain(_ah) \ 440116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 441138570Ssam#define ath_hal_getdefantenna(_ah) \ 442138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 443138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 444138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 445155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 446155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 447138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 448138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 449138570Ssam#define ath_hal_setslottime(_ah, _us) \ 450138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 451138570Ssam#define ath_hal_getslottime(_ah) \ 452138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 453138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 454138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 455138570Ssam#define ath_hal_getacktimeout(_ah) \ 456138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 457138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 458138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 459138570Ssam#define ath_hal_getctstimeout(_ah) \ 460138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 461138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 462138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 463138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 464138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 465138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 466138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 467138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 468155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 469155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 470155489Ssam ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL)) 471138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 472138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 473162410Ssam#define ath_hal_hastkipsplit(_ah) \ 474138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 475162410Ssam#define ath_hal_gettkipsplit(_ah) \ 476162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 477162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 478162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 479138570Ssam#define ath_hal_hwphycounters(_ah) \ 480138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 481138570Ssam#define ath_hal_hasdiversity(_ah) \ 482138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 483138570Ssam#define ath_hal_getdiversity(_ah) \ 484138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 485138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 486138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 487138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 488138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 489138570Ssam#define ath_hal_setdiag(_ah, _v) \ 490138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 491138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 492138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 493138570Ssam#define ath_hal_hasveol(_ah) \ 494138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 495138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 496138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 497138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 498138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 499138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 500138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 501138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 502138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 503138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 504138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 505138570Ssam#define ath_hal_settpscale(_ah, _v) \ 506138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 507138570Ssam#define ath_hal_hastpc(_ah) \ 508138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 509138570Ssam#define ath_hal_gettpc(_ah) \ 510138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 511138570Ssam#define ath_hal_settpc(_ah, _v) \ 512138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 513138570Ssam#define ath_hal_hasbursting(_ah) \ 514138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 515147057Ssam#ifdef notyet 516147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 517147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 518147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 519147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 520147057Ssam#else 521147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 522147057Ssam#endif 523155515Ssam#define ath_hal_hasrfsilent(_ah) \ 524155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 525155515Ssam#define ath_hal_getrfkill(_ah) \ 526155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 527155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 528155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 529155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 530155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 531155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 532155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 533155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 534155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 535155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 536155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 537155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 538155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 539155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 540155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 541154140Ssam#if HAL_ABI_VERSION < 0x05120700 542154140Ssam#define ath_hal_process_noisefloor(_ah) 543154140Ssam#define ath_hal_getchannoise(_ah, _c) (-96) 544154140Ssam#define HAL_CAP_TPC_ACK 100 545154140Ssam#define HAL_CAP_TPC_CTS 101 546154140Ssam#else 547154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 548154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 549154140Ssam#endif 550155515Ssam#if HAL_ABI_VERSION < 0x05122200 551155515Ssam#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 552155515Ssam#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 553155515Ssam#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 554155515Ssam#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 555155515Ssam#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 556155515Ssam#endif 557165571Ssam#if HAL_ABI_VERSION < 0x06102501 558165571Ssam#define ath_hal_ispublicsafetysku(ah) \ 559165571Ssam (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 560165571Ssam (ah)->ah_regdomain == 0x12) 561165571Ssam#endif 562166016Ssam#if HAL_ABI_VERSION < 0x06122400 563166016Ssam/* XXX yech, can't get to regdomain so just hack a compat shim */ 564166016Ssam#define ath_hal_isgsmsku(ah) \ 565166016Ssam ((ah)->ah_countryCode == 843) 566166016Ssam#endif 567116743Ssam 568116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 569116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 570165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 571165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 572116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 573116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 574116743Ssam _rtsrate, _rtsdura) \ 575116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 576116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 577155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 578138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 579116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 580138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 581116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 582138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 583138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 584165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 585165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 586155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 587155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 588116743Ssam 589138570Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 590138570Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 591138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 592138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 593155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 594155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 595155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 596155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 597138570Ssam 598155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 599155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 600155515Ssam 601116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 602