if_athvar.h revision 165185
1116743Ssam/*- 2159938Ssam * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 3. Neither the names of the above-listed copyright holders nor the names 16116743Ssam * of any contributors may be used to endorse or promote products derived 17116743Ssam * from this software without specific prior written permission. 18116743Ssam * 19116743Ssam * Alternatively, this software may be distributed under the terms of the 20116743Ssam * GNU General Public License ("GPL") version 2 as published by the Free 21116743Ssam * Software Foundation. 22116743Ssam * 23116743Ssam * NO WARRANTY 24116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 35116743Ssam * 36116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 165185 2006-12-13 19:34:35Z sam $ 37116743Ssam */ 38116743Ssam 39116743Ssam/* 40116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 41116743Ssam */ 42116743Ssam#ifndef _DEV_ATH_ATHVAR_H 43116743Ssam#define _DEV_ATH_ATHVAR_H 44116743Ssam 45116743Ssam#include <sys/taskqueue.h> 46116743Ssam 47116743Ssam#include <contrib/dev/ath/ah.h> 48165185Ssam#include <contrib/dev/ath/ah_desc.h> 49119783Ssam#include <net80211/ieee80211_radiotap.h> 50116743Ssam#include <dev/ath/if_athioctl.h> 51138570Ssam#include <dev/ath/if_athrate.h> 52116743Ssam 53116743Ssam#define ATH_TIMEOUT 1000 54116743Ssam 55155481Ssam#ifndef ATH_RXBUF 56116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 57155481Ssam#endif 58155481Ssam#ifndef ATH_TXBUF 59140438Ssam#define ATH_TXBUF 100 /* number of TX buffers */ 60155481Ssam#endif 61140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 62138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 63155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 64138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 65116743Ssam 66147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 67147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 68147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 69147067Ssam 70147057Ssam/* 71147057Ssam * The key cache is used for h/w cipher state and also for 72147057Ssam * tracking station state such as the current tx antenna. 73147057Ssam * We also setup a mapping table between key cache slot indices 74147057Ssam * and station state to short-circuit node lookups on rx. 75147057Ssam * Different parts have different size key caches. We handle 76147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 77147057Ssam */ 78147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 79147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 80147057Ssam 81138570Ssam/* driver-specific node state */ 82116743Ssamstruct ath_node { 83119150Ssam struct ieee80211_node an_node; /* base class */ 84138570Ssam u_int32_t an_avgrssi; /* average rssi over all rx frames */ 85138570Ssam /* variable-length rate control state follows */ 86116743Ssam}; 87138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 88138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 89116743Ssam 90138570Ssam#define ATH_RSSI_LPF_LEN 10 91138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 92138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 93138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 94138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 95138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 96138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 97138570Ssam if ((y) >= -20) \ 98138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 99138570Ssam} while (0) 100138570Ssam 101116743Ssamstruct ath_buf { 102138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 103116743Ssam int bf_nseg; 104156073Ssam int bf_flags; /* tx descriptor flags */ 105116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 106165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 107116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 108138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 109116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 110116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 111116743Ssam bus_size_t bf_mapsize; 112140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 113116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 114116743Ssam}; 115138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 116116743Ssam 117138570Ssam/* 118138570Ssam * DMA state for tx/rx descriptors. 119138570Ssam */ 120138570Ssamstruct ath_descdma { 121138570Ssam const char* dd_name; 122138570Ssam struct ath_desc *dd_desc; /* descriptors */ 123138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 124158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 125138570Ssam bus_dma_segment_t dd_dseg; 126138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 127138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 128138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 129138570Ssam}; 130138570Ssam 131138570Ssam/* 132138570Ssam * Data transmit queue state. One of these exists for each 133138570Ssam * hardware transmit queue. Packets sent to us from above 134138570Ssam * are assigned to queues based on their priority. Not all 135138570Ssam * devices support a complete set of hardware transmit queues. 136138570Ssam * For those devices the array sc_ac2q will map multiple 137138570Ssam * priorities to fewer hardware queues (typically all to one 138138570Ssam * hardware queue). 139138570Ssam */ 140138570Ssamstruct ath_txq { 141138570Ssam u_int axq_qnum; /* hardware q number */ 142156073Ssam u_int axq_depth; /* queue depth (stat only) */ 143138570Ssam u_int axq_intrcnt; /* interrupt count */ 144138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 145138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 146138570Ssam struct mtx axq_lock; /* lock on q and link */ 147155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 148138570Ssam}; 149138570Ssam 150155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 151155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 152155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 153155482Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \ 154161425Simp} while (0) 155138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 156138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 157138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 158138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 159138570Ssam 160138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 161138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 162138570Ssam (_tq)->axq_depth++; \ 163138570Ssam} while (0) 164138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 165138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 166138570Ssam (_tq)->axq_depth--; \ 167138570Ssam} while (0) 168138570Ssam 169155491Ssamstruct taskqueue; 170155486Ssamstruct ath_tx99; 171155486Ssam 172116743Ssamstruct ath_softc { 173147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 174138570Ssam struct ath_stats sc_stats; /* interface statistics */ 175116743Ssam struct ieee80211com sc_ic; /* IEEE 802.11 common */ 176138570Ssam int sc_countrycode; 177138570Ssam int sc_debug; 178138570Ssam void (*sc_recv_mgmt)(struct ieee80211com *, 179138570Ssam struct mbuf *, 180138570Ssam struct ieee80211_node *, 181138570Ssam int, int, u_int32_t); 182117812Ssam int (*sc_newstate)(struct ieee80211com *, 183117812Ssam enum ieee80211_state, int); 184138570Ssam void (*sc_node_free)(struct ieee80211_node *); 185116743Ssam device_t sc_dev; 186159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 187159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 188116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 189116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 190155491Ssam struct taskqueue *sc_tq; /* private task queue */ 191116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 192138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 193155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 194138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 195147057Ssam unsigned int sc_invalid : 1, /* disable hardware accesses */ 196138570Ssam sc_mrretry : 1, /* multi-rate retry support */ 197138570Ssam sc_softled : 1, /* enable LED gpio status */ 198138570Ssam sc_splitmic: 1, /* split TKIP MIC keys */ 199138570Ssam sc_needmib : 1, /* enable MIB stats intr */ 200138570Ssam sc_diversity : 1,/* enable rx diversity */ 201138570Ssam sc_hasveol : 1, /* tx VEOL support */ 202140432Ssam sc_ledstate: 1, /* LED on/off state */ 203144961Ssam sc_blinking: 1, /* LED blink operation active */ 204147057Ssam sc_mcastkey: 1, /* mcast key cache search */ 205155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 206147057Ssam sc_hasclrkey:1; /* CLR key supported */ 207116743Ssam /* rate tables */ 208116743Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 209116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 210116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 211155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 212138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 213138570Ssam HAL_CHANNEL sc_curchan; /* current h/w channel */ 214116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 215140432Ssam struct { 216140432Ssam u_int8_t ieeerate; /* IEEE rate */ 217140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 218140761Ssam u_int8_t txflags; /* radiotap tx flags */ 219140432Ssam u_int16_t ledon; /* softled on time */ 220140432Ssam u_int16_t ledoff; /* softled off time */ 221140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 222155477Ssam u_int8_t sc_minrateix; /* min h/w rate index */ 223155483Ssam u_int8_t sc_mcastrix; /* mcast h/w rate index */ 224138570Ssam u_int8_t sc_protrix; /* protection rate index */ 225155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 226138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 227116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 228138570Ssam u_int sc_keymax; /* size of key cache */ 229147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 230116743Ssam 231140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 232140432Ssam u_int sc_ledon; /* pin setting for LED on */ 233140432Ssam u_int sc_ledidle; /* idle polling interval */ 234140432Ssam int sc_ledevent; /* time of last LED event */ 235140432Ssam u_int8_t sc_rxrate; /* current rx rate for LED */ 236140432Ssam u_int8_t sc_txrate; /* current tx rate for LED */ 237140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 238140432Ssam struct callout sc_ledtimer; /* led off timer */ 239138570Ssam 240155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 241155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 242155515Ssam 243119783Ssam struct bpf_if *sc_drvbpf; 244119783Ssam union { 245119783Ssam struct ath_tx_radiotap_header th; 246119783Ssam u_int8_t pad[64]; 247119783Ssam } u_tx_rt; 248127698Ssam int sc_tx_th_len; 249119783Ssam union { 250140761Ssam struct ath_rx_radiotap_header th; 251119783Ssam u_int8_t pad[64]; 252119783Ssam } u_rx_rt; 253140761Ssam int sc_rx_th_len; 254154140Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 255119783Ssam 256138570Ssam struct ath_descdma sc_rxdma; /* RX descriptos */ 257138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 258116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 259116743Ssam struct task sc_rxtask; /* rx int processing */ 260138570Ssam struct task sc_rxorntask; /* rxorn int processing */ 261138570Ssam u_int8_t sc_defant; /* current default antenna */ 262138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 263155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 264116743Ssam 265138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 266138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 267138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 268155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 269116743Ssam int sc_tx_timer; /* transmit timeout */ 270138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 271138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 272138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 273138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 274116743Ssam struct task sc_txtask; /* tx int processing */ 275116743Ssam 276138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 277138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 278116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 279138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 280138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 281138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 282138570Ssam struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 283116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 284138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 285138570Ssam enum { 286138570Ssam OK, /* no change needed */ 287138570Ssam UPDATE, /* update pending */ 288138570Ssam COMMIT /* beacon sent, commit change */ 289138570Ssam } sc_updateslot; /* slot time update fsm */ 290159938Ssam struct ath_txq sc_mcastq; /* mcast xmits w/ ps sta's */ 291116743Ssam 292116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 293155515Ssam int sc_calinterval; /* current polling interval */ 294155515Ssam int sc_caltries; /* cals at current interval */ 295155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 296116743Ssam struct callout sc_scan_ch; /* callout handle for scan */ 297155515Ssam struct callout sc_dfs_ch; /* callout handle for dfs */ 298116743Ssam}; 299119783Ssam#define sc_tx_th u_tx_rt.th 300140761Ssam#define sc_rx_th u_rx_rt.th 301116743Ssam 302121100Ssam#define ATH_LOCK_INIT(_sc) \ 303121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 304121100Ssam MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 305121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 306121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 307121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 308121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 309121100Ssam 310138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 311138570Ssam 312155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 313155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 314155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 315155482Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \ 316155482Ssam} while (0) 317121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 318121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 319121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 320121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 321121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 322121100Ssam 323116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 324116743Ssamint ath_detach(struct ath_softc *); 325116743Ssamvoid ath_resume(struct ath_softc *); 326116743Ssamvoid ath_suspend(struct ath_softc *); 327116743Ssamvoid ath_shutdown(struct ath_softc *); 328116743Ssamvoid ath_intr(void *); 329116743Ssam 330116743Ssam/* 331116743Ssam * HAL definitions to comply with local coding convention. 332116743Ssam */ 333138570Ssam#define ath_hal_detach(_ah) \ 334138570Ssam ((*(_ah)->ah_detach)((_ah))) 335116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 336116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 337116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 338116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 339116743Ssam#define ath_hal_getmac(_ah, _mac) \ 340116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 341138570Ssam#define ath_hal_setmac(_ah, _mac) \ 342138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 343116743Ssam#define ath_hal_intrset(_ah, _mask) \ 344116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 345116743Ssam#define ath_hal_intrget(_ah) \ 346116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 347116743Ssam#define ath_hal_intrpend(_ah) \ 348116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 349116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 350116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 351116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 352116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 353155515Ssam#define ath_hal_setpower(_ah, _mode) \ 354155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 355138570Ssam#define ath_hal_keycachesize(_ah) \ 356138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 357116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 358116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 359138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 360138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 361116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 362116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 363116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 364116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 365116743Ssam#define ath_hal_getrxfilter(_ah) \ 366116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 367116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 368116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 369116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 370116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 371116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 372116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 373116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 374116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 375116743Ssam#define ath_hal_gettsf32(_ah) \ 376116743Ssam ((*(_ah)->ah_getTsf32)((_ah))) 377116743Ssam#define ath_hal_gettsf64(_ah) \ 378116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 379116743Ssam#define ath_hal_resettsf(_ah) \ 380116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 381116743Ssam#define ath_hal_rxena(_ah) \ 382116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 383116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 384116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 385116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 386116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 387138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 388138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 389116743Ssam#define ath_hal_getrxbuf(_ah) \ 390116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 391116743Ssam#define ath_hal_txstart(_ah, _q) \ 392116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 393116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 394116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 395155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 396155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 397116743Ssam#define ath_hal_setledstate(_ah, _state) \ 398116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 399138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 400138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 401116743Ssam#define ath_hal_beaconreset(_ah) \ 402116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 403138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 404138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 405116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 406138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 407138570Ssam#define ath_hal_phydisable(_ah) \ 408138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 409138570Ssam#define ath_hal_setopmode(_ah) \ 410138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 411116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 412116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 413116743Ssam#define ath_hal_stoppcurecv(_ah) \ 414116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 415116743Ssam#define ath_hal_startpcurecv(_ah) \ 416116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 417116743Ssam#define ath_hal_stopdmarecv(_ah) \ 418116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 419138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 420138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 421138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 422155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 423163187Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (void **)(_outdata), _outsize) 424116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 425116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 426116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 427116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 428116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 429116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 430138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 431138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 432138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 433138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 434116743Ssam#define ath_hal_getrfgain(_ah) \ 435116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 436138570Ssam#define ath_hal_getdefantenna(_ah) \ 437138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 438138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 439138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 440155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 441155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 442138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 443138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 444138570Ssam#define ath_hal_setslottime(_ah, _us) \ 445138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 446138570Ssam#define ath_hal_getslottime(_ah) \ 447138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 448138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 449138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 450138570Ssam#define ath_hal_getacktimeout(_ah) \ 451138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 452138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 453138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 454138570Ssam#define ath_hal_getctstimeout(_ah) \ 455138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 456138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 457138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 458138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 459138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 460138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 461138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 462138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 463155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 464155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 465155489Ssam ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL)) 466138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 467138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 468162410Ssam#define ath_hal_hastkipsplit(_ah) \ 469138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 470162410Ssam#define ath_hal_gettkipsplit(_ah) \ 471162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 472162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 473162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 474138570Ssam#define ath_hal_hwphycounters(_ah) \ 475138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 476138570Ssam#define ath_hal_hasdiversity(_ah) \ 477138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 478138570Ssam#define ath_hal_getdiversity(_ah) \ 479138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 480138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 481138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 482138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 483138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 484138570Ssam#define ath_hal_setdiag(_ah, _v) \ 485138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 486138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 487138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 488138570Ssam#define ath_hal_hasveol(_ah) \ 489138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 490138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 491138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 492138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 493138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 494138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 495138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 496138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 497138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 498138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 499138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 500138570Ssam#define ath_hal_settpscale(_ah, _v) \ 501138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 502138570Ssam#define ath_hal_hastpc(_ah) \ 503138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 504138570Ssam#define ath_hal_gettpc(_ah) \ 505138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 506138570Ssam#define ath_hal_settpc(_ah, _v) \ 507138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 508138570Ssam#define ath_hal_hasbursting(_ah) \ 509138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 510147057Ssam#ifdef notyet 511147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 512147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 513147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 514147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 515147057Ssam#else 516147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 517147057Ssam#endif 518155515Ssam#define ath_hal_hasrfsilent(_ah) \ 519155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 520155515Ssam#define ath_hal_getrfkill(_ah) \ 521155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 522155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 523155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 524155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 525155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 526155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 527155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 528155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 529155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 530155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 531155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 532155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 533155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 534155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 535155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 536154140Ssam#if HAL_ABI_VERSION < 0x05120700 537154140Ssam#define ath_hal_process_noisefloor(_ah) 538154140Ssam#define ath_hal_getchannoise(_ah, _c) (-96) 539154140Ssam#define HAL_CAP_TPC_ACK 100 540154140Ssam#define HAL_CAP_TPC_CTS 101 541154140Ssam#else 542154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 543154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 544154140Ssam#endif 545155515Ssam#if HAL_ABI_VERSION < 0x05122200 546155515Ssam#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 547155515Ssam#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 548155515Ssam#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 549155515Ssam#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 550155515Ssam#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 551155515Ssam#endif 552116743Ssam 553116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 554116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 555165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 556165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 557116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 558116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 559116743Ssam _rtsrate, _rtsdura) \ 560116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 561116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 562155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 563138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 564116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 565138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 566116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 567138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 568138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 569165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 570165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 571155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 572155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 573116743Ssam 574138570Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 575138570Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 576138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 577138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 578155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 579155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 580155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 581155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 582138570Ssam 583155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 584155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 585155515Ssam 586116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 587