if_athvar.h revision 162410
1/*-
2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 *    of any contributors may be used to endorse or promote products derived
17 *    from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 162410 2006-09-18 16:26:19Z sam $
37 */
38
39/*
40 * Defintions for the Atheros Wireless LAN controller driver.
41 */
42#ifndef _DEV_ATH_ATHVAR_H
43#define _DEV_ATH_ATHVAR_H
44
45#include <sys/taskqueue.h>
46
47#include <contrib/dev/ath/ah.h>
48#include <net80211/ieee80211_radiotap.h>
49#include <dev/ath/if_athioctl.h>
50#include <dev/ath/if_athrate.h>
51
52#define	ATH_TIMEOUT		1000
53
54#ifndef ATH_RXBUF
55#define	ATH_RXBUF	40		/* number of RX buffers */
56#endif
57#ifndef ATH_TXBUF
58#define	ATH_TXBUF	100		/* number of TX buffers */
59#endif
60#define	ATH_TXDESC	10		/* number of descriptors per buffer */
61#define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
62#define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
63#define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
64
65#define	ATH_BEACON_AIFS_DEFAULT	 0	/* default aifs for ap beacon q */
66#define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
67#define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
68
69/*
70 * The key cache is used for h/w cipher state and also for
71 * tracking station state such as the current tx antenna.
72 * We also setup a mapping table between key cache slot indices
73 * and station state to short-circuit node lookups on rx.
74 * Different parts have different size key caches.  We handle
75 * up to ATH_KEYMAX entries (could dynamically allocate state).
76 */
77#define	ATH_KEYMAX	128		/* max key cache size we handle */
78#define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
79
80/* driver-specific node state */
81struct ath_node {
82	struct ieee80211_node an_node;	/* base class */
83	u_int32_t	an_avgrssi;	/* average rssi over all rx frames */
84	/* variable-length rate control state follows */
85};
86#define	ATH_NODE(ni)	((struct ath_node *)(ni))
87#define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
88
89#define ATH_RSSI_LPF_LEN	10
90#define ATH_RSSI_DUMMY_MARKER	0x127
91#define ATH_EP_MUL(x, mul)	((x) * (mul))
92#define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
93#define ATH_LPF_RSSI(x, y, len) \
94    ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
95#define ATH_RSSI_LPF(x, y) do {						\
96    if ((y) >= -20)							\
97    	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
98} while (0)
99
100struct ath_buf {
101	STAILQ_ENTRY(ath_buf)	bf_list;
102	int			bf_nseg;
103	int			bf_flags;	/* tx descriptor flags */
104	struct ath_desc		*bf_desc;	/* virtual addr of desc */
105	bus_addr_t		bf_daddr;	/* physical addr of desc */
106	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
107	struct mbuf		*bf_m;		/* mbuf for buf */
108	struct ieee80211_node	*bf_node;	/* pointer to the node */
109	bus_size_t		bf_mapsize;
110#define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
111	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
112};
113typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
114
115/*
116 * DMA state for tx/rx descriptors.
117 */
118struct ath_descdma {
119	const char*		dd_name;
120	struct ath_desc		*dd_desc;	/* descriptors */
121	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
122	bus_size_t		dd_desc_len;	/* size of dd_desc */
123	bus_dma_segment_t	dd_dseg;
124	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
125	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
126	struct ath_buf		*dd_bufptr;	/* associated buffers */
127};
128
129/*
130 * Data transmit queue state.  One of these exists for each
131 * hardware transmit queue.  Packets sent to us from above
132 * are assigned to queues based on their priority.  Not all
133 * devices support a complete set of hardware transmit queues.
134 * For those devices the array sc_ac2q will map multiple
135 * priorities to fewer hardware queues (typically all to one
136 * hardware queue).
137 */
138struct ath_txq {
139	u_int			axq_qnum;	/* hardware q number */
140	u_int			axq_depth;	/* queue depth (stat only) */
141	u_int			axq_intrcnt;	/* interrupt count */
142	u_int32_t		*axq_link;	/* link ptr in last TX desc */
143	STAILQ_HEAD(, ath_buf)	axq_q;		/* transmit queue */
144	struct mtx		axq_lock;	/* lock on q and link */
145	char			axq_name[12];	/* e.g. "ath0_txq4" */
146};
147
148#define	ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
149	snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
150		device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
151	mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \
152} while (0)
153#define	ATH_TXQ_LOCK_DESTROY(_tq)	mtx_destroy(&(_tq)->axq_lock)
154#define	ATH_TXQ_LOCK(_tq)		mtx_lock(&(_tq)->axq_lock)
155#define	ATH_TXQ_UNLOCK(_tq)		mtx_unlock(&(_tq)->axq_lock)
156#define	ATH_TXQ_LOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock, MA_OWNED)
157
158#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
159	STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
160	(_tq)->axq_depth++; \
161} while (0)
162#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
163	STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
164	(_tq)->axq_depth--; \
165} while (0)
166
167struct taskqueue;
168struct ath_tx99;
169
170struct ath_softc {
171	struct ifnet		*sc_ifp;	/* interface common */
172	struct ath_stats	sc_stats;	/* interface statistics */
173	struct ieee80211com	sc_ic;		/* IEEE 802.11 common */
174	int			sc_countrycode;
175	int			sc_debug;
176	void			(*sc_recv_mgmt)(struct ieee80211com *,
177					struct mbuf *,
178					struct ieee80211_node *,
179					int, int, u_int32_t);
180	int			(*sc_newstate)(struct ieee80211com *,
181					enum ieee80211_state, int);
182	void 			(*sc_node_free)(struct ieee80211_node *);
183	device_t		sc_dev;
184	HAL_BUS_TAG		sc_st;		/* bus space tag */
185	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
186	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
187	struct mtx		sc_mtx;		/* master lock (recursive) */
188	struct taskqueue	*sc_tq;		/* private task queue */
189	struct ath_hal		*sc_ah;		/* Atheros HAL */
190	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
191	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
192	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
193	unsigned int		sc_invalid : 1,	/* disable hardware accesses */
194				sc_mrretry : 1,	/* multi-rate retry support */
195				sc_softled : 1,	/* enable LED gpio status */
196				sc_splitmic: 1,	/* split TKIP MIC keys */
197				sc_needmib : 1,	/* enable MIB stats intr */
198				sc_diversity : 1,/* enable rx diversity */
199				sc_hasveol : 1,	/* tx VEOL support */
200				sc_ledstate: 1,	/* LED on/off state */
201				sc_blinking: 1,	/* LED blink operation active */
202				sc_mcastkey: 1,	/* mcast key cache search */
203				sc_syncbeacon:1,/* sync/resync beacon timers */
204				sc_hasclrkey:1;	/* CLR key supported */
205						/* rate tables */
206	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
207	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
208	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
209	HAL_OPMODE		sc_opmode;	/* current operating mode */
210	u_int16_t		sc_curtxpow;	/* current tx power limit */
211	HAL_CHANNEL		sc_curchan;	/* current h/w channel */
212	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
213	struct {
214		u_int8_t	ieeerate;	/* IEEE rate */
215		u_int8_t	rxflags;	/* radiotap rx flags */
216		u_int8_t	txflags;	/* radiotap tx flags */
217		u_int16_t	ledon;		/* softled on time */
218		u_int16_t	ledoff;		/* softled off time */
219	} sc_hwmap[32];				/* h/w rate ix mappings */
220	u_int8_t		sc_minrateix;	/* min h/w rate index */
221	u_int8_t		sc_mcastrix;	/* mcast h/w rate index */
222	u_int8_t		sc_protrix;	/* protection rate index */
223	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
224	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
225	HAL_INT			sc_imask;	/* interrupt mask copy */
226	u_int			sc_keymax;	/* size of key cache */
227	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
228
229	u_int			sc_ledpin;	/* GPIO pin for driving LED */
230	u_int			sc_ledon;	/* pin setting for LED on */
231	u_int			sc_ledidle;	/* idle polling interval */
232	int			sc_ledevent;	/* time of last LED event */
233	u_int8_t		sc_rxrate;	/* current rx rate for LED */
234	u_int8_t		sc_txrate;	/* current tx rate for LED */
235	u_int16_t		sc_ledoff;	/* off time for current blink */
236	struct callout		sc_ledtimer;	/* led off timer */
237
238	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
239	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
240
241	struct bpf_if		*sc_drvbpf;
242	union {
243		struct ath_tx_radiotap_header th;
244		u_int8_t	pad[64];
245	} u_tx_rt;
246	int			sc_tx_th_len;
247	union {
248		struct ath_rx_radiotap_header th;
249		u_int8_t	pad[64];
250	} u_rx_rt;
251	int			sc_rx_th_len;
252	u_int			sc_monpass;	/* frames to pass in mon.mode */
253
254	struct ath_descdma	sc_rxdma;	/* RX descriptos */
255	ath_bufhead		sc_rxbuf;	/* receive buffer */
256	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
257	struct task		sc_rxtask;	/* rx int processing */
258	struct task		sc_rxorntask;	/* rxorn int processing */
259	u_int8_t		sc_defant;	/* current default antenna */
260	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
261	u_int64_t		sc_lastrx;	/* tsf at last rx'd frame */
262
263	struct ath_descdma	sc_txdma;	/* TX descriptors */
264	ath_bufhead		sc_txbuf;	/* transmit buffer */
265	struct mtx		sc_txbuflock;	/* txbuf lock */
266	char			sc_txname[12];	/* e.g. "ath0_buf" */
267	int			sc_tx_timer;	/* transmit timeout */
268	u_int			sc_txqsetup;	/* h/w queues setup */
269	u_int			sc_txintrperiod;/* tx interrupt batching */
270	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
271	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
272	struct task		sc_txtask;	/* tx int processing */
273
274	struct ath_descdma	sc_bdma;	/* beacon descriptors */
275	ath_bufhead		sc_bbuf;	/* beacon buffers */
276	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
277	u_int			sc_bmisscount;	/* missed beacon transmits */
278	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
279	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
280	struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
281	struct task		sc_bmisstask;	/* bmiss int processing */
282	struct task		sc_bstucktask;	/* stuck beacon processing */
283	enum {
284		OK,				/* no change needed */
285		UPDATE,				/* update pending */
286		COMMIT				/* beacon sent, commit change */
287	} sc_updateslot;			/* slot time update fsm */
288	struct ath_txq		sc_mcastq;	/* mcast xmits w/ ps sta's */
289
290	struct callout		sc_cal_ch;	/* callout handle for cals */
291	int			sc_calinterval;	/* current polling interval */
292	int			sc_caltries;	/* cals at current interval */
293	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
294	struct callout		sc_scan_ch;	/* callout handle for scan */
295	struct callout		sc_dfs_ch;	/* callout handle for dfs */
296};
297#define	sc_tx_th		u_tx_rt.th
298#define	sc_rx_th		u_rx_rt.th
299
300#define	ATH_LOCK_INIT(_sc) \
301	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
302		 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
303#define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
304#define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
305#define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
306#define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
307
308#define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
309
310#define	ATH_TXBUF_LOCK_INIT(_sc) do { \
311	snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
312		device_get_nameunit((_sc)->sc_dev)); \
313	mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \
314} while (0)
315#define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
316#define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
317#define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
318#define	ATH_TXBUF_LOCK_ASSERT(_sc) \
319	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
320
321int	ath_attach(u_int16_t, struct ath_softc *);
322int	ath_detach(struct ath_softc *);
323void	ath_resume(struct ath_softc *);
324void	ath_suspend(struct ath_softc *);
325void	ath_shutdown(struct ath_softc *);
326void	ath_intr(void *);
327
328/*
329 * HAL definitions to comply with local coding convention.
330 */
331#define	ath_hal_detach(_ah) \
332	((*(_ah)->ah_detach)((_ah)))
333#define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
334	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
335#define	ath_hal_getratetable(_ah, _mode) \
336	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
337#define	ath_hal_getmac(_ah, _mac) \
338	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
339#define	ath_hal_setmac(_ah, _mac) \
340	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
341#define	ath_hal_intrset(_ah, _mask) \
342	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
343#define	ath_hal_intrget(_ah) \
344	((*(_ah)->ah_getInterrupts)((_ah)))
345#define	ath_hal_intrpend(_ah) \
346	((*(_ah)->ah_isInterruptPending)((_ah)))
347#define	ath_hal_getisr(_ah, _pmask) \
348	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
349#define	ath_hal_updatetxtriglevel(_ah, _inc) \
350	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
351#define	ath_hal_setpower(_ah, _mode) \
352	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
353#define	ath_hal_keycachesize(_ah) \
354	((*(_ah)->ah_getKeyCacheSize)((_ah)))
355#define	ath_hal_keyreset(_ah, _ix) \
356	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
357#define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
358	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
359#define	ath_hal_keyisvalid(_ah, _ix) \
360	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
361#define	ath_hal_keysetmac(_ah, _ix, _mac) \
362	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
363#define	ath_hal_getrxfilter(_ah) \
364	((*(_ah)->ah_getRxFilter)((_ah)))
365#define	ath_hal_setrxfilter(_ah, _filter) \
366	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
367#define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
368	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
369#define	ath_hal_waitforbeacon(_ah, _bf) \
370	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
371#define	ath_hal_putrxbuf(_ah, _bufaddr) \
372	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
373#define	ath_hal_gettsf32(_ah) \
374	((*(_ah)->ah_getTsf32)((_ah)))
375#define	ath_hal_gettsf64(_ah) \
376	((*(_ah)->ah_getTsf64)((_ah)))
377#define	ath_hal_resettsf(_ah) \
378	((*(_ah)->ah_resetTsf)((_ah)))
379#define	ath_hal_rxena(_ah) \
380	((*(_ah)->ah_enableReceive)((_ah)))
381#define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
382	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
383#define	ath_hal_gettxbuf(_ah, _q) \
384	((*(_ah)->ah_getTxDP)((_ah), (_q)))
385#define	ath_hal_numtxpending(_ah, _q) \
386	((*(_ah)->ah_numTxPending)((_ah), (_q)))
387#define	ath_hal_getrxbuf(_ah) \
388	((*(_ah)->ah_getRxDP)((_ah)))
389#define	ath_hal_txstart(_ah, _q) \
390	((*(_ah)->ah_startTxDma)((_ah), (_q)))
391#define	ath_hal_setchannel(_ah, _chan) \
392	((*(_ah)->ah_setChannel)((_ah), (_chan)))
393#define	ath_hal_calibrate(_ah, _chan, _iqcal) \
394	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
395#define	ath_hal_setledstate(_ah, _state) \
396	((*(_ah)->ah_setLedState)((_ah), (_state)))
397#define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
398	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
399#define	ath_hal_beaconreset(_ah) \
400	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
401#define	ath_hal_beacontimers(_ah, _bs) \
402	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
403#define	ath_hal_setassocid(_ah, _bss, _associd) \
404	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
405#define	ath_hal_phydisable(_ah) \
406	((*(_ah)->ah_phyDisable)((_ah)))
407#define	ath_hal_setopmode(_ah) \
408	((*(_ah)->ah_setPCUConfig)((_ah)))
409#define	ath_hal_stoptxdma(_ah, _qnum) \
410	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
411#define	ath_hal_stoppcurecv(_ah) \
412	((*(_ah)->ah_stopPcuReceive)((_ah)))
413#define	ath_hal_startpcurecv(_ah) \
414	((*(_ah)->ah_startPcuReceive)((_ah)))
415#define	ath_hal_stopdmarecv(_ah) \
416	((*(_ah)->ah_stopDmaReceive)((_ah)))
417#define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
418	((*(_ah)->ah_getDiagState)((_ah), (_id), \
419		(_indata), (_insize), (_outdata), (_outsize)))
420#define	ath_hal_getfatalstate(_ah, _outdata, _outsize) \
421	ath_hal_getdiagstate(_ah, 27, NULL, 0, (void **)(_outdata), _outsize)
422#define	ath_hal_setuptxqueue(_ah, _type, _irq) \
423	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
424#define	ath_hal_resettxqueue(_ah, _q) \
425	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
426#define	ath_hal_releasetxqueue(_ah, _q) \
427	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
428#define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
429	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
430#define	ath_hal_settxqueueprops(_ah, _q, _qi) \
431	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
432#define	ath_hal_getrfgain(_ah) \
433	((*(_ah)->ah_getRfGain)((_ah)))
434#define	ath_hal_getdefantenna(_ah) \
435	((*(_ah)->ah_getDefAntenna)((_ah)))
436#define	ath_hal_setdefantenna(_ah, _ant) \
437	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
438#define	ath_hal_rxmonitor(_ah, _arg, _chan) \
439	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
440#define	ath_hal_mibevent(_ah, _stats) \
441	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
442#define	ath_hal_setslottime(_ah, _us) \
443	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
444#define	ath_hal_getslottime(_ah) \
445	((*(_ah)->ah_getSlotTime)((_ah)))
446#define	ath_hal_setacktimeout(_ah, _us) \
447	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
448#define	ath_hal_getacktimeout(_ah) \
449	((*(_ah)->ah_getAckTimeout)((_ah)))
450#define	ath_hal_setctstimeout(_ah, _us) \
451	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
452#define	ath_hal_getctstimeout(_ah) \
453	((*(_ah)->ah_getCTSTimeout)((_ah)))
454#define	ath_hal_getcapability(_ah, _cap, _param, _result) \
455	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
456#define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
457	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
458#define	ath_hal_ciphersupported(_ah, _cipher) \
459	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
460#define	ath_hal_getregdomain(_ah, _prd) \
461	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
462#define	ath_hal_setregdomain(_ah, _rd) \
463	((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL))
464#define	ath_hal_getcountrycode(_ah, _pcc) \
465	(*(_pcc) = (_ah)->ah_countryCode)
466#define	ath_hal_hastkipsplit(_ah) \
467	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
468#define	ath_hal_gettkipsplit(_ah) \
469	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
470#define	ath_hal_settkipsplit(_ah, _v) \
471	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
472#define	ath_hal_hwphycounters(_ah) \
473	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
474#define	ath_hal_hasdiversity(_ah) \
475	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
476#define	ath_hal_getdiversity(_ah) \
477	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
478#define	ath_hal_setdiversity(_ah, _v) \
479	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
480#define	ath_hal_getdiag(_ah, _pv) \
481	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
482#define	ath_hal_setdiag(_ah, _v) \
483	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
484#define	ath_hal_getnumtxqueues(_ah, _pv) \
485	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
486#define	ath_hal_hasveol(_ah) \
487	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
488#define	ath_hal_hastxpowlimit(_ah) \
489	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
490#define	ath_hal_settxpowlimit(_ah, _pow) \
491	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
492#define	ath_hal_gettxpowlimit(_ah, _ppow) \
493	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
494#define	ath_hal_getmaxtxpow(_ah, _ppow) \
495	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
496#define	ath_hal_gettpscale(_ah, _scale) \
497	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
498#define	ath_hal_settpscale(_ah, _v) \
499	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
500#define	ath_hal_hastpc(_ah) \
501	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
502#define	ath_hal_gettpc(_ah) \
503	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
504#define	ath_hal_settpc(_ah, _v) \
505	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
506#define	ath_hal_hasbursting(_ah) \
507	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
508#ifdef notyet
509#define	ath_hal_hasmcastkeysearch(_ah) \
510	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
511#define	ath_hal_getmcastkeysearch(_ah) \
512	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
513#else
514#define	ath_hal_getmcastkeysearch(_ah)	0
515#endif
516#define	ath_hal_hasrfsilent(_ah) \
517	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
518#define	ath_hal_getrfkill(_ah) \
519	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
520#define	ath_hal_setrfkill(_ah, _onoff) \
521	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
522#define	ath_hal_getrfsilent(_ah, _prfsilent) \
523	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
524#define	ath_hal_setrfsilent(_ah, _rfsilent) \
525	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
526#define	ath_hal_gettpack(_ah, _ptpack) \
527	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
528#define	ath_hal_settpack(_ah, _tpack) \
529	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
530#define	ath_hal_gettpcts(_ah, _ptpcts) \
531	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
532#define	ath_hal_settpcts(_ah, _tpcts) \
533	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
534#if HAL_ABI_VERSION < 0x05120700
535#define	ath_hal_process_noisefloor(_ah)
536#define	ath_hal_getchannoise(_ah, _c)	(-96)
537#define	HAL_CAP_TPC_ACK	100
538#define	HAL_CAP_TPC_CTS	101
539#else
540#define	ath_hal_getchannoise(_ah, _c) \
541	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
542#endif
543#if HAL_ABI_VERSION < 0x05122200
544#define	HAL_TXQ_TXOKINT_ENABLE	TXQ_FLAG_TXOKINT_ENABLE
545#define	HAL_TXQ_TXERRINT_ENABLE	TXQ_FLAG_TXERRINT_ENABLE
546#define	HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
547#define	HAL_TXQ_TXEOLINT_ENABLE	TXQ_FLAG_TXEOLINT_ENABLE
548#define	HAL_TXQ_TXURNINT_ENABLE	TXQ_FLAG_TXURNINT_ENABLE
549#endif
550
551#define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
552	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
553#define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
554	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0))
555#define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
556		_txr0, _txtr0, _keyix, _ant, _flags, \
557		_rtsrate, _rtsdura) \
558	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
559		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
560		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
561#define	ath_hal_setupxtxdesc(_ah, _ds, \
562		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
563	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
564		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
565#define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
566	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
567#define	ath_hal_txprocdesc(_ah, _ds) \
568	((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
569#define	ath_hal_gettxintrtxqs(_ah, _txqs) \
570	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
571
572#define ath_hal_gpioCfgOutput(_ah, _gpio) \
573        ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
574#define ath_hal_gpioset(_ah, _gpio, _b) \
575        ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
576#define ath_hal_gpioget(_ah, _gpio) \
577        ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
578#define ath_hal_gpiosetintr(_ah, _gpio, _b) \
579        ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
580
581#define ath_hal_radar_wait(_ah, _chan) \
582	((*(_ah)->ah_radarWait)((_ah), (_chan)))
583
584#endif /* _DEV_ATH_ATHVAR_H */
585