if_athvar.h revision 155496
1212405Sdavidxu/*- 2212405Sdavidxu * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3212405Sdavidxu * All rights reserved. 4212405Sdavidxu * 5212405Sdavidxu * Redistribution and use in source and binary forms, with or without 6212405Sdavidxu * modification, are permitted provided that the following conditions 7212405Sdavidxu * are met: 8212405Sdavidxu * 1. Redistributions of source code must retain the above copyright 9212405Sdavidxu * notice, this list of conditions and the following disclaimer, 10212405Sdavidxu * without modification. 11212405Sdavidxu * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12212405Sdavidxu * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13212405Sdavidxu * redistribution must be conditioned upon including a substantially 14212405Sdavidxu * similar Disclaimer requirement for further binary redistribution. 15212405Sdavidxu * 3. Neither the names of the above-listed copyright holders nor the names 16212405Sdavidxu * of any contributors may be used to endorse or promote products derived 17212405Sdavidxu * from this software without specific prior written permission. 18212405Sdavidxu * 19212405Sdavidxu * Alternatively, this software may be distributed under the terms of the 20212405Sdavidxu * GNU General Public License ("GPL") version 2 as published by the Free 21212405Sdavidxu * Software Foundation. 22212405Sdavidxu * 23212405Sdavidxu * NO WARRANTY 24212405Sdavidxu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25212405Sdavidxu * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26212405Sdavidxu * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27212405Sdavidxu * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28212405Sdavidxu * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29212405Sdavidxu * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30212405Sdavidxu * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31276630Skib * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32212405Sdavidxu * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33276630Skib * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34212405Sdavidxu * THE POSSIBILITY OF SUCH DAMAGES. 35276630Skib * 36276630Skib * $FreeBSD: head/sys/dev/ath/if_athvar.h 155496 2006-02-09 22:21:53Z sam $ 37276630Skib */ 38276630Skib 39212405Sdavidxu/* 40276630Skib * Defintions for the Atheros Wireless LAN controller driver. 41276630Skib */ 42276630Skib#ifndef _DEV_ATH_ATHVAR_H 43276630Skib#define _DEV_ATH_ATHVAR_H 44212405Sdavidxu 45276630Skib#include <sys/taskqueue.h> 46212405Sdavidxu 47212405Sdavidxu#include <contrib/dev/ath/ah.h> 48212405Sdavidxu#include <net80211/ieee80211_radiotap.h> 49212405Sdavidxu#include <dev/ath/if_athioctl.h> 50212405Sdavidxu#include <dev/ath/if_athrate.h> 51212405Sdavidxu 52212405Sdavidxu#define ATH_TIMEOUT 1000 53212405Sdavidxu 54212405Sdavidxu#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 100 /* number of TX buffers */ 59#endif 60#define ATH_TXDESC 10 /* number of descriptors per buffer */ 61#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 62#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 63#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 64 65#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 66#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 67#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 68 69/* 70 * The key cache is used for h/w cipher state and also for 71 * tracking station state such as the current tx antenna. 72 * We also setup a mapping table between key cache slot indices 73 * and station state to short-circuit node lookups on rx. 74 * Different parts have different size key caches. We handle 75 * up to ATH_KEYMAX entries (could dynamically allocate state). 76 */ 77#define ATH_KEYMAX 128 /* max key cache size we handle */ 78#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 79 80/* driver-specific node state */ 81struct ath_node { 82 struct ieee80211_node an_node; /* base class */ 83 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 84 /* variable-length rate control state follows */ 85}; 86#define ATH_NODE(ni) ((struct ath_node *)(ni)) 87#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 88 89#define ATH_RSSI_LPF_LEN 10 90#define ATH_RSSI_DUMMY_MARKER 0x127 91#define ATH_EP_MUL(x, mul) ((x) * (mul)) 92#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 93#define ATH_LPF_RSSI(x, y, len) \ 94 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 95#define ATH_RSSI_LPF(x, y) do { \ 96 if ((y) >= -20) \ 97 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 98} while (0) 99 100struct ath_buf { 101 STAILQ_ENTRY(ath_buf) bf_list; 102 int bf_nseg; 103 int bf_flags; /* tx descriptor flags */ 104 struct ath_desc *bf_desc; /* virtual addr of desc */ 105 bus_addr_t bf_daddr; /* physical addr of desc */ 106 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 107 struct mbuf *bf_m; /* mbuf for buf */ 108 struct ieee80211_node *bf_node; /* pointer to the node */ 109 bus_size_t bf_mapsize; 110#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 111 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 112}; 113typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 114 115/* 116 * DMA state for tx/rx descriptors. 117 */ 118struct ath_descdma { 119 const char* dd_name; 120 struct ath_desc *dd_desc; /* descriptors */ 121 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 122 bus_addr_t dd_desc_len; /* size of dd_desc */ 123 bus_dma_segment_t dd_dseg; 124 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 125 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 126 struct ath_buf *dd_bufptr; /* associated buffers */ 127}; 128 129/* 130 * Data transmit queue state. One of these exists for each 131 * hardware transmit queue. Packets sent to us from above 132 * are assigned to queues based on their priority. Not all 133 * devices support a complete set of hardware transmit queues. 134 * For those devices the array sc_ac2q will map multiple 135 * priorities to fewer hardware queues (typically all to one 136 * hardware queue). 137 */ 138struct ath_txq { 139 u_int axq_qnum; /* hardware q number */ 140 u_int axq_depth; /* queue depth (stat only) */ 141 u_int axq_intrcnt; /* interrupt count */ 142 u_int32_t *axq_link; /* link ptr in last TX desc */ 143 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 144 struct mtx axq_lock; /* lock on q and link */ 145 char axq_name[12]; /* e.g. "ath0_txq4" */ 146}; 147 148#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 149 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 150 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 151 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \ 152} while (0); 153#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 154#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 155#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 156#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 157 158#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 159 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 160 (_tq)->axq_depth++; \ 161} while (0) 162#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 163 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 164 (_tq)->axq_depth--; \ 165} while (0) 166 167struct taskqueue; 168struct ath_tx99; 169 170struct ath_softc { 171 struct ifnet *sc_ifp; /* interface common */ 172 struct ath_stats sc_stats; /* interface statistics */ 173 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 174 int sc_countrycode; 175 int sc_debug; 176 void (*sc_recv_mgmt)(struct ieee80211com *, 177 struct mbuf *, 178 struct ieee80211_node *, 179 int, int, u_int32_t); 180 int (*sc_newstate)(struct ieee80211com *, 181 enum ieee80211_state, int); 182 void (*sc_node_free)(struct ieee80211_node *); 183 device_t sc_dev; 184 bus_space_tag_t sc_st; /* bus space tag */ 185 bus_space_handle_t sc_sh; /* bus space handle */ 186 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 187 struct mtx sc_mtx; /* master lock (recursive) */ 188 struct taskqueue *sc_tq; /* private task queue */ 189 struct ath_hal *sc_ah; /* Atheros HAL */ 190 struct ath_ratectrl *sc_rc; /* tx rate control support */ 191 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 192 void (*sc_setdefantenna)(struct ath_softc *, u_int); 193 unsigned int sc_invalid : 1, /* disable hardware accesses */ 194 sc_mrretry : 1, /* multi-rate retry support */ 195 sc_softled : 1, /* enable LED gpio status */ 196 sc_splitmic: 1, /* split TKIP MIC keys */ 197 sc_needmib : 1, /* enable MIB stats intr */ 198 sc_diversity : 1,/* enable rx diversity */ 199 sc_hasveol : 1, /* tx VEOL support */ 200 sc_ledstate: 1, /* LED on/off state */ 201 sc_blinking: 1, /* LED blink operation active */ 202 sc_mcastkey: 1, /* mcast key cache search */ 203 sc_syncbeacon:1,/* sync/resync beacon timers */ 204 sc_hasclrkey:1; /* CLR key supported */ 205 /* rate tables */ 206 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 207 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 208 enum ieee80211_phymode sc_curmode; /* current phy mode */ 209 HAL_OPMODE sc_opmode; /* current operating mode */ 210 u_int16_t sc_curtxpow; /* current tx power limit */ 211 HAL_CHANNEL sc_curchan; /* current h/w channel */ 212 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 213 struct { 214 u_int8_t ieeerate; /* IEEE rate */ 215 u_int8_t rxflags; /* radiotap rx flags */ 216 u_int8_t txflags; /* radiotap tx flags */ 217 u_int16_t ledon; /* softled on time */ 218 u_int16_t ledoff; /* softled off time */ 219 } sc_hwmap[32]; /* h/w rate ix mappings */ 220 u_int8_t sc_minrateix; /* min h/w rate index */ 221 u_int8_t sc_mcastrix; /* mcast h/w rate index */ 222 u_int8_t sc_protrix; /* protection rate index */ 223 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 224 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 225 HAL_INT sc_imask; /* interrupt mask copy */ 226 u_int sc_keymax; /* size of key cache */ 227 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 228 229 u_int sc_ledpin; /* GPIO pin for driving LED */ 230 u_int sc_ledon; /* pin setting for LED on */ 231 u_int sc_ledidle; /* idle polling interval */ 232 int sc_ledevent; /* time of last LED event */ 233 u_int8_t sc_rxrate; /* current rx rate for LED */ 234 u_int8_t sc_txrate; /* current tx rate for LED */ 235 u_int16_t sc_ledoff; /* off time for current blink */ 236 struct callout sc_ledtimer; /* led off timer */ 237 238 struct bpf_if *sc_drvbpf; 239 union { 240 struct ath_tx_radiotap_header th; 241 u_int8_t pad[64]; 242 } u_tx_rt; 243 int sc_tx_th_len; 244 union { 245 struct ath_rx_radiotap_header th; 246 u_int8_t pad[64]; 247 } u_rx_rt; 248 int sc_rx_th_len; 249 u_int sc_monpass; /* frames to pass in mon.mode */ 250 251 struct task sc_fataltask; /* fatal int processing */ 252 253 struct ath_descdma sc_rxdma; /* RX descriptos */ 254 ath_bufhead sc_rxbuf; /* receive buffer */ 255 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 256 struct task sc_rxtask; /* rx int processing */ 257 struct task sc_rxorntask; /* rxorn int processing */ 258 u_int8_t sc_defant; /* current default antenna */ 259 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 260 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 261 262 struct ath_descdma sc_txdma; /* TX descriptors */ 263 ath_bufhead sc_txbuf; /* transmit buffer */ 264 struct mtx sc_txbuflock; /* txbuf lock */ 265 char sc_txname[12]; /* e.g. "ath0_buf" */ 266 int sc_tx_timer; /* transmit timeout */ 267 u_int sc_txqsetup; /* h/w queues setup */ 268 u_int sc_txintrperiod;/* tx interrupt batching */ 269 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 270 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 271 struct task sc_txtask; /* tx int processing */ 272 273 struct ath_descdma sc_bdma; /* beacon descriptors */ 274 ath_bufhead sc_bbuf; /* beacon buffers */ 275 u_int sc_bhalq; /* HAL q for outgoing beacons */ 276 u_int sc_bmisscount; /* missed beacon transmits */ 277 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 278 struct ath_txq *sc_cabq; /* tx q for cab frames */ 279 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 280 struct task sc_bmisstask; /* bmiss int processing */ 281 struct task sc_bstucktask; /* stuck beacon processing */ 282 enum { 283 OK, /* no change needed */ 284 UPDATE, /* update pending */ 285 COMMIT /* beacon sent, commit change */ 286 } sc_updateslot; /* slot time update fsm */ 287 288 struct callout sc_cal_ch; /* callout handle for cals */ 289 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 290 struct callout sc_scan_ch; /* callout handle for scan */ 291}; 292#define sc_tx_th u_tx_rt.th 293#define sc_rx_th u_rx_rt.th 294 295#define ATH_LOCK_INIT(_sc) \ 296 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 297 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 298#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 299#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 300#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 301#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 302 303#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 304 305#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 306 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 307 device_get_nameunit((_sc)->sc_dev)); \ 308 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \ 309} while (0) 310#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 311#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 312#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 313#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 314 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 315 316int ath_attach(u_int16_t, struct ath_softc *); 317int ath_detach(struct ath_softc *); 318void ath_resume(struct ath_softc *); 319void ath_suspend(struct ath_softc *); 320void ath_shutdown(struct ath_softc *); 321void ath_intr(void *); 322 323/* 324 * HAL definitions to comply with local coding convention. 325 */ 326#define ath_hal_detach(_ah) \ 327 ((*(_ah)->ah_detach)((_ah))) 328#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 329 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 330#define ath_hal_getratetable(_ah, _mode) \ 331 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 332#define ath_hal_getmac(_ah, _mac) \ 333 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 334#define ath_hal_setmac(_ah, _mac) \ 335 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 336#define ath_hal_intrset(_ah, _mask) \ 337 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 338#define ath_hal_intrget(_ah) \ 339 ((*(_ah)->ah_getInterrupts)((_ah))) 340#define ath_hal_intrpend(_ah) \ 341 ((*(_ah)->ah_isInterruptPending)((_ah))) 342#define ath_hal_getisr(_ah, _pmask) \ 343 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 344#define ath_hal_updatetxtriglevel(_ah, _inc) \ 345 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 346#define ath_hal_setpower(_ah, _mode, _sleepduration) \ 347 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 348#define ath_hal_keycachesize(_ah) \ 349 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 350#define ath_hal_keyreset(_ah, _ix) \ 351 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 352#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 353 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 354#define ath_hal_keyisvalid(_ah, _ix) \ 355 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 356#define ath_hal_keysetmac(_ah, _ix, _mac) \ 357 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 358#define ath_hal_getrxfilter(_ah) \ 359 ((*(_ah)->ah_getRxFilter)((_ah))) 360#define ath_hal_setrxfilter(_ah, _filter) \ 361 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 362#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 363 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 364#define ath_hal_waitforbeacon(_ah, _bf) \ 365 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 366#define ath_hal_putrxbuf(_ah, _bufaddr) \ 367 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 368#define ath_hal_gettsf32(_ah) \ 369 ((*(_ah)->ah_getTsf32)((_ah))) 370#define ath_hal_gettsf64(_ah) \ 371 ((*(_ah)->ah_getTsf64)((_ah))) 372#define ath_hal_resettsf(_ah) \ 373 ((*(_ah)->ah_resetTsf)((_ah))) 374#define ath_hal_rxena(_ah) \ 375 ((*(_ah)->ah_enableReceive)((_ah))) 376#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 377 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 378#define ath_hal_gettxbuf(_ah, _q) \ 379 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 380#define ath_hal_numtxpending(_ah, _q) \ 381 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 382#define ath_hal_getrxbuf(_ah) \ 383 ((*(_ah)->ah_getRxDP)((_ah))) 384#define ath_hal_txstart(_ah, _q) \ 385 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 386#define ath_hal_setchannel(_ah, _chan) \ 387 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 388#define ath_hal_calibrate(_ah, _chan) \ 389 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 390#define ath_hal_setledstate(_ah, _state) \ 391 ((*(_ah)->ah_setLedState)((_ah), (_state))) 392#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 393 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 394#define ath_hal_beaconreset(_ah) \ 395 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 396#define ath_hal_beacontimers(_ah, _bs) \ 397 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 398#define ath_hal_setassocid(_ah, _bss, _associd) \ 399 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 400#define ath_hal_phydisable(_ah) \ 401 ((*(_ah)->ah_phyDisable)((_ah))) 402#define ath_hal_setopmode(_ah) \ 403 ((*(_ah)->ah_setPCUConfig)((_ah))) 404#define ath_hal_stoptxdma(_ah, _qnum) \ 405 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 406#define ath_hal_stoppcurecv(_ah) \ 407 ((*(_ah)->ah_stopPcuReceive)((_ah))) 408#define ath_hal_startpcurecv(_ah) \ 409 ((*(_ah)->ah_startPcuReceive)((_ah))) 410#define ath_hal_stopdmarecv(_ah) \ 411 ((*(_ah)->ah_stopDmaReceive)((_ah))) 412#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 413 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 414 (_indata), (_insize), (_outdata), (_outsize))) 415#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 416 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 417#define ath_hal_resettxqueue(_ah, _q) \ 418 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 419#define ath_hal_releasetxqueue(_ah, _q) \ 420 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 421#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 422 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 423#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 424 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 425#define ath_hal_getrfgain(_ah) \ 426 ((*(_ah)->ah_getRfGain)((_ah))) 427#define ath_hal_getdefantenna(_ah) \ 428 ((*(_ah)->ah_getDefAntenna)((_ah))) 429#define ath_hal_setdefantenna(_ah, _ant) \ 430 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 431#define ath_hal_rxmonitor(_ah, _arg) \ 432 ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 433#define ath_hal_mibevent(_ah, _stats) \ 434 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 435#define ath_hal_setslottime(_ah, _us) \ 436 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 437#define ath_hal_getslottime(_ah) \ 438 ((*(_ah)->ah_getSlotTime)((_ah))) 439#define ath_hal_setacktimeout(_ah, _us) \ 440 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 441#define ath_hal_getacktimeout(_ah) \ 442 ((*(_ah)->ah_getAckTimeout)((_ah))) 443#define ath_hal_setctstimeout(_ah, _us) \ 444 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 445#define ath_hal_getctstimeout(_ah) \ 446 ((*(_ah)->ah_getCTSTimeout)((_ah))) 447#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 448 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 449#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 450 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 451#define ath_hal_ciphersupported(_ah, _cipher) \ 452 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 453#define ath_hal_getregdomain(_ah, _prd) \ 454 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 455#define ath_hal_setregdomain(_ah, _rd) \ 456 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL)) 457#define ath_hal_getcountrycode(_ah, _pcc) \ 458 (*(_pcc) = (_ah)->ah_countryCode) 459#define ath_hal_tkipsplit(_ah) \ 460 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 461#define ath_hal_hwphycounters(_ah) \ 462 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 463#define ath_hal_hasdiversity(_ah) \ 464 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 465#define ath_hal_getdiversity(_ah) \ 466 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 467#define ath_hal_setdiversity(_ah, _v) \ 468 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 469#define ath_hal_getdiag(_ah, _pv) \ 470 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 471#define ath_hal_setdiag(_ah, _v) \ 472 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 473#define ath_hal_getnumtxqueues(_ah, _pv) \ 474 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 475#define ath_hal_hasveol(_ah) \ 476 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 477#define ath_hal_hastxpowlimit(_ah) \ 478 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 479#define ath_hal_settxpowlimit(_ah, _pow) \ 480 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 481#define ath_hal_gettxpowlimit(_ah, _ppow) \ 482 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 483#define ath_hal_getmaxtxpow(_ah, _ppow) \ 484 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 485#define ath_hal_gettpscale(_ah, _scale) \ 486 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 487#define ath_hal_settpscale(_ah, _v) \ 488 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 489#define ath_hal_hastpc(_ah) \ 490 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 491#define ath_hal_gettpc(_ah) \ 492 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 493#define ath_hal_settpc(_ah, _v) \ 494 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 495#define ath_hal_hasbursting(_ah) \ 496 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 497#ifdef notyet 498#define ath_hal_hasmcastkeysearch(_ah) \ 499 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 500#define ath_hal_getmcastkeysearch(_ah) \ 501 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 502#else 503#define ath_hal_getmcastkeysearch(_ah) 0 504#endif 505#if HAL_ABI_VERSION < 0x05120700 506#define ath_hal_process_noisefloor(_ah) 507#define ath_hal_getchannoise(_ah, _c) (-96) 508#define HAL_CAP_TPC_ACK 100 509#define HAL_CAP_TPC_CTS 101 510#else 511#define ath_hal_getchannoise(_ah, _c) \ 512 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 513#endif 514 515#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 516 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 517#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 518 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 519#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 520 _txr0, _txtr0, _keyix, _ant, _flags, \ 521 _rtsrate, _rtsdura) \ 522 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 523 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 524 (_flags), (_rtsrate), (_rtsdura))) 525#define ath_hal_setupxtxdesc(_ah, _ds, \ 526 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 527 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 528 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 529#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 530 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 531#define ath_hal_txprocdesc(_ah, _ds) \ 532 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 533 534#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 535 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 536#define ath_hal_gpioset(_ah, _gpio, _b) \ 537 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 538 539#endif /* _DEV_ATH_ATHVAR_H */ 540