if_athvar.h revision 155482
1116743Ssam/*- 2139530Ssam * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 3. Neither the names of the above-listed copyright holders nor the names 16116743Ssam * of any contributors may be used to endorse or promote products derived 17116743Ssam * from this software without specific prior written permission. 18116743Ssam * 19116743Ssam * Alternatively, this software may be distributed under the terms of the 20116743Ssam * GNU General Public License ("GPL") version 2 as published by the Free 21116743Ssam * Software Foundation. 22116743Ssam * 23116743Ssam * NO WARRANTY 24116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 35116743Ssam * 36116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 155482 2006-02-09 21:09:26Z sam $ 37116743Ssam */ 38116743Ssam 39116743Ssam/* 40116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 41116743Ssam */ 42116743Ssam#ifndef _DEV_ATH_ATHVAR_H 43116743Ssam#define _DEV_ATH_ATHVAR_H 44116743Ssam 45116743Ssam#include <sys/taskqueue.h> 46116743Ssam 47116743Ssam#include <contrib/dev/ath/ah.h> 48119783Ssam#include <net80211/ieee80211_radiotap.h> 49116743Ssam#include <dev/ath/if_athioctl.h> 50138570Ssam#include <dev/ath/if_athrate.h> 51116743Ssam 52116743Ssam#define ATH_TIMEOUT 1000 53116743Ssam 54155481Ssam#ifndef ATH_RXBUF 55116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 56155481Ssam#endif 57155481Ssam#ifndef ATH_TXBUF 58140438Ssam#define ATH_TXBUF 100 /* number of TX buffers */ 59155481Ssam#endif 60140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 61138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 62155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 63138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 64116743Ssam 65147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 66147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 67147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 68147067Ssam 69147057Ssam/* 70147057Ssam * The key cache is used for h/w cipher state and also for 71147057Ssam * tracking station state such as the current tx antenna. 72147057Ssam * We also setup a mapping table between key cache slot indices 73147057Ssam * and station state to short-circuit node lookups on rx. 74147057Ssam * Different parts have different size key caches. We handle 75147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 76147057Ssam */ 77147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 78147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 79147057Ssam 80138570Ssam/* driver-specific node state */ 81116743Ssamstruct ath_node { 82119150Ssam struct ieee80211_node an_node; /* base class */ 83138570Ssam u_int32_t an_avgrssi; /* average rssi over all rx frames */ 84138570Ssam HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ 85138570Ssam /* variable-length rate control state follows */ 86116743Ssam}; 87138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 88138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 89116743Ssam 90138570Ssam#define ATH_RSSI_LPF_LEN 10 91138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 92138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 93138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 94138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 95138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 96138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 97138570Ssam if ((y) >= -20) \ 98138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 99138570Ssam} while (0) 100138570Ssam 101116743Ssamstruct ath_buf { 102138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 103116743Ssam int bf_nseg; 104147803Ssam int bf_flags; /* tx descriptor flags */ 105116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 106116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 107138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 108116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 109116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 110116743Ssam bus_size_t bf_mapsize; 111140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 112116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 113116743Ssam}; 114138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 115116743Ssam 116138570Ssam/* 117138570Ssam * DMA state for tx/rx descriptors. 118138570Ssam */ 119138570Ssamstruct ath_descdma { 120138570Ssam const char* dd_name; 121138570Ssam struct ath_desc *dd_desc; /* descriptors */ 122138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 123138570Ssam bus_addr_t dd_desc_len; /* size of dd_desc */ 124138570Ssam bus_dma_segment_t dd_dseg; 125138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 126138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 127138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 128138570Ssam}; 129138570Ssam 130138570Ssam/* 131138570Ssam * Data transmit queue state. One of these exists for each 132138570Ssam * hardware transmit queue. Packets sent to us from above 133138570Ssam * are assigned to queues based on their priority. Not all 134138570Ssam * devices support a complete set of hardware transmit queues. 135138570Ssam * For those devices the array sc_ac2q will map multiple 136138570Ssam * priorities to fewer hardware queues (typically all to one 137138570Ssam * hardware queue). 138138570Ssam */ 139138570Ssamstruct ath_txq { 140138570Ssam u_int axq_qnum; /* hardware q number */ 141138570Ssam u_int axq_depth; /* queue depth (stat only) */ 142138570Ssam u_int axq_intrcnt; /* interrupt count */ 143138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 144138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 145138570Ssam struct mtx axq_lock; /* lock on q and link */ 146155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 147138570Ssam}; 148138570Ssam 149155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 150155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 151155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 152155482Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \ 153155482Ssam} while (0); 154138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 155138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 156138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 157138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 158138570Ssam 159138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 160138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 161138570Ssam (_tq)->axq_depth++; \ 162138570Ssam} while (0) 163138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 164138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 165138570Ssam (_tq)->axq_depth--; \ 166138570Ssam} while (0) 167138570Ssam 168116743Ssamstruct ath_softc { 169147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 170138570Ssam struct ath_stats sc_stats; /* interface statistics */ 171116743Ssam struct ieee80211com sc_ic; /* IEEE 802.11 common */ 172138570Ssam int sc_regdomain; 173138570Ssam int sc_countrycode; 174138570Ssam int sc_debug; 175138570Ssam void (*sc_recv_mgmt)(struct ieee80211com *, 176138570Ssam struct mbuf *, 177138570Ssam struct ieee80211_node *, 178138570Ssam int, int, u_int32_t); 179117812Ssam int (*sc_newstate)(struct ieee80211com *, 180117812Ssam enum ieee80211_state, int); 181138570Ssam void (*sc_node_free)(struct ieee80211_node *); 182116743Ssam device_t sc_dev; 183116743Ssam bus_space_tag_t sc_st; /* bus space tag */ 184116743Ssam bus_space_handle_t sc_sh; /* bus space handle */ 185116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 186116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 187116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 188138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 189138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 190147057Ssam unsigned int sc_invalid : 1, /* disable hardware accesses */ 191138570Ssam sc_mrretry : 1, /* multi-rate retry support */ 192138570Ssam sc_softled : 1, /* enable LED gpio status */ 193138570Ssam sc_splitmic: 1, /* split TKIP MIC keys */ 194138570Ssam sc_needmib : 1, /* enable MIB stats intr */ 195138570Ssam sc_diversity : 1,/* enable rx diversity */ 196138570Ssam sc_hasveol : 1, /* tx VEOL support */ 197140432Ssam sc_ledstate: 1, /* LED on/off state */ 198144961Ssam sc_blinking: 1, /* LED blink operation active */ 199147057Ssam sc_mcastkey: 1, /* mcast key cache search */ 200147057Ssam sc_hasclrkey:1; /* CLR key supported */ 201116743Ssam /* rate tables */ 202116743Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 203116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 204116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 205138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 206138570Ssam HAL_CHANNEL sc_curchan; /* current h/w channel */ 207116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 208140432Ssam struct { 209140432Ssam u_int8_t ieeerate; /* IEEE rate */ 210140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 211140761Ssam u_int8_t txflags; /* radiotap tx flags */ 212140432Ssam u_int16_t ledon; /* softled on time */ 213140432Ssam u_int16_t ledoff; /* softled off time */ 214140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 215155477Ssam u_int8_t sc_minrateix; /* min h/w rate index */ 216138570Ssam u_int8_t sc_protrix; /* protection rate index */ 217138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 218116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 219138570Ssam u_int sc_keymax; /* size of key cache */ 220147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 221116743Ssam 222140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 223140432Ssam u_int sc_ledon; /* pin setting for LED on */ 224140432Ssam u_int sc_ledidle; /* idle polling interval */ 225140432Ssam int sc_ledevent; /* time of last LED event */ 226140432Ssam u_int8_t sc_rxrate; /* current rx rate for LED */ 227140432Ssam u_int8_t sc_txrate; /* current tx rate for LED */ 228140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 229140432Ssam struct callout sc_ledtimer; /* led off timer */ 230138570Ssam 231119783Ssam struct bpf_if *sc_drvbpf; 232119783Ssam union { 233119783Ssam struct ath_tx_radiotap_header th; 234119783Ssam u_int8_t pad[64]; 235119783Ssam } u_tx_rt; 236127698Ssam int sc_tx_th_len; 237119783Ssam union { 238140761Ssam struct ath_rx_radiotap_header th; 239119783Ssam u_int8_t pad[64]; 240119783Ssam } u_rx_rt; 241140761Ssam int sc_rx_th_len; 242154140Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 243119783Ssam 244116743Ssam struct task sc_fataltask; /* fatal int processing */ 245116743Ssam 246138570Ssam struct ath_descdma sc_rxdma; /* RX descriptos */ 247138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 248116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 249116743Ssam struct task sc_rxtask; /* rx int processing */ 250138570Ssam struct task sc_rxorntask; /* rxorn int processing */ 251138570Ssam u_int8_t sc_defant; /* current default antenna */ 252138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 253116743Ssam 254138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 255138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 256138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 257155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 258116743Ssam int sc_tx_timer; /* transmit timeout */ 259138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 260138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 261138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 262138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 263116743Ssam struct task sc_txtask; /* tx int processing */ 264116743Ssam 265138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 266138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 267116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 268138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 269138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 270138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 271138570Ssam struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 272116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 273138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 274138570Ssam enum { 275138570Ssam OK, /* no change needed */ 276138570Ssam UPDATE, /* update pending */ 277138570Ssam COMMIT /* beacon sent, commit change */ 278138570Ssam } sc_updateslot; /* slot time update fsm */ 279116743Ssam 280116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 281116743Ssam struct callout sc_scan_ch; /* callout handle for scan */ 282116743Ssam}; 283119783Ssam#define sc_tx_th u_tx_rt.th 284140761Ssam#define sc_rx_th u_rx_rt.th 285116743Ssam 286121100Ssam#define ATH_LOCK_INIT(_sc) \ 287121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 288121100Ssam MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 289121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 290121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 291121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 292121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 293121100Ssam 294138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 295138570Ssam 296155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 297155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 298155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 299155482Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \ 300155482Ssam} while (0) 301121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 302121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 303121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 304121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 305121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 306121100Ssam 307116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 308116743Ssamint ath_detach(struct ath_softc *); 309116743Ssamvoid ath_resume(struct ath_softc *); 310116743Ssamvoid ath_suspend(struct ath_softc *); 311116743Ssamvoid ath_shutdown(struct ath_softc *); 312116743Ssamvoid ath_intr(void *); 313116743Ssam 314116743Ssam/* 315116743Ssam * HAL definitions to comply with local coding convention. 316116743Ssam */ 317138570Ssam#define ath_hal_detach(_ah) \ 318138570Ssam ((*(_ah)->ah_detach)((_ah))) 319116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 320116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 321116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 322116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 323116743Ssam#define ath_hal_getmac(_ah, _mac) \ 324116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 325138570Ssam#define ath_hal_setmac(_ah, _mac) \ 326138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 327116743Ssam#define ath_hal_intrset(_ah, _mask) \ 328116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 329116743Ssam#define ath_hal_intrget(_ah) \ 330116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 331116743Ssam#define ath_hal_intrpend(_ah) \ 332116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 333116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 334116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 335116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 336116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 337116743Ssam#define ath_hal_setpower(_ah, _mode, _sleepduration) \ 338116743Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 339138570Ssam#define ath_hal_keycachesize(_ah) \ 340138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 341116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 342116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 343138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 344138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 345116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 346116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 347116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 348116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 349116743Ssam#define ath_hal_getrxfilter(_ah) \ 350116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 351116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 352116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 353116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 354116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 355116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 356116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 357116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 358116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 359116743Ssam#define ath_hal_gettsf32(_ah) \ 360116743Ssam ((*(_ah)->ah_getTsf32)((_ah))) 361116743Ssam#define ath_hal_gettsf64(_ah) \ 362116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 363116743Ssam#define ath_hal_resettsf(_ah) \ 364116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 365116743Ssam#define ath_hal_rxena(_ah) \ 366116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 367116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 368116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 369116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 370116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 371138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 372138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 373116743Ssam#define ath_hal_getrxbuf(_ah) \ 374116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 375116743Ssam#define ath_hal_txstart(_ah, _q) \ 376116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 377116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 378116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 379116743Ssam#define ath_hal_calibrate(_ah, _chan) \ 380116743Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 381116743Ssam#define ath_hal_setledstate(_ah, _state) \ 382116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 383138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 384138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 385116743Ssam#define ath_hal_beaconreset(_ah) \ 386116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 387138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 388138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 389116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 390138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 391138570Ssam#define ath_hal_phydisable(_ah) \ 392138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 393138570Ssam#define ath_hal_setopmode(_ah) \ 394138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 395116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 396116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 397116743Ssam#define ath_hal_stoppcurecv(_ah) \ 398116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 399116743Ssam#define ath_hal_startpcurecv(_ah) \ 400116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 401116743Ssam#define ath_hal_stopdmarecv(_ah) \ 402116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 403138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 404138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 405138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 406116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 407116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 408116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 409116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 410116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 411116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 412138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 413138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 414138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 415138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 416116743Ssam#define ath_hal_getrfgain(_ah) \ 417116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 418138570Ssam#define ath_hal_getdefantenna(_ah) \ 419138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 420138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 421138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 422138570Ssam#define ath_hal_rxmonitor(_ah, _arg) \ 423138570Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 424138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 425138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 426138570Ssam#define ath_hal_setslottime(_ah, _us) \ 427138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 428138570Ssam#define ath_hal_getslottime(_ah) \ 429138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 430138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 431138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 432138570Ssam#define ath_hal_getacktimeout(_ah) \ 433138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 434138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 435138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 436138570Ssam#define ath_hal_getctstimeout(_ah) \ 437138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 438138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 439138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 440138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 441138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 442138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 443138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 444138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 445138570Ssam ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 446138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 447138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 448138570Ssam#define ath_hal_tkipsplit(_ah) \ 449138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 450138570Ssam#define ath_hal_hwphycounters(_ah) \ 451138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 452138570Ssam#define ath_hal_hasdiversity(_ah) \ 453138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 454138570Ssam#define ath_hal_getdiversity(_ah) \ 455138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 456138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 457138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 458138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 459138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 460138570Ssam#define ath_hal_setdiag(_ah, _v) \ 461138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 462138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 463138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 464138570Ssam#define ath_hal_hasveol(_ah) \ 465138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 466138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 467138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 468138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 469138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 470138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 471138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 472138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 473138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 474138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 475138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 476138570Ssam#define ath_hal_settpscale(_ah, _v) \ 477138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 478138570Ssam#define ath_hal_hastpc(_ah) \ 479138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 480138570Ssam#define ath_hal_gettpc(_ah) \ 481138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 482138570Ssam#define ath_hal_settpc(_ah, _v) \ 483138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 484138570Ssam#define ath_hal_hasbursting(_ah) \ 485138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 486147057Ssam#ifdef notyet 487147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 488147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 489147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 490147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 491147057Ssam#else 492147057Ssam#define ath_hal_getmcastkeysearch(_ah) 0 493147057Ssam#endif 494154140Ssam#if HAL_ABI_VERSION < 0x05120700 495154140Ssam#define ath_hal_process_noisefloor(_ah) 496154140Ssam#define ath_hal_getchannoise(_ah, _c) (-96) 497154140Ssam#define HAL_CAP_TPC_ACK 100 498154140Ssam#define HAL_CAP_TPC_CTS 101 499154140Ssam#else 500154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 501154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 502154140Ssam#endif 503116743Ssam 504116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 505116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 506123044Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 507123044Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 508116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 509116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 510116743Ssam _rtsrate, _rtsdura) \ 511116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 512116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 513116743Ssam (_flags), (_rtsrate), (_rtsdura))) 514138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 515116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 516138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 517116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 518138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 519138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 520116743Ssam#define ath_hal_txprocdesc(_ah, _ds) \ 521116743Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 522116743Ssam 523138570Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 524138570Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 525138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 526138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 527138570Ssam 528116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 529