if_athvar.h revision 154140
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 154140 2006-01-09 17:13:20Z sam $ 37 */ 38 39/* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42#ifndef _DEV_ATH_ATHVAR_H 43#define _DEV_ATH_ATHVAR_H 44 45#include <sys/taskqueue.h> 46 47#include <contrib/dev/ath/ah.h> 48#include <net80211/ieee80211_radiotap.h> 49#include <dev/ath/if_athioctl.h> 50#include <dev/ath/if_athrate.h> 51 52#define ATH_TIMEOUT 1000 53 54#define ATH_RXBUF 40 /* number of RX buffers */ 55#define ATH_TXBUF 100 /* number of TX buffers */ 56#define ATH_TXDESC 10 /* number of descriptors per buffer */ 57#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 58#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 59 60#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 61#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 62#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 63 64/* 65 * The key cache is used for h/w cipher state and also for 66 * tracking station state such as the current tx antenna. 67 * We also setup a mapping table between key cache slot indices 68 * and station state to short-circuit node lookups on rx. 69 * Different parts have different size key caches. We handle 70 * up to ATH_KEYMAX entries (could dynamically allocate state). 71 */ 72#define ATH_KEYMAX 128 /* max key cache size we handle */ 73#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 74 75/* driver-specific node state */ 76struct ath_node { 77 struct ieee80211_node an_node; /* base class */ 78 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 79 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */ 80 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 81 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */ 82 /* variable-length rate control state follows */ 83}; 84#define ATH_NODE(ni) ((struct ath_node *)(ni)) 85#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 86 87#define ATH_RSSI_LPF_LEN 10 88#define ATH_RSSI_DUMMY_MARKER 0x127 89#define ATH_EP_MUL(x, mul) ((x) * (mul)) 90#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 91#define ATH_LPF_RSSI(x, y, len) \ 92 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 93#define ATH_RSSI_LPF(x, y) do { \ 94 if ((y) >= -20) \ 95 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 96} while (0) 97 98struct ath_buf { 99 STAILQ_ENTRY(ath_buf) bf_list; 100 int bf_nseg; 101 int bf_flags; /* tx descriptor flags */ 102 struct ath_desc *bf_desc; /* virtual addr of desc */ 103 bus_addr_t bf_daddr; /* physical addr of desc */ 104 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 105 struct mbuf *bf_m; /* mbuf for buf */ 106 struct ieee80211_node *bf_node; /* pointer to the node */ 107 bus_size_t bf_mapsize; 108#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 109 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 110}; 111typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 112 113/* 114 * DMA state for tx/rx descriptors. 115 */ 116struct ath_descdma { 117 const char* dd_name; 118 struct ath_desc *dd_desc; /* descriptors */ 119 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 120 bus_addr_t dd_desc_len; /* size of dd_desc */ 121 bus_dma_segment_t dd_dseg; 122 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 123 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 124 struct ath_buf *dd_bufptr; /* associated buffers */ 125}; 126 127/* 128 * Data transmit queue state. One of these exists for each 129 * hardware transmit queue. Packets sent to us from above 130 * are assigned to queues based on their priority. Not all 131 * devices support a complete set of hardware transmit queues. 132 * For those devices the array sc_ac2q will map multiple 133 * priorities to fewer hardware queues (typically all to one 134 * hardware queue). 135 */ 136struct ath_txq { 137 u_int axq_qnum; /* hardware q number */ 138 u_int axq_depth; /* queue depth (stat only) */ 139 u_int axq_intrcnt; /* interrupt count */ 140 u_int32_t *axq_link; /* link ptr in last TX desc */ 141 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 142 struct mtx axq_lock; /* lock on q and link */ 143}; 144 145#define ATH_TXQ_LOCK_INIT(_sc, _tq) \ 146 mtx_init(&(_tq)->axq_lock, \ 147 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 148#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 149#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 150#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 151#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 152 153#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 154 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 155 (_tq)->axq_depth++; \ 156} while (0) 157#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 158 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 159 (_tq)->axq_depth--; \ 160} while (0) 161 162struct ath_softc { 163 struct ifnet *sc_ifp; /* interface common */ 164 struct ath_stats sc_stats; /* interface statistics */ 165 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 166 int sc_regdomain; 167 int sc_countrycode; 168 int sc_debug; 169 void (*sc_recv_mgmt)(struct ieee80211com *, 170 struct mbuf *, 171 struct ieee80211_node *, 172 int, int, u_int32_t); 173 int (*sc_newstate)(struct ieee80211com *, 174 enum ieee80211_state, int); 175 void (*sc_node_free)(struct ieee80211_node *); 176 device_t sc_dev; 177 bus_space_tag_t sc_st; /* bus space tag */ 178 bus_space_handle_t sc_sh; /* bus space handle */ 179 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 180 struct mtx sc_mtx; /* master lock (recursive) */ 181 struct ath_hal *sc_ah; /* Atheros HAL */ 182 struct ath_ratectrl *sc_rc; /* tx rate control support */ 183 void (*sc_setdefantenna)(struct ath_softc *, u_int); 184 unsigned int sc_invalid : 1, /* disable hardware accesses */ 185 sc_mrretry : 1, /* multi-rate retry support */ 186 sc_softled : 1, /* enable LED gpio status */ 187 sc_splitmic: 1, /* split TKIP MIC keys */ 188 sc_needmib : 1, /* enable MIB stats intr */ 189 sc_diversity : 1,/* enable rx diversity */ 190 sc_hasveol : 1, /* tx VEOL support */ 191 sc_ledstate: 1, /* LED on/off state */ 192 sc_blinking: 1, /* LED blink operation active */ 193 sc_mcastkey: 1, /* mcast key cache search */ 194 sc_hasclrkey:1; /* CLR key supported */ 195 /* rate tables */ 196 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 197 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 198 enum ieee80211_phymode sc_curmode; /* current phy mode */ 199 u_int16_t sc_curtxpow; /* current tx power limit */ 200 HAL_CHANNEL sc_curchan; /* current h/w channel */ 201 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 202 struct { 203 u_int8_t ieeerate; /* IEEE rate */ 204 u_int8_t rxflags; /* radiotap rx flags */ 205 u_int8_t txflags; /* radiotap tx flags */ 206 u_int16_t ledon; /* softled on time */ 207 u_int16_t ledoff; /* softled off time */ 208 } sc_hwmap[32]; /* h/w rate ix mappings */ 209 u_int8_t sc_protrix; /* protection rate index */ 210 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 211 HAL_INT sc_imask; /* interrupt mask copy */ 212 u_int sc_keymax; /* size of key cache */ 213 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 214 215 u_int sc_ledpin; /* GPIO pin for driving LED */ 216 u_int sc_ledon; /* pin setting for LED on */ 217 u_int sc_ledidle; /* idle polling interval */ 218 int sc_ledevent; /* time of last LED event */ 219 u_int8_t sc_rxrate; /* current rx rate for LED */ 220 u_int8_t sc_txrate; /* current tx rate for LED */ 221 u_int16_t sc_ledoff; /* off time for current blink */ 222 struct callout sc_ledtimer; /* led off timer */ 223 224 struct bpf_if *sc_drvbpf; 225 union { 226 struct ath_tx_radiotap_header th; 227 u_int8_t pad[64]; 228 } u_tx_rt; 229 int sc_tx_th_len; 230 union { 231 struct ath_rx_radiotap_header th; 232 u_int8_t pad[64]; 233 } u_rx_rt; 234 int sc_rx_th_len; 235 u_int sc_monpass; /* frames to pass in mon.mode */ 236 237 struct task sc_fataltask; /* fatal int processing */ 238 239 struct ath_descdma sc_rxdma; /* RX descriptos */ 240 ath_bufhead sc_rxbuf; /* receive buffer */ 241 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 242 struct task sc_rxtask; /* rx int processing */ 243 struct task sc_rxorntask; /* rxorn int processing */ 244 u_int8_t sc_defant; /* current default antenna */ 245 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 246 247 struct ath_descdma sc_txdma; /* TX descriptors */ 248 ath_bufhead sc_txbuf; /* transmit buffer */ 249 struct mtx sc_txbuflock; /* txbuf lock */ 250 int sc_tx_timer; /* transmit timeout */ 251 u_int sc_txqsetup; /* h/w queues setup */ 252 u_int sc_txintrperiod;/* tx interrupt batching */ 253 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 254 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 255 struct task sc_txtask; /* tx int processing */ 256 257 struct ath_descdma sc_bdma; /* beacon descriptors */ 258 ath_bufhead sc_bbuf; /* beacon buffers */ 259 u_int sc_bhalq; /* HAL q for outgoing beacons */ 260 u_int sc_bmisscount; /* missed beacon transmits */ 261 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 262 struct ath_txq *sc_cabq; /* tx q for cab frames */ 263 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 264 struct task sc_bmisstask; /* bmiss int processing */ 265 struct task sc_bstucktask; /* stuck beacon processing */ 266 enum { 267 OK, /* no change needed */ 268 UPDATE, /* update pending */ 269 COMMIT /* beacon sent, commit change */ 270 } sc_updateslot; /* slot time update fsm */ 271 272 struct callout sc_cal_ch; /* callout handle for cals */ 273 struct callout sc_scan_ch; /* callout handle for scan */ 274}; 275#define sc_tx_th u_tx_rt.th 276#define sc_rx_th u_rx_rt.th 277 278#define ATH_LOCK_INIT(_sc) \ 279 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 280 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 281#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 282#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 283#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 284#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 285 286#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 287 288#define ATH_TXBUF_LOCK_INIT(_sc) \ 289 mtx_init(&(_sc)->sc_txbuflock, \ 290 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 291#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 292#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 293#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 294#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 295 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 296 297int ath_attach(u_int16_t, struct ath_softc *); 298int ath_detach(struct ath_softc *); 299void ath_resume(struct ath_softc *); 300void ath_suspend(struct ath_softc *); 301void ath_shutdown(struct ath_softc *); 302void ath_intr(void *); 303 304/* 305 * HAL definitions to comply with local coding convention. 306 */ 307#define ath_hal_detach(_ah) \ 308 ((*(_ah)->ah_detach)((_ah))) 309#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 310 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 311#define ath_hal_getratetable(_ah, _mode) \ 312 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 313#define ath_hal_getmac(_ah, _mac) \ 314 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 315#define ath_hal_setmac(_ah, _mac) \ 316 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 317#define ath_hal_intrset(_ah, _mask) \ 318 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 319#define ath_hal_intrget(_ah) \ 320 ((*(_ah)->ah_getInterrupts)((_ah))) 321#define ath_hal_intrpend(_ah) \ 322 ((*(_ah)->ah_isInterruptPending)((_ah))) 323#define ath_hal_getisr(_ah, _pmask) \ 324 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 325#define ath_hal_updatetxtriglevel(_ah, _inc) \ 326 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 327#define ath_hal_setpower(_ah, _mode, _sleepduration) \ 328 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 329#define ath_hal_keycachesize(_ah) \ 330 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 331#define ath_hal_keyreset(_ah, _ix) \ 332 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 333#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 334 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 335#define ath_hal_keyisvalid(_ah, _ix) \ 336 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 337#define ath_hal_keysetmac(_ah, _ix, _mac) \ 338 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 339#define ath_hal_getrxfilter(_ah) \ 340 ((*(_ah)->ah_getRxFilter)((_ah))) 341#define ath_hal_setrxfilter(_ah, _filter) \ 342 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 343#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 344 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 345#define ath_hal_waitforbeacon(_ah, _bf) \ 346 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 347#define ath_hal_putrxbuf(_ah, _bufaddr) \ 348 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 349#define ath_hal_gettsf32(_ah) \ 350 ((*(_ah)->ah_getTsf32)((_ah))) 351#define ath_hal_gettsf64(_ah) \ 352 ((*(_ah)->ah_getTsf64)((_ah))) 353#define ath_hal_resettsf(_ah) \ 354 ((*(_ah)->ah_resetTsf)((_ah))) 355#define ath_hal_rxena(_ah) \ 356 ((*(_ah)->ah_enableReceive)((_ah))) 357#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 358 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 359#define ath_hal_gettxbuf(_ah, _q) \ 360 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 361#define ath_hal_numtxpending(_ah, _q) \ 362 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 363#define ath_hal_getrxbuf(_ah) \ 364 ((*(_ah)->ah_getRxDP)((_ah))) 365#define ath_hal_txstart(_ah, _q) \ 366 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 367#define ath_hal_setchannel(_ah, _chan) \ 368 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 369#define ath_hal_calibrate(_ah, _chan) \ 370 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 371#define ath_hal_setledstate(_ah, _state) \ 372 ((*(_ah)->ah_setLedState)((_ah), (_state))) 373#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 374 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 375#define ath_hal_beaconreset(_ah) \ 376 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 377#define ath_hal_beacontimers(_ah, _bs) \ 378 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 379#define ath_hal_setassocid(_ah, _bss, _associd) \ 380 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 381#define ath_hal_phydisable(_ah) \ 382 ((*(_ah)->ah_phyDisable)((_ah))) 383#define ath_hal_setopmode(_ah) \ 384 ((*(_ah)->ah_setPCUConfig)((_ah))) 385#define ath_hal_stoptxdma(_ah, _qnum) \ 386 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 387#define ath_hal_stoppcurecv(_ah) \ 388 ((*(_ah)->ah_stopPcuReceive)((_ah))) 389#define ath_hal_startpcurecv(_ah) \ 390 ((*(_ah)->ah_startPcuReceive)((_ah))) 391#define ath_hal_stopdmarecv(_ah) \ 392 ((*(_ah)->ah_stopDmaReceive)((_ah))) 393#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 394 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 395 (_indata), (_insize), (_outdata), (_outsize))) 396#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 397 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 398#define ath_hal_resettxqueue(_ah, _q) \ 399 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 400#define ath_hal_releasetxqueue(_ah, _q) \ 401 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 402#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 403 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 404#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 405 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 406#define ath_hal_getrfgain(_ah) \ 407 ((*(_ah)->ah_getRfGain)((_ah))) 408#define ath_hal_getdefantenna(_ah) \ 409 ((*(_ah)->ah_getDefAntenna)((_ah))) 410#define ath_hal_setdefantenna(_ah, _ant) \ 411 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 412#define ath_hal_rxmonitor(_ah, _arg) \ 413 ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 414#define ath_hal_mibevent(_ah, _stats) \ 415 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 416#define ath_hal_setslottime(_ah, _us) \ 417 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 418#define ath_hal_getslottime(_ah) \ 419 ((*(_ah)->ah_getSlotTime)((_ah))) 420#define ath_hal_setacktimeout(_ah, _us) \ 421 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 422#define ath_hal_getacktimeout(_ah) \ 423 ((*(_ah)->ah_getAckTimeout)((_ah))) 424#define ath_hal_setctstimeout(_ah, _us) \ 425 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 426#define ath_hal_getctstimeout(_ah) \ 427 ((*(_ah)->ah_getCTSTimeout)((_ah))) 428#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 429 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 430#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 431 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 432#define ath_hal_ciphersupported(_ah, _cipher) \ 433 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 434#define ath_hal_getregdomain(_ah, _prd) \ 435 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 436#define ath_hal_getcountrycode(_ah, _pcc) \ 437 (*(_pcc) = (_ah)->ah_countryCode) 438#define ath_hal_tkipsplit(_ah) \ 439 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 440#define ath_hal_hwphycounters(_ah) \ 441 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 442#define ath_hal_hasdiversity(_ah) \ 443 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 444#define ath_hal_getdiversity(_ah) \ 445 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 446#define ath_hal_setdiversity(_ah, _v) \ 447 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 448#define ath_hal_getdiag(_ah, _pv) \ 449 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 450#define ath_hal_setdiag(_ah, _v) \ 451 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 452#define ath_hal_getnumtxqueues(_ah, _pv) \ 453 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 454#define ath_hal_hasveol(_ah) \ 455 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 456#define ath_hal_hastxpowlimit(_ah) \ 457 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 458#define ath_hal_settxpowlimit(_ah, _pow) \ 459 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 460#define ath_hal_gettxpowlimit(_ah, _ppow) \ 461 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 462#define ath_hal_getmaxtxpow(_ah, _ppow) \ 463 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 464#define ath_hal_gettpscale(_ah, _scale) \ 465 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 466#define ath_hal_settpscale(_ah, _v) \ 467 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 468#define ath_hal_hastpc(_ah) \ 469 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 470#define ath_hal_gettpc(_ah) \ 471 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 472#define ath_hal_settpc(_ah, _v) \ 473 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 474#define ath_hal_hasbursting(_ah) \ 475 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 476#ifdef notyet 477#define ath_hal_hasmcastkeysearch(_ah) \ 478 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 479#define ath_hal_getmcastkeysearch(_ah) \ 480 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 481#else 482#define ath_hal_getmcastkeysearch(_ah) 0 483#endif 484#if HAL_ABI_VERSION < 0x05120700 485#define ath_hal_process_noisefloor(_ah) 486#define ath_hal_getchannoise(_ah, _c) (-96) 487#define HAL_CAP_TPC_ACK 100 488#define HAL_CAP_TPC_CTS 101 489#else 490#define ath_hal_getchannoise(_ah, _c) \ 491 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 492#endif 493 494#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 495 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 496#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 497 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 498#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 499 _txr0, _txtr0, _keyix, _ant, _flags, \ 500 _rtsrate, _rtsdura) \ 501 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 502 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 503 (_flags), (_rtsrate), (_rtsdura))) 504#define ath_hal_setupxtxdesc(_ah, _ds, \ 505 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 506 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 507 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 508#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 509 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 510#define ath_hal_txprocdesc(_ah, _ds) \ 511 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 512 513#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 514 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 515#define ath_hal_gpioset(_ah, _gpio, _b) \ 516 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 517 518#endif /* _DEV_ATH_ATHVAR_H */ 519