if_athvar.h revision 127698
1116743Ssam/*- 2116743Ssam * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 3. Neither the names of the above-listed copyright holders nor the names 16116743Ssam * of any contributors may be used to endorse or promote products derived 17116743Ssam * from this software without specific prior written permission. 18116743Ssam * 19116743Ssam * Alternatively, this software may be distributed under the terms of the 20116743Ssam * GNU General Public License ("GPL") version 2 as published by the Free 21116743Ssam * Software Foundation. 22116743Ssam * 23116743Ssam * NO WARRANTY 24116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 35116743Ssam * 36116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 127698 2004-04-01 00:38:45Z sam $ 37116743Ssam */ 38116743Ssam 39116743Ssam/* 40116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 41116743Ssam */ 42116743Ssam#ifndef _DEV_ATH_ATHVAR_H 43116743Ssam#define _DEV_ATH_ATHVAR_H 44116743Ssam 45116743Ssam#include <sys/taskqueue.h> 46116743Ssam 47116743Ssam#include <contrib/dev/ath/ah.h> 48119783Ssam#include <net80211/ieee80211_radiotap.h> 49116743Ssam#include <dev/ath/if_athioctl.h> 50116743Ssam 51116743Ssam#define ATH_TIMEOUT 1000 52116743Ssam 53116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 54116743Ssam#define ATH_TXBUF 60 /* number of TX buffers */ 55116743Ssam#define ATH_TXDESC 8 /* number of descriptors per buffer */ 56116743Ssam 57120105Ssamstruct ath_recv_hist { 58120105Ssam int arh_ticks; /* sample time by system clock */ 59120105Ssam u_int8_t arh_rssi; /* rssi */ 60120105Ssam u_int8_t arh_antenna; /* antenna */ 61120105Ssam}; 62120105Ssam#define ATH_RHIST_SIZE 16 /* number of samples */ 63120105Ssam#define ATH_RHIST_NOTIME (~0) 64120105Ssam 65116743Ssam/* driver-specific node */ 66116743Ssamstruct ath_node { 67119150Ssam struct ieee80211_node an_node; /* base class */ 68116743Ssam u_int an_tx_ok; /* tx ok pkt */ 69116743Ssam u_int an_tx_err; /* tx !ok pkt */ 70116743Ssam u_int an_tx_retr; /* tx retry count */ 71116743Ssam int an_tx_upper; /* tx upper rate req cnt */ 72116743Ssam u_int an_tx_antenna; /* antenna for last good frame */ 73119150Ssam u_int an_rx_antenna; /* antenna for last rcvd frame */ 74120105Ssam struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 75120105Ssam u_int an_rx_hist_next;/* index of next ``free entry'' */ 76116743Ssam}; 77119150Ssam#define ATH_NODE(_n) ((struct ath_node *)(_n)) 78116743Ssam 79116743Ssamstruct ath_buf { 80116743Ssam TAILQ_ENTRY(ath_buf) bf_list; 81116743Ssam int bf_nseg; 82116743Ssam bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 83116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 84116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 85116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 86116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 87116743Ssam bus_size_t bf_mapsize; 88116743Ssam#define ATH_MAX_SCATTER 64 89116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 90116743Ssam}; 91116743Ssam 92116743Ssamstruct ath_softc { 93116743Ssam struct ieee80211com sc_ic; /* IEEE 802.11 common */ 94117812Ssam int (*sc_newstate)(struct ieee80211com *, 95117812Ssam enum ieee80211_state, int); 96116743Ssam device_t sc_dev; 97116743Ssam bus_space_tag_t sc_st; /* bus space tag */ 98116743Ssam bus_space_handle_t sc_sh; /* bus space handle */ 99116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 100116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 101116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 102116743Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 103116743Ssam sc_doani : 1,/* dynamic noise immunity */ 104116743Ssam sc_probing : 1;/* probing AP on beacon miss */ 105116743Ssam /* rate tables */ 106116743Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 107116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 108116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 109116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 110119144Ssam u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 111116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 112116743Ssam 113119783Ssam struct bpf_if *sc_drvbpf; 114119783Ssam union { 115119783Ssam struct ath_tx_radiotap_header th; 116119783Ssam u_int8_t pad[64]; 117119783Ssam } u_tx_rt; 118127698Ssam int sc_tx_th_len; 119119783Ssam union { 120119783Ssam struct ath_rx_radiotap_header th; 121119783Ssam u_int8_t pad[64]; 122119783Ssam } u_rx_rt; 123127698Ssam int sc_rx_th_len; 124119783Ssam 125116743Ssam struct ath_desc *sc_desc; /* TX/RX descriptors */ 126116743Ssam bus_dma_segment_t sc_dseg; 127116743Ssam bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 128116743Ssam bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 129116743Ssam bus_addr_t sc_desc_len; /* size of sc_desc */ 130116743Ssam 131116743Ssam struct task sc_fataltask; /* fatal int processing */ 132116743Ssam struct task sc_rxorntask; /* rxorn int processing */ 133116743Ssam 134116743Ssam TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 135116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 136116743Ssam struct task sc_rxtask; /* rx int processing */ 137116743Ssam 138116743Ssam u_int sc_txhalq; /* HAL q for outgoing frames */ 139116743Ssam u_int32_t *sc_txlink; /* link ptr in last TX desc */ 140116743Ssam int sc_tx_timer; /* transmit timeout */ 141116743Ssam TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 142116743Ssam struct mtx sc_txbuflock; /* txbuf lock */ 143116743Ssam TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 144116743Ssam struct mtx sc_txqlock; /* lock on txq and txlink */ 145116743Ssam struct task sc_txtask; /* tx int processing */ 146116743Ssam 147116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 148116743Ssam struct ath_buf *sc_bcbuf; /* beacon buffer */ 149116743Ssam struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 150116743Ssam struct task sc_swbatask; /* swba int processing */ 151116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 152116743Ssam 153116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 154116743Ssam struct callout sc_scan_ch; /* callout handle for scan */ 155116743Ssam struct ath_stats sc_stats; /* interface statistics */ 156116743Ssam}; 157119783Ssam#define sc_tx_th u_tx_rt.th 158119783Ssam#define sc_rx_th u_rx_rt.th 159116743Ssam 160121100Ssam#define ATH_LOCK_INIT(_sc) \ 161121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 162121100Ssam MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 163121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 164121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 165121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 166121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 167121100Ssam 168121100Ssam#define ATH_TXBUF_LOCK_INIT(_sc) \ 169121100Ssam mtx_init(&(_sc)->sc_txbuflock, \ 170121100Ssam device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 171121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 172121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 173121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 174121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 175121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 176121100Ssam 177121100Ssam#define ATH_TXQ_LOCK_INIT(_sc) \ 178121100Ssam mtx_init(&(_sc)->sc_txqlock, \ 179121100Ssam device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 180121100Ssam#define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 181121100Ssam#define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 182121100Ssam#define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 183121100Ssam#define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 184121100Ssam 185116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 186116743Ssamint ath_detach(struct ath_softc *); 187116743Ssamvoid ath_resume(struct ath_softc *); 188116743Ssamvoid ath_suspend(struct ath_softc *); 189116743Ssamvoid ath_shutdown(struct ath_softc *); 190116743Ssamvoid ath_intr(void *); 191116743Ssam 192116743Ssam/* 193116743Ssam * HAL definitions to comply with local coding convention. 194116743Ssam */ 195116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 196116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 197116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 198116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 199117516Ssam#define ath_hal_getregdomain(_ah) \ 200117516Ssam ((*(_ah)->ah_getRegDomain)((_ah))) 201117516Ssam#define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 202116743Ssam#define ath_hal_getmac(_ah, _mac) \ 203116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 204116743Ssam#define ath_hal_detach(_ah) \ 205116743Ssam ((*(_ah)->ah_detach)((_ah))) 206116743Ssam#define ath_hal_intrset(_ah, _mask) \ 207116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 208116743Ssam#define ath_hal_intrget(_ah) \ 209116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 210116743Ssam#define ath_hal_intrpend(_ah) \ 211116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 212116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 213116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 214116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 215116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 216116743Ssam#define ath_hal_setpower(_ah, _mode, _sleepduration) \ 217116743Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 218116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 219116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 220116743Ssam#define ath_hal_keyset(_ah, _ix, _pk) \ 221116743Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 222116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 223116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 224116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 225116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 226116743Ssam#define ath_hal_getrxfilter(_ah) \ 227116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 228116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 229116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 230116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 231116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 232116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 233116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 234116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 235116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 236116743Ssam#define ath_hal_gettsf32(_ah) \ 237116743Ssam ((*(_ah)->ah_getTsf32)((_ah))) 238116743Ssam#define ath_hal_gettsf64(_ah) \ 239116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 240116743Ssam#define ath_hal_resettsf(_ah) \ 241116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 242116743Ssam#define ath_hal_rxena(_ah) \ 243116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 244116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 245116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 246116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 247116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 248116743Ssam#define ath_hal_getrxbuf(_ah) \ 249116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 250116743Ssam#define ath_hal_txstart(_ah, _q) \ 251116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 252116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 253116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 254116743Ssam#define ath_hal_calibrate(_ah, _chan) \ 255116743Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 256116743Ssam#define ath_hal_setledstate(_ah, _state) \ 257116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 258116743Ssam#define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 259116743Ssam ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 260116743Ssam#define ath_hal_beaconreset(_ah) \ 261116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 262116743Ssam#define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 263116743Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 264116743Ssam (_dc), (_cc))) 265116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 266116743Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 267116743Ssam#define ath_hal_setopmode(_ah, _opmode) \ 268116743Ssam ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 269116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 270116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 271116743Ssam#define ath_hal_stoppcurecv(_ah) \ 272116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 273116743Ssam#define ath_hal_startpcurecv(_ah) \ 274116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 275116743Ssam#define ath_hal_stopdmarecv(_ah) \ 276116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 277116743Ssam#define ath_hal_dumpstate(_ah) \ 278116743Ssam ((*(_ah)->ah_dumpState)((_ah))) 279123044Ssam#define ath_hal_getdiagstate(_ah, _id, _data, _size) \ 280123044Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size))) 281116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 282116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 283116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 284116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 285116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 286116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 287116743Ssam#define ath_hal_hasveol(_ah) \ 288116743Ssam ((*(_ah)->ah_hasVEOL)((_ah))) 289116743Ssam#define ath_hal_getrfgain(_ah) \ 290116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 291116743Ssam#define ath_hal_rxmonitor(_ah) \ 292116743Ssam ((*(_ah)->ah_rxMonitor)((_ah))) 293116743Ssam 294116743Ssam#define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 295116743Ssam _rate, _antmode) \ 296116743Ssam ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 297116743Ssam (_flen), (_hlen), (_rate), (_antmode))) 298116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 299116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 300123044Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 301123044Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 302116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 303116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 304116743Ssam _rtsrate, _rtsdura) \ 305116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 306116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 307116743Ssam (_flags), (_rtsrate), (_rtsdura))) 308116743Ssam#define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 309116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 310116743Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 311116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 312116743Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 313116743Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 314116743Ssam#define ath_hal_txprocdesc(_ah, _ds) \ 315116743Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 316116743Ssam 317116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 318