1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD$ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38241567Sadrian#include <machine/atomic.h> 39241567Sadrian 40185522Ssam#include <dev/ath/ath_hal/ah.h> 41185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 42119783Ssam#include <net80211/ieee80211_radiotap.h> 43116743Ssam#include <dev/ath/if_athioctl.h> 44138570Ssam#include <dev/ath/if_athrate.h> 45242782Sadrian#ifdef ATH_DEBUG_ALQ 46242782Sadrian#include <dev/ath/if_ath_alq.h> 47242782Sadrian#endif 48116743Ssam 49116743Ssam#define ATH_TIMEOUT 1000 50116743Ssam 51220033Sadrian/* 52237000Sadrian * There is a separate TX ath_buf pool for management frames. 53237000Sadrian * This ensures that management frames such as probe responses 54237000Sadrian * and BAR frames can be transmitted during periods of high 55237000Sadrian * TX activity. 56237000Sadrian */ 57237000Sadrian#define ATH_MGMT_TXBUF 32 58237000Sadrian 59237000Sadrian/* 60220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 61220033Sadrian */ 62220053Sadrian#ifdef ATH_ENABLE_11N 63235804Sadrian#define ATH_TXBUF 512 64220033Sadrian#define ATH_RXBUF 512 65220033Sadrian#endif 66220033Sadrian 67155481Ssam#ifndef ATH_RXBUF 68116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 69155481Ssam#endif 70155481Ssam#ifndef ATH_TXBUF 71170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 72155481Ssam#endif 73178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 74178354Ssam 75140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 76138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79116743Ssam 80225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83147067Ssam 84147057Ssam/* 85272292Sadrian * The following bits can be set during the PCI (and perhaps non-PCI 86272292Sadrian * later) device probe path. 87272292Sadrian * 88272292Sadrian * It controls some of the driver and HAL behaviour. 89272292Sadrian */ 90272292Sadrian 91272292Sadrian#define ATH_PCI_CUS198 0x0001 92272292Sadrian#define ATH_PCI_CUS230 0x0002 93272292Sadrian#define ATH_PCI_CUS217 0x0004 94272292Sadrian#define ATH_PCI_CUS252 0x0008 95272292Sadrian#define ATH_PCI_WOW 0x0010 96272292Sadrian#define ATH_PCI_BT_ANT_DIV 0x0020 97272292Sadrian#define ATH_PCI_D3_L1_WAR 0x0040 98272292Sadrian#define ATH_PCI_AR9565_1ANT 0x0080 99272292Sadrian#define ATH_PCI_AR9565_2ANT 0x0100 100272292Sadrian#define ATH_PCI_NO_PLL_PWRSAVE 0x0200 101272292Sadrian#define ATH_PCI_KILLER 0x0400 102272292Sadrian 103272292Sadrian/* 104147057Ssam * The key cache is used for h/w cipher state and also for 105147057Ssam * tracking station state such as the current tx antenna. 106147057Ssam * We also setup a mapping table between key cache slot indices 107147057Ssam * and station state to short-circuit node lookups on rx. 108147057Ssam * Different parts have different size key caches. We handle 109147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 110147057Ssam */ 111147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 112147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 113147057Ssam 114170530Ssamstruct taskqueue; 115170530Ssamstruct kthread; 116170530Ssamstruct ath_buf; 117170530Ssam 118227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 119227328Sadrian 120227328Sadrian/* 121227328Sadrian * Per-TID state 122227328Sadrian * 123227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 124227328Sadrian */ 125227328Sadrianstruct ath_tid { 126241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 127227328Sadrian struct ath_node *an; /* pointer to parent */ 128227328Sadrian int tid; /* tid */ 129298939Spfg int ac; /* which AC gets this traffic */ 130227328Sadrian int hwq_depth; /* how many buffers are on HW */ 131243786Sadrian u_int axq_depth; /* SW queue depth */ 132227328Sadrian 133240585Sadrian struct { 134241336Sadrian TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 135240585Sadrian u_int axq_depth; /* SW queue depth */ 136240585Sadrian } filtq; 137240585Sadrian 138227328Sadrian /* 139227328Sadrian * Entry on the ath_txq; when there's traffic 140227328Sadrian * to send 141227328Sadrian */ 142227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 143227328Sadrian int sched; 144227328Sadrian int paused; /* >0 if the TID has been paused */ 145240585Sadrian 146240585Sadrian /* 147240585Sadrian * These are flags - perhaps later collapse 148240585Sadrian * down to a single uint32_t ? 149240585Sadrian */ 150235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 151233908Sadrian int bar_wait; /* waiting for BAR */ 152233908Sadrian int bar_tx; /* BAR TXed */ 153240585Sadrian int isfiltered; /* is this node currently filtered */ 154227328Sadrian 155227328Sadrian /* 156227328Sadrian * Is the TID being cleaned up after a transition 157227328Sadrian * from aggregation to non-aggregation? 158227328Sadrian * When this is set to 1, this TID will be paused 159227328Sadrian * and no further traffic will be queued until all 160227328Sadrian * the hardware packets pending for this TID have been 161227328Sadrian * TXed/completed; at which point (non-aggregation) 162227328Sadrian * traffic will resume being TXed. 163227328Sadrian */ 164227328Sadrian int cleanup_inprogress; 165227328Sadrian /* 166227328Sadrian * How many hardware-queued packets are 167227328Sadrian * waiting to be cleaned up. 168227328Sadrian * This is only valid if cleanup_inprogress is 1. 169227328Sadrian */ 170227328Sadrian int incomp; 171227328Sadrian 172227328Sadrian /* 173227328Sadrian * The following implements a ring representing 174227328Sadrian * the frames in the current BAW. 175227328Sadrian * To avoid copying the array content each time 176227328Sadrian * the BAW is moved, the baw_head/baw_tail point 177227328Sadrian * to the current BAW begin/end; when the BAW is 178227328Sadrian * shifted the head/tail of the array are also 179227328Sadrian * appropriately shifted. 180227328Sadrian */ 181227328Sadrian /* active tx buffers, beginning at current BAW */ 182227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 183227328Sadrian /* where the baw head is in the array */ 184227328Sadrian int baw_head; 185227328Sadrian /* where the BAW tail is in the array */ 186227328Sadrian int baw_tail; 187227328Sadrian}; 188227328Sadrian 189138570Ssam/* driver-specific node state */ 190116743Ssamstruct ath_node { 191119150Ssam struct ieee80211_node an_node; /* base class */ 192178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 193178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 194241170Sadrian uint32_t an_is_powersave; /* node is sleeping */ 195242271Sadrian uint32_t an_stack_psq; /* net80211 psq isn't empty */ 196242271Sadrian uint32_t an_tim_set; /* TIM has been set */ 197170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 198227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 199227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 200250607Sadrian struct mtx an_mtx; /* protecting the rate control state */ 201241567Sadrian uint32_t an_swq_depth; /* how many SWQ packets for this 202241567Sadrian node */ 203245708Sadrian int clrdmask; /* has clrdmask been set */ 204250665Sadrian uint32_t an_leak_count; /* How many frames to leak during pause */ 205138570Ssam /* variable-length rate control state follows */ 206116743Ssam}; 207138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 208138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 209116743Ssam 210138570Ssam#define ATH_RSSI_LPF_LEN 10 211138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 212138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 213138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 214138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 215138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 216138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 217138570Ssam if ((y) >= -20) \ 218138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 219138570Ssam} while (0) 220184358Ssam#define ATH_EP_RND(x,mul) \ 221184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 222184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 223138570Ssam 224237000Sadriantypedef enum { 225237000Sadrian ATH_BUFTYPE_NORMAL = 0, 226237000Sadrian ATH_BUFTYPE_MGMT = 1, 227237000Sadrian} ath_buf_type_t; 228237000Sadrian 229116743Ssamstruct ath_buf { 230227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 231227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 232116743Ssam int bf_nseg; 233238436Sadrian HAL_STATUS bf_rxstatus; 234186904Ssam uint16_t bf_flags; /* status flags (below) */ 235239282Sadrian uint16_t bf_descid; /* 16 bit descriptor ID */ 236116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 237165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 238116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 239138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 240116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 241116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 242227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 243227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 244116743Ssam bus_size_t bf_mapsize; 245140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 246116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 247251014Sadrian uint32_t bf_nextfraglen; /* length of next fragment */ 248227328Sadrian 249227328Sadrian /* Completion function to call on TX complete (fail or not) */ 250227328Sadrian /* 251227328Sadrian * "fail" here is set to 1 if the queue entries were removed 252227328Sadrian * through a call to ath_tx_draintxq(). 253227328Sadrian */ 254227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 255227328Sadrian 256227328Sadrian /* This state is kept to support software retries and aggregation */ 257227328Sadrian struct { 258237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 259227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 260227328Sadrian 261237046Sadrian uint8_t bfs_retries; /* retry count */ 262237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 263237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 264237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 265244109Sadrian uint8_t bfs_tx_queue; /* destination hardware TX queue */ 266237046Sadrian 267234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 268234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 269234109Sadrian bfs_isretried:1, /* retried frame? */ 270234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 271234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 272234109Sadrian bfs_shpream:1, /* use short preamble */ 273234109Sadrian bfs_istxfrag:1, /* is fragmented */ 274234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 275234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 276236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 277234109Sadrian 278227328Sadrian /* 279227328Sadrian * These fields are passed into the 280227328Sadrian * descriptor setup functions. 281227328Sadrian */ 282237153Sadrian 283237153Sadrian /* Make this an 8 bit value? */ 284227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 285237153Sadrian 286237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 287237153Sadrian 288237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 289227328Sadrian uint16_t bfs_al; /* length of aggregate */ 290237153Sadrian 291237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 292237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 293237153Sadrian uint8_t bfs_try0; /* first try count */ 294237153Sadrian 295237153Sadrian uint16_t bfs_txpower; /* tx power */ 296227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 297237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 298237153Sadrian 299237153Sadrian /* 16 bit? */ 300237153Sadrian int32_t bfs_keyix; /* crypto key index */ 301237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 302237153Sadrian 303237153Sadrian /* Make this an 8 bit value? */ 304227328Sadrian enum ieee80211_protmode bfs_protmode; 305237153Sadrian 306237153Sadrian /* 16 bit? */ 307237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 308227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 309227328Sadrian } bf_state; 310116743Ssam}; 311227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 312116743Ssam 313237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 314186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 315248745Sadrian#define ATH_BUF_FIFOEND 0x00000004 316248745Sadrian#define ATH_BUF_FIFOPTR 0x00000008 317186904Ssam 318248745Sadrian#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 319248745Sadrian 320138570Ssam/* 321138570Ssam * DMA state for tx/rx descriptors. 322138570Ssam */ 323138570Ssamstruct ath_descdma { 324138570Ssam const char* dd_name; 325138570Ssam struct ath_desc *dd_desc; /* descriptors */ 326238708Sadrian int dd_descsize; /* size of single descriptor */ 327138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 328158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 329138570Ssam bus_dma_segment_t dd_dseg; 330138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 331138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 332138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 333138570Ssam}; 334138570Ssam 335138570Ssam/* 336138570Ssam * Data transmit queue state. One of these exists for each 337138570Ssam * hardware transmit queue. Packets sent to us from above 338138570Ssam * are assigned to queues based on their priority. Not all 339138570Ssam * devices support a complete set of hardware transmit queues. 340138570Ssam * For those devices the array sc_ac2q will map multiple 341138570Ssam * priorities to fewer hardware queues (typically all to one 342138570Ssam * hardware queue). 343138570Ssam */ 344138570Ssamstruct ath_txq { 345227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 346138570Ssam u_int axq_qnum; /* hardware q number */ 347178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 348190579Ssam u_int axq_ac; /* WME AC */ 349186904Ssam u_int axq_flags; 350250783Sadrian//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 351250783Sadrian#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 352156073Ssam u_int axq_depth; /* queue depth (stat only) */ 353227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 354138570Ssam u_int axq_intrcnt; /* interrupt count */ 355138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 356227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 357248671Sadrian struct mtx axq_lock; /* lock on q and link */ 358248671Sadrian 359248311Sadrian /* 360248745Sadrian * This is the FIFO staging buffer when doing EDMA. 361248745Sadrian * 362248745Sadrian * For legacy chips, we just push the head pointer to 363248745Sadrian * the hardware and we ignore this list. 364248745Sadrian * 365248745Sadrian * For EDMA, the staging buffer is treated as normal; 366248745Sadrian * when it's time to push a list of frames to the hardware 367248745Sadrian * we move that list here and we stamp buffers with 368248745Sadrian * flags to identify the beginning/end of that particular 369248745Sadrian * FIFO entry. 370248745Sadrian */ 371248745Sadrian struct { 372248745Sadrian TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 373302100Sadrian u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */ 374248745Sadrian } fifo; 375302100Sadrian u_int axq_fifo_depth; /* how many FIFO slots are active */ 376248745Sadrian 377248745Sadrian /* 378248311Sadrian * XXX the holdingbf field is protected by the TXBUF lock 379248671Sadrian * for now, NOT the TXQ lock. 380248311Sadrian * 381248311Sadrian * Architecturally, it would likely be better to move 382248311Sadrian * the holdingbf field to a separate array in ath_softc 383248311Sadrian * just to highlight that it's not protected by the normal 384248311Sadrian * TX path lock. 385248311Sadrian */ 386248264Sadrian struct ath_buf *axq_holdingbf; /* holding TX buffer */ 387155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 388227344Sadrian 389227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 390248671Sadrian /* 391248671Sadrian * This is protected by the general TX path lock, not (for now) 392248671Sadrian * by the TXQ lock. 393248671Sadrian */ 394227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 395138570Ssam}; 396138570Ssam 397248671Sadrian#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 398248671Sadrian snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 399248671Sadrian device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 400248671Sadrian mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 401248671Sadrian } while (0) 402248671Sadrian#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 403248671Sadrian#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 404248671Sadrian#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 405248671Sadrian#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 406250391Sadrian#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 407250391Sadrian MA_NOTOWNED) 408248671Sadrian 409248671Sadrian 410227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 411227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 412227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 413241170Sadrian#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 414241170Sadrian MA_NOTOWNED) 415227328Sadrian 416241336Sadrian/* 417241336Sadrian * These are for the hardware queue. 418241336Sadrian */ 419227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 420227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 421227344Sadrian (_tq)->axq_depth++; \ 422227344Sadrian} while (0) 423138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 424227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 425138570Ssam (_tq)->axq_depth++; \ 426138570Ssam} while (0) 427227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 428227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 429138570Ssam (_tq)->axq_depth--; \ 430138570Ssam} while (0) 431239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 432227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 433138570Ssam 434241336Sadrian/* 435241566Sadrian * These are for the TID software queue. 436241336Sadrian */ 437241336Sadrian#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 438241336Sadrian TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 439241336Sadrian (_tq)->axq_depth++; \ 440250609Sadrian (_tq)->an->an_swq_depth++; \ 441241336Sadrian} while (0) 442241336Sadrian#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 443241336Sadrian TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 444241336Sadrian (_tq)->axq_depth++; \ 445250609Sadrian (_tq)->an->an_swq_depth++; \ 446241336Sadrian} while (0) 447241336Sadrian#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 448241336Sadrian TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 449241336Sadrian (_tq)->axq_depth--; \ 450250609Sadrian (_tq)->an->an_swq_depth--; \ 451241336Sadrian} while (0) 452241336Sadrian#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 453241336Sadrian#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 454241336Sadrian 455241566Sadrian/* 456241566Sadrian * These are for the TID filtered frame queue 457241566Sadrian */ 458241566Sadrian#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 459241566Sadrian TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 460241566Sadrian (_tq)->axq_depth++; \ 461250609Sadrian (_tq)->an->an_swq_depth++; \ 462241566Sadrian} while (0) 463241566Sadrian#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 464241566Sadrian TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 465241566Sadrian (_tq)->axq_depth++; \ 466250609Sadrian (_tq)->an->an_swq_depth++; \ 467241566Sadrian} while (0) 468241566Sadrian#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 469241566Sadrian TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 470241566Sadrian (_tq)->axq_depth--; \ 471250609Sadrian (_tq)->an->an_swq_depth--; \ 472241566Sadrian} while (0) 473241566Sadrian#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 474241566Sadrian#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 475241566Sadrian 476178354Ssamstruct ath_vap { 477178354Ssam struct ieee80211vap av_vap; /* base class */ 478178354Ssam int av_bslot; /* beacon slot index */ 479178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 480178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 481178354Ssam 482178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 483283535Sadrian struct mbuf *, int, 484283535Sadrian const struct ieee80211_rx_stats *, int, int); 485178354Ssam int (*av_newstate)(struct ieee80211vap *, 486178354Ssam enum ieee80211_state, int); 487178354Ssam void (*av_bmiss)(struct ieee80211vap *); 488241170Sadrian void (*av_node_ps)(struct ieee80211_node *, int); 489242271Sadrian int (*av_set_tim)(struct ieee80211_node *, int); 490250665Sadrian void (*av_recv_pspoll)(struct ieee80211_node *, 491250665Sadrian struct mbuf *); 492178354Ssam}; 493178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 494178354Ssam 495155491Ssamstruct taskqueue; 496155486Ssamstruct ath_tx99; 497155486Ssam 498227328Sadrian/* 499227328Sadrian * Whether to reset the TX/RX queue with or without 500227328Sadrian * a queue flush. 501227328Sadrian */ 502227328Sadriantypedef enum { 503227328Sadrian ATH_RESET_DEFAULT = 0, 504227328Sadrian ATH_RESET_NOLOSS = 1, 505227328Sadrian ATH_RESET_FULL = 2, 506227328Sadrian} ATH_RESET_TYPE; 507227328Sadrian 508238055Sadrianstruct ath_rx_methods { 509248529Sadrian void (*recv_sched_queue)(struct ath_softc *sc, 510248529Sadrian HAL_RX_QUEUE q, int dosched); 511248529Sadrian void (*recv_sched)(struct ath_softc *sc, int dosched); 512238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 513238055Sadrian int (*recv_start)(struct ath_softc *sc); 514238055Sadrian void (*recv_flush)(struct ath_softc *sc); 515238055Sadrian void (*recv_tasklet)(void *arg, int npending); 516238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 517238055Sadrian struct ath_buf *bf); 518238284Sadrian int (*recv_setup)(struct ath_softc *sc); 519238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 520238055Sadrian}; 521238055Sadrian 522238284Sadrian/* 523238284Sadrian * Represent the current state of the RX FIFO. 524238284Sadrian */ 525238284Sadrianstruct ath_rx_edma { 526238284Sadrian struct ath_buf **m_fifo; 527238284Sadrian int m_fifolen; 528238284Sadrian int m_fifo_head; 529238284Sadrian int m_fifo_tail; 530238284Sadrian int m_fifo_depth; 531238284Sadrian struct mbuf *m_rxpending; 532265409Sadrian struct ath_buf *m_holdbf; 533238284Sadrian}; 534238284Sadrian 535238855Sadrianstruct ath_tx_edma_fifo { 536238855Sadrian struct ath_buf **m_fifo; 537238855Sadrian int m_fifolen; 538238855Sadrian int m_fifo_head; 539238855Sadrian int m_fifo_tail; 540238855Sadrian int m_fifo_depth; 541238855Sadrian}; 542238855Sadrian 543238710Sadrianstruct ath_tx_methods { 544238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 545238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 546238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 547238931Sadrian 548238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 549238931Sadrian struct ath_txq *txq); 550238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 551238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 552239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 553239204Sadrian ATH_RESET_TYPE reset_type); 554238710Sadrian}; 555238710Sadrian 556116743Ssamstruct ath_softc { 557287197Sglebius struct ieee80211com sc_ic; 558287197Sglebius struct ath_stats sc_stats; /* device statistics */ 559227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 560234090Sadrian struct ath_intr_stats sc_intr_stats; 561235491Sadrian uint64_t sc_debug; 562240899Sadrian uint64_t sc_ktrdebug; 563178354Ssam int sc_nvaps; /* # vaps */ 564178354Ssam int sc_nstavaps; /* # station vaps */ 565195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 566178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 567178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 568178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 569178354Ssam 570238055Sadrian struct ath_rx_methods sc_rx; 571238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 572249565Sadrian ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 573238710Sadrian struct ath_tx_methods sc_tx; 574238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 575238710Sadrian 576245465Sadrian /* 577245465Sadrian * This is (currently) protected by the TX queue lock; 578245465Sadrian * it should migrate to a separate lock later 579245465Sadrian * so as to minimise contention. 580245465Sadrian */ 581245465Sadrian ath_bufhead sc_txbuf_list; 582245465Sadrian 583238284Sadrian int sc_rx_statuslen; 584238284Sadrian int sc_tx_desclen; 585238284Sadrian int sc_tx_statuslen; 586238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 587238284Sadrian int sc_edma_bufsize; 588271887Sadrian int sc_rx_stopped; /* XXX only for EDMA */ 589271887Sadrian int sc_rx_resetted; /* XXX only for EDMA */ 590238055Sadrian 591227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 592138570Ssam void (*sc_node_free)(struct ieee80211_node *); 593116743Ssam device_t sc_dev; 594159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 595159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 596116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 597116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 598227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 599227328Sadrian char sc_pcu_mtx_name[32]; 600238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 601238433Sadrian char sc_rx_mtx_name[32]; 602246453Sadrian struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 603242391Sadrian char sc_tx_mtx_name[32]; 604246453Sadrian struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 605246453Sadrian char sc_tx_ic_mtx_name[32]; 606155491Ssam struct taskqueue *sc_tq; /* private task queue */ 607116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 608138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 609155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 610138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 611242527Sadrian 612242527Sadrian /* 613242527Sadrian * First set of flags. 614242527Sadrian */ 615242527Sadrian uint32_t sc_invalid : 1,/* disable hardware accesses */ 616178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 617238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 618178354Ssam sc_softled : 1,/* enable LED gpio status */ 619228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 620178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 621178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 622178354Ssam sc_diversity: 1,/* enable rx diversity */ 623178354Ssam sc_hasveol : 1,/* tx VEOL support */ 624178354Ssam sc_ledstate : 1,/* LED on/off state */ 625178354Ssam sc_blinking : 1,/* LED blink operation active */ 626178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 627178354Ssam sc_scanning : 1,/* scanning active */ 628155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 629178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 630165571Ssam sc_xchanmode: 1,/* extended channel mode */ 631170530Ssam sc_outdoor : 1,/* outdoor operation */ 632178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 633178354Ssam sc_hasbmask : 1,/* bssid mask support */ 634195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 635178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 636178354Ssam sc_beacons : 1,/* beacons running */ 637178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 638178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 639179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 640185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 641186904Ssam sc_tdma : 1,/* TDMA in use */ 642189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 643220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 644224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 645238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 646265115Sadrian sc_isedma : 1,/* supports EDMA */ 647265115Sadrian sc_do_mybeacon : 1; /* supports mybeacon */ 648242527Sadrian 649242527Sadrian /* 650242527Sadrian * Second set of flags. 651242527Sadrian */ 652287197Sglebius u_int32_t sc_running : 1, /* initialized */ 653287197Sglebius sc_use_ent : 1, 654247366Sadrian sc_rx_stbc : 1, 655250865Sadrian sc_tx_stbc : 1, 656298608Sadrian sc_has_ldpc : 1, 657251401Sadrian sc_hasenforcetxop : 1, /* support enforce TxOP */ 658251655Sadrian sc_hasdivcomb : 1, /* RX diversity combining */ 659301181Sadrian sc_rx_lnamixer : 1, /* RX using LNA mixing */ 660301181Sadrian sc_btcoex_mci : 1; /* MCI bluetooth coex */ 661242527Sadrian 662248671Sadrian int sc_cabq_enable; /* Enable cabq transmission */ 663248671Sadrian 664242527Sadrian /* 665242527Sadrian * Enterprise mode configuration for AR9380 and later chipsets. 666242527Sadrian */ 667242527Sadrian uint32_t sc_ent_cfg; 668242527Sadrian 669178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 670178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 671116743Ssam /* rate tables */ 672188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 673116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 674116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 675155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 676138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 677170530Ssam u_int16_t sc_curaid; /* current association id */ 678187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 679170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 680116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 681140432Ssam struct { 682140432Ssam u_int8_t ieeerate; /* IEEE rate */ 683140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 684140761Ssam u_int8_t txflags; /* radiotap tx flags */ 685140432Ssam u_int16_t ledon; /* softled on time */ 686140432Ssam u_int16_t ledoff; /* softled off time */ 687140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 688138570Ssam u_int8_t sc_protrix; /* protection rate index */ 689170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 690155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 691170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 692170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 693138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 694227346Sadrian 695116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 696227651Sadrian 697227346Sadrian /* 698227346Sadrian * These are modified in the interrupt handler as well as 699227346Sadrian * the task queues and other contexts. Thus these must be 700227346Sadrian * protected by a mutex, or they could clash. 701227346Sadrian * 702227346Sadrian * For now, access to these is behind the ATH_LOCK, 703227346Sadrian * just to save time. 704227346Sadrian */ 705227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 706227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 707227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 708227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 709227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 710227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 711227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 712227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 713227346Sadrian 714138570Ssam u_int sc_keymax; /* size of key cache */ 715147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 716116743Ssam 717228891Sadrian /* 718228891Sadrian * Software based LED blinking 719228891Sadrian */ 720140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 721140432Ssam u_int sc_ledon; /* pin setting for LED on */ 722140432Ssam u_int sc_ledidle; /* idle polling interval */ 723140432Ssam int sc_ledevent; /* time of last LED event */ 724184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 725140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 726140432Ssam struct callout sc_ledtimer; /* led off timer */ 727138570Ssam 728228891Sadrian /* 729228891Sadrian * Hardware based LED blinking 730228891Sadrian */ 731228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 732228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 733228891Sadrian 734155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 735155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 736155515Ssam 737178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 738138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 739116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 740116743Ssam struct task sc_rxtask; /* rx int processing */ 741138570Ssam u_int8_t sc_defant; /* current default antenna */ 742138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 743155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 744192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 745192468Ssam struct ath_rx_radiotap_header sc_rx_th; 746192468Ssam int sc_rx_th_len; 747192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 748116743Ssam 749138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 750239282Sadrian uint16_t sc_txbuf_descid; 751138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 752237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 753237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 754237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 755238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 756138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 757155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 758138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 759138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 760138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 761138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 762116743Ssam struct task sc_txtask; /* tx int processing */ 763233673Sadrian struct task sc_txqtask; /* tx proc processing */ 764238709Sadrian 765238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 766238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 767238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 768238709Sadrian 769189605Ssam int sc_wd_timer; /* count down for wd timer */ 770189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 771192468Ssam struct ath_tx_radiotap_header sc_tx_th; 772192468Ssam int sc_tx_th_len; 773116743Ssam 774138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 775138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 776116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 777138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 778138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 779138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 780116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 781138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 782232163Sadrian struct task sc_resettask; /* interface reset task */ 783234369Sadrian struct task sc_fataltask; /* fatal task */ 784138570Ssam enum { 785138570Ssam OK, /* no change needed */ 786138570Ssam UPDATE, /* update pending */ 787138570Ssam COMMIT /* beacon sent, commit change */ 788138570Ssam } sc_updateslot; /* slot time update fsm */ 789178354Ssam int sc_slotupdate; /* slot to advance fsm */ 790178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 791178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 792116743Ssam 793116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 794185744Ssam int sc_lastlongcal; /* last long cal completed */ 795185744Ssam int sc_lastcalreset;/* last cal reset done */ 796217684Sadrian int sc_lastani; /* last ANI poll */ 797217684Sadrian int sc_lastshortcal; /* last short calibration */ 798217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 799155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 800186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 801186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 802186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 803186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 804186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 805186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 806186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 807186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 808217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 809249639Sadrian uint32_t sc_txchainmask; /* hardware TX chainmask */ 810249639Sadrian uint32_t sc_rxchainmask; /* hardware RX chainmask */ 811249639Sadrian uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 812249639Sadrian uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 813249639Sadrian uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 814247085Sadrian int sc_aggr_limit; /* TX limit on all aggregates */ 815247087Sadrian int sc_delim_min_pad; /* Minimum delimiter count */ 816222585Sadrian 817232764Sadrian /* Queue limits */ 818232764Sadrian 819227328Sadrian /* 820232764Sadrian * To avoid queue starvation in congested conditions, 821232764Sadrian * these parameters tune the maximum number of frames 822232764Sadrian * queued to the data/mcastq before they're dropped. 823232764Sadrian * 824232764Sadrian * This is to prevent: 825232764Sadrian * + a single destination overwhelming everything, including 826232764Sadrian * management/multicast frames; 827232764Sadrian * + multicast frames overwhelming everything (when the 828232764Sadrian * air is sufficiently busy that cabq can't drain.) 829250665Sadrian * + A node in powersave shouldn't be allowed to exhaust 830250665Sadrian * all available mbufs; 831232764Sadrian * 832232764Sadrian * These implement: 833232764Sadrian * + data_minfree is the maximum number of free buffers 834232764Sadrian * overall to successfully allow a data frame. 835232764Sadrian * 836232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 837232764Sadrian */ 838250326Sadrian int sc_txq_node_maxdepth; 839232764Sadrian int sc_txq_data_minfree; 840232764Sadrian int sc_txq_mcastq_maxdepth; 841250665Sadrian int sc_txq_node_psq_maxdepth; 842232764Sadrian 843232764Sadrian /* 844250866Sadrian * Software queue twiddles 845227328Sadrian * 846250866Sadrian * hwq_limit_nonaggr: 847250866Sadrian * when to begin limiting non-aggregate frames to the 848250866Sadrian * hardware queue, regardless of the TID. 849250866Sadrian * hwq_limit_aggr: 850250866Sadrian * when to begin limiting A-MPDU frames to the 851250866Sadrian * hardware queue, regardless of the TID. 852227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 853227328Sadrian * TID will be scheduled again 854227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 855227328Sadrian * stops being scheduled. 856227328Sadrian */ 857250866Sadrian int sc_hwq_limit_nonaggr; 858250866Sadrian int sc_hwq_limit_aggr; 859227328Sadrian int sc_tid_hwq_lo; 860227328Sadrian int sc_tid_hwq_hi; 861227328Sadrian 862222585Sadrian /* DFS related state */ 863222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 864222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 865222585Sadrian struct task sc_dfstask; /* DFS processing task */ 866227328Sadrian 867244951Sadrian /* Spectral related state */ 868244951Sadrian void *sc_spectral; 869244951Sadrian int sc_dospectral; 870244951Sadrian 871251655Sadrian /* LNA diversity related state */ 872251655Sadrian void *sc_lna_div; 873251655Sadrian int sc_dolnadiv; 874251655Sadrian 875242782Sadrian /* ALQ */ 876242853Skevlo#ifdef ATH_DEBUG_ALQ 877242782Sadrian struct if_ath_alq sc_alq; 878242782Sadrian#endif 879242782Sadrian 880227328Sadrian /* TX AMPDU handling */ 881227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 882227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 883227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 884227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 885227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 886227328Sadrian struct ieee80211_tx_ampdu *); 887227328Sadrian void (*sc_addba_response_timeout) 888227328Sadrian (struct ieee80211_node *, 889227328Sadrian struct ieee80211_tx_ampdu *); 890227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 891227328Sadrian struct ieee80211_tx_ampdu *tap, 892227328Sadrian int status); 893265115Sadrian 894265115Sadrian /* 895265205Sadrian * Powersave state tracking. 896265205Sadrian * 897265205Sadrian * target/cur powerstate is the chip power state. 898265205Sadrian * target selfgen state is the self-generated frames 899265205Sadrian * state. The chip can be awake but transmitted frames 900265205Sadrian * can have the PWRMGT bit set to 1 so the destination 901265205Sadrian * thinks the node is asleep. 902265115Sadrian */ 903265115Sadrian HAL_POWER_MODE sc_target_powerstate; 904265205Sadrian HAL_POWER_MODE sc_target_selfgen_state; 905265205Sadrian 906265115Sadrian HAL_POWER_MODE sc_cur_powerstate; 907265205Sadrian 908265115Sadrian int sc_powersave_refcnt; 909272292Sadrian 910272292Sadrian /* ATH_PCI_* flags */ 911272292Sadrian uint32_t sc_pci_devinfo; 912301181Sadrian 913301181Sadrian /* BT coex */ 914301181Sadrian struct { 915301181Sadrian struct ath_descdma buf; 916301181Sadrian 917301181Sadrian /* gpm/sched buffer, saved pointers */ 918301181Sadrian char *sched_buf; 919301181Sadrian bus_addr_t sched_paddr; 920301181Sadrian char *gpm_buf; 921301181Sadrian bus_addr_t gpm_paddr; 922301181Sadrian 923301181Sadrian uint32_t wlan_channels[4]; 924301181Sadrian } sc_btcoex; 925116743Ssam}; 926116743Ssam 927121100Ssam#define ATH_LOCK_INIT(_sc) \ 928121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 929167252Ssam NULL, MTX_DEF | MTX_RECURSE) 930121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 931121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 932121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 933121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 934227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 935121100Ssam 936227328Sadrian/* 937246453Sadrian * The TX lock is non-reentrant and serialises the TX frame send 938246453Sadrian * and completion operations. 939242391Sadrian */ 940242391Sadrian#define ATH_TX_LOCK_INIT(_sc) do {\ 941242391Sadrian snprintf((_sc)->sc_tx_mtx_name, \ 942242391Sadrian sizeof((_sc)->sc_tx_mtx_name), \ 943242391Sadrian "%s TX lock", \ 944242391Sadrian device_get_nameunit((_sc)->sc_dev)); \ 945242391Sadrian mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 946242391Sadrian NULL, MTX_DEF); \ 947242391Sadrian } while (0) 948242391Sadrian#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 949242391Sadrian#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 950242391Sadrian#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 951242391Sadrian#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 952242391Sadrian MA_OWNED) 953242391Sadrian#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 954242391Sadrian MA_NOTOWNED) 955246745Sadrian#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 956246745Sadrian mtx_trylock(&(_sc)->sc_tx_mtx)) 957242391Sadrian 958242391Sadrian/* 959227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 960227328Sadrian * Although currently the interrupt code is run in netisr context and 961227328Sadrian * doesn't require this, this may change in the future. 962227328Sadrian * Please keep this in mind when protecting certain code paths 963227328Sadrian * with the PCU lock. 964227328Sadrian * 965227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 966227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 967227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 968227328Sadrian * 969227328Sadrian * Although the current single-thread taskqueue mechanism protects the 970227328Sadrian * majority of these situations by simply serialising them, there are 971227328Sadrian * a few others which occur at the same time. These include the TX path 972227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 973227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 974227328Sadrian */ 975227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 976227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 977227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 978227328Sadrian "%s PCU lock", \ 979227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 980227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 981227328Sadrian NULL, MTX_DEF); \ 982227328Sadrian } while (0) 983227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 984227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 985227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 986227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 987227328Sadrian MA_OWNED) 988227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 989227651Sadrian MA_NOTOWNED) 990227328Sadrian 991238433Sadrian/* 992238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 993238433Sadrian * RX FIFO/list isn't modified by various execution paths. 994238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 995238433Sadrian * RX path can be executed via various reset/channel change paths. 996238433Sadrian */ 997238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 998238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 999238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 1000238433Sadrian "%s RX lock", \ 1001238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 1002238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 1003238433Sadrian NULL, MTX_DEF); \ 1004238433Sadrian } while (0) 1005238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 1006238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 1007238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 1008238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1009238433Sadrian MA_OWNED) 1010238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1011238433Sadrian MA_NOTOWNED) 1012238433Sadrian 1013138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 1014138570Ssam 1015155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 1016155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 1017155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 1018167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 1019155482Ssam} while (0) 1020121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 1021121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 1022121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 1023121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 1024121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 1025250391Sadrian#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 1026250391Sadrian mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 1027121100Ssam 1028238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 1029238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 1030238709Sadrian "%s_buf", \ 1031238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 1032238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 1033238709Sadrian MTX_DEF); \ 1034238709Sadrian} while (0) 1035238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 1036238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 1037238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 1038238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 1039238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 1040238709Sadrian 1041116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 1042116743Ssamint ath_detach(struct ath_softc *); 1043116743Ssamvoid ath_resume(struct ath_softc *); 1044116743Ssamvoid ath_suspend(struct ath_softc *); 1045116743Ssamvoid ath_shutdown(struct ath_softc *); 1046116743Ssamvoid ath_intr(void *); 1047116743Ssam 1048116743Ssam/* 1049116743Ssam * HAL definitions to comply with local coding convention. 1050116743Ssam */ 1051138570Ssam#define ath_hal_detach(_ah) \ 1052138570Ssam ((*(_ah)->ah_detach)((_ah))) 1053290612Sadrian#define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \ 1054290612Sadrian ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \ 1055290612Sadrian (_resettype), (_pstatus))) 1056186904Ssam#define ath_hal_macversion(_ah) \ 1057186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1058116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 1059116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1060116743Ssam#define ath_hal_getmac(_ah, _mac) \ 1061116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1062138570Ssam#define ath_hal_setmac(_ah, _mac) \ 1063138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1064178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 1065178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1066178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 1067178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1068116743Ssam#define ath_hal_intrset(_ah, _mask) \ 1069116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1070116743Ssam#define ath_hal_intrget(_ah) \ 1071116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 1072116743Ssam#define ath_hal_intrpend(_ah) \ 1073116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 1074116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 1075116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1076116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 1077116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1078155515Ssam#define ath_hal_setpower(_ah, _mode) \ 1079155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1080265115Sadrian#define ath_hal_setselfgenpower(_ah, _mode) \ 1081265115Sadrian ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) 1082138570Ssam#define ath_hal_keycachesize(_ah) \ 1083138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1084116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 1085116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1086138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1087138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1088116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 1089116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1090116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 1091116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1092116743Ssam#define ath_hal_getrxfilter(_ah) \ 1093116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 1094116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 1095116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1096116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1097116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1098116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 1099116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1100238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1101238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1102186904Ssam/* NB: common across all chips */ 1103186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1104116743Ssam#define ath_hal_gettsf32(_ah) \ 1105186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 1106116743Ssam#define ath_hal_gettsf64(_ah) \ 1107116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 1108243425Sadrian#define ath_hal_settsf64(_ah, _val) \ 1109243425Sadrian ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1110116743Ssam#define ath_hal_resettsf(_ah) \ 1111116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 1112116743Ssam#define ath_hal_rxena(_ah) \ 1113116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 1114116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1115116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1116116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 1117116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1118138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 1119138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1120238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 1121238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1122116743Ssam#define ath_hal_txstart(_ah, _q) \ 1123116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1124116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 1125116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1126155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1127155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1128185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1129185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1130185744Ssam#define ath_hal_calreset(_ah, _chan) \ 1131185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1132116743Ssam#define ath_hal_setledstate(_ah, _state) \ 1133116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 1134138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1135138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1136116743Ssam#define ath_hal_beaconreset(_ah) \ 1137116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1138186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 1139186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1140138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 1141138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1142225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 1143225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 1144116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 1145138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1146138570Ssam#define ath_hal_phydisable(_ah) \ 1147138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 1148138570Ssam#define ath_hal_setopmode(_ah) \ 1149138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 1150116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 1151116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1152116743Ssam#define ath_hal_stoppcurecv(_ah) \ 1153116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 1154116743Ssam#define ath_hal_startpcurecv(_ah) \ 1155116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 1156116743Ssam#define ath_hal_stopdmarecv(_ah) \ 1157116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 1158138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1159138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1160138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 1161155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1162170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1163116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1164116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1165116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 1166116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1167116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 1168116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1169138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1170138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1171138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1172138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1173186904Ssam/* NB: common across all chips */ 1174186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1175186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 1176186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1177116743Ssam#define ath_hal_getrfgain(_ah) \ 1178116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 1179138570Ssam#define ath_hal_getdefantenna(_ah) \ 1180138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 1181138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 1182138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1183155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1184155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1185217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 1186217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1187138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 1188138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1189138570Ssam#define ath_hal_setslottime(_ah, _us) \ 1190138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1191138570Ssam#define ath_hal_getslottime(_ah) \ 1192138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 1193138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 1194138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1195138570Ssam#define ath_hal_getacktimeout(_ah) \ 1196138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 1197138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 1198138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1199138570Ssam#define ath_hal_getctstimeout(_ah) \ 1200138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 1201138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1202138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1203138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1204138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1205138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 1206138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1207138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 1208155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1209155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 1210184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1211138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 1212138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 1213178354Ssam#define ath_hal_gettkipmic(_ah) \ 1214178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1215178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 1216178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1217162410Ssam#define ath_hal_hastkipsplit(_ah) \ 1218138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1219162410Ssam#define ath_hal_gettkipsplit(_ah) \ 1220162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1221162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 1222162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1223178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 1224178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1225138570Ssam#define ath_hal_hwphycounters(_ah) \ 1226138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1227138570Ssam#define ath_hal_hasdiversity(_ah) \ 1228138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1229138570Ssam#define ath_hal_getdiversity(_ah) \ 1230138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1231138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 1232138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1233166954Ssam#define ath_hal_getantennaswitch(_ah) \ 1234166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1235166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 1236166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1237138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 1238138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1239138570Ssam#define ath_hal_setdiag(_ah, _v) \ 1240138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1241138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 1242138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1243138570Ssam#define ath_hal_hasveol(_ah) \ 1244138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1245138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 1246138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1247138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 1248138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1249138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1250138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1251138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1252138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1253138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 1254138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1255138570Ssam#define ath_hal_settpscale(_ah, _v) \ 1256138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1257138570Ssam#define ath_hal_hastpc(_ah) \ 1258138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1259138570Ssam#define ath_hal_gettpc(_ah) \ 1260138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1261138570Ssam#define ath_hal_settpc(_ah, _v) \ 1262138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1263138570Ssam#define ath_hal_hasbursting(_ah) \ 1264138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1265203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1266203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1267147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1268147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1269147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1270147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1271170530Ssam#define ath_hal_hasfastframes(_ah) \ 1272170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1273178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1274178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1275195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1276195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1277178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1278178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1279178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1280178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1281178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1282178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1283155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1284155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1285155515Ssam#define ath_hal_getrfkill(_ah) \ 1286155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1287155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1288155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1289155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1290155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1291155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1292155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1293155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1294155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1295155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1296155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1297155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1298155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1299155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1300155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1301184354Ssam#define ath_hal_hasintmit(_ah) \ 1302230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1303230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1304184354Ssam#define ath_hal_getintmit(_ah) \ 1305230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1306230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1307184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1308230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1309230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1310265115Sadrian#define ath_hal_hasmybeacon(_ah) \ 1311265115Sadrian (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) 1312238280Sadrian 1313250865Sadrian#define ath_hal_hasenforcetxop(_ah) \ 1314250865Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1315250865Sadrian#define ath_hal_getenforcetxop(_ah) \ 1316250865Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1317250865Sadrian#define ath_hal_setenforcetxop(_ah, _v) \ 1318250865Sadrian ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1319250865Sadrian 1320251401Sadrian#define ath_hal_hasrxlnamixer(_ah) \ 1321251401Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1322250865Sadrian 1323251655Sadrian#define ath_hal_hasdivantcomb(_ah) \ 1324251655Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1325298608Sadrian#define ath_hal_hasldpc(_ah) \ 1326298608Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK) 1327298608Sadrian#define ath_hal_hasldpcwar(_ah) \ 1328298608Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK) 1329251655Sadrian 1330238280Sadrian/* EDMA definitions */ 1331237953Sadrian#define ath_hal_hasedma(_ah) \ 1332237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1333237953Sadrian 0, NULL) == HAL_OK) 1334238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1335238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1336238280Sadrian == HAL_OK) 1337238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1338238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1339238280Sadrian == HAL_OK) 1340238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1341238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1342238280Sadrian == HAL_OK) 1343238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1344238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1345238280Sadrian == HAL_OK) 1346238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1347238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1348238280Sadrian == HAL_OK) 1349238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1350238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1351238280Sadrian == HAL_OK) 1352238280Sadrian 1353154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1354154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1355238280Sadrian 1356238280Sadrian/* 802.11n HAL methods */ 1357218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1358218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1359218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1360218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1361231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1362231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1363231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1364231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1365218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1366230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1367230493Sadrian 0, NULL) == HAL_OK) 1368220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1369230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1370230493Sadrian 0, NULL) == HAL_OK) 1371220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1372220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1373225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1374230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1375230493Sadrian 0, NULL) == HAL_OK) 1376116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1377116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1378165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1379165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1380116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1381116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1382116743Ssam _rtsrate, _rtsdura) \ 1383116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1384116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1385155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1386138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1387116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1388138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1389116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1390239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1391239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1392239051Sadrian (_first), (_last), (_ds0))) 1393165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1394165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1395155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1396155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1397217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1398217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1399238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1400238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1401238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1402238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1403238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1404238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1405238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1406238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1407238731Sadrian (_size))) 1408242510Sadrian#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1409242510Sadrian ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1410116743Ssam 1411218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1412218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1413218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1414218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1415239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1416239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1417239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1418239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1419233895Sadrian (_first), (_last), (_lastaggr))) 1420218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1421218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1422227328Sadrian 1423218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1424218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1425218067Sadrian (_series), (_ns), (_flags))) 1426227328Sadrian 1427227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1428242510Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1429242510Sadrian#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1430227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1431227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1432227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1433227328Sadrian 1434218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1435218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1436227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1437227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1438247774Sadrian#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1439247774Sadrian ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1440218066Sadrian 1441230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1442230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1443230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1444230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1445230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1446230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1447230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1448230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1449230493Sadrian 1450222585Sadrian/* 1451235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1452235957Sadrian */ 1453235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1454235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1455235957Sadrian#define ath_hal_disablepcie(_ah) \ 1456235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1457235957Sadrian 1458235957Sadrian/* 1459222585Sadrian * This is badly-named; you need to set the correct parameters 1460222585Sadrian * to begin to receive useful radar events; and even then 1461222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1462222585Sadrian * more information. 1463222585Sadrian */ 1464222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1465222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1466222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1467222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1468239656Sadrian#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1469239656Sadrian ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1470222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1471230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1472230493Sadrian (_buf), (_event))) 1473224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1474224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1475230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1476155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1477234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1478234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1479230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1480230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1481247286Sadrian#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1482247286Sadrian ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1483155515Ssam 1484245002Sadrian#define ath_hal_spectral_supported(_ah) \ 1485245002Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1486244947Sadrian#define ath_hal_spectral_get_config(_ah, _p) \ 1487244947Sadrian ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1488244947Sadrian#define ath_hal_spectral_configure(_ah, _p) \ 1489244947Sadrian ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1490244947Sadrian#define ath_hal_spectral_start(_ah) \ 1491244947Sadrian ((*(_ah)->ah_spectralStart)((_ah))) 1492244947Sadrian#define ath_hal_spectral_stop(_ah) \ 1493244947Sadrian ((*(_ah)->ah_spectralStop)((_ah))) 1494244947Sadrian 1495251484Sadrian#define ath_hal_btcoex_supported(_ah) \ 1496251484Sadrian (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1497251484Sadrian#define ath_hal_btcoex_set_info(_ah, _info) \ 1498251484Sadrian ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1499251484Sadrian#define ath_hal_btcoex_set_config(_ah, _cfg) \ 1500251484Sadrian ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1501251484Sadrian#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1502251484Sadrian ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1503251484Sadrian#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1504251484Sadrian ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1505251484Sadrian#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1506251484Sadrian ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1507251484Sadrian#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1508251484Sadrian ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1509251484Sadrian#define ath_hal_btcoex_enable(_ah) \ 1510251484Sadrian ((*(_ah)->ah_btCoexEnable)((_ah))) 1511251484Sadrian#define ath_hal_btcoex_disable(_ah) \ 1512251484Sadrian ((*(_ah)->ah_btCoexDisable)((_ah))) 1513251484Sadrian 1514301181Sadrian#define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \ 1515301181Sadrian ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp))) 1516301181Sadrian#define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \ 1517301181Sadrian ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt))) 1518301181Sadrian#define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \ 1519301181Sadrian ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm))) 1520301181Sadrian#define ath_hal_btcoex_mci_state(_ah, _st, _pd) \ 1521301181Sadrian ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd))) 1522301181Sadrian#define ath_hal_btcoex_mci_detach(_ah) \ 1523301181Sadrian ((*(_ah)->ah_btMciDetach)((_ah))) 1524301181Sadrian 1525251655Sadrian#define ath_hal_div_comb_conf_get(_ah, _conf) \ 1526251655Sadrian ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1527251655Sadrian#define ath_hal_div_comb_conf_set(_ah, _conf) \ 1528251655Sadrian ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1529251655Sadrian 1530116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1531