1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_var.h> 77#include <net/if_dl.h> 78#include <net/if_media.h> 79#include <net/if_types.h> 80#include <net/if_arp.h> 81#include <net/ethernet.h> 82#include <net/if_llc.h> 83 84#include <net80211/ieee80211_var.h> 85#include <net80211/ieee80211_regdomain.h> 86#ifdef IEEE80211_SUPPORT_SUPERG 87#include <net80211/ieee80211_superg.h> 88#endif 89 90#include <net/bpf.h> 91 92#ifdef INET 93#include <netinet/in.h> 94#include <netinet/if_ether.h> 95#endif 96 97#include <dev/ath/if_athvar.h> 98 99#include <dev/ath/if_ath_debug.h> 100#include <dev/ath/if_ath_misc.h> 101#include <dev/ath/if_ath_tx.h> 102#include <dev/ath/if_ath_beacon.h> 103 104#ifdef ATH_TX99_DIAG 105#include <dev/ath/ath_tx99/ath_tx99.h> 106#endif 107 108/* 109 * Setup a h/w transmit queue for beacons. 110 */ 111int 112ath_beaconq_setup(struct ath_softc *sc) 113{ 114 struct ath_hal *ah = sc->sc_ah; 115 HAL_TXQ_INFO qi; 116 117 memset(&qi, 0, sizeof(qi)); 118 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 119 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 120 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 121 /* NB: for dynamic turbo, don't enable any other interrupts */ 122 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 123 if (sc->sc_isedma) 124 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 125 HAL_TXQ_TXERRINT_ENABLE; 126 127 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 128} 129 130/* 131 * Setup the transmit queue parameters for the beacon queue. 132 */ 133int 134ath_beaconq_config(struct ath_softc *sc) 135{ 136#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 137 struct ieee80211com *ic = &sc->sc_ic; 138 struct ath_hal *ah = sc->sc_ah; 139 HAL_TXQ_INFO qi; 140 141 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 142 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 143 ic->ic_opmode == IEEE80211_M_MBSS) { 144 /* 145 * Always burst out beacon and CAB traffic. 146 */ 147 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 148 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 149 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 150 } else { 151 struct wmeParams *wmep = 152 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 153 /* 154 * Adhoc mode; important thing is to use 2x cwmin. 155 */ 156 qi.tqi_aifs = wmep->wmep_aifsn; 157 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 158 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 159 } 160 161 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 162 device_printf(sc->sc_dev, "unable to update parameters for " 163 "beacon hardware queue!\n"); 164 return 0; 165 } else { 166 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 167 return 1; 168 } 169#undef ATH_EXPONENT_TO_VALUE 170} 171 172/* 173 * Allocate and setup an initial beacon frame. 174 */ 175int 176ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 177{ 178 struct ieee80211vap *vap = ni->ni_vap; 179 struct ath_vap *avp = ATH_VAP(vap); 180 struct ath_buf *bf; 181 struct mbuf *m; 182 int error; 183 184 bf = avp->av_bcbuf; 185 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 186 __func__, bf->bf_m, bf->bf_node); 187 if (bf->bf_m != NULL) { 188 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 189 m_freem(bf->bf_m); 190 bf->bf_m = NULL; 191 } 192 if (bf->bf_node != NULL) { 193 ieee80211_free_node(bf->bf_node); 194 bf->bf_node = NULL; 195 } 196 197 /* 198 * NB: the beacon data buffer must be 32-bit aligned; 199 * we assume the mbuf routines will return us something 200 * with this alignment (perhaps should assert). 201 */ 202 m = ieee80211_beacon_alloc(ni); 203 if (m == NULL) { 204 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 205 sc->sc_stats.ast_be_nombuf++; 206 return ENOMEM; 207 } 208 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 209 bf->bf_segs, &bf->bf_nseg, 210 BUS_DMA_NOWAIT); 211 if (error != 0) { 212 device_printf(sc->sc_dev, 213 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 214 __func__, error); 215 m_freem(m); 216 return error; 217 } 218 219 /* 220 * Calculate a TSF adjustment factor required for staggered 221 * beacons. Note that we assume the format of the beacon 222 * frame leaves the tstamp field immediately following the 223 * header. 224 */ 225 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 226 uint64_t tsfadjust; 227 struct ieee80211_frame *wh; 228 229 /* 230 * The beacon interval is in TU's; the TSF is in usecs. 231 * We figure out how many TU's to add to align the timestamp 232 * then convert to TSF units and handle byte swapping before 233 * inserting it in the frame. The hardware will then add this 234 * each time a beacon frame is sent. Note that we align vap's 235 * 1..N and leave vap 0 untouched. This means vap 0 has a 236 * timestamp in one beacon interval while the others get a 237 * timstamp aligned to the next interval. 238 */ 239 tsfadjust = ni->ni_intval * 240 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 241 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 242 243 DPRINTF(sc, ATH_DEBUG_BEACON, 244 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 245 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 246 avp->av_bslot, ni->ni_intval, 247 (long long unsigned) le64toh(tsfadjust)); 248 249 wh = mtod(m, struct ieee80211_frame *); 250 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 251 } 252 bf->bf_m = m; 253 bf->bf_node = ieee80211_ref_node(ni); 254 255 return 0; 256} 257 258/* 259 * Setup the beacon frame for transmit. 260 */ 261static void 262ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 263{ 264#define USE_SHPREAMBLE(_ic) \ 265 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 266 == IEEE80211_F_SHPREAMBLE) 267 struct ieee80211_node *ni = bf->bf_node; 268 struct ieee80211com *ic = ni->ni_ic; 269 struct mbuf *m = bf->bf_m; 270 struct ath_hal *ah = sc->sc_ah; 271 struct ath_desc *ds; 272 int flags, antenna; 273 const HAL_RATE_TABLE *rt; 274 u_int8_t rix, rate; 275 HAL_DMA_ADDR bufAddrList[4]; 276 uint32_t segLenList[4]; 277 HAL_11N_RATE_SERIES rc[4]; 278 279 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 280 __func__, m, m->m_len); 281 282 /* setup descriptors */ 283 ds = bf->bf_desc; 284 bf->bf_last = bf; 285 bf->bf_lastds = ds; 286 287 flags = HAL_TXDESC_NOACK; 288 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 289 /* self-linked descriptor */ 290 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 291 flags |= HAL_TXDESC_VEOL; 292 /* 293 * Let hardware handle antenna switching. 294 */ 295 antenna = sc->sc_txantenna; 296 } else { 297 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 298 /* 299 * Switch antenna every 4 beacons. 300 * XXX assumes two antenna 301 */ 302 if (sc->sc_txantenna != 0) 303 antenna = sc->sc_txantenna; 304 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 305 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 306 else 307 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 308 } 309 310 KASSERT(bf->bf_nseg == 1, 311 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 312 313 /* 314 * Calculate rate code. 315 * XXX everything at min xmit rate 316 */ 317 rix = 0; 318 rt = sc->sc_currates; 319 rate = rt->info[rix].rateCode; 320 if (USE_SHPREAMBLE(ic)) 321 rate |= rt->info[rix].shortPreamble; 322 ath_hal_setuptxdesc(ah, ds 323 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 324 , sizeof(struct ieee80211_frame)/* header length */ 325 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 326 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 327 , rate, 1 /* series 0 rate/tries */ 328 , HAL_TXKEYIX_INVALID /* no encryption */ 329 , antenna /* antenna mode */ 330 , flags /* no ack, veol for beacons */ 331 , 0 /* rts/cts rate */ 332 , 0 /* rts/cts duration */ 333 ); 334 335 /* 336 * The EDMA HAL currently assumes that _all_ rate control 337 * settings are done in ath_hal_set11nratescenario(), rather 338 * than in ath_hal_setuptxdesc(). 339 */ 340 if (sc->sc_isedma) { 341 memset(&rc, 0, sizeof(rc)); 342 343 rc[0].ChSel = sc->sc_txchainmask; 344 rc[0].Tries = 1; 345 rc[0].Rate = rt->info[rix].rateCode; 346 rc[0].RateIndex = rix; 347 rc[0].tx_power_cap = 0x3f; 348 rc[0].PktDuration = 349 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 350 rix, 0); 351 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 352 } 353 354 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 355 segLenList[0] = roundup(m->m_len, 4); 356 segLenList[1] = segLenList[2] = segLenList[3] = 0; 357 bufAddrList[0] = bf->bf_segs[0].ds_addr; 358 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 359 ath_hal_filltxdesc(ah, ds 360 , bufAddrList 361 , segLenList 362 , 0 /* XXX desc id */ 363 , sc->sc_bhalq /* hardware TXQ */ 364 , AH_TRUE /* first segment */ 365 , AH_TRUE /* last segment */ 366 , ds /* first descriptor */ 367 ); 368#if 0 369 ath_desc_swap(ds); 370#endif 371#undef USE_SHPREAMBLE 372} 373 374void 375ath_beacon_update(struct ieee80211vap *vap, int item) 376{ 377 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 378 379 setbit(bo->bo_flags, item); 380} 381 382/* 383 * Handle a beacon miss. 384 */ 385void 386ath_beacon_miss(struct ath_softc *sc) 387{ 388 HAL_SURVEY_SAMPLE hs; 389 HAL_BOOL ret; 390 uint32_t hangs; 391 392 bzero(&hs, sizeof(hs)); 393 394 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 395 396 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 397 DPRINTF(sc, ATH_DEBUG_BEACON, 398 "%s: hang=0x%08x\n", 399 __func__, 400 hangs); 401 } 402 403#ifdef ATH_DEBUG_ALQ 404 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 405 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 406#endif 407 408 DPRINTF(sc, ATH_DEBUG_BEACON, 409 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 410 "extchanbusy=%u, cyclecount=%u\n", 411 __func__, 412 ret, 413 hs.tx_busy, 414 hs.rx_busy, 415 hs.chan_busy, 416 hs.ext_chan_busy, 417 hs.cycle_count); 418} 419 420/* 421 * Transmit a beacon frame at SWBA. Dynamic updates to the 422 * frame contents are done as needed and the slot time is 423 * also adjusted based on current state. 424 */ 425void 426ath_beacon_proc(void *arg, int pending) 427{ 428 struct ath_softc *sc = arg; 429 struct ath_hal *ah = sc->sc_ah; 430 struct ieee80211vap *vap; 431 struct ath_buf *bf; 432 int slot, otherant; 433 uint32_t bfaddr; 434 435 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 436 __func__, pending); 437 /* 438 * Check if the previous beacon has gone out. If 439 * not don't try to post another, skip this period 440 * and wait for the next. Missed beacons indicate 441 * a problem and should not occur. If we miss too 442 * many consecutive beacons reset the device. 443 */ 444 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 445 sc->sc_bmisscount++; 446 sc->sc_stats.ast_be_missed++; 447 ath_beacon_miss(sc); 448 DPRINTF(sc, ATH_DEBUG_BEACON, 449 "%s: missed %u consecutive beacons\n", 450 __func__, sc->sc_bmisscount); 451 if (sc->sc_bmisscount >= ath_bstuck_threshold) 452 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 453 return; 454 } 455 if (sc->sc_bmisscount != 0) { 456 DPRINTF(sc, ATH_DEBUG_BEACON, 457 "%s: resume beacon xmit after %u misses\n", 458 __func__, sc->sc_bmisscount); 459 sc->sc_bmisscount = 0; 460#ifdef ATH_DEBUG_ALQ 461 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 462 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 463#endif 464 } 465 466 if (sc->sc_stagbeacons) { /* staggered beacons */ 467 struct ieee80211com *ic = &sc->sc_ic; 468 uint32_t tsftu; 469 470 tsftu = ath_hal_gettsf32(ah) >> 10; 471 /* XXX lintval */ 472 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 473 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 474 bfaddr = 0; 475 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 476 bf = ath_beacon_generate(sc, vap); 477 if (bf != NULL) 478 bfaddr = bf->bf_daddr; 479 } 480 } else { /* burst'd beacons */ 481 uint32_t *bflink = &bfaddr; 482 483 for (slot = 0; slot < ATH_BCBUF; slot++) { 484 vap = sc->sc_bslot[slot]; 485 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 486 bf = ath_beacon_generate(sc, vap); 487 /* 488 * XXX TODO: this should use settxdesclinkptr() 489 * otherwise it won't work for EDMA chipsets! 490 */ 491 if (bf != NULL) { 492 /* XXX should do this using the ds */ 493 *bflink = bf->bf_daddr; 494 ath_hal_gettxdesclinkptr(sc->sc_ah, 495 bf->bf_desc, &bflink); 496 } 497 } 498 } 499 /* 500 * XXX TODO: this should use settxdesclinkptr() 501 * otherwise it won't work for EDMA chipsets! 502 */ 503 *bflink = 0; /* terminate list */ 504 } 505 506 /* 507 * Handle slot time change when a non-ERP station joins/leaves 508 * an 11g network. The 802.11 layer notifies us via callback, 509 * we mark updateslot, then wait one beacon before effecting 510 * the change. This gives associated stations at least one 511 * beacon interval to note the state change. 512 */ 513 /* XXX locking */ 514 if (sc->sc_updateslot == UPDATE) { 515 sc->sc_updateslot = COMMIT; /* commit next beacon */ 516 sc->sc_slotupdate = slot; 517 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 518 ath_setslottime(sc); /* commit change to h/w */ 519 520 /* 521 * Check recent per-antenna transmit statistics and flip 522 * the default antenna if noticeably more frames went out 523 * on the non-default antenna. 524 * XXX assumes 2 anntenae 525 */ 526 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 527 otherant = sc->sc_defant & 1 ? 2 : 1; 528 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 529 ath_setdefantenna(sc, otherant); 530 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 531 } 532 533 /* Program the CABQ with the contents of the CABQ txq and start it */ 534 ATH_TXQ_LOCK(sc->sc_cabq); 535 ath_beacon_cabq_start(sc); 536 ATH_TXQ_UNLOCK(sc->sc_cabq); 537 538 /* Program the new beacon frame if we have one for this interval */ 539 if (bfaddr != 0) { 540 /* 541 * Stop any current dma and put the new frame on the queue. 542 * This should never fail since we check above that no frames 543 * are still pending on the queue. 544 */ 545 if (! sc->sc_isedma) { 546 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 547 DPRINTF(sc, ATH_DEBUG_ANY, 548 "%s: beacon queue %u did not stop?\n", 549 __func__, sc->sc_bhalq); 550 } 551 } 552 /* NB: cabq traffic should already be queued and primed */ 553 554 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 555 ath_hal_txstart(ah, sc->sc_bhalq); 556 557 sc->sc_stats.ast_be_xmit++; 558 } 559} 560 561static void 562ath_beacon_cabq_start_edma(struct ath_softc *sc) 563{ 564 struct ath_buf *bf, *bf_last; 565 struct ath_txq *cabq = sc->sc_cabq; 566#if 0 567 struct ath_buf *bfi; 568 int i = 0; 569#endif 570 571 ATH_TXQ_LOCK_ASSERT(cabq); 572 573 if (TAILQ_EMPTY(&cabq->axq_q)) 574 return; 575 bf = TAILQ_FIRST(&cabq->axq_q); 576 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 577 578 /* 579 * This is a dirty, dirty hack to push the contents of 580 * the cabq staging queue into the FIFO. 581 * 582 * This ideally should live in the EDMA code file 583 * and only push things into the CABQ if there's a FIFO 584 * slot. 585 * 586 * We can't treat this like a normal TX queue because 587 * in the case of multi-VAP traffic, we may have to flush 588 * the CABQ each new (staggered) beacon that goes out. 589 * But for non-staggered beacons, we could in theory 590 * handle multicast traffic for all VAPs in one FIFO 591 * push. Just keep all of this in mind if you're wondering 592 * how to correctly/better handle multi-VAP CABQ traffic 593 * with EDMA. 594 */ 595 596 /* 597 * Is the CABQ FIFO free? If not, complain loudly and 598 * don't queue anything. Maybe we'll flush the CABQ 599 * traffic, maybe we won't. But that'll happen next 600 * beacon interval. 601 */ 602 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 603 device_printf(sc->sc_dev, 604 "%s: Q%d: CAB FIFO queue=%d?\n", 605 __func__, 606 cabq->axq_qnum, 607 cabq->axq_fifo_depth); 608 return; 609 } 610 611 /* 612 * Ok, so here's the gymnastics reqiured to make this 613 * all sensible. 614 */ 615 616 /* 617 * Tag the first/last buffer appropriately. 618 */ 619 bf->bf_flags |= ATH_BUF_FIFOPTR; 620 bf_last->bf_flags |= ATH_BUF_FIFOEND; 621 622#if 0 623 i = 0; 624 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 625 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 626 i++; 627 } 628#endif 629 630 /* 631 * We now need to push this set of frames onto the tail 632 * of the FIFO queue. We don't adjust the aggregate 633 * count, only the queue depth counter(s). 634 * We also need to blank the link pointer now. 635 */ 636 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 637 cabq->axq_link = NULL; 638 cabq->fifo.axq_depth += cabq->axq_depth; 639 cabq->axq_depth = 0; 640 641 /* Bump FIFO queue */ 642 cabq->axq_fifo_depth++; 643 644 /* Push the first entry into the hardware */ 645 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 646 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 647 648 /* NB: gated by beacon so safe to start here */ 649 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 650 651} 652 653static void 654ath_beacon_cabq_start_legacy(struct ath_softc *sc) 655{ 656 struct ath_buf *bf; 657 struct ath_txq *cabq = sc->sc_cabq; 658 659 ATH_TXQ_LOCK_ASSERT(cabq); 660 if (TAILQ_EMPTY(&cabq->axq_q)) 661 return; 662 bf = TAILQ_FIRST(&cabq->axq_q); 663 664 /* Push the first entry into the hardware */ 665 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 666 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 667 668 /* NB: gated by beacon so safe to start here */ 669 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 670} 671 672/* 673 * Start CABQ transmission - this assumes that all frames are prepped 674 * and ready in the CABQ. 675 */ 676void 677ath_beacon_cabq_start(struct ath_softc *sc) 678{ 679 struct ath_txq *cabq = sc->sc_cabq; 680 681 ATH_TXQ_LOCK_ASSERT(cabq); 682 683 if (TAILQ_EMPTY(&cabq->axq_q)) 684 return; 685 686 if (sc->sc_isedma) 687 ath_beacon_cabq_start_edma(sc); 688 else 689 ath_beacon_cabq_start_legacy(sc); 690} 691 692struct ath_buf * 693ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 694{ 695 struct ath_vap *avp = ATH_VAP(vap); 696 struct ath_txq *cabq = sc->sc_cabq; 697 struct ath_buf *bf; 698 struct mbuf *m; 699 int nmcastq, error; 700 701 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 702 ("not running, state %d", vap->iv_state)); 703 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 704 705 /* 706 * Update dynamic beacon contents. If this returns 707 * non-zero then we need to remap the memory because 708 * the beacon frame changed size (probably because 709 * of the TIM bitmap). 710 */ 711 bf = avp->av_bcbuf; 712 m = bf->bf_m; 713 /* XXX lock mcastq? */ 714 nmcastq = avp->av_mcastq.axq_depth; 715 716 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) { 717 /* XXX too conservative? */ 718 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 719 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 720 bf->bf_segs, &bf->bf_nseg, 721 BUS_DMA_NOWAIT); 722 if (error != 0) { 723 if_printf(vap->iv_ifp, 724 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 725 __func__, error); 726 return NULL; 727 } 728 } 729 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) { 730 DPRINTF(sc, ATH_DEBUG_BEACON, 731 "%s: cabq did not drain, mcastq %u cabq %u\n", 732 __func__, nmcastq, cabq->axq_depth); 733 sc->sc_stats.ast_cabq_busy++; 734 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 735 /* 736 * CABQ traffic from a previous vap is still pending. 737 * We must drain the q before this beacon frame goes 738 * out as otherwise this vap's stations will get cab 739 * frames from a different vap. 740 * XXX could be slow causing us to miss DBA 741 */ 742 /* 743 * XXX TODO: this doesn't stop CABQ DMA - it assumes 744 * that since we're about to transmit a beacon, we've 745 * already stopped transmitting on the CABQ. But this 746 * doesn't at all mean that the CABQ DMA QCU will 747 * accept a new TXDP! So what, should we do a DMA 748 * stop? What if it fails? 749 * 750 * More thought is required here. 751 */ 752 /* 753 * XXX can we even stop TX DMA here? Check what the 754 * reference driver does for cabq for beacons, given 755 * that stopping TX requires RX is paused. 756 */ 757 ath_tx_draintxq(sc, cabq); 758 } 759 } 760 ath_beacon_setup(sc, bf); 761 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 762 763 /* 764 * Enable the CAB queue before the beacon queue to 765 * insure cab frames are triggered by this beacon. 766 */ 767 if (vap->iv_bcn_off.bo_tim[4] & 1) { 768 769 /* NB: only at DTIM */ 770 ATH_TXQ_LOCK(&avp->av_mcastq); 771 if (nmcastq) { 772 struct ath_buf *bfm, *bfc_last; 773 774 /* 775 * Move frames from the s/w mcast q to the h/w cab q. 776 * 777 * XXX TODO: if we chain together multiple VAPs 778 * worth of CABQ traffic, should we keep the 779 * MORE data bit set on the last frame of each 780 * intermediary VAP (ie, only clear the MORE 781 * bit of the last frame on the last vap?) 782 */ 783 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 784 ATH_TXQ_LOCK(cabq); 785 786 /* 787 * If there's already a frame on the CABQ, we 788 * need to link to the end of the last frame. 789 * We can't use axq_link here because 790 * EDMA descriptors require some recalculation 791 * (checksum) to occur. 792 */ 793 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 794 if (bfc_last != NULL) { 795 ath_hal_settxdesclink(sc->sc_ah, 796 bfc_last->bf_lastds, 797 bfm->bf_daddr); 798 } 799 ath_txqmove(cabq, &avp->av_mcastq); 800 ATH_TXQ_UNLOCK(cabq); 801 /* 802 * XXX not entirely accurate, in case a mcast 803 * queue frame arrived before we grabbed the TX 804 * lock. 805 */ 806 sc->sc_stats.ast_cabq_xmit += nmcastq; 807 } 808 ATH_TXQ_UNLOCK(&avp->av_mcastq); 809 } 810 return bf; 811} 812 813void 814ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 815{ 816 struct ath_vap *avp = ATH_VAP(vap); 817 struct ath_hal *ah = sc->sc_ah; 818 struct ath_buf *bf; 819 struct mbuf *m; 820 int error; 821 822 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 823 824 /* 825 * Update dynamic beacon contents. If this returns 826 * non-zero then we need to remap the memory because 827 * the beacon frame changed size (probably because 828 * of the TIM bitmap). 829 */ 830 bf = avp->av_bcbuf; 831 m = bf->bf_m; 832 if (ieee80211_beacon_update(bf->bf_node, m, 0)) { 833 /* XXX too conservative? */ 834 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 835 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 836 bf->bf_segs, &bf->bf_nseg, 837 BUS_DMA_NOWAIT); 838 if (error != 0) { 839 if_printf(vap->iv_ifp, 840 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 841 __func__, error); 842 return; 843 } 844 } 845 ath_beacon_setup(sc, bf); 846 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 847 848 /* NB: caller is known to have already stopped tx dma */ 849 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 850 ath_hal_txstart(ah, sc->sc_bhalq); 851} 852 853/* 854 * Reclaim beacon resources and return buffer to the pool. 855 */ 856void 857ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 858{ 859 860 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 861 __func__, bf, bf->bf_m, bf->bf_node); 862 if (bf->bf_m != NULL) { 863 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 864 m_freem(bf->bf_m); 865 bf->bf_m = NULL; 866 } 867 if (bf->bf_node != NULL) { 868 ieee80211_free_node(bf->bf_node); 869 bf->bf_node = NULL; 870 } 871 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 872} 873 874/* 875 * Reclaim beacon resources. 876 */ 877void 878ath_beacon_free(struct ath_softc *sc) 879{ 880 struct ath_buf *bf; 881 882 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 883 DPRINTF(sc, ATH_DEBUG_NODE, 884 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 885 __func__, bf, bf->bf_m, bf->bf_node); 886 if (bf->bf_m != NULL) { 887 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 888 m_freem(bf->bf_m); 889 bf->bf_m = NULL; 890 } 891 if (bf->bf_node != NULL) { 892 ieee80211_free_node(bf->bf_node); 893 bf->bf_node = NULL; 894 } 895 } 896} 897 898/* 899 * Configure the beacon and sleep timers. 900 * 901 * When operating as an AP this resets the TSF and sets 902 * up the hardware to notify us when we need to issue beacons. 903 * 904 * When operating in station mode this sets up the beacon 905 * timers according to the timestamp of the last received 906 * beacon and the current TSF, configures PCF and DTIM 907 * handling, programs the sleep registers so the hardware 908 * will wakeup in time to receive beacons, and configures 909 * the beacon miss handling so we'll receive a BMISS 910 * interrupt when we stop seeing beacons from the AP 911 * we've associated with. 912 */ 913void 914ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 915{ 916#define TSF_TO_TU(_h,_l) \ 917 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 918#define FUDGE 2 919 struct ath_hal *ah = sc->sc_ah; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct ieee80211_node *ni; 922 u_int32_t nexttbtt, intval, tsftu; 923 u_int32_t nexttbtt_u8, intval_u8; 924 u_int64_t tsf, tsf_beacon; 925 926 if (vap == NULL) 927 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 928 /* 929 * Just ensure that we aren't being called when the last 930 * VAP is destroyed. 931 */ 932 if (vap == NULL) { 933 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 934 __func__); 935 return; 936 } 937 938 ni = ieee80211_ref_node(vap->iv_bss); 939 940 ATH_LOCK(sc); 941 ath_power_set_power_state(sc, HAL_PM_AWAKE); 942 ATH_UNLOCK(sc); 943 944 /* extract tstamp from last beacon and convert to TU */ 945 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4), 946 le32dec(ni->ni_tstamp.data)); 947 948 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 949 tsf_beacon |= le32dec(ni->ni_tstamp.data); 950 951 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 952 ic->ic_opmode == IEEE80211_M_MBSS) { 953 /* 954 * For multi-bss ap/mesh support beacons are either staggered 955 * evenly over N slots or burst together. For the former 956 * arrange for the SWBA to be delivered for each slot. 957 * Slots that are not occupied will generate nothing. 958 */ 959 /* NB: the beacon interval is kept internally in TU's */ 960 intval = ni->ni_intval & HAL_BEACON_PERIOD; 961 if (sc->sc_stagbeacons) 962 intval /= ATH_BCBUF; 963 } else { 964 /* NB: the beacon interval is kept internally in TU's */ 965 intval = ni->ni_intval & HAL_BEACON_PERIOD; 966 } 967 if (nexttbtt == 0) /* e.g. for ap mode */ 968 nexttbtt = intval; 969 else if (intval) /* NB: can be 0 for monitor mode */ 970 nexttbtt = roundup(nexttbtt, intval); 971 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 972 __func__, nexttbtt, intval, ni->ni_intval); 973 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 974 HAL_BEACON_STATE bs; 975 int dtimperiod, dtimcount; 976 int cfpperiod, cfpcount; 977 978 /* 979 * Setup dtim and cfp parameters according to 980 * last beacon we received (which may be none). 981 */ 982 dtimperiod = ni->ni_dtim_period; 983 if (dtimperiod <= 0) /* NB: 0 if not known */ 984 dtimperiod = 1; 985 dtimcount = ni->ni_dtim_count; 986 if (dtimcount >= dtimperiod) /* NB: sanity check */ 987 dtimcount = 0; /* XXX? */ 988 cfpperiod = 1; /* NB: no PCF support yet */ 989 cfpcount = 0; 990 /* 991 * Pull nexttbtt forward to reflect the current 992 * TSF and calculate dtim+cfp state for the result. 993 */ 994 tsf = ath_hal_gettsf64(ah); 995 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 996 997 DPRINTF(sc, ATH_DEBUG_BEACON, 998 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 999 __func__, 1000 (unsigned long long) tsf_beacon, 1001 (unsigned long long) tsf, 1002 nexttbtt, 1003 tsftu); 1004 DPRINTF(sc, ATH_DEBUG_BEACON, 1005 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 1006 __func__, 1007 (unsigned long long) tsf_beacon, 1008 (unsigned long long) tsf, 1009 (long long) tsf - 1010 (long long) tsf_beacon); 1011 1012 DPRINTF(sc, ATH_DEBUG_BEACON, 1013 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1014 __func__, 1015 (unsigned long long) nexttbtt, 1016 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1017 1018 /* XXX cfpcount? */ 1019 1020 if (nexttbtt > tsftu) { 1021 uint32_t countdiff, oldtbtt, remainder; 1022 1023 oldtbtt = nexttbtt; 1024 remainder = (nexttbtt - tsftu) % intval; 1025 nexttbtt = tsftu + remainder; 1026 1027 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1028 if (dtimcount > countdiff) { 1029 dtimcount -= countdiff; 1030 } else { 1031 dtimcount += dtimperiod - countdiff; 1032 } 1033 } else { //nexttbtt <= tsftu 1034 uint32_t countdiff, oldtbtt, remainder; 1035 1036 oldtbtt = nexttbtt; 1037 remainder = (tsftu - nexttbtt) % intval; 1038 nexttbtt = tsftu - remainder + intval; 1039 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1040 if (dtimcount > countdiff) { 1041 dtimcount -= countdiff; 1042 } else { 1043 dtimcount += dtimperiod - countdiff; 1044 } 1045 } 1046 1047 DPRINTF(sc, ATH_DEBUG_BEACON, 1048 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1049 __func__, 1050 (unsigned long long) nexttbtt, 1051 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1052 1053 memset(&bs, 0, sizeof(bs)); 1054 bs.bs_intval = intval; 1055 bs.bs_nexttbtt = nexttbtt; 1056 bs.bs_dtimperiod = dtimperiod*intval; 1057 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1058 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1059 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1060 bs.bs_cfpmaxduration = 0; 1061#if 0 1062 /* 1063 * The 802.11 layer records the offset to the DTIM 1064 * bitmap while receiving beacons; use it here to 1065 * enable h/w detection of our AID being marked in 1066 * the bitmap vector (to indicate frames for us are 1067 * pending at the AP). 1068 * XXX do DTIM handling in s/w to WAR old h/w bugs 1069 * XXX enable based on h/w rev for newer chips 1070 */ 1071 bs.bs_timoffset = ni->ni_timoff; 1072#endif 1073 /* 1074 * Calculate the number of consecutive beacons to miss 1075 * before taking a BMISS interrupt. 1076 * Note that we clamp the result to at most 10 beacons. 1077 */ 1078 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1079 if (bs.bs_bmissthreshold > 10) 1080 bs.bs_bmissthreshold = 10; 1081 else if (bs.bs_bmissthreshold <= 0) 1082 bs.bs_bmissthreshold = 1; 1083 1084 /* 1085 * Calculate sleep duration. The configuration is 1086 * given in ms. We insure a multiple of the beacon 1087 * period is used. Also, if the sleep duration is 1088 * greater than the DTIM period then it makes senses 1089 * to make it a multiple of that. 1090 * 1091 * XXX fixed at 100ms 1092 */ 1093 bs.bs_sleepduration = 1094 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1095 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1096 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1097 1098 DPRINTF(sc, ATH_DEBUG_BEACON, 1099 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1100 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1101 "maxdur %u next %u timoffset %u\n" 1102 , __func__ 1103 , tsf 1104 , tsftu 1105 , bs.bs_intval 1106 , bs.bs_nexttbtt 1107 , bs.bs_dtimperiod 1108 , bs.bs_nextdtim 1109 , bs.bs_bmissthreshold 1110 , bs.bs_sleepduration 1111 , bs.bs_cfpperiod 1112 , bs.bs_cfpmaxduration 1113 , bs.bs_cfpnext 1114 , bs.bs_timoffset 1115 ); 1116 ath_hal_intrset(ah, 0); 1117 ath_hal_beacontimers(ah, &bs); 1118 sc->sc_imask |= HAL_INT_BMISS; 1119 ath_hal_intrset(ah, sc->sc_imask); 1120 } else { 1121 ath_hal_intrset(ah, 0); 1122 if (nexttbtt == intval) 1123 intval |= HAL_BEACON_RESET_TSF; 1124 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1125 /* 1126 * In IBSS mode enable the beacon timers but only 1127 * enable SWBA interrupts if we need to manually 1128 * prepare beacon frames. Otherwise we use a 1129 * self-linked tx descriptor and let the hardware 1130 * deal with things. 1131 */ 1132 intval |= HAL_BEACON_ENA; 1133 if (!sc->sc_hasveol) 1134 sc->sc_imask |= HAL_INT_SWBA; 1135 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1136 /* 1137 * Pull nexttbtt forward to reflect 1138 * the current TSF. 1139 */ 1140 tsf = ath_hal_gettsf64(ah); 1141 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1142 do { 1143 nexttbtt += intval; 1144 } while (nexttbtt < tsftu); 1145 } 1146 ath_beaconq_config(sc); 1147 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1148 ic->ic_opmode == IEEE80211_M_MBSS) { 1149 /* 1150 * In AP/mesh mode we enable the beacon timers 1151 * and SWBA interrupts to prepare beacon frames. 1152 */ 1153 intval |= HAL_BEACON_ENA; 1154 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1155 ath_beaconq_config(sc); 1156 } 1157 1158 /* 1159 * Now dirty things because for now, the EDMA HAL has 1160 * nexttbtt and intval is TU/8. 1161 */ 1162 if (sc->sc_isedma) { 1163 nexttbtt_u8 = (nexttbtt << 3); 1164 intval_u8 = (intval << 3); 1165 if (intval & HAL_BEACON_ENA) 1166 intval_u8 |= HAL_BEACON_ENA; 1167 if (intval & HAL_BEACON_RESET_TSF) 1168 intval_u8 |= HAL_BEACON_RESET_TSF; 1169 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1170 } else 1171 ath_hal_beaconinit(ah, nexttbtt, intval); 1172 sc->sc_bmisscount = 0; 1173 ath_hal_intrset(ah, sc->sc_imask); 1174 /* 1175 * When using a self-linked beacon descriptor in 1176 * ibss mode load it once here. 1177 */ 1178 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1179 ath_beacon_start_adhoc(sc, vap); 1180 } 1181 ieee80211_free_node(ni); 1182 1183 ATH_LOCK(sc); 1184 ath_power_restore_power_state(sc); 1185 ATH_UNLOCK(sc); 1186#undef FUDGE 1187#undef TSF_TO_TU 1188} 1189