if_ath_beacon.c revision 250619
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_beacon.c 250619 2013-05-13 21:18:00Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88 89#include <net/bpf.h> 90 91#ifdef INET 92#include <netinet/in.h> 93#include <netinet/if_ether.h> 94#endif 95 96#include <dev/ath/if_athvar.h> 97 98#include <dev/ath/if_ath_debug.h> 99#include <dev/ath/if_ath_misc.h> 100#include <dev/ath/if_ath_tx.h> 101#include <dev/ath/if_ath_beacon.h> 102 103#ifdef ATH_TX99_DIAG 104#include <dev/ath/ath_tx99/ath_tx99.h> 105#endif 106 107/* 108 * Setup a h/w transmit queue for beacons. 109 */ 110int 111ath_beaconq_setup(struct ath_softc *sc) 112{ 113 struct ath_hal *ah = sc->sc_ah; 114 HAL_TXQ_INFO qi; 115 116 memset(&qi, 0, sizeof(qi)); 117 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 118 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 119 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 120 /* NB: for dynamic turbo, don't enable any other interrupts */ 121 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 122 if (sc->sc_isedma) 123 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 124 HAL_TXQ_TXERRINT_ENABLE; 125 126 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 127} 128 129/* 130 * Setup the transmit queue parameters for the beacon queue. 131 */ 132int 133ath_beaconq_config(struct ath_softc *sc) 134{ 135#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 136 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 137 struct ath_hal *ah = sc->sc_ah; 138 HAL_TXQ_INFO qi; 139 140 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 141 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 142 ic->ic_opmode == IEEE80211_M_MBSS) { 143 /* 144 * Always burst out beacon and CAB traffic. 145 */ 146 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 147 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 148 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 149 } else { 150 struct wmeParams *wmep = 151 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 152 /* 153 * Adhoc mode; important thing is to use 2x cwmin. 154 */ 155 qi.tqi_aifs = wmep->wmep_aifsn; 156 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 157 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 158 } 159 160 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 161 device_printf(sc->sc_dev, "unable to update parameters for " 162 "beacon hardware queue!\n"); 163 return 0; 164 } else { 165 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 166 return 1; 167 } 168#undef ATH_EXPONENT_TO_VALUE 169} 170 171/* 172 * Allocate and setup an initial beacon frame. 173 */ 174int 175ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 176{ 177 struct ieee80211vap *vap = ni->ni_vap; 178 struct ath_vap *avp = ATH_VAP(vap); 179 struct ath_buf *bf; 180 struct mbuf *m; 181 int error; 182 183 bf = avp->av_bcbuf; 184 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 185 __func__, bf->bf_m, bf->bf_node); 186 if (bf->bf_m != NULL) { 187 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 188 m_freem(bf->bf_m); 189 bf->bf_m = NULL; 190 } 191 if (bf->bf_node != NULL) { 192 ieee80211_free_node(bf->bf_node); 193 bf->bf_node = NULL; 194 } 195 196 /* 197 * NB: the beacon data buffer must be 32-bit aligned; 198 * we assume the mbuf routines will return us something 199 * with this alignment (perhaps should assert). 200 */ 201 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 202 if (m == NULL) { 203 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 204 sc->sc_stats.ast_be_nombuf++; 205 return ENOMEM; 206 } 207 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 208 bf->bf_segs, &bf->bf_nseg, 209 BUS_DMA_NOWAIT); 210 if (error != 0) { 211 device_printf(sc->sc_dev, 212 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 213 __func__, error); 214 m_freem(m); 215 return error; 216 } 217 218 /* 219 * Calculate a TSF adjustment factor required for staggered 220 * beacons. Note that we assume the format of the beacon 221 * frame leaves the tstamp field immediately following the 222 * header. 223 */ 224 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 225 uint64_t tsfadjust; 226 struct ieee80211_frame *wh; 227 228 /* 229 * The beacon interval is in TU's; the TSF is in usecs. 230 * We figure out how many TU's to add to align the timestamp 231 * then convert to TSF units and handle byte swapping before 232 * inserting it in the frame. The hardware will then add this 233 * each time a beacon frame is sent. Note that we align vap's 234 * 1..N and leave vap 0 untouched. This means vap 0 has a 235 * timestamp in one beacon interval while the others get a 236 * timstamp aligned to the next interval. 237 */ 238 tsfadjust = ni->ni_intval * 239 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 240 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 241 242 DPRINTF(sc, ATH_DEBUG_BEACON, 243 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 244 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 245 avp->av_bslot, ni->ni_intval, 246 (long long unsigned) le64toh(tsfadjust)); 247 248 wh = mtod(m, struct ieee80211_frame *); 249 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 250 } 251 bf->bf_m = m; 252 bf->bf_node = ieee80211_ref_node(ni); 253 254 return 0; 255} 256 257/* 258 * Setup the beacon frame for transmit. 259 */ 260static void 261ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 262{ 263#define USE_SHPREAMBLE(_ic) \ 264 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 265 == IEEE80211_F_SHPREAMBLE) 266 struct ieee80211_node *ni = bf->bf_node; 267 struct ieee80211com *ic = ni->ni_ic; 268 struct mbuf *m = bf->bf_m; 269 struct ath_hal *ah = sc->sc_ah; 270 struct ath_desc *ds; 271 int flags, antenna; 272 const HAL_RATE_TABLE *rt; 273 u_int8_t rix, rate; 274 HAL_DMA_ADDR bufAddrList[4]; 275 uint32_t segLenList[4]; 276 HAL_11N_RATE_SERIES rc[4]; 277 278 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 279 __func__, m, m->m_len); 280 281 /* setup descriptors */ 282 ds = bf->bf_desc; 283 bf->bf_last = bf; 284 bf->bf_lastds = ds; 285 286 flags = HAL_TXDESC_NOACK; 287 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 288 /* self-linked descriptor */ 289 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 290 flags |= HAL_TXDESC_VEOL; 291 /* 292 * Let hardware handle antenna switching. 293 */ 294 antenna = sc->sc_txantenna; 295 } else { 296 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 297 /* 298 * Switch antenna every 4 beacons. 299 * XXX assumes two antenna 300 */ 301 if (sc->sc_txantenna != 0) 302 antenna = sc->sc_txantenna; 303 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 304 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 305 else 306 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 307 } 308 309 KASSERT(bf->bf_nseg == 1, 310 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 311 312 /* 313 * Calculate rate code. 314 * XXX everything at min xmit rate 315 */ 316 rix = 0; 317 rt = sc->sc_currates; 318 rate = rt->info[rix].rateCode; 319 if (USE_SHPREAMBLE(ic)) 320 rate |= rt->info[rix].shortPreamble; 321 ath_hal_setuptxdesc(ah, ds 322 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 323 , sizeof(struct ieee80211_frame)/* header length */ 324 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 325 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 326 , rate, 1 /* series 0 rate/tries */ 327 , HAL_TXKEYIX_INVALID /* no encryption */ 328 , antenna /* antenna mode */ 329 , flags /* no ack, veol for beacons */ 330 , 0 /* rts/cts rate */ 331 , 0 /* rts/cts duration */ 332 ); 333 334 /* 335 * The EDMA HAL currently assumes that _all_ rate control 336 * settings are done in ath_hal_set11nratescenario(), rather 337 * than in ath_hal_setuptxdesc(). 338 */ 339 if (sc->sc_isedma) { 340 memset(&rc, 0, sizeof(rc)); 341 342 rc[0].ChSel = sc->sc_txchainmask; 343 rc[0].Tries = 1; 344 rc[0].Rate = rt->info[rix].rateCode; 345 rc[0].RateIndex = rix; 346 rc[0].tx_power_cap = 0x3f; 347 rc[0].PktDuration = 348 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 349 rix, 0); 350 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 351 } 352 353 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 354 segLenList[0] = roundup(m->m_len, 4); 355 segLenList[1] = segLenList[2] = segLenList[3] = 0; 356 bufAddrList[0] = bf->bf_segs[0].ds_addr; 357 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 358 ath_hal_filltxdesc(ah, ds 359 , bufAddrList 360 , segLenList 361 , 0 /* XXX desc id */ 362 , sc->sc_bhalq /* hardware TXQ */ 363 , AH_TRUE /* first segment */ 364 , AH_TRUE /* last segment */ 365 , ds /* first descriptor */ 366 ); 367#if 0 368 ath_desc_swap(ds); 369#endif 370#undef USE_SHPREAMBLE 371} 372 373void 374ath_beacon_update(struct ieee80211vap *vap, int item) 375{ 376 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 377 378 setbit(bo->bo_flags, item); 379} 380 381/* 382 * Handle a beacon miss. 383 */ 384static void 385ath_beacon_miss(struct ath_softc *sc) 386{ 387 HAL_SURVEY_SAMPLE hs; 388 HAL_BOOL ret; 389 uint32_t hangs; 390 391 bzero(&hs, sizeof(hs)); 392 393 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 394 395 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 396 DPRINTF(sc, ATH_DEBUG_BEACON, 397 "%s: hang=0x%08x\n", 398 __func__, 399 hangs); 400 } 401 402#ifdef ATH_DEBUG_ALQ 403 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 404 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 405#endif 406 407 DPRINTF(sc, ATH_DEBUG_BEACON, 408 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 409 "extchanbusy=%u, cyclecount=%u\n", 410 __func__, 411 ret, 412 hs.tx_busy, 413 hs.rx_busy, 414 hs.chan_busy, 415 hs.ext_chan_busy, 416 hs.cycle_count); 417} 418 419/* 420 * Transmit a beacon frame at SWBA. Dynamic updates to the 421 * frame contents are done as needed and the slot time is 422 * also adjusted based on current state. 423 */ 424void 425ath_beacon_proc(void *arg, int pending) 426{ 427 struct ath_softc *sc = arg; 428 struct ath_hal *ah = sc->sc_ah; 429 struct ieee80211vap *vap; 430 struct ath_buf *bf; 431 int slot, otherant; 432 uint32_t bfaddr; 433 434 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 435 __func__, pending); 436 /* 437 * Check if the previous beacon has gone out. If 438 * not don't try to post another, skip this period 439 * and wait for the next. Missed beacons indicate 440 * a problem and should not occur. If we miss too 441 * many consecutive beacons reset the device. 442 */ 443 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 444 sc->sc_bmisscount++; 445 sc->sc_stats.ast_be_missed++; 446 ath_beacon_miss(sc); 447 DPRINTF(sc, ATH_DEBUG_BEACON, 448 "%s: missed %u consecutive beacons\n", 449 __func__, sc->sc_bmisscount); 450 if (sc->sc_bmisscount >= ath_bstuck_threshold) 451 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 452 return; 453 } 454 if (sc->sc_bmisscount != 0) { 455 DPRINTF(sc, ATH_DEBUG_BEACON, 456 "%s: resume beacon xmit after %u misses\n", 457 __func__, sc->sc_bmisscount); 458 sc->sc_bmisscount = 0; 459#ifdef ATH_DEBUG_ALQ 460 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 461 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 462#endif 463 } 464 465 if (sc->sc_stagbeacons) { /* staggered beacons */ 466 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 467 uint32_t tsftu; 468 469 tsftu = ath_hal_gettsf32(ah) >> 10; 470 /* XXX lintval */ 471 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 472 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 473 bfaddr = 0; 474 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 475 bf = ath_beacon_generate(sc, vap); 476 if (bf != NULL) 477 bfaddr = bf->bf_daddr; 478 } 479 } else { /* burst'd beacons */ 480 uint32_t *bflink = &bfaddr; 481 482 for (slot = 0; slot < ATH_BCBUF; slot++) { 483 vap = sc->sc_bslot[slot]; 484 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 485 bf = ath_beacon_generate(sc, vap); 486 /* 487 * XXX TODO: this should use settxdesclinkptr() 488 * otherwise it won't work for EDMA chipsets! 489 */ 490 if (bf != NULL) { 491 /* XXX should do this using the ds */ 492 *bflink = bf->bf_daddr; 493 ath_hal_gettxdesclinkptr(sc->sc_ah, 494 bf->bf_desc, &bflink); 495 } 496 } 497 } 498 /* 499 * XXX TODO: this should use settxdesclinkptr() 500 * otherwise it won't work for EDMA chipsets! 501 */ 502 *bflink = 0; /* terminate list */ 503 } 504 505 /* 506 * Handle slot time change when a non-ERP station joins/leaves 507 * an 11g network. The 802.11 layer notifies us via callback, 508 * we mark updateslot, then wait one beacon before effecting 509 * the change. This gives associated stations at least one 510 * beacon interval to note the state change. 511 */ 512 /* XXX locking */ 513 if (sc->sc_updateslot == UPDATE) { 514 sc->sc_updateslot = COMMIT; /* commit next beacon */ 515 sc->sc_slotupdate = slot; 516 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 517 ath_setslottime(sc); /* commit change to h/w */ 518 519 /* 520 * Check recent per-antenna transmit statistics and flip 521 * the default antenna if noticeably more frames went out 522 * on the non-default antenna. 523 * XXX assumes 2 anntenae 524 */ 525 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 526 otherant = sc->sc_defant & 1 ? 2 : 1; 527 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 528 ath_setdefantenna(sc, otherant); 529 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 530 } 531 532 /* Program the CABQ with the contents of the CABQ txq and start it */ 533 ATH_TXQ_LOCK(sc->sc_cabq); 534 ath_beacon_cabq_start(sc); 535 ATH_TXQ_UNLOCK(sc->sc_cabq); 536 537 /* Program the new beacon frame if we have one for this interval */ 538 if (bfaddr != 0) { 539 /* 540 * Stop any current dma and put the new frame on the queue. 541 * This should never fail since we check above that no frames 542 * are still pending on the queue. 543 */ 544 if (! sc->sc_isedma) { 545 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 546 DPRINTF(sc, ATH_DEBUG_ANY, 547 "%s: beacon queue %u did not stop?\n", 548 __func__, sc->sc_bhalq); 549 } 550 } 551 /* NB: cabq traffic should already be queued and primed */ 552 553 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 554 ath_hal_txstart(ah, sc->sc_bhalq); 555 556 sc->sc_stats.ast_be_xmit++; 557 } 558} 559 560static void 561ath_beacon_cabq_start_edma(struct ath_softc *sc) 562{ 563 struct ath_buf *bf, *bf_last; 564 struct ath_txq *cabq = sc->sc_cabq; 565#if 0 566 struct ath_buf *bfi; 567 int i = 0; 568#endif 569 570 ATH_TXQ_LOCK_ASSERT(cabq); 571 572 if (TAILQ_EMPTY(&cabq->axq_q)) 573 return; 574 bf = TAILQ_FIRST(&cabq->axq_q); 575 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 576 577 /* 578 * This is a dirty, dirty hack to push the contents of 579 * the cabq staging queue into the FIFO. 580 * 581 * This ideally should live in the EDMA code file 582 * and only push things into the CABQ if there's a FIFO 583 * slot. 584 * 585 * We can't treat this like a normal TX queue because 586 * in the case of multi-VAP traffic, we may have to flush 587 * the CABQ each new (staggered) beacon that goes out. 588 * But for non-staggered beacons, we could in theory 589 * handle multicast traffic for all VAPs in one FIFO 590 * push. Just keep all of this in mind if you're wondering 591 * how to correctly/better handle multi-VAP CABQ traffic 592 * with EDMA. 593 */ 594 595 /* 596 * Is the CABQ FIFO free? If not, complain loudly and 597 * don't queue anything. Maybe we'll flush the CABQ 598 * traffic, maybe we won't. But that'll happen next 599 * beacon interval. 600 */ 601 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 602 device_printf(sc->sc_dev, 603 "%s: Q%d: CAB FIFO queue=%d?\n", 604 __func__, 605 cabq->axq_qnum, 606 cabq->axq_fifo_depth); 607 return; 608 } 609 610 /* 611 * Ok, so here's the gymnastics reqiured to make this 612 * all sensible. 613 */ 614 615 /* 616 * Tag the first/last buffer appropriately. 617 */ 618 bf->bf_flags |= ATH_BUF_FIFOPTR; 619 bf_last->bf_flags |= ATH_BUF_FIFOEND; 620 621#if 0 622 i = 0; 623 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 624 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 625 i++; 626 } 627#endif 628 629 /* 630 * We now need to push this set of frames onto the tail 631 * of the FIFO queue. We don't adjust the aggregate 632 * count, only the queue depth counter(s). 633 * We also need to blank the link pointer now. 634 */ 635 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 636 cabq->axq_link = NULL; 637 cabq->fifo.axq_depth += cabq->axq_depth; 638 cabq->axq_depth = 0; 639 640 /* Bump FIFO queue */ 641 cabq->axq_fifo_depth++; 642 643 /* Push the first entry into the hardware */ 644 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 645 646 /* NB: gated by beacon so safe to start here */ 647 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 648 649} 650 651static void 652ath_beacon_cabq_start_legacy(struct ath_softc *sc) 653{ 654 struct ath_buf *bf; 655 struct ath_txq *cabq = sc->sc_cabq; 656 657 ATH_TXQ_LOCK_ASSERT(cabq); 658 if (TAILQ_EMPTY(&cabq->axq_q)) 659 return; 660 bf = TAILQ_FIRST(&cabq->axq_q); 661 662 /* Push the first entry into the hardware */ 663 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 664 665 /* NB: gated by beacon so safe to start here */ 666 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 667} 668 669/* 670 * Start CABQ transmission - this assumes that all frames are prepped 671 * and ready in the CABQ. 672 */ 673void 674ath_beacon_cabq_start(struct ath_softc *sc) 675{ 676 struct ath_txq *cabq = sc->sc_cabq; 677 678 ATH_TXQ_LOCK_ASSERT(cabq); 679 680 if (TAILQ_EMPTY(&cabq->axq_q)) 681 return; 682 683 if (sc->sc_isedma) 684 ath_beacon_cabq_start_edma(sc); 685 else 686 ath_beacon_cabq_start_legacy(sc); 687} 688 689struct ath_buf * 690ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 691{ 692 struct ath_vap *avp = ATH_VAP(vap); 693 struct ath_txq *cabq = sc->sc_cabq; 694 struct ath_buf *bf; 695 struct mbuf *m; 696 int nmcastq, error; 697 698 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 699 ("not running, state %d", vap->iv_state)); 700 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 701 702 /* 703 * Update dynamic beacon contents. If this returns 704 * non-zero then we need to remap the memory because 705 * the beacon frame changed size (probably because 706 * of the TIM bitmap). 707 */ 708 bf = avp->av_bcbuf; 709 m = bf->bf_m; 710 /* XXX lock mcastq? */ 711 nmcastq = avp->av_mcastq.axq_depth; 712 713 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 714 /* XXX too conservative? */ 715 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 716 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 717 bf->bf_segs, &bf->bf_nseg, 718 BUS_DMA_NOWAIT); 719 if (error != 0) { 720 if_printf(vap->iv_ifp, 721 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 722 __func__, error); 723 return NULL; 724 } 725 } 726 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 727 DPRINTF(sc, ATH_DEBUG_BEACON, 728 "%s: cabq did not drain, mcastq %u cabq %u\n", 729 __func__, nmcastq, cabq->axq_depth); 730 sc->sc_stats.ast_cabq_busy++; 731 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 732 /* 733 * CABQ traffic from a previous vap is still pending. 734 * We must drain the q before this beacon frame goes 735 * out as otherwise this vap's stations will get cab 736 * frames from a different vap. 737 * XXX could be slow causing us to miss DBA 738 */ 739 ath_tx_draintxq(sc, cabq); 740 } 741 } 742 ath_beacon_setup(sc, bf); 743 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 744 745 /* 746 * Enable the CAB queue before the beacon queue to 747 * insure cab frames are triggered by this beacon. 748 */ 749 if (avp->av_boff.bo_tim[4] & 1) { 750 751 /* NB: only at DTIM */ 752 ATH_TXQ_LOCK(&avp->av_mcastq); 753 if (nmcastq) { 754 struct ath_buf *bfm, *bfc_last; 755 756 /* 757 * Move frames from the s/w mcast q to the h/w cab q. 758 * 759 * XXX TODO: if we chain together multiple VAPs 760 * worth of CABQ traffic, should we keep the 761 * MORE data bit set on the last frame of each 762 * intermediary VAP (ie, only clear the MORE 763 * bit of the last frame on the last vap?) 764 */ 765 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 766 ATH_TXQ_LOCK(cabq); 767 768 /* 769 * If there's already a frame on the CABQ, we 770 * need to link to the end of the last frame. 771 * We can't use axq_link here because 772 * EDMA descriptors require some recalculation 773 * (checksum) to occur. 774 */ 775 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 776 if (bfc_last != NULL) { 777 ath_hal_settxdesclink(sc->sc_ah, 778 bfc_last->bf_lastds, 779 bfm->bf_daddr); 780 } 781 ath_txqmove(cabq, &avp->av_mcastq); 782 ATH_TXQ_UNLOCK(cabq); 783 /* 784 * XXX not entirely accurate, in case a mcast 785 * queue frame arrived before we grabbed the TX 786 * lock. 787 */ 788 sc->sc_stats.ast_cabq_xmit += nmcastq; 789 } 790 ATH_TXQ_UNLOCK(&avp->av_mcastq); 791 } 792 return bf; 793} 794 795void 796ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 797{ 798 struct ath_vap *avp = ATH_VAP(vap); 799 struct ath_hal *ah = sc->sc_ah; 800 struct ath_buf *bf; 801 struct mbuf *m; 802 int error; 803 804 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 805 806 /* 807 * Update dynamic beacon contents. If this returns 808 * non-zero then we need to remap the memory because 809 * the beacon frame changed size (probably because 810 * of the TIM bitmap). 811 */ 812 bf = avp->av_bcbuf; 813 m = bf->bf_m; 814 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 815 /* XXX too conservative? */ 816 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 817 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 818 bf->bf_segs, &bf->bf_nseg, 819 BUS_DMA_NOWAIT); 820 if (error != 0) { 821 if_printf(vap->iv_ifp, 822 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 823 __func__, error); 824 return; 825 } 826 } 827 ath_beacon_setup(sc, bf); 828 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 829 830 /* NB: caller is known to have already stopped tx dma */ 831 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 832 ath_hal_txstart(ah, sc->sc_bhalq); 833} 834 835/* 836 * Reclaim beacon resources and return buffer to the pool. 837 */ 838void 839ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 840{ 841 842 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 843 __func__, bf, bf->bf_m, bf->bf_node); 844 if (bf->bf_m != NULL) { 845 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 846 m_freem(bf->bf_m); 847 bf->bf_m = NULL; 848 } 849 if (bf->bf_node != NULL) { 850 ieee80211_free_node(bf->bf_node); 851 bf->bf_node = NULL; 852 } 853 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 854} 855 856/* 857 * Reclaim beacon resources. 858 */ 859void 860ath_beacon_free(struct ath_softc *sc) 861{ 862 struct ath_buf *bf; 863 864 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 865 DPRINTF(sc, ATH_DEBUG_NODE, 866 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 867 __func__, bf, bf->bf_m, bf->bf_node); 868 if (bf->bf_m != NULL) { 869 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 870 m_freem(bf->bf_m); 871 bf->bf_m = NULL; 872 } 873 if (bf->bf_node != NULL) { 874 ieee80211_free_node(bf->bf_node); 875 bf->bf_node = NULL; 876 } 877 } 878} 879 880/* 881 * Configure the beacon and sleep timers. 882 * 883 * When operating as an AP this resets the TSF and sets 884 * up the hardware to notify us when we need to issue beacons. 885 * 886 * When operating in station mode this sets up the beacon 887 * timers according to the timestamp of the last received 888 * beacon and the current TSF, configures PCF and DTIM 889 * handling, programs the sleep registers so the hardware 890 * will wakeup in time to receive beacons, and configures 891 * the beacon miss handling so we'll receive a BMISS 892 * interrupt when we stop seeing beacons from the AP 893 * we've associated with. 894 */ 895void 896ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 897{ 898#define TSF_TO_TU(_h,_l) \ 899 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 900#define FUDGE 2 901 struct ath_hal *ah = sc->sc_ah; 902 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 903 struct ieee80211_node *ni; 904 u_int32_t nexttbtt, intval, tsftu; 905 u_int32_t nexttbtt_u8, intval_u8; 906 u_int64_t tsf; 907 908 if (vap == NULL) 909 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 910 /* 911 * Just ensure that we aren't being called when the last 912 * VAP is destroyed. 913 */ 914 if (vap == NULL) { 915 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 916 __func__); 917 return; 918 } 919 920 ni = ieee80211_ref_node(vap->iv_bss); 921 922 /* extract tstamp from last beacon and convert to TU */ 923 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 924 LE_READ_4(ni->ni_tstamp.data)); 925 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 926 ic->ic_opmode == IEEE80211_M_MBSS) { 927 /* 928 * For multi-bss ap/mesh support beacons are either staggered 929 * evenly over N slots or burst together. For the former 930 * arrange for the SWBA to be delivered for each slot. 931 * Slots that are not occupied will generate nothing. 932 */ 933 /* NB: the beacon interval is kept internally in TU's */ 934 intval = ni->ni_intval & HAL_BEACON_PERIOD; 935 if (sc->sc_stagbeacons) 936 intval /= ATH_BCBUF; 937 } else { 938 /* NB: the beacon interval is kept internally in TU's */ 939 intval = ni->ni_intval & HAL_BEACON_PERIOD; 940 } 941 if (nexttbtt == 0) /* e.g. for ap mode */ 942 nexttbtt = intval; 943 else if (intval) /* NB: can be 0 for monitor mode */ 944 nexttbtt = roundup(nexttbtt, intval); 945 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 946 __func__, nexttbtt, intval, ni->ni_intval); 947 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 948 HAL_BEACON_STATE bs; 949 int dtimperiod, dtimcount; 950 int cfpperiod, cfpcount; 951 952 /* 953 * Setup dtim and cfp parameters according to 954 * last beacon we received (which may be none). 955 */ 956 dtimperiod = ni->ni_dtim_period; 957 if (dtimperiod <= 0) /* NB: 0 if not known */ 958 dtimperiod = 1; 959 dtimcount = ni->ni_dtim_count; 960 if (dtimcount >= dtimperiod) /* NB: sanity check */ 961 dtimcount = 0; /* XXX? */ 962 cfpperiod = 1; /* NB: no PCF support yet */ 963 cfpcount = 0; 964 /* 965 * Pull nexttbtt forward to reflect the current 966 * TSF and calculate dtim+cfp state for the result. 967 */ 968 tsf = ath_hal_gettsf64(ah); 969 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 970 do { 971 nexttbtt += intval; 972 if (--dtimcount < 0) { 973 dtimcount = dtimperiod - 1; 974 if (--cfpcount < 0) 975 cfpcount = cfpperiod - 1; 976 } 977 } while (nexttbtt < tsftu); 978 memset(&bs, 0, sizeof(bs)); 979 bs.bs_intval = intval; 980 bs.bs_nexttbtt = nexttbtt; 981 bs.bs_dtimperiod = dtimperiod*intval; 982 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 983 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 984 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 985 bs.bs_cfpmaxduration = 0; 986#if 0 987 /* 988 * The 802.11 layer records the offset to the DTIM 989 * bitmap while receiving beacons; use it here to 990 * enable h/w detection of our AID being marked in 991 * the bitmap vector (to indicate frames for us are 992 * pending at the AP). 993 * XXX do DTIM handling in s/w to WAR old h/w bugs 994 * XXX enable based on h/w rev for newer chips 995 */ 996 bs.bs_timoffset = ni->ni_timoff; 997#endif 998 /* 999 * Calculate the number of consecutive beacons to miss 1000 * before taking a BMISS interrupt. 1001 * Note that we clamp the result to at most 10 beacons. 1002 */ 1003 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1004 if (bs.bs_bmissthreshold > 10) 1005 bs.bs_bmissthreshold = 10; 1006 else if (bs.bs_bmissthreshold <= 0) 1007 bs.bs_bmissthreshold = 1; 1008 1009 /* 1010 * Calculate sleep duration. The configuration is 1011 * given in ms. We insure a multiple of the beacon 1012 * period is used. Also, if the sleep duration is 1013 * greater than the DTIM period then it makes senses 1014 * to make it a multiple of that. 1015 * 1016 * XXX fixed at 100ms 1017 */ 1018 bs.bs_sleepduration = 1019 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1020 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1021 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1022 1023 DPRINTF(sc, ATH_DEBUG_BEACON, 1024 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 1025 , __func__ 1026 , tsf, tsftu 1027 , bs.bs_intval 1028 , bs.bs_nexttbtt 1029 , bs.bs_dtimperiod 1030 , bs.bs_nextdtim 1031 , bs.bs_bmissthreshold 1032 , bs.bs_sleepduration 1033 , bs.bs_cfpperiod 1034 , bs.bs_cfpmaxduration 1035 , bs.bs_cfpnext 1036 , bs.bs_timoffset 1037 ); 1038 ath_hal_intrset(ah, 0); 1039 ath_hal_beacontimers(ah, &bs); 1040 sc->sc_imask |= HAL_INT_BMISS; 1041 ath_hal_intrset(ah, sc->sc_imask); 1042 } else { 1043 ath_hal_intrset(ah, 0); 1044 if (nexttbtt == intval) 1045 intval |= HAL_BEACON_RESET_TSF; 1046 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1047 /* 1048 * In IBSS mode enable the beacon timers but only 1049 * enable SWBA interrupts if we need to manually 1050 * prepare beacon frames. Otherwise we use a 1051 * self-linked tx descriptor and let the hardware 1052 * deal with things. 1053 */ 1054 intval |= HAL_BEACON_ENA; 1055 if (!sc->sc_hasveol) 1056 sc->sc_imask |= HAL_INT_SWBA; 1057 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1058 /* 1059 * Pull nexttbtt forward to reflect 1060 * the current TSF. 1061 */ 1062 tsf = ath_hal_gettsf64(ah); 1063 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1064 do { 1065 nexttbtt += intval; 1066 } while (nexttbtt < tsftu); 1067 } 1068 ath_beaconq_config(sc); 1069 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1070 ic->ic_opmode == IEEE80211_M_MBSS) { 1071 /* 1072 * In AP/mesh mode we enable the beacon timers 1073 * and SWBA interrupts to prepare beacon frames. 1074 */ 1075 intval |= HAL_BEACON_ENA; 1076 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1077 ath_beaconq_config(sc); 1078 } 1079 1080 /* 1081 * Now dirty things because for now, the EDMA HAL has 1082 * nexttbtt and intval is TU/8. 1083 */ 1084 if (sc->sc_isedma) { 1085 nexttbtt_u8 = (nexttbtt << 3); 1086 intval_u8 = (intval << 3); 1087 if (intval & HAL_BEACON_ENA) 1088 intval_u8 |= HAL_BEACON_ENA; 1089 if (intval & HAL_BEACON_RESET_TSF) 1090 intval_u8 |= HAL_BEACON_RESET_TSF; 1091 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1092 } else 1093 ath_hal_beaconinit(ah, nexttbtt, intval); 1094 sc->sc_bmisscount = 0; 1095 ath_hal_intrset(ah, sc->sc_imask); 1096 /* 1097 * When using a self-linked beacon descriptor in 1098 * ibss mode load it once here. 1099 */ 1100 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1101 ath_beacon_start_adhoc(sc, vap); 1102 } 1103 sc->sc_syncbeacon = 0; 1104 ieee80211_free_node(ni); 1105#undef FUDGE 1106#undef TSF_TO_TU 1107} 1108