if_ath.c revision 250326
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 250326 2013-05-07 07:52:18Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_rx_edma.h> 112#include <dev/ath/if_ath_tx_edma.h> 113#include <dev/ath/if_ath_beacon.h> 114#include <dev/ath/if_ath_spectral.h> 115#include <dev/ath/if_athdfs.h> 116 117#ifdef ATH_TX99_DIAG 118#include <dev/ath/ath_tx99/ath_tx99.h> 119#endif 120 121#ifdef ATH_DEBUG_ALQ 122#include <dev/ath/if_ath_alq.h> 123#endif 124 125/* 126 * Only enable this if you're working on PS-POLL support. 127 */ 128#undef ATH_SW_PSQ 129 130/* 131 * ATH_BCBUF determines the number of vap's that can transmit 132 * beacons and also (currently) the number of vap's that can 133 * have unique mac addresses/bssid. When staggering beacons 134 * 4 is probably a good max as otherwise the beacons become 135 * very closely spaced and there is limited time for cab q traffic 136 * to go out. You can burst beacons instead but that is not good 137 * for stations in power save and at some point you really want 138 * another radio (and channel). 139 * 140 * The limit on the number of mac addresses is tied to our use of 141 * the U/L bit and tracking addresses in a byte; it would be 142 * worthwhile to allow more for applications like proxy sta. 143 */ 144CTASSERT(ATH_BCBUF <= 8); 145 146static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 147 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 148 const uint8_t [IEEE80211_ADDR_LEN], 149 const uint8_t [IEEE80211_ADDR_LEN]); 150static void ath_vap_delete(struct ieee80211vap *); 151static void ath_init(void *); 152static void ath_stop_locked(struct ifnet *); 153static void ath_stop(struct ifnet *); 154static int ath_reset_vap(struct ieee80211vap *, u_long); 155static void ath_start_queue(struct ifnet *ifp); 156static int ath_media_change(struct ifnet *); 157static void ath_watchdog(void *); 158static int ath_ioctl(struct ifnet *, u_long, caddr_t); 159static void ath_fatal_proc(void *, int); 160static void ath_bmiss_vap(struct ieee80211vap *); 161static void ath_bmiss_proc(void *, int); 162static void ath_key_update_begin(struct ieee80211vap *); 163static void ath_key_update_end(struct ieee80211vap *); 164static void ath_update_mcast(struct ifnet *); 165static void ath_update_promisc(struct ifnet *); 166static void ath_updateslot(struct ifnet *); 167static void ath_bstuck_proc(void *, int); 168static void ath_reset_proc(void *, int); 169static int ath_desc_alloc(struct ath_softc *); 170static void ath_desc_free(struct ath_softc *); 171static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 172 const uint8_t [IEEE80211_ADDR_LEN]); 173static void ath_node_cleanup(struct ieee80211_node *); 174static void ath_node_free(struct ieee80211_node *); 175static void ath_node_getsignal(const struct ieee80211_node *, 176 int8_t *, int8_t *); 177static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 178static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 179static int ath_tx_setup(struct ath_softc *, int, int); 180static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 181static void ath_tx_cleanup(struct ath_softc *); 182static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, 183 int dosched); 184static void ath_tx_proc_q0(void *, int); 185static void ath_tx_proc_q0123(void *, int); 186static void ath_tx_proc(void *, int); 187static void ath_txq_sched_tasklet(void *, int); 188static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 189static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 190static void ath_scan_start(struct ieee80211com *); 191static void ath_scan_end(struct ieee80211com *); 192static void ath_set_channel(struct ieee80211com *); 193#ifdef ATH_ENABLE_11N 194static void ath_update_chw(struct ieee80211com *); 195#endif /* ATH_ENABLE_11N */ 196static void ath_calibrate(void *); 197static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 198static void ath_setup_stationkey(struct ieee80211_node *); 199static void ath_newassoc(struct ieee80211_node *, int); 200static int ath_setregdomain(struct ieee80211com *, 201 struct ieee80211_regdomain *, int, 202 struct ieee80211_channel []); 203static void ath_getradiocaps(struct ieee80211com *, int, int *, 204 struct ieee80211_channel []); 205static int ath_getchannels(struct ath_softc *); 206 207static int ath_rate_setup(struct ath_softc *, u_int mode); 208static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 209 210static void ath_announce(struct ath_softc *); 211 212static void ath_dfs_tasklet(void *, int); 213static void ath_node_powersave(struct ieee80211_node *, int); 214static int ath_node_set_tim(struct ieee80211_node *, int); 215 216#ifdef IEEE80211_SUPPORT_TDMA 217#include <dev/ath/if_ath_tdma.h> 218#endif 219 220SYSCTL_DECL(_hw_ath); 221 222/* XXX validate sysctl values */ 223static int ath_longcalinterval = 30; /* long cals every 30 secs */ 224SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 225 0, "long chip calibration interval (secs)"); 226static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 227SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 228 0, "short chip calibration interval (msecs)"); 229static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 230SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 231 0, "reset chip calibration results (secs)"); 232static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 233SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 234 0, "ANI calibration (msecs)"); 235 236int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 237SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 238 0, "rx buffers allocated"); 239TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 240int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 241SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 242 0, "tx buffers allocated"); 243TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 244int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */ 245SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RW, &ath_txbuf_mgmt, 246 0, "tx (mgmt) buffers allocated"); 247TUNABLE_INT("hw.ath.txbuf_mgmt", &ath_txbuf_mgmt); 248 249int ath_bstuck_threshold = 4; /* max missed beacons */ 250SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 251 0, "max missed beacon xmits before chip reset"); 252 253MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 254 255void 256ath_legacy_attach_comp_func(struct ath_softc *sc) 257{ 258 259 /* 260 * Special case certain configurations. Note the 261 * CAB queue is handled by these specially so don't 262 * include them when checking the txq setup mask. 263 */ 264 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 265 case 0x01: 266 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 267 break; 268 case 0x0f: 269 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 270 break; 271 default: 272 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 273 break; 274 } 275} 276 277#define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 278#define HAL_MODE_HT40 \ 279 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 280 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 281int 282ath_attach(u_int16_t devid, struct ath_softc *sc) 283{ 284 struct ifnet *ifp; 285 struct ieee80211com *ic; 286 struct ath_hal *ah = NULL; 287 HAL_STATUS status; 288 int error = 0, i; 289 u_int wmodes; 290 uint8_t macaddr[IEEE80211_ADDR_LEN]; 291 int rx_chainmask, tx_chainmask; 292 293 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 294 295 CURVNET_SET(vnet0); 296 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 297 if (ifp == NULL) { 298 device_printf(sc->sc_dev, "can not if_alloc()\n"); 299 error = ENOSPC; 300 CURVNET_RESTORE(); 301 goto bad; 302 } 303 ic = ifp->if_l2com; 304 305 /* set these up early for if_printf use */ 306 if_initname(ifp, device_get_name(sc->sc_dev), 307 device_get_unit(sc->sc_dev)); 308 CURVNET_RESTORE(); 309 310 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 311 sc->sc_eepromdata, &status); 312 if (ah == NULL) { 313 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 314 status); 315 error = ENXIO; 316 goto bad; 317 } 318 sc->sc_ah = ah; 319 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 320#ifdef ATH_DEBUG 321 sc->sc_debug = ath_debug; 322#endif 323 324 /* 325 * Setup the DMA/EDMA functions based on the current 326 * hardware support. 327 * 328 * This is required before the descriptors are allocated. 329 */ 330 if (ath_hal_hasedma(sc->sc_ah)) { 331 sc->sc_isedma = 1; 332 ath_recv_setup_edma(sc); 333 ath_xmit_setup_edma(sc); 334 } else { 335 ath_recv_setup_legacy(sc); 336 ath_xmit_setup_legacy(sc); 337 } 338 339 /* 340 * Check if the MAC has multi-rate retry support. 341 * We do this by trying to setup a fake extended 342 * descriptor. MAC's that don't have support will 343 * return false w/o doing anything. MAC's that do 344 * support it will return true w/o doing anything. 345 */ 346 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 347 348 /* 349 * Check if the device has hardware counters for PHY 350 * errors. If so we need to enable the MIB interrupt 351 * so we can act on stat triggers. 352 */ 353 if (ath_hal_hwphycounters(ah)) 354 sc->sc_needmib = 1; 355 356 /* 357 * Get the hardware key cache size. 358 */ 359 sc->sc_keymax = ath_hal_keycachesize(ah); 360 if (sc->sc_keymax > ATH_KEYMAX) { 361 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 362 ATH_KEYMAX, sc->sc_keymax); 363 sc->sc_keymax = ATH_KEYMAX; 364 } 365 /* 366 * Reset the key cache since some parts do not 367 * reset the contents on initial power up. 368 */ 369 for (i = 0; i < sc->sc_keymax; i++) 370 ath_hal_keyreset(ah, i); 371 372 /* 373 * Collect the default channel list. 374 */ 375 error = ath_getchannels(sc); 376 if (error != 0) 377 goto bad; 378 379 /* 380 * Setup rate tables for all potential media types. 381 */ 382 ath_rate_setup(sc, IEEE80211_MODE_11A); 383 ath_rate_setup(sc, IEEE80211_MODE_11B); 384 ath_rate_setup(sc, IEEE80211_MODE_11G); 385 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 386 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 387 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 388 ath_rate_setup(sc, IEEE80211_MODE_11NA); 389 ath_rate_setup(sc, IEEE80211_MODE_11NG); 390 ath_rate_setup(sc, IEEE80211_MODE_HALF); 391 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 392 393 /* NB: setup here so ath_rate_update is happy */ 394 ath_setcurmode(sc, IEEE80211_MODE_11A); 395 396 /* 397 * Allocate TX descriptors and populate the lists. 398 */ 399 error = ath_desc_alloc(sc); 400 if (error != 0) { 401 if_printf(ifp, "failed to allocate TX descriptors: %d\n", 402 error); 403 goto bad; 404 } 405 error = ath_txdma_setup(sc); 406 if (error != 0) { 407 if_printf(ifp, "failed to allocate TX descriptors: %d\n", 408 error); 409 goto bad; 410 } 411 412 /* 413 * Allocate RX descriptors and populate the lists. 414 */ 415 error = ath_rxdma_setup(sc); 416 if (error != 0) { 417 if_printf(ifp, "failed to allocate RX descriptors: %d\n", 418 error); 419 goto bad; 420 } 421 422 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 423 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 424 425 ATH_TXBUF_LOCK_INIT(sc); 426 427 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 428 taskqueue_thread_enqueue, &sc->sc_tq); 429 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 430 "%s taskq", ifp->if_xname); 431 432 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc); 433 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 434 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 435 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 436 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc); 437 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 438 439 /* XXX make this a higher priority taskqueue? */ 440 TASK_INIT(&sc->sc_txpkttask, 0, ath_start_task, sc); 441 442 /* 443 * Allocate hardware transmit queues: one queue for 444 * beacon frames and one data queue for each QoS 445 * priority. Note that the hal handles resetting 446 * these queues at the needed time. 447 * 448 * XXX PS-Poll 449 */ 450 sc->sc_bhalq = ath_beaconq_setup(sc); 451 if (sc->sc_bhalq == (u_int) -1) { 452 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 453 error = EIO; 454 goto bad2; 455 } 456 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 457 if (sc->sc_cabq == NULL) { 458 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 459 error = EIO; 460 goto bad2; 461 } 462 /* NB: insure BK queue is the lowest priority h/w queue */ 463 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 464 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 465 ieee80211_wme_acnames[WME_AC_BK]); 466 error = EIO; 467 goto bad2; 468 } 469 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 470 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 471 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 472 /* 473 * Not enough hardware tx queues to properly do WME; 474 * just punt and assign them all to the same h/w queue. 475 * We could do a better job of this if, for example, 476 * we allocate queues when we switch from station to 477 * AP mode. 478 */ 479 if (sc->sc_ac2q[WME_AC_VI] != NULL) 480 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 481 if (sc->sc_ac2q[WME_AC_BE] != NULL) 482 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 483 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 484 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 485 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 486 } 487 488 /* 489 * Attach the TX completion function. 490 * 491 * The non-EDMA chips may have some special case optimisations; 492 * this method gives everyone a chance to attach cleanly. 493 */ 494 sc->sc_tx.xmit_attach_comp_func(sc); 495 496 /* 497 * Setup rate control. Some rate control modules 498 * call back to change the anntena state so expose 499 * the necessary entry points. 500 * XXX maybe belongs in struct ath_ratectrl? 501 */ 502 sc->sc_setdefantenna = ath_setdefantenna; 503 sc->sc_rc = ath_rate_attach(sc); 504 if (sc->sc_rc == NULL) { 505 error = EIO; 506 goto bad2; 507 } 508 509 /* Attach DFS module */ 510 if (! ath_dfs_attach(sc)) { 511 device_printf(sc->sc_dev, 512 "%s: unable to attach DFS\n", __func__); 513 error = EIO; 514 goto bad2; 515 } 516 517 /* Attach spectral module */ 518 if (ath_spectral_attach(sc) < 0) { 519 device_printf(sc->sc_dev, 520 "%s: unable to attach spectral\n", __func__); 521 error = EIO; 522 goto bad2; 523 } 524 525 /* Start DFS processing tasklet */ 526 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 527 528 /* Configure LED state */ 529 sc->sc_blinking = 0; 530 sc->sc_ledstate = 1; 531 sc->sc_ledon = 0; /* low true */ 532 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 533 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 534 535 /* 536 * Don't setup hardware-based blinking. 537 * 538 * Although some NICs may have this configured in the 539 * default reset register values, the user may wish 540 * to alter which pins have which function. 541 * 542 * The reference driver attaches the MAC network LED to GPIO1 and 543 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 544 * NIC has these reversed. 545 */ 546 sc->sc_hardled = (1 == 0); 547 sc->sc_led_net_pin = -1; 548 sc->sc_led_pwr_pin = -1; 549 /* 550 * Auto-enable soft led processing for IBM cards and for 551 * 5211 minipci cards. Users can also manually enable/disable 552 * support with a sysctl. 553 */ 554 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 555 ath_led_config(sc); 556 ath_hal_setledstate(ah, HAL_LED_INIT); 557 558 ifp->if_softc = sc; 559 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 560 ifp->if_start = ath_start_queue; 561 ifp->if_ioctl = ath_ioctl; 562 ifp->if_init = ath_init; 563 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 564 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 565 IFQ_SET_READY(&ifp->if_snd); 566 567 ic->ic_ifp = ifp; 568 /* XXX not right but it's not used anywhere important */ 569 ic->ic_phytype = IEEE80211_T_OFDM; 570 ic->ic_opmode = IEEE80211_M_STA; 571 ic->ic_caps = 572 IEEE80211_C_STA /* station mode */ 573 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 574 | IEEE80211_C_HOSTAP /* hostap mode */ 575 | IEEE80211_C_MONITOR /* monitor mode */ 576 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 577 | IEEE80211_C_WDS /* 4-address traffic works */ 578 | IEEE80211_C_MBSS /* mesh point link mode */ 579 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 580 | IEEE80211_C_SHSLOT /* short slot time supported */ 581 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 582#ifndef ATH_ENABLE_11N 583 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 584#endif 585 | IEEE80211_C_TXFRAG /* handle tx frags */ 586#ifdef ATH_ENABLE_DFS 587 | IEEE80211_C_DFS /* Enable radar detection */ 588#endif 589 ; 590 /* 591 * Query the hal to figure out h/w crypto support. 592 */ 593 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 594 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 595 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 596 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 597 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 598 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 599 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 600 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 601 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 602 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 603 /* 604 * Check if h/w does the MIC and/or whether the 605 * separate key cache entries are required to 606 * handle both tx+rx MIC keys. 607 */ 608 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 609 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 610 /* 611 * If the h/w supports storing tx+rx MIC keys 612 * in one cache slot automatically enable use. 613 */ 614 if (ath_hal_hastkipsplit(ah) || 615 !ath_hal_settkipsplit(ah, AH_FALSE)) 616 sc->sc_splitmic = 1; 617 /* 618 * If the h/w can do TKIP MIC together with WME then 619 * we use it; otherwise we force the MIC to be done 620 * in software by the net80211 layer. 621 */ 622 if (ath_hal_haswmetkipmic(ah)) 623 sc->sc_wmetkipmic = 1; 624 } 625 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 626 /* 627 * Check for multicast key search support. 628 */ 629 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 630 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 631 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 632 } 633 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 634 /* 635 * Mark key cache slots associated with global keys 636 * as in use. If we knew TKIP was not to be used we 637 * could leave the +32, +64, and +32+64 slots free. 638 */ 639 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 640 setbit(sc->sc_keymap, i); 641 setbit(sc->sc_keymap, i+64); 642 if (sc->sc_splitmic) { 643 setbit(sc->sc_keymap, i+32); 644 setbit(sc->sc_keymap, i+32+64); 645 } 646 } 647 /* 648 * TPC support can be done either with a global cap or 649 * per-packet support. The latter is not available on 650 * all parts. We're a bit pedantic here as all parts 651 * support a global cap. 652 */ 653 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 654 ic->ic_caps |= IEEE80211_C_TXPMGT; 655 656 /* 657 * Mark WME capability only if we have sufficient 658 * hardware queues to do proper priority scheduling. 659 */ 660 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 661 ic->ic_caps |= IEEE80211_C_WME; 662 /* 663 * Check for misc other capabilities. 664 */ 665 if (ath_hal_hasbursting(ah)) 666 ic->ic_caps |= IEEE80211_C_BURST; 667 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 668 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 669 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 670 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 671 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah); 672 if (ath_hal_hasfastframes(ah)) 673 ic->ic_caps |= IEEE80211_C_FF; 674 wmodes = ath_hal_getwirelessmodes(ah); 675 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 676 ic->ic_caps |= IEEE80211_C_TURBOP; 677#ifdef IEEE80211_SUPPORT_TDMA 678 if (ath_hal_macversion(ah) > 0x78) { 679 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 680 ic->ic_tdma_update = ath_tdma_update; 681 } 682#endif 683 684 /* 685 * TODO: enforce that at least this many frames are available 686 * in the txbuf list before allowing data frames (raw or 687 * otherwise) to be transmitted. 688 */ 689 sc->sc_txq_data_minfree = 10; 690 /* 691 * Leave this as default to maintain legacy behaviour. 692 * Shortening the cabq/mcastq may end up causing some 693 * undesirable behaviour. 694 */ 695 sc->sc_txq_mcastq_maxdepth = ath_txbuf; 696 697 /* 698 * Default the maximum queue depth for a given node 699 * to 1/4'th the TX buffers, or 64, whichever 700 * is larger. 701 */ 702 sc->sc_txq_node_maxdepth = MAX(64, ath_txbuf / 4); 703 704 /* Enable CABQ by default */ 705 sc->sc_cabq_enable = 1; 706 707 /* 708 * Allow the TX and RX chainmasks to be overridden by 709 * environment variables and/or device.hints. 710 * 711 * This must be done early - before the hardware is 712 * calibrated or before the 802.11n stream calculation 713 * is done. 714 */ 715 if (resource_int_value(device_get_name(sc->sc_dev), 716 device_get_unit(sc->sc_dev), "rx_chainmask", 717 &rx_chainmask) == 0) { 718 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 719 rx_chainmask); 720 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 721 } 722 if (resource_int_value(device_get_name(sc->sc_dev), 723 device_get_unit(sc->sc_dev), "tx_chainmask", 724 &tx_chainmask) == 0) { 725 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 726 tx_chainmask); 727 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 728 } 729 730 /* 731 * Query the TX/RX chainmask configuration. 732 * 733 * This is only relevant for 11n devices. 734 */ 735 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 736 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 737 738 /* 739 * Disable MRR with protected frames by default. 740 * Only 802.11n series NICs can handle this. 741 */ 742 sc->sc_mrrprot = 0; /* XXX should be a capability */ 743 744 /* 745 * Query the enterprise mode information the HAL. 746 */ 747 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0, 748 &sc->sc_ent_cfg) == HAL_OK) 749 sc->sc_use_ent = 1; 750 751#ifdef ATH_ENABLE_11N 752 /* 753 * Query HT capabilities 754 */ 755 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 756 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 757 uint32_t rxs, txs; 758 759 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 760 761 sc->sc_mrrprot = 1; /* XXX should be a capability */ 762 763 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 764 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 765 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 766 | IEEE80211_HTCAP_MAXAMSDU_3839 767 /* max A-MSDU length */ 768 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 769 ; 770 771 /* 772 * Enable short-GI for HT20 only if the hardware 773 * advertises support. 774 * Notably, anything earlier than the AR9287 doesn't. 775 */ 776 if ((ath_hal_getcapability(ah, 777 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 778 (wmodes & HAL_MODE_HT20)) { 779 device_printf(sc->sc_dev, 780 "[HT] enabling short-GI in 20MHz mode\n"); 781 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 782 } 783 784 if (wmodes & HAL_MODE_HT40) 785 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 786 | IEEE80211_HTCAP_SHORTGI40; 787 788 /* 789 * TX/RX streams need to be taken into account when 790 * negotiating which MCS rates it'll receive and 791 * what MCS rates are available for TX. 792 */ 793 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 794 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 795 ic->ic_txstream = txs; 796 ic->ic_rxstream = rxs; 797 798 /* 799 * Setup TX and RX STBC based on what the HAL allows and 800 * the currently configured chainmask set. 801 * Ie - don't enable STBC TX if only one chain is enabled. 802 * STBC RX is fine on a single RX chain; it just won't 803 * provide any real benefit. 804 */ 805 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0, 806 NULL) == HAL_OK) { 807 sc->sc_rx_stbc = 1; 808 device_printf(sc->sc_dev, 809 "[HT] 1 stream STBC receive enabled\n"); 810 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM; 811 } 812 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0, 813 NULL) == HAL_OK) { 814 sc->sc_tx_stbc = 1; 815 device_printf(sc->sc_dev, 816 "[HT] 1 stream STBC transmit enabled\n"); 817 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 818 } 819 820 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 821 &sc->sc_rts_aggr_limit); 822 if (sc->sc_rts_aggr_limit != (64 * 1024)) 823 device_printf(sc->sc_dev, 824 "[HT] RTS aggregates limited to %d KiB\n", 825 sc->sc_rts_aggr_limit / 1024); 826 827 device_printf(sc->sc_dev, 828 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 829 } 830#endif 831 832 /* 833 * Initial aggregation settings. 834 */ 835 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; 836 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 837 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 838 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; 839 sc->sc_delim_min_pad = 0; 840 841 /* 842 * Check if the hardware requires PCI register serialisation. 843 * Some of the Owl based MACs require this. 844 */ 845 if (mp_ncpus > 1 && 846 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 847 0, NULL) == HAL_OK) { 848 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 849 device_printf(sc->sc_dev, 850 "Enabling register serialisation\n"); 851 } 852 853 /* 854 * Initialise the deferred completed RX buffer list. 855 */ 856 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]); 857 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]); 858 859 /* 860 * Indicate we need the 802.11 header padded to a 861 * 32-bit boundary for 4-address and QoS frames. 862 */ 863 ic->ic_flags |= IEEE80211_F_DATAPAD; 864 865 /* 866 * Query the hal about antenna support. 867 */ 868 sc->sc_defant = ath_hal_getdefantenna(ah); 869 870 /* 871 * Not all chips have the VEOL support we want to 872 * use with IBSS beacons; check here for it. 873 */ 874 sc->sc_hasveol = ath_hal_hasveol(ah); 875 876 /* get mac address from hardware */ 877 ath_hal_getmac(ah, macaddr); 878 if (sc->sc_hasbmask) 879 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 880 881 /* NB: used to size node table key mapping array */ 882 ic->ic_max_keyix = sc->sc_keymax; 883 /* call MI attach routine. */ 884 ieee80211_ifattach(ic, macaddr); 885 ic->ic_setregdomain = ath_setregdomain; 886 ic->ic_getradiocaps = ath_getradiocaps; 887 sc->sc_opmode = HAL_M_STA; 888 889 /* override default methods */ 890 ic->ic_newassoc = ath_newassoc; 891 ic->ic_updateslot = ath_updateslot; 892 ic->ic_wme.wme_update = ath_wme_update; 893 ic->ic_vap_create = ath_vap_create; 894 ic->ic_vap_delete = ath_vap_delete; 895 ic->ic_raw_xmit = ath_raw_xmit; 896 ic->ic_update_mcast = ath_update_mcast; 897 ic->ic_update_promisc = ath_update_promisc; 898 ic->ic_node_alloc = ath_node_alloc; 899 sc->sc_node_free = ic->ic_node_free; 900 ic->ic_node_free = ath_node_free; 901 sc->sc_node_cleanup = ic->ic_node_cleanup; 902 ic->ic_node_cleanup = ath_node_cleanup; 903 ic->ic_node_getsignal = ath_node_getsignal; 904 ic->ic_scan_start = ath_scan_start; 905 ic->ic_scan_end = ath_scan_end; 906 ic->ic_set_channel = ath_set_channel; 907#ifdef ATH_ENABLE_11N 908 /* 802.11n specific - but just override anyway */ 909 sc->sc_addba_request = ic->ic_addba_request; 910 sc->sc_addba_response = ic->ic_addba_response; 911 sc->sc_addba_stop = ic->ic_addba_stop; 912 sc->sc_bar_response = ic->ic_bar_response; 913 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 914 915 ic->ic_addba_request = ath_addba_request; 916 ic->ic_addba_response = ath_addba_response; 917 ic->ic_addba_response_timeout = ath_addba_response_timeout; 918 ic->ic_addba_stop = ath_addba_stop; 919 ic->ic_bar_response = ath_bar_response; 920 921 ic->ic_update_chw = ath_update_chw; 922#endif /* ATH_ENABLE_11N */ 923 924#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 925 /* 926 * There's one vendor bitmap entry in the RX radiotap 927 * header; make sure that's taken into account. 928 */ 929 ieee80211_radiotap_attachv(ic, 930 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0, 931 ATH_TX_RADIOTAP_PRESENT, 932 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1, 933 ATH_RX_RADIOTAP_PRESENT); 934#else 935 /* 936 * No vendor bitmap/extensions are present. 937 */ 938 ieee80211_radiotap_attach(ic, 939 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 940 ATH_TX_RADIOTAP_PRESENT, 941 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 942 ATH_RX_RADIOTAP_PRESENT); 943#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 944 945 /* 946 * Setup the ALQ logging if required 947 */ 948#ifdef ATH_DEBUG_ALQ 949 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev)); 950 if_ath_alq_setcfg(&sc->sc_alq, 951 sc->sc_ah->ah_macVersion, 952 sc->sc_ah->ah_macRev, 953 sc->sc_ah->ah_phyRev, 954 sc->sc_ah->ah_magic); 955#endif 956 957 /* 958 * Setup dynamic sysctl's now that country code and 959 * regdomain are available from the hal. 960 */ 961 ath_sysctlattach(sc); 962 ath_sysctl_stats_attach(sc); 963 ath_sysctl_hal_attach(sc); 964 965 if (bootverbose) 966 ieee80211_announce(ic); 967 ath_announce(sc); 968 return 0; 969bad2: 970 ath_tx_cleanup(sc); 971 ath_desc_free(sc); 972 ath_txdma_teardown(sc); 973 ath_rxdma_teardown(sc); 974bad: 975 if (ah) 976 ath_hal_detach(ah); 977 978 /* 979 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE.. 980 */ 981 if (ifp != NULL && ifp->if_vnet) { 982 CURVNET_SET(ifp->if_vnet); 983 if_free(ifp); 984 CURVNET_RESTORE(); 985 } else if (ifp != NULL) 986 if_free(ifp); 987 sc->sc_invalid = 1; 988 return error; 989} 990 991int 992ath_detach(struct ath_softc *sc) 993{ 994 struct ifnet *ifp = sc->sc_ifp; 995 996 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 997 __func__, ifp->if_flags); 998 999 /* 1000 * NB: the order of these is important: 1001 * o stop the chip so no more interrupts will fire 1002 * o call the 802.11 layer before detaching the hal to 1003 * insure callbacks into the driver to delete global 1004 * key cache entries can be handled 1005 * o free the taskqueue which drains any pending tasks 1006 * o reclaim the tx queue data structures after calling 1007 * the 802.11 layer as we'll get called back to reclaim 1008 * node state and potentially want to use them 1009 * o to cleanup the tx queues the hal is called, so detach 1010 * it last 1011 * Other than that, it's straightforward... 1012 */ 1013 ath_stop(ifp); 1014 ieee80211_ifdetach(ifp->if_l2com); 1015 taskqueue_free(sc->sc_tq); 1016#ifdef ATH_TX99_DIAG 1017 if (sc->sc_tx99 != NULL) 1018 sc->sc_tx99->detach(sc->sc_tx99); 1019#endif 1020 ath_rate_detach(sc->sc_rc); 1021#ifdef ATH_DEBUG_ALQ 1022 if_ath_alq_tidyup(&sc->sc_alq); 1023#endif 1024 ath_spectral_detach(sc); 1025 ath_dfs_detach(sc); 1026 ath_desc_free(sc); 1027 ath_txdma_teardown(sc); 1028 ath_rxdma_teardown(sc); 1029 ath_tx_cleanup(sc); 1030 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 1031 1032 CURVNET_SET(ifp->if_vnet); 1033 if_free(ifp); 1034 CURVNET_RESTORE(); 1035 1036 return 0; 1037} 1038 1039/* 1040 * MAC address handling for multiple BSS on the same radio. 1041 * The first vap uses the MAC address from the EEPROM. For 1042 * subsequent vap's we set the U/L bit (bit 1) in the MAC 1043 * address and use the next six bits as an index. 1044 */ 1045static void 1046assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 1047{ 1048 int i; 1049 1050 if (clone && sc->sc_hasbmask) { 1051 /* NB: we only do this if h/w supports multiple bssid */ 1052 for (i = 0; i < 8; i++) 1053 if ((sc->sc_bssidmask & (1<<i)) == 0) 1054 break; 1055 if (i != 0) 1056 mac[0] |= (i << 2)|0x2; 1057 } else 1058 i = 0; 1059 sc->sc_bssidmask |= 1<<i; 1060 sc->sc_hwbssidmask[0] &= ~mac[0]; 1061 if (i == 0) 1062 sc->sc_nbssid0++; 1063} 1064 1065static void 1066reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 1067{ 1068 int i = mac[0] >> 2; 1069 uint8_t mask; 1070 1071 if (i != 0 || --sc->sc_nbssid0 == 0) { 1072 sc->sc_bssidmask &= ~(1<<i); 1073 /* recalculate bssid mask from remaining addresses */ 1074 mask = 0xff; 1075 for (i = 1; i < 8; i++) 1076 if (sc->sc_bssidmask & (1<<i)) 1077 mask &= ~((i<<2)|0x2); 1078 sc->sc_hwbssidmask[0] |= mask; 1079 } 1080} 1081 1082/* 1083 * Assign a beacon xmit slot. We try to space out 1084 * assignments so when beacons are staggered the 1085 * traffic coming out of the cab q has maximal time 1086 * to go out before the next beacon is scheduled. 1087 */ 1088static int 1089assign_bslot(struct ath_softc *sc) 1090{ 1091 u_int slot, free; 1092 1093 free = 0; 1094 for (slot = 0; slot < ATH_BCBUF; slot++) 1095 if (sc->sc_bslot[slot] == NULL) { 1096 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 1097 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 1098 return slot; 1099 free = slot; 1100 /* NB: keep looking for a double slot */ 1101 } 1102 return free; 1103} 1104 1105static struct ieee80211vap * 1106ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1107 enum ieee80211_opmode opmode, int flags, 1108 const uint8_t bssid[IEEE80211_ADDR_LEN], 1109 const uint8_t mac0[IEEE80211_ADDR_LEN]) 1110{ 1111 struct ath_softc *sc = ic->ic_ifp->if_softc; 1112 struct ath_vap *avp; 1113 struct ieee80211vap *vap; 1114 uint8_t mac[IEEE80211_ADDR_LEN]; 1115 int needbeacon, error; 1116 enum ieee80211_opmode ic_opmode; 1117 1118 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 1119 M_80211_VAP, M_WAITOK | M_ZERO); 1120 needbeacon = 0; 1121 IEEE80211_ADDR_COPY(mac, mac0); 1122 1123 ATH_LOCK(sc); 1124 ic_opmode = opmode; /* default to opmode of new vap */ 1125 switch (opmode) { 1126 case IEEE80211_M_STA: 1127 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 1128 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 1129 goto bad; 1130 } 1131 if (sc->sc_nvaps) { 1132 /* 1133 * With multiple vaps we must fall back 1134 * to s/w beacon miss handling. 1135 */ 1136 flags |= IEEE80211_CLONE_NOBEACONS; 1137 } 1138 if (flags & IEEE80211_CLONE_NOBEACONS) { 1139 /* 1140 * Station mode w/o beacons are implemented w/ AP mode. 1141 */ 1142 ic_opmode = IEEE80211_M_HOSTAP; 1143 } 1144 break; 1145 case IEEE80211_M_IBSS: 1146 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 1147 device_printf(sc->sc_dev, 1148 "only 1 ibss vap supported\n"); 1149 goto bad; 1150 } 1151 needbeacon = 1; 1152 break; 1153 case IEEE80211_M_AHDEMO: 1154#ifdef IEEE80211_SUPPORT_TDMA 1155 if (flags & IEEE80211_CLONE_TDMA) { 1156 if (sc->sc_nvaps != 0) { 1157 device_printf(sc->sc_dev, 1158 "only 1 tdma vap supported\n"); 1159 goto bad; 1160 } 1161 needbeacon = 1; 1162 flags |= IEEE80211_CLONE_NOBEACONS; 1163 } 1164 /* fall thru... */ 1165#endif 1166 case IEEE80211_M_MONITOR: 1167 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1168 /* 1169 * Adopt existing mode. Adding a monitor or ahdemo 1170 * vap to an existing configuration is of dubious 1171 * value but should be ok. 1172 */ 1173 /* XXX not right for monitor mode */ 1174 ic_opmode = ic->ic_opmode; 1175 } 1176 break; 1177 case IEEE80211_M_HOSTAP: 1178 case IEEE80211_M_MBSS: 1179 needbeacon = 1; 1180 break; 1181 case IEEE80211_M_WDS: 1182 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1183 device_printf(sc->sc_dev, 1184 "wds not supported in sta mode\n"); 1185 goto bad; 1186 } 1187 /* 1188 * Silently remove any request for a unique 1189 * bssid; WDS vap's always share the local 1190 * mac address. 1191 */ 1192 flags &= ~IEEE80211_CLONE_BSSID; 1193 if (sc->sc_nvaps == 0) 1194 ic_opmode = IEEE80211_M_HOSTAP; 1195 else 1196 ic_opmode = ic->ic_opmode; 1197 break; 1198 default: 1199 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1200 goto bad; 1201 } 1202 /* 1203 * Check that a beacon buffer is available; the code below assumes it. 1204 */ 1205 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1206 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1207 goto bad; 1208 } 1209 1210 /* STA, AHDEMO? */ 1211 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 1212 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1213 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1214 } 1215 1216 vap = &avp->av_vap; 1217 /* XXX can't hold mutex across if_alloc */ 1218 ATH_UNLOCK(sc); 1219 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 1220 bssid, mac); 1221 ATH_LOCK(sc); 1222 if (error != 0) { 1223 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1224 __func__, error); 1225 goto bad2; 1226 } 1227 1228 /* h/w crypto support */ 1229 vap->iv_key_alloc = ath_key_alloc; 1230 vap->iv_key_delete = ath_key_delete; 1231 vap->iv_key_set = ath_key_set; 1232 vap->iv_key_update_begin = ath_key_update_begin; 1233 vap->iv_key_update_end = ath_key_update_end; 1234 1235 /* override various methods */ 1236 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1237 vap->iv_recv_mgmt = ath_recv_mgmt; 1238 vap->iv_reset = ath_reset_vap; 1239 vap->iv_update_beacon = ath_beacon_update; 1240 avp->av_newstate = vap->iv_newstate; 1241 vap->iv_newstate = ath_newstate; 1242 avp->av_bmiss = vap->iv_bmiss; 1243 vap->iv_bmiss = ath_bmiss_vap; 1244 1245 avp->av_node_ps = vap->iv_node_ps; 1246 vap->iv_node_ps = ath_node_powersave; 1247 1248 avp->av_set_tim = vap->iv_set_tim; 1249 vap->iv_set_tim = ath_node_set_tim; 1250 1251 /* Set default parameters */ 1252 1253 /* 1254 * Anything earlier than some AR9300 series MACs don't 1255 * support a smaller MPDU density. 1256 */ 1257 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1258 /* 1259 * All NICs can handle the maximum size, however 1260 * AR5416 based MACs can only TX aggregates w/ RTS 1261 * protection when the total aggregate size is <= 8k. 1262 * However, for now that's enforced by the TX path. 1263 */ 1264 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1265 1266 avp->av_bslot = -1; 1267 if (needbeacon) { 1268 /* 1269 * Allocate beacon state and setup the q for buffered 1270 * multicast frames. We know a beacon buffer is 1271 * available because we checked above. 1272 */ 1273 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1274 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1275 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1276 /* 1277 * Assign the vap to a beacon xmit slot. As above 1278 * this cannot fail to find a free one. 1279 */ 1280 avp->av_bslot = assign_bslot(sc); 1281 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1282 ("beacon slot %u not empty", avp->av_bslot)); 1283 sc->sc_bslot[avp->av_bslot] = vap; 1284 sc->sc_nbcnvaps++; 1285 } 1286 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1287 /* 1288 * Multple vaps are to transmit beacons and we 1289 * have h/w support for TSF adjusting; enable 1290 * use of staggered beacons. 1291 */ 1292 sc->sc_stagbeacons = 1; 1293 } 1294 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1295 } 1296 1297 ic->ic_opmode = ic_opmode; 1298 if (opmode != IEEE80211_M_WDS) { 1299 sc->sc_nvaps++; 1300 if (opmode == IEEE80211_M_STA) 1301 sc->sc_nstavaps++; 1302 if (opmode == IEEE80211_M_MBSS) 1303 sc->sc_nmeshvaps++; 1304 } 1305 switch (ic_opmode) { 1306 case IEEE80211_M_IBSS: 1307 sc->sc_opmode = HAL_M_IBSS; 1308 break; 1309 case IEEE80211_M_STA: 1310 sc->sc_opmode = HAL_M_STA; 1311 break; 1312 case IEEE80211_M_AHDEMO: 1313#ifdef IEEE80211_SUPPORT_TDMA 1314 if (vap->iv_caps & IEEE80211_C_TDMA) { 1315 sc->sc_tdma = 1; 1316 /* NB: disable tsf adjust */ 1317 sc->sc_stagbeacons = 0; 1318 } 1319 /* 1320 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1321 * just ap mode. 1322 */ 1323 /* fall thru... */ 1324#endif 1325 case IEEE80211_M_HOSTAP: 1326 case IEEE80211_M_MBSS: 1327 sc->sc_opmode = HAL_M_HOSTAP; 1328 break; 1329 case IEEE80211_M_MONITOR: 1330 sc->sc_opmode = HAL_M_MONITOR; 1331 break; 1332 default: 1333 /* XXX should not happen */ 1334 break; 1335 } 1336 if (sc->sc_hastsfadd) { 1337 /* 1338 * Configure whether or not TSF adjust should be done. 1339 */ 1340 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1341 } 1342 if (flags & IEEE80211_CLONE_NOBEACONS) { 1343 /* 1344 * Enable s/w beacon miss handling. 1345 */ 1346 sc->sc_swbmiss = 1; 1347 } 1348 ATH_UNLOCK(sc); 1349 1350 /* complete setup */ 1351 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1352 return vap; 1353bad2: 1354 reclaim_address(sc, mac); 1355 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1356bad: 1357 free(avp, M_80211_VAP); 1358 ATH_UNLOCK(sc); 1359 return NULL; 1360} 1361 1362static void 1363ath_vap_delete(struct ieee80211vap *vap) 1364{ 1365 struct ieee80211com *ic = vap->iv_ic; 1366 struct ifnet *ifp = ic->ic_ifp; 1367 struct ath_softc *sc = ifp->if_softc; 1368 struct ath_hal *ah = sc->sc_ah; 1369 struct ath_vap *avp = ATH_VAP(vap); 1370 1371 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1372 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1373 /* 1374 * Quiesce the hardware while we remove the vap. In 1375 * particular we need to reclaim all references to 1376 * the vap state by any frames pending on the tx queues. 1377 */ 1378 ath_hal_intrset(ah, 0); /* disable interrupts */ 1379 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1380 /* XXX Do all frames from all vaps/nodes need draining here? */ 1381 ath_stoprecv(sc, 1); /* stop recv side */ 1382 } 1383 1384 ieee80211_vap_detach(vap); 1385 1386 /* 1387 * XXX Danger Will Robinson! Danger! 1388 * 1389 * Because ieee80211_vap_detach() can queue a frame (the station 1390 * diassociate message?) after we've drained the TXQ and 1391 * flushed the software TXQ, we will end up with a frame queued 1392 * to a node whose vap is about to be freed. 1393 * 1394 * To work around this, flush the hardware/software again. 1395 * This may be racy - the ath task may be running and the packet 1396 * may be being scheduled between sw->hw txq. Tsk. 1397 * 1398 * TODO: figure out why a new node gets allocated somewhere around 1399 * here (after the ath_tx_swq() call; and after an ath_stop_locked() 1400 * call!) 1401 */ 1402 1403 ath_draintxq(sc, ATH_RESET_DEFAULT); 1404 1405 ATH_LOCK(sc); 1406 /* 1407 * Reclaim beacon state. Note this must be done before 1408 * the vap instance is reclaimed as we may have a reference 1409 * to it in the buffer for the beacon frame. 1410 */ 1411 if (avp->av_bcbuf != NULL) { 1412 if (avp->av_bslot != -1) { 1413 sc->sc_bslot[avp->av_bslot] = NULL; 1414 sc->sc_nbcnvaps--; 1415 } 1416 ath_beacon_return(sc, avp->av_bcbuf); 1417 avp->av_bcbuf = NULL; 1418 if (sc->sc_nbcnvaps == 0) { 1419 sc->sc_stagbeacons = 0; 1420 if (sc->sc_hastsfadd) 1421 ath_hal_settsfadjust(sc->sc_ah, 0); 1422 } 1423 /* 1424 * Reclaim any pending mcast frames for the vap. 1425 */ 1426 ath_tx_draintxq(sc, &avp->av_mcastq); 1427 } 1428 /* 1429 * Update bookkeeping. 1430 */ 1431 if (vap->iv_opmode == IEEE80211_M_STA) { 1432 sc->sc_nstavaps--; 1433 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1434 sc->sc_swbmiss = 0; 1435 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1436 vap->iv_opmode == IEEE80211_M_MBSS) { 1437 reclaim_address(sc, vap->iv_myaddr); 1438 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1439 if (vap->iv_opmode == IEEE80211_M_MBSS) 1440 sc->sc_nmeshvaps--; 1441 } 1442 if (vap->iv_opmode != IEEE80211_M_WDS) 1443 sc->sc_nvaps--; 1444#ifdef IEEE80211_SUPPORT_TDMA 1445 /* TDMA operation ceases when the last vap is destroyed */ 1446 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1447 sc->sc_tdma = 0; 1448 sc->sc_swbmiss = 0; 1449 } 1450#endif 1451 free(avp, M_80211_VAP); 1452 1453 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1454 /* 1455 * Restart rx+tx machines if still running (RUNNING will 1456 * be reset if we just destroyed the last vap). 1457 */ 1458 if (ath_startrecv(sc) != 0) 1459 if_printf(ifp, "%s: unable to restart recv logic\n", 1460 __func__); 1461 if (sc->sc_beacons) { /* restart beacons */ 1462#ifdef IEEE80211_SUPPORT_TDMA 1463 if (sc->sc_tdma) 1464 ath_tdma_config(sc, NULL); 1465 else 1466#endif 1467 ath_beacon_config(sc, NULL); 1468 } 1469 ath_hal_intrset(ah, sc->sc_imask); 1470 } 1471 ATH_UNLOCK(sc); 1472} 1473 1474void 1475ath_suspend(struct ath_softc *sc) 1476{ 1477 struct ifnet *ifp = sc->sc_ifp; 1478 struct ieee80211com *ic = ifp->if_l2com; 1479 1480 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1481 __func__, ifp->if_flags); 1482 1483 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1484 1485 ieee80211_suspend_all(ic); 1486 /* 1487 * NB: don't worry about putting the chip in low power 1488 * mode; pci will power off our socket on suspend and 1489 * CardBus detaches the device. 1490 */ 1491 1492 /* 1493 * XXX ensure none of the taskqueues are running 1494 * XXX ensure sc_invalid is 1 1495 * XXX ensure the calibration callout is disabled 1496 */ 1497 1498 /* Disable the PCIe PHY, complete with workarounds */ 1499 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1500} 1501 1502/* 1503 * Reset the key cache since some parts do not reset the 1504 * contents on resume. First we clear all entries, then 1505 * re-load keys that the 802.11 layer assumes are setup 1506 * in h/w. 1507 */ 1508static void 1509ath_reset_keycache(struct ath_softc *sc) 1510{ 1511 struct ifnet *ifp = sc->sc_ifp; 1512 struct ieee80211com *ic = ifp->if_l2com; 1513 struct ath_hal *ah = sc->sc_ah; 1514 int i; 1515 1516 for (i = 0; i < sc->sc_keymax; i++) 1517 ath_hal_keyreset(ah, i); 1518 ieee80211_crypto_reload_keys(ic); 1519} 1520 1521/* 1522 * Fetch the current chainmask configuration based on the current 1523 * operating channel and options. 1524 */ 1525static void 1526ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan) 1527{ 1528 1529 /* 1530 * Set TX chainmask to the currently configured chainmask; 1531 * the TX chainmask depends upon the current operating mode. 1532 */ 1533 sc->sc_cur_rxchainmask = sc->sc_rxchainmask; 1534 if (IEEE80211_IS_CHAN_HT(chan)) { 1535 sc->sc_cur_txchainmask = sc->sc_txchainmask; 1536 } else { 1537 sc->sc_cur_txchainmask = 1; 1538 } 1539 1540 DPRINTF(sc, ATH_DEBUG_RESET, 1541 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n", 1542 __func__, 1543 sc->sc_cur_txchainmask, 1544 sc->sc_cur_rxchainmask); 1545} 1546 1547void 1548ath_resume(struct ath_softc *sc) 1549{ 1550 struct ifnet *ifp = sc->sc_ifp; 1551 struct ieee80211com *ic = ifp->if_l2com; 1552 struct ath_hal *ah = sc->sc_ah; 1553 HAL_STATUS status; 1554 1555 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1556 __func__, ifp->if_flags); 1557 1558 /* Re-enable PCIe, re-enable the PCIe bus */ 1559 ath_hal_enablepcie(ah, 0, 0); 1560 1561 /* 1562 * Must reset the chip before we reload the 1563 * keycache as we were powered down on suspend. 1564 */ 1565 ath_update_chainmasks(sc, 1566 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan); 1567 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 1568 sc->sc_cur_rxchainmask); 1569 ath_hal_reset(ah, sc->sc_opmode, 1570 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1571 AH_FALSE, &status); 1572 ath_reset_keycache(sc); 1573 1574 /* Let DFS at it in case it's a DFS channel */ 1575 ath_dfs_radar_enable(sc, ic->ic_curchan); 1576 1577 /* Let spectral at in case spectral is enabled */ 1578 ath_spectral_enable(sc, ic->ic_curchan); 1579 1580 /* Restore the LED configuration */ 1581 ath_led_config(sc); 1582 ath_hal_setledstate(ah, HAL_LED_INIT); 1583 1584 if (sc->sc_resume_up) 1585 ieee80211_resume_all(ic); 1586 1587 /* XXX beacons ? */ 1588} 1589 1590void 1591ath_shutdown(struct ath_softc *sc) 1592{ 1593 struct ifnet *ifp = sc->sc_ifp; 1594 1595 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1596 __func__, ifp->if_flags); 1597 1598 ath_stop(ifp); 1599 /* NB: no point powering down chip as we're about to reboot */ 1600} 1601 1602/* 1603 * Interrupt handler. Most of the actual processing is deferred. 1604 */ 1605void 1606ath_intr(void *arg) 1607{ 1608 struct ath_softc *sc = arg; 1609 struct ifnet *ifp = sc->sc_ifp; 1610 struct ath_hal *ah = sc->sc_ah; 1611 HAL_INT status = 0; 1612 uint32_t txqs; 1613 1614 /* 1615 * If we're inside a reset path, just print a warning and 1616 * clear the ISR. The reset routine will finish it for us. 1617 */ 1618 ATH_PCU_LOCK(sc); 1619 if (sc->sc_inreset_cnt) { 1620 HAL_INT status; 1621 ath_hal_getisr(ah, &status); /* clear ISR */ 1622 ath_hal_intrset(ah, 0); /* disable further intr's */ 1623 DPRINTF(sc, ATH_DEBUG_ANY, 1624 "%s: in reset, ignoring: status=0x%x\n", 1625 __func__, status); 1626 ATH_PCU_UNLOCK(sc); 1627 return; 1628 } 1629 1630 if (sc->sc_invalid) { 1631 /* 1632 * The hardware is not ready/present, don't touch anything. 1633 * Note this can happen early on if the IRQ is shared. 1634 */ 1635 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1636 ATH_PCU_UNLOCK(sc); 1637 return; 1638 } 1639 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 1640 ATH_PCU_UNLOCK(sc); 1641 return; 1642 } 1643 1644 if ((ifp->if_flags & IFF_UP) == 0 || 1645 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1646 HAL_INT status; 1647 1648 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1649 __func__, ifp->if_flags); 1650 ath_hal_getisr(ah, &status); /* clear ISR */ 1651 ath_hal_intrset(ah, 0); /* disable further intr's */ 1652 ATH_PCU_UNLOCK(sc); 1653 return; 1654 } 1655 1656 /* 1657 * Figure out the reason(s) for the interrupt. Note 1658 * that the hal returns a pseudo-ISR that may include 1659 * bits we haven't explicitly enabled so we mask the 1660 * value to insure we only process bits we requested. 1661 */ 1662 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1663 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1664 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); 1665#ifdef ATH_DEBUG_ALQ 1666 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate, 1667 ah->ah_syncstate); 1668#endif /* ATH_DEBUG_ALQ */ 1669#ifdef ATH_KTR_INTR_DEBUG 1670 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, 1671 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 1672 ah->ah_intrstate[0], 1673 ah->ah_intrstate[1], 1674 ah->ah_intrstate[2], 1675 ah->ah_intrstate[3], 1676 ah->ah_intrstate[6]); 1677#endif 1678 1679 /* Squirrel away SYNC interrupt debugging */ 1680 if (ah->ah_syncstate != 0) { 1681 int i; 1682 for (i = 0; i < 32; i++) 1683 if (ah->ah_syncstate & (i << i)) 1684 sc->sc_intr_stats.sync_intr[i]++; 1685 } 1686 1687 status &= sc->sc_imask; /* discard unasked for bits */ 1688 1689 /* Short-circuit un-handled interrupts */ 1690 if (status == 0x0) { 1691 ATH_PCU_UNLOCK(sc); 1692 return; 1693 } 1694 1695 /* 1696 * Take a note that we're inside the interrupt handler, so 1697 * the reset routines know to wait. 1698 */ 1699 sc->sc_intr_cnt++; 1700 ATH_PCU_UNLOCK(sc); 1701 1702 /* 1703 * Handle the interrupt. We won't run concurrent with the reset 1704 * or channel change routines as they'll wait for sc_intr_cnt 1705 * to be 0 before continuing. 1706 */ 1707 if (status & HAL_INT_FATAL) { 1708 sc->sc_stats.ast_hardware++; 1709 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1710 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 1711 } else { 1712 if (status & HAL_INT_SWBA) { 1713 /* 1714 * Software beacon alert--time to send a beacon. 1715 * Handle beacon transmission directly; deferring 1716 * this is too slow to meet timing constraints 1717 * under load. 1718 */ 1719#ifdef IEEE80211_SUPPORT_TDMA 1720 if (sc->sc_tdma) { 1721 if (sc->sc_tdmaswba == 0) { 1722 struct ieee80211com *ic = ifp->if_l2com; 1723 struct ieee80211vap *vap = 1724 TAILQ_FIRST(&ic->ic_vaps); 1725 ath_tdma_beacon_send(sc, vap); 1726 sc->sc_tdmaswba = 1727 vap->iv_tdma->tdma_bintval; 1728 } else 1729 sc->sc_tdmaswba--; 1730 } else 1731#endif 1732 { 1733 ath_beacon_proc(sc, 0); 1734#ifdef IEEE80211_SUPPORT_SUPERG 1735 /* 1736 * Schedule the rx taskq in case there's no 1737 * traffic so any frames held on the staging 1738 * queue are aged and potentially flushed. 1739 */ 1740 sc->sc_rx.recv_sched(sc, 1); 1741#endif 1742 } 1743 } 1744 if (status & HAL_INT_RXEOL) { 1745 int imask; 1746 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL"); 1747 ATH_PCU_LOCK(sc); 1748 /* 1749 * NB: the hardware should re-read the link when 1750 * RXE bit is written, but it doesn't work at 1751 * least on older hardware revs. 1752 */ 1753 sc->sc_stats.ast_rxeol++; 1754 /* 1755 * Disable RXEOL/RXORN - prevent an interrupt 1756 * storm until the PCU logic can be reset. 1757 * In case the interface is reset some other 1758 * way before "sc_kickpcu" is called, don't 1759 * modify sc_imask - that way if it is reset 1760 * by a call to ath_reset() somehow, the 1761 * interrupt mask will be correctly reprogrammed. 1762 */ 1763 imask = sc->sc_imask; 1764 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 1765 ath_hal_intrset(ah, imask); 1766 /* 1767 * Only blank sc_rxlink if we've not yet kicked 1768 * the PCU. 1769 * 1770 * This isn't entirely correct - the correct solution 1771 * would be to have a PCU lock and engage that for 1772 * the duration of the PCU fiddling; which would include 1773 * running the RX process. Otherwise we could end up 1774 * messing up the RX descriptor chain and making the 1775 * RX desc list much shorter. 1776 */ 1777 if (! sc->sc_kickpcu) 1778 sc->sc_rxlink = NULL; 1779 sc->sc_kickpcu = 1; 1780 ATH_PCU_UNLOCK(sc); 1781 /* 1782 * Enqueue an RX proc, to handled whatever 1783 * is in the RX queue. 1784 * This will then kick the PCU. 1785 */ 1786 sc->sc_rx.recv_sched(sc, 1); 1787 } 1788 if (status & HAL_INT_TXURN) { 1789 sc->sc_stats.ast_txurn++; 1790 /* bump tx trigger level */ 1791 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1792 } 1793 /* 1794 * Handle both the legacy and RX EDMA interrupt bits. 1795 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC. 1796 */ 1797 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) { 1798 sc->sc_stats.ast_rx_intr++; 1799 sc->sc_rx.recv_sched(sc, 1); 1800 } 1801 if (status & HAL_INT_TX) { 1802 sc->sc_stats.ast_tx_intr++; 1803 /* 1804 * Grab all the currently set bits in the HAL txq bitmap 1805 * and blank them. This is the only place we should be 1806 * doing this. 1807 */ 1808 if (! sc->sc_isedma) { 1809 ATH_PCU_LOCK(sc); 1810 txqs = 0xffffffff; 1811 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 1812 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3, 1813 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x", 1814 txqs, 1815 sc->sc_txq_active, 1816 sc->sc_txq_active | txqs); 1817 sc->sc_txq_active |= txqs; 1818 ATH_PCU_UNLOCK(sc); 1819 } 1820 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1821 } 1822 if (status & HAL_INT_BMISS) { 1823 sc->sc_stats.ast_bmiss++; 1824 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1825 } 1826 if (status & HAL_INT_GTT) 1827 sc->sc_stats.ast_tx_timeout++; 1828 if (status & HAL_INT_CST) 1829 sc->sc_stats.ast_tx_cst++; 1830 if (status & HAL_INT_MIB) { 1831 sc->sc_stats.ast_mib++; 1832 ATH_PCU_LOCK(sc); 1833 /* 1834 * Disable interrupts until we service the MIB 1835 * interrupt; otherwise it will continue to fire. 1836 */ 1837 ath_hal_intrset(ah, 0); 1838 /* 1839 * Let the hal handle the event. We assume it will 1840 * clear whatever condition caused the interrupt. 1841 */ 1842 ath_hal_mibevent(ah, &sc->sc_halstats); 1843 /* 1844 * Don't reset the interrupt if we've just 1845 * kicked the PCU, or we may get a nested 1846 * RXEOL before the rxproc has had a chance 1847 * to run. 1848 */ 1849 if (sc->sc_kickpcu == 0) 1850 ath_hal_intrset(ah, sc->sc_imask); 1851 ATH_PCU_UNLOCK(sc); 1852 } 1853 if (status & HAL_INT_RXORN) { 1854 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1855 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN"); 1856 sc->sc_stats.ast_rxorn++; 1857 } 1858 } 1859 ATH_PCU_LOCK(sc); 1860 sc->sc_intr_cnt--; 1861 ATH_PCU_UNLOCK(sc); 1862} 1863 1864static void 1865ath_fatal_proc(void *arg, int pending) 1866{ 1867 struct ath_softc *sc = arg; 1868 struct ifnet *ifp = sc->sc_ifp; 1869 u_int32_t *state; 1870 u_int32_t len; 1871 void *sp; 1872 1873 if_printf(ifp, "hardware error; resetting\n"); 1874 /* 1875 * Fatal errors are unrecoverable. Typically these 1876 * are caused by DMA errors. Collect h/w state from 1877 * the hal so we can diagnose what's going on. 1878 */ 1879 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1880 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1881 state = sp; 1882 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1883 state[0], state[1] , state[2], state[3], 1884 state[4], state[5]); 1885 } 1886 ath_reset(ifp, ATH_RESET_NOLOSS); 1887} 1888 1889static void 1890ath_bmiss_vap(struct ieee80211vap *vap) 1891{ 1892 /* 1893 * Workaround phantom bmiss interrupts by sanity-checking 1894 * the time of our last rx'd frame. If it is within the 1895 * beacon miss interval then ignore the interrupt. If it's 1896 * truly a bmiss we'll get another interrupt soon and that'll 1897 * be dispatched up for processing. Note this applies only 1898 * for h/w beacon miss events. 1899 */ 1900 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1901 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1902 struct ath_softc *sc = ifp->if_softc; 1903 u_int64_t lastrx = sc->sc_lastrx; 1904 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1905 /* XXX should take a locked ref to iv_bss */ 1906 u_int bmisstimeout = 1907 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1908 1909 DPRINTF(sc, ATH_DEBUG_BEACON, 1910 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1911 __func__, (unsigned long long) tsf, 1912 (unsigned long long)(tsf - lastrx), 1913 (unsigned long long) lastrx, bmisstimeout); 1914 1915 if (tsf - lastrx <= bmisstimeout) { 1916 sc->sc_stats.ast_bmiss_phantom++; 1917 return; 1918 } 1919 } 1920 ATH_VAP(vap)->av_bmiss(vap); 1921} 1922 1923int 1924ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1925{ 1926 uint32_t rsize; 1927 void *sp; 1928 1929 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 1930 return 0; 1931 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1932 *hangs = *(uint32_t *)sp; 1933 return 1; 1934} 1935 1936static void 1937ath_bmiss_proc(void *arg, int pending) 1938{ 1939 struct ath_softc *sc = arg; 1940 struct ifnet *ifp = sc->sc_ifp; 1941 uint32_t hangs; 1942 1943 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1944 1945 /* 1946 * Do a reset upon any becaon miss event. 1947 * 1948 * It may be a non-recognised RX clear hang which needs a reset 1949 * to clear. 1950 */ 1951 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1952 ath_reset(ifp, ATH_RESET_NOLOSS); 1953 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs); 1954 } else { 1955 ath_reset(ifp, ATH_RESET_NOLOSS); 1956 ieee80211_beacon_miss(ifp->if_l2com); 1957 } 1958} 1959 1960/* 1961 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1962 * calcs together with WME. If necessary disable the crypto 1963 * hardware and mark the 802.11 state so keys will be setup 1964 * with the MIC work done in software. 1965 */ 1966static void 1967ath_settkipmic(struct ath_softc *sc) 1968{ 1969 struct ifnet *ifp = sc->sc_ifp; 1970 struct ieee80211com *ic = ifp->if_l2com; 1971 1972 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1973 if (ic->ic_flags & IEEE80211_F_WME) { 1974 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1975 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1976 } else { 1977 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1978 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1979 } 1980 } 1981} 1982 1983static void 1984ath_init(void *arg) 1985{ 1986 struct ath_softc *sc = (struct ath_softc *) arg; 1987 struct ifnet *ifp = sc->sc_ifp; 1988 struct ieee80211com *ic = ifp->if_l2com; 1989 struct ath_hal *ah = sc->sc_ah; 1990 HAL_STATUS status; 1991 1992 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1993 __func__, ifp->if_flags); 1994 1995 ATH_LOCK(sc); 1996 /* 1997 * Stop anything previously setup. This is safe 1998 * whether this is the first time through or not. 1999 */ 2000 ath_stop_locked(ifp); 2001 2002 /* 2003 * The basic interface to setting the hardware in a good 2004 * state is ``reset''. On return the hardware is known to 2005 * be powered up and with interrupts disabled. This must 2006 * be followed by initialization of the appropriate bits 2007 * and then setup of the interrupt mask. 2008 */ 2009 ath_settkipmic(sc); 2010 ath_update_chainmasks(sc, ic->ic_curchan); 2011 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2012 sc->sc_cur_rxchainmask); 2013 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 2014 if_printf(ifp, "unable to reset hardware; hal status %u\n", 2015 status); 2016 ATH_UNLOCK(sc); 2017 return; 2018 } 2019 ath_chan_change(sc, ic->ic_curchan); 2020 2021 /* Let DFS at it in case it's a DFS channel */ 2022 ath_dfs_radar_enable(sc, ic->ic_curchan); 2023 2024 /* Let spectral at in case spectral is enabled */ 2025 ath_spectral_enable(sc, ic->ic_curchan); 2026 2027 /* 2028 * Likewise this is set during reset so update 2029 * state cached in the driver. 2030 */ 2031 sc->sc_diversity = ath_hal_getdiversity(ah); 2032 sc->sc_lastlongcal = 0; 2033 sc->sc_resetcal = 1; 2034 sc->sc_lastcalreset = 0; 2035 sc->sc_lastani = 0; 2036 sc->sc_lastshortcal = 0; 2037 sc->sc_doresetcal = AH_FALSE; 2038 /* 2039 * Beacon timers were cleared here; give ath_newstate() 2040 * a hint that the beacon timers should be poked when 2041 * things transition to the RUN state. 2042 */ 2043 sc->sc_beacons = 0; 2044 2045 /* 2046 * Setup the hardware after reset: the key cache 2047 * is filled as needed and the receive engine is 2048 * set going. Frame transmit is handled entirely 2049 * in the frame output path; there's nothing to do 2050 * here except setup the interrupt mask. 2051 */ 2052 if (ath_startrecv(sc) != 0) { 2053 if_printf(ifp, "unable to start recv logic\n"); 2054 ATH_UNLOCK(sc); 2055 return; 2056 } 2057 2058 /* 2059 * Enable interrupts. 2060 */ 2061 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 2062 | HAL_INT_RXEOL | HAL_INT_RXORN 2063 | HAL_INT_TXURN 2064 | HAL_INT_FATAL | HAL_INT_GLOBAL; 2065 2066 /* 2067 * Enable RX EDMA bits. Note these overlap with 2068 * HAL_INT_RX and HAL_INT_RXDESC respectively. 2069 */ 2070 if (sc->sc_isedma) 2071 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP); 2072 2073 /* 2074 * Enable MIB interrupts when there are hardware phy counters. 2075 * Note we only do this (at the moment) for station mode. 2076 */ 2077 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 2078 sc->sc_imask |= HAL_INT_MIB; 2079 2080 /* Enable global TX timeout and carrier sense timeout if available */ 2081 if (ath_hal_gtxto_supported(ah)) 2082 sc->sc_imask |= HAL_INT_GTT; 2083 2084 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 2085 __func__, sc->sc_imask); 2086 2087 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2088 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 2089 ath_hal_intrset(ah, sc->sc_imask); 2090 2091 ATH_UNLOCK(sc); 2092 2093#ifdef ATH_TX99_DIAG 2094 if (sc->sc_tx99 != NULL) 2095 sc->sc_tx99->start(sc->sc_tx99); 2096 else 2097#endif 2098 ieee80211_start_all(ic); /* start all vap's */ 2099} 2100 2101static void 2102ath_stop_locked(struct ifnet *ifp) 2103{ 2104 struct ath_softc *sc = ifp->if_softc; 2105 struct ath_hal *ah = sc->sc_ah; 2106 2107 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 2108 __func__, sc->sc_invalid, ifp->if_flags); 2109 2110 ATH_LOCK_ASSERT(sc); 2111 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2112 /* 2113 * Shutdown the hardware and driver: 2114 * reset 802.11 state machine 2115 * turn off timers 2116 * disable interrupts 2117 * turn off the radio 2118 * clear transmit machinery 2119 * clear receive machinery 2120 * drain and release tx queues 2121 * reclaim beacon resources 2122 * power down hardware 2123 * 2124 * Note that some of this work is not possible if the 2125 * hardware is gone (invalid). 2126 */ 2127#ifdef ATH_TX99_DIAG 2128 if (sc->sc_tx99 != NULL) 2129 sc->sc_tx99->stop(sc->sc_tx99); 2130#endif 2131 callout_stop(&sc->sc_wd_ch); 2132 sc->sc_wd_timer = 0; 2133 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2134 if (!sc->sc_invalid) { 2135 if (sc->sc_softled) { 2136 callout_stop(&sc->sc_ledtimer); 2137 ath_hal_gpioset(ah, sc->sc_ledpin, 2138 !sc->sc_ledon); 2139 sc->sc_blinking = 0; 2140 } 2141 ath_hal_intrset(ah, 0); 2142 } 2143 ath_draintxq(sc, ATH_RESET_DEFAULT); 2144 if (!sc->sc_invalid) { 2145 ath_stoprecv(sc, 1); 2146 ath_hal_phydisable(ah); 2147 } else 2148 sc->sc_rxlink = NULL; 2149 ath_beacon_free(sc); /* XXX not needed */ 2150 } 2151} 2152 2153#define MAX_TXRX_ITERATIONS 1000 2154static void 2155ath_txrx_stop_locked(struct ath_softc *sc) 2156{ 2157 int i = MAX_TXRX_ITERATIONS; 2158 2159 ATH_UNLOCK_ASSERT(sc); 2160 ATH_PCU_LOCK_ASSERT(sc); 2161 2162 /* 2163 * Sleep until all the pending operations have completed. 2164 * 2165 * The caller must ensure that reset has been incremented 2166 * or the pending operations may continue being queued. 2167 */ 2168 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 2169 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 2170 if (i <= 0) 2171 break; 2172 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1); 2173 i--; 2174 } 2175 2176 if (i <= 0) 2177 device_printf(sc->sc_dev, 2178 "%s: didn't finish after %d iterations\n", 2179 __func__, MAX_TXRX_ITERATIONS); 2180} 2181#undef MAX_TXRX_ITERATIONS 2182 2183#if 0 2184static void 2185ath_txrx_stop(struct ath_softc *sc) 2186{ 2187 ATH_UNLOCK_ASSERT(sc); 2188 ATH_PCU_UNLOCK_ASSERT(sc); 2189 2190 ATH_PCU_LOCK(sc); 2191 ath_txrx_stop_locked(sc); 2192 ATH_PCU_UNLOCK(sc); 2193} 2194#endif 2195 2196static void 2197ath_txrx_start(struct ath_softc *sc) 2198{ 2199 2200 taskqueue_unblock(sc->sc_tq); 2201} 2202 2203/* 2204 * Grab the reset lock, and wait around until noone else 2205 * is trying to do anything with it. 2206 * 2207 * This is totally horrible but we can't hold this lock for 2208 * long enough to do TX/RX or we end up with net80211/ip stack 2209 * LORs and eventual deadlock. 2210 * 2211 * "dowait" signals whether to spin, waiting for the reset 2212 * lock count to reach 0. This should (for now) only be used 2213 * during the reset path, as the rest of the code may not 2214 * be locking-reentrant enough to behave correctly. 2215 * 2216 * Another, cleaner way should be found to serialise all of 2217 * these operations. 2218 */ 2219#define MAX_RESET_ITERATIONS 10 2220static int 2221ath_reset_grablock(struct ath_softc *sc, int dowait) 2222{ 2223 int w = 0; 2224 int i = MAX_RESET_ITERATIONS; 2225 2226 ATH_PCU_LOCK_ASSERT(sc); 2227 do { 2228 if (sc->sc_inreset_cnt == 0) { 2229 w = 1; 2230 break; 2231 } 2232 if (dowait == 0) { 2233 w = 0; 2234 break; 2235 } 2236 ATH_PCU_UNLOCK(sc); 2237 pause("ath_reset_grablock", 1); 2238 i--; 2239 ATH_PCU_LOCK(sc); 2240 } while (i > 0); 2241 2242 /* 2243 * We always increment the refcounter, regardless 2244 * of whether we succeeded to get it in an exclusive 2245 * way. 2246 */ 2247 sc->sc_inreset_cnt++; 2248 2249 if (i <= 0) 2250 device_printf(sc->sc_dev, 2251 "%s: didn't finish after %d iterations\n", 2252 __func__, MAX_RESET_ITERATIONS); 2253 2254 if (w == 0) 2255 device_printf(sc->sc_dev, 2256 "%s: warning, recursive reset path!\n", 2257 __func__); 2258 2259 return w; 2260} 2261#undef MAX_RESET_ITERATIONS 2262 2263/* 2264 * XXX TODO: write ath_reset_releaselock 2265 */ 2266 2267static void 2268ath_stop(struct ifnet *ifp) 2269{ 2270 struct ath_softc *sc = ifp->if_softc; 2271 2272 ATH_LOCK(sc); 2273 ath_stop_locked(ifp); 2274 ATH_UNLOCK(sc); 2275} 2276 2277/* 2278 * Reset the hardware w/o losing operational state. This is 2279 * basically a more efficient way of doing ath_stop, ath_init, 2280 * followed by state transitions to the current 802.11 2281 * operational state. Used to recover from various errors and 2282 * to reset or reload hardware state. 2283 */ 2284int 2285ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type) 2286{ 2287 struct ath_softc *sc = ifp->if_softc; 2288 struct ieee80211com *ic = ifp->if_l2com; 2289 struct ath_hal *ah = sc->sc_ah; 2290 HAL_STATUS status; 2291 int i; 2292 2293 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2294 2295 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2296 ATH_PCU_UNLOCK_ASSERT(sc); 2297 ATH_UNLOCK_ASSERT(sc); 2298 2299 /* Try to (stop any further TX/RX from occuring */ 2300 taskqueue_block(sc->sc_tq); 2301 2302 ATH_PCU_LOCK(sc); 2303 ath_hal_intrset(ah, 0); /* disable interrupts */ 2304 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */ 2305 if (ath_reset_grablock(sc, 1) == 0) { 2306 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2307 __func__); 2308 } 2309 ATH_PCU_UNLOCK(sc); 2310 2311 /* 2312 * Should now wait for pending TX/RX to complete 2313 * and block future ones from occuring. This needs to be 2314 * done before the TX queue is drained. 2315 */ 2316 ath_draintxq(sc, reset_type); /* stop xmit side */ 2317 2318 /* 2319 * Regardless of whether we're doing a no-loss flush or 2320 * not, stop the PCU and handle what's in the RX queue. 2321 * That way frames aren't dropped which shouldn't be. 2322 */ 2323 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2324 ath_rx_flush(sc); 2325 2326 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2327 /* NB: indicate channel change so we do a full reset */ 2328 ath_update_chainmasks(sc, ic->ic_curchan); 2329 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2330 sc->sc_cur_rxchainmask); 2331 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 2332 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 2333 __func__, status); 2334 sc->sc_diversity = ath_hal_getdiversity(ah); 2335 2336 /* Let DFS at it in case it's a DFS channel */ 2337 ath_dfs_radar_enable(sc, ic->ic_curchan); 2338 2339 /* Let spectral at in case spectral is enabled */ 2340 ath_spectral_enable(sc, ic->ic_curchan); 2341 2342 if (ath_startrecv(sc) != 0) /* restart recv */ 2343 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 2344 /* 2345 * We may be doing a reset in response to an ioctl 2346 * that changes the channel so update any state that 2347 * might change as a result. 2348 */ 2349 ath_chan_change(sc, ic->ic_curchan); 2350 if (sc->sc_beacons) { /* restart beacons */ 2351#ifdef IEEE80211_SUPPORT_TDMA 2352 if (sc->sc_tdma) 2353 ath_tdma_config(sc, NULL); 2354 else 2355#endif 2356 ath_beacon_config(sc, NULL); 2357 } 2358 2359 /* 2360 * Release the reset lock and re-enable interrupts here. 2361 * If an interrupt was being processed in ath_intr(), 2362 * it would disable interrupts at this point. So we have 2363 * to atomically enable interrupts and decrement the 2364 * reset counter - this way ath_intr() doesn't end up 2365 * disabling interrupts without a corresponding enable 2366 * in the rest or channel change path. 2367 */ 2368 ATH_PCU_LOCK(sc); 2369 sc->sc_inreset_cnt--; 2370 /* XXX only do this if sc_inreset_cnt == 0? */ 2371 ath_hal_intrset(ah, sc->sc_imask); 2372 ATH_PCU_UNLOCK(sc); 2373 2374 /* 2375 * TX and RX can be started here. If it were started with 2376 * sc_inreset_cnt > 0, the TX and RX path would abort. 2377 * Thus if this is a nested call through the reset or 2378 * channel change code, TX completion will occur but 2379 * RX completion and ath_start / ath_tx_start will not 2380 * run. 2381 */ 2382 2383 /* Restart TX/RX as needed */ 2384 ath_txrx_start(sc); 2385 2386 /* Restart TX completion and pending TX */ 2387 if (reset_type == ATH_RESET_NOLOSS) { 2388 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2389 if (ATH_TXQ_SETUP(sc, i)) { 2390 ATH_TXQ_LOCK(&sc->sc_txq[i]); 2391 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 2392 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 2393 2394 ATH_TX_LOCK(sc); 2395 ath_txq_sched(sc, &sc->sc_txq[i]); 2396 ATH_TX_UNLOCK(sc); 2397 } 2398 } 2399 } 2400 2401 /* 2402 * This may have been set during an ath_start() call which 2403 * set this once it detected a concurrent TX was going on. 2404 * So, clear it. 2405 */ 2406 IF_LOCK(&ifp->if_snd); 2407 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2408 IF_UNLOCK(&ifp->if_snd); 2409 2410 /* Handle any frames in the TX queue */ 2411 /* 2412 * XXX should this be done by the caller, rather than 2413 * ath_reset() ? 2414 */ 2415 ath_tx_kick(sc); /* restart xmit */ 2416 return 0; 2417} 2418 2419static int 2420ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 2421{ 2422 struct ieee80211com *ic = vap->iv_ic; 2423 struct ifnet *ifp = ic->ic_ifp; 2424 struct ath_softc *sc = ifp->if_softc; 2425 struct ath_hal *ah = sc->sc_ah; 2426 2427 switch (cmd) { 2428 case IEEE80211_IOC_TXPOWER: 2429 /* 2430 * If per-packet TPC is enabled, then we have nothing 2431 * to do; otherwise we need to force the global limit. 2432 * All this can happen directly; no need to reset. 2433 */ 2434 if (!ath_hal_gettpc(ah)) 2435 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 2436 return 0; 2437 } 2438 /* XXX? Full or NOLOSS? */ 2439 return ath_reset(ifp, ATH_RESET_FULL); 2440} 2441 2442struct ath_buf * 2443_ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype) 2444{ 2445 struct ath_buf *bf; 2446 2447 ATH_TXBUF_LOCK_ASSERT(sc); 2448 2449 if (btype == ATH_BUFTYPE_MGMT) 2450 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt); 2451 else 2452 bf = TAILQ_FIRST(&sc->sc_txbuf); 2453 2454 if (bf == NULL) { 2455 sc->sc_stats.ast_tx_getnobuf++; 2456 } else { 2457 if (bf->bf_flags & ATH_BUF_BUSY) { 2458 sc->sc_stats.ast_tx_getbusybuf++; 2459 bf = NULL; 2460 } 2461 } 2462 2463 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) { 2464 if (btype == ATH_BUFTYPE_MGMT) 2465 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list); 2466 else { 2467 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 2468 sc->sc_txbuf_cnt--; 2469 2470 /* 2471 * This shuldn't happen; however just to be 2472 * safe print a warning and fudge the txbuf 2473 * count. 2474 */ 2475 if (sc->sc_txbuf_cnt < 0) { 2476 device_printf(sc->sc_dev, 2477 "%s: sc_txbuf_cnt < 0?\n", 2478 __func__); 2479 sc->sc_txbuf_cnt = 0; 2480 } 2481 } 2482 } else 2483 bf = NULL; 2484 2485 if (bf == NULL) { 2486 /* XXX should check which list, mgmt or otherwise */ 2487 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 2488 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 2489 "out of xmit buffers" : "xmit buffer busy"); 2490 return NULL; 2491 } 2492 2493 /* XXX TODO: should do this at buffer list initialisation */ 2494 /* XXX (then, ensure the buffer has the right flag set) */ 2495 bf->bf_flags = 0; 2496 if (btype == ATH_BUFTYPE_MGMT) 2497 bf->bf_flags |= ATH_BUF_MGMT; 2498 else 2499 bf->bf_flags &= (~ATH_BUF_MGMT); 2500 2501 /* Valid bf here; clear some basic fields */ 2502 bf->bf_next = NULL; /* XXX just to be sure */ 2503 bf->bf_last = NULL; /* XXX again, just to be sure */ 2504 bf->bf_comp = NULL; /* XXX again, just to be sure */ 2505 bzero(&bf->bf_state, sizeof(bf->bf_state)); 2506 2507 /* 2508 * Track the descriptor ID only if doing EDMA 2509 */ 2510 if (sc->sc_isedma) { 2511 bf->bf_descid = sc->sc_txbuf_descid; 2512 sc->sc_txbuf_descid++; 2513 } 2514 2515 return bf; 2516} 2517 2518/* 2519 * When retrying a software frame, buffers marked ATH_BUF_BUSY 2520 * can't be thrown back on the queue as they could still be 2521 * in use by the hardware. 2522 * 2523 * This duplicates the buffer, or returns NULL. 2524 * 2525 * The descriptor is also copied but the link pointers and 2526 * the DMA segments aren't copied; this frame should thus 2527 * be again passed through the descriptor setup/chain routines 2528 * so the link is correct. 2529 * 2530 * The caller must free the buffer using ath_freebuf(). 2531 */ 2532struct ath_buf * 2533ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf) 2534{ 2535 struct ath_buf *tbf; 2536 2537 tbf = ath_getbuf(sc, 2538 (bf->bf_flags & ATH_BUF_MGMT) ? 2539 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL); 2540 if (tbf == NULL) 2541 return NULL; /* XXX failure? Why? */ 2542 2543 /* Copy basics */ 2544 tbf->bf_next = NULL; 2545 tbf->bf_nseg = bf->bf_nseg; 2546 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE; 2547 tbf->bf_status = bf->bf_status; 2548 tbf->bf_m = bf->bf_m; 2549 tbf->bf_node = bf->bf_node; 2550 /* will be setup by the chain/setup function */ 2551 tbf->bf_lastds = NULL; 2552 /* for now, last == self */ 2553 tbf->bf_last = tbf; 2554 tbf->bf_comp = bf->bf_comp; 2555 2556 /* NOTE: DMA segments will be setup by the setup/chain functions */ 2557 2558 /* The caller has to re-init the descriptor + links */ 2559 2560 /* 2561 * Free the DMA mapping here, before we NULL the mbuf. 2562 * We must only call bus_dmamap_unload() once per mbuf chain 2563 * or behaviour is undefined. 2564 */ 2565 if (bf->bf_m != NULL) { 2566 /* 2567 * XXX is this POSTWRITE call required? 2568 */ 2569 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2570 BUS_DMASYNC_POSTWRITE); 2571 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2572 } 2573 2574 bf->bf_m = NULL; 2575 bf->bf_node = NULL; 2576 2577 /* Copy state */ 2578 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 2579 2580 return tbf; 2581} 2582 2583struct ath_buf * 2584ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype) 2585{ 2586 struct ath_buf *bf; 2587 2588 ATH_TXBUF_LOCK(sc); 2589 bf = _ath_getbuf_locked(sc, btype); 2590 /* 2591 * If a mgmt buffer was requested but we're out of those, 2592 * try requesting a normal one. 2593 */ 2594 if (bf == NULL && btype == ATH_BUFTYPE_MGMT) 2595 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 2596 ATH_TXBUF_UNLOCK(sc); 2597 if (bf == NULL) { 2598 struct ifnet *ifp = sc->sc_ifp; 2599 2600 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 2601 sc->sc_stats.ast_tx_qstop++; 2602 IF_LOCK(&ifp->if_snd); 2603 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2604 IF_UNLOCK(&ifp->if_snd); 2605 } 2606 return bf; 2607} 2608 2609static void 2610ath_start_queue(struct ifnet *ifp) 2611{ 2612 struct ath_softc *sc = ifp->if_softc; 2613 2614 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: start"); 2615 ath_tx_kick(sc); 2616 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: finished"); 2617} 2618 2619void 2620ath_start_task(void *arg, int npending) 2621{ 2622 struct ath_softc *sc = (struct ath_softc *) arg; 2623 struct ifnet *ifp = sc->sc_ifp; 2624 2625 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: start"); 2626 2627 /* XXX is it ok to hold the ATH_LOCK here? */ 2628 ATH_PCU_LOCK(sc); 2629 if (sc->sc_inreset_cnt > 0) { 2630 device_printf(sc->sc_dev, 2631 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 2632 ATH_PCU_UNLOCK(sc); 2633 IF_LOCK(&ifp->if_snd); 2634 sc->sc_stats.ast_tx_qstop++; 2635 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2636 IF_UNLOCK(&ifp->if_snd); 2637 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish"); 2638 return; 2639 } 2640 sc->sc_txstart_cnt++; 2641 ATH_PCU_UNLOCK(sc); 2642 2643 ATH_TX_LOCK(sc); 2644 ath_start(sc->sc_ifp); 2645 ATH_TX_UNLOCK(sc); 2646 2647 ATH_PCU_LOCK(sc); 2648 sc->sc_txstart_cnt--; 2649 ATH_PCU_UNLOCK(sc); 2650 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: finished"); 2651} 2652 2653void 2654ath_start(struct ifnet *ifp) 2655{ 2656 struct ath_softc *sc = ifp->if_softc; 2657 struct ieee80211_node *ni; 2658 struct ath_buf *bf; 2659 struct mbuf *m, *next; 2660 ath_bufhead frags; 2661 int npkts = 0; 2662 2663 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 2664 return; 2665 2666 ATH_TX_LOCK_ASSERT(sc); 2667 2668 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start: called"); 2669 2670 for (;;) { 2671 /* 2672 * Grab the frame that we're going to try and transmit. 2673 */ 2674 IFQ_DEQUEUE(&ifp->if_snd, m); 2675 if (m == NULL) 2676 break; 2677 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 2678 2679 /* 2680 * Enforce how deep a node queue can get. 2681 * 2682 * XXX it would be nicer if we kept an mbuf queue per 2683 * node and only whacked them into ath_bufs when we 2684 * are ready to schedule some traffic from them. 2685 * .. that may come later. 2686 * 2687 * XXX we should also track the per-node hardware queue 2688 * depth so it is easy to limit the _SUM_ of the swq and 2689 * hwq frames. Since we only schedule two HWQ frames 2690 * at a time, this should be OK for now. 2691 */ 2692 if ((!(m->m_flags & M_EAPOL)) && 2693 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) { 2694 sc->sc_stats.ast_tx_nodeq_overflow++; 2695 if (ni != NULL) 2696 ieee80211_free_node(ni); 2697 m_freem(m); 2698 m = NULL; 2699 continue; 2700 } 2701 2702 /* 2703 * Check how many TX buffers are available. 2704 * 2705 * If this is for non-EAPOL traffic, just leave some 2706 * space free in order for buffer cloning and raw 2707 * frame transmission to occur. 2708 * 2709 * If it's for EAPOL traffic, ignore this for now. 2710 * Management traffic will be sent via the raw transmit 2711 * method which bypasses this check. 2712 * 2713 * This is needed to ensure that EAPOL frames during 2714 * (re) keying have a chance to go out. 2715 * 2716 * See kern/138379 for more information. 2717 */ 2718 if ((!(m->m_flags & M_EAPOL)) && 2719 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) { 2720 sc->sc_stats.ast_tx_nobuf++; 2721 IF_LOCK(&ifp->if_snd); 2722 _IF_PREPEND(&ifp->if_snd, m); 2723 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2724 IF_UNLOCK(&ifp->if_snd); 2725 m = NULL; 2726 break; 2727 } 2728 2729 /* 2730 * Grab a TX buffer and associated resources. 2731 * 2732 * If it's an EAPOL frame, allocate a MGMT ath_buf. 2733 * That way even with temporary buffer exhaustion due to 2734 * the data path doesn't leave us without the ability 2735 * to transmit management frames. 2736 * 2737 * Otherwise allocate a normal buffer. 2738 */ 2739 if (m->m_flags & M_EAPOL) 2740 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 2741 else 2742 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL); 2743 2744 if (bf == NULL) { 2745 /* 2746 * If we failed to allocate a buffer, prepend it 2747 * and continue. 2748 * 2749 * We shouldn't fail normally, due to the check 2750 * above. 2751 */ 2752 sc->sc_stats.ast_tx_nobuf++; 2753 IF_LOCK(&ifp->if_snd); 2754 _IF_PREPEND(&ifp->if_snd, m); 2755 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2756 IF_UNLOCK(&ifp->if_snd); 2757 m = NULL; 2758 break; 2759 } 2760 2761 npkts ++; 2762 2763 /* 2764 * Check for fragmentation. If this frame 2765 * has been broken up verify we have enough 2766 * buffers to send all the fragments so all 2767 * go out or none... 2768 */ 2769 TAILQ_INIT(&frags); 2770 if ((m->m_flags & M_FRAG) && 2771 !ath_txfrag_setup(sc, &frags, m, ni)) { 2772 DPRINTF(sc, ATH_DEBUG_XMIT, 2773 "%s: out of txfrag buffers\n", __func__); 2774 sc->sc_stats.ast_tx_nofrag++; 2775 ifp->if_oerrors++; 2776 ath_freetx(m); 2777 goto bad; 2778 } 2779 ifp->if_opackets++; 2780 nextfrag: 2781 /* 2782 * Pass the frame to the h/w for transmission. 2783 * Fragmented frames have each frag chained together 2784 * with m_nextpkt. We know there are sufficient ath_buf's 2785 * to send all the frags because of work done by 2786 * ath_txfrag_setup. We leave m_nextpkt set while 2787 * calling ath_tx_start so it can use it to extend the 2788 * the tx duration to cover the subsequent frag and 2789 * so it can reclaim all the mbufs in case of an error; 2790 * ath_tx_start clears m_nextpkt once it commits to 2791 * handing the frame to the hardware. 2792 */ 2793 next = m->m_nextpkt; 2794 if (ath_tx_start(sc, ni, bf, m)) { 2795 bad: 2796 ifp->if_oerrors++; 2797 reclaim: 2798 bf->bf_m = NULL; 2799 bf->bf_node = NULL; 2800 ATH_TXBUF_LOCK(sc); 2801 ath_returnbuf_head(sc, bf); 2802 ath_txfrag_cleanup(sc, &frags, ni); 2803 ATH_TXBUF_UNLOCK(sc); 2804 /* 2805 * XXX todo, free the node outside of 2806 * the TX lock context! 2807 */ 2808 if (ni != NULL) 2809 ieee80211_free_node(ni); 2810 continue; 2811 } 2812 2813 /* 2814 * Check here if the node is in power save state. 2815 */ 2816 ath_tx_update_tim(sc, ni, 1); 2817 2818 if (next != NULL) { 2819 /* 2820 * Beware of state changing between frags. 2821 * XXX check sta power-save state? 2822 */ 2823 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2824 DPRINTF(sc, ATH_DEBUG_XMIT, 2825 "%s: flush fragmented packet, state %s\n", 2826 __func__, 2827 ieee80211_state_name[ni->ni_vap->iv_state]); 2828 /* XXX dmamap */ 2829 ath_freetx(next); 2830 goto reclaim; 2831 } 2832 m = next; 2833 bf = TAILQ_FIRST(&frags); 2834 KASSERT(bf != NULL, ("no buf for txfrag")); 2835 TAILQ_REMOVE(&frags, bf, bf_list); 2836 goto nextfrag; 2837 } 2838 2839 sc->sc_wd_timer = 5; 2840 } 2841 ATH_KTR(sc, ATH_KTR_TX, 1, "ath_start: finished; npkts=%d", npkts); 2842} 2843static int 2844ath_media_change(struct ifnet *ifp) 2845{ 2846 int error = ieee80211_media_change(ifp); 2847 /* NB: only the fixed rate can change and that doesn't need a reset */ 2848 return (error == ENETRESET ? 0 : error); 2849} 2850 2851/* 2852 * Block/unblock tx+rx processing while a key change is done. 2853 * We assume the caller serializes key management operations 2854 * so we only need to worry about synchronization with other 2855 * uses that originate in the driver. 2856 */ 2857static void 2858ath_key_update_begin(struct ieee80211vap *vap) 2859{ 2860 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2861 struct ath_softc *sc = ifp->if_softc; 2862 2863 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2864 taskqueue_block(sc->sc_tq); 2865 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2866} 2867 2868static void 2869ath_key_update_end(struct ieee80211vap *vap) 2870{ 2871 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2872 struct ath_softc *sc = ifp->if_softc; 2873 2874 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2875 IF_UNLOCK(&ifp->if_snd); 2876 taskqueue_unblock(sc->sc_tq); 2877} 2878 2879static void 2880ath_update_promisc(struct ifnet *ifp) 2881{ 2882 struct ath_softc *sc = ifp->if_softc; 2883 u_int32_t rfilt; 2884 2885 /* configure rx filter */ 2886 rfilt = ath_calcrxfilter(sc); 2887 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2888 2889 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2890} 2891 2892static void 2893ath_update_mcast(struct ifnet *ifp) 2894{ 2895 struct ath_softc *sc = ifp->if_softc; 2896 u_int32_t mfilt[2]; 2897 2898 /* calculate and install multicast filter */ 2899 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2900 struct ifmultiaddr *ifma; 2901 /* 2902 * Merge multicast addresses to form the hardware filter. 2903 */ 2904 mfilt[0] = mfilt[1] = 0; 2905 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2907 caddr_t dl; 2908 u_int32_t val; 2909 u_int8_t pos; 2910 2911 /* calculate XOR of eight 6bit values */ 2912 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2913 val = LE_READ_4(dl + 0); 2914 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2915 val = LE_READ_4(dl + 3); 2916 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2917 pos &= 0x3f; 2918 mfilt[pos / 32] |= (1 << (pos % 32)); 2919 } 2920 if_maddr_runlock(ifp); 2921 } else 2922 mfilt[0] = mfilt[1] = ~0; 2923 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2924 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2925 __func__, mfilt[0], mfilt[1]); 2926} 2927 2928void 2929ath_mode_init(struct ath_softc *sc) 2930{ 2931 struct ifnet *ifp = sc->sc_ifp; 2932 struct ath_hal *ah = sc->sc_ah; 2933 u_int32_t rfilt; 2934 2935 /* configure rx filter */ 2936 rfilt = ath_calcrxfilter(sc); 2937 ath_hal_setrxfilter(ah, rfilt); 2938 2939 /* configure operational mode */ 2940 ath_hal_setopmode(ah); 2941 2942 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE, 2943 "%s: ah=%p, ifp=%p, if_addr=%p\n", 2944 __func__, 2945 ah, 2946 ifp, 2947 (ifp == NULL) ? NULL : ifp->if_addr); 2948 2949 /* handle any link-level address change */ 2950 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2951 2952 /* calculate and install multicast filter */ 2953 ath_update_mcast(ifp); 2954} 2955 2956/* 2957 * Set the slot time based on the current setting. 2958 */ 2959void 2960ath_setslottime(struct ath_softc *sc) 2961{ 2962 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2963 struct ath_hal *ah = sc->sc_ah; 2964 u_int usec; 2965 2966 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2967 usec = 13; 2968 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2969 usec = 21; 2970 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2971 /* honor short/long slot time only in 11g */ 2972 /* XXX shouldn't honor on pure g or turbo g channel */ 2973 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2974 usec = HAL_SLOT_TIME_9; 2975 else 2976 usec = HAL_SLOT_TIME_20; 2977 } else 2978 usec = HAL_SLOT_TIME_9; 2979 2980 DPRINTF(sc, ATH_DEBUG_RESET, 2981 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2982 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2983 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2984 2985 ath_hal_setslottime(ah, usec); 2986 sc->sc_updateslot = OK; 2987} 2988 2989/* 2990 * Callback from the 802.11 layer to update the 2991 * slot time based on the current setting. 2992 */ 2993static void 2994ath_updateslot(struct ifnet *ifp) 2995{ 2996 struct ath_softc *sc = ifp->if_softc; 2997 struct ieee80211com *ic = ifp->if_l2com; 2998 2999 /* 3000 * When not coordinating the BSS, change the hardware 3001 * immediately. For other operation we defer the change 3002 * until beacon updates have propagated to the stations. 3003 */ 3004 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3005 ic->ic_opmode == IEEE80211_M_MBSS) 3006 sc->sc_updateslot = UPDATE; 3007 else 3008 ath_setslottime(sc); 3009} 3010 3011/* 3012 * Append the contents of src to dst; both queues 3013 * are assumed to be locked. 3014 */ 3015void 3016ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 3017{ 3018 3019 ATH_TXQ_LOCK_ASSERT(src); 3020 ATH_TXQ_LOCK_ASSERT(dst); 3021 3022 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 3023 dst->axq_link = src->axq_link; 3024 src->axq_link = NULL; 3025 dst->axq_depth += src->axq_depth; 3026 dst->axq_aggr_depth += src->axq_aggr_depth; 3027 src->axq_depth = 0; 3028 src->axq_aggr_depth = 0; 3029} 3030 3031/* 3032 * Reset the hardware, with no loss. 3033 * 3034 * This can't be used for a general case reset. 3035 */ 3036static void 3037ath_reset_proc(void *arg, int pending) 3038{ 3039 struct ath_softc *sc = arg; 3040 struct ifnet *ifp = sc->sc_ifp; 3041 3042#if 0 3043 if_printf(ifp, "%s: resetting\n", __func__); 3044#endif 3045 ath_reset(ifp, ATH_RESET_NOLOSS); 3046} 3047 3048/* 3049 * Reset the hardware after detecting beacons have stopped. 3050 */ 3051static void 3052ath_bstuck_proc(void *arg, int pending) 3053{ 3054 struct ath_softc *sc = arg; 3055 struct ifnet *ifp = sc->sc_ifp; 3056 uint32_t hangs = 0; 3057 3058 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 3059 if_printf(ifp, "bb hang detected (0x%x)\n", hangs); 3060 3061 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3062 sc->sc_bmisscount); 3063 sc->sc_stats.ast_bstuck++; 3064 /* 3065 * This assumes that there's no simultaneous channel mode change 3066 * occuring. 3067 */ 3068 ath_reset(ifp, ATH_RESET_NOLOSS); 3069} 3070 3071static void 3072ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3073{ 3074 bus_addr_t *paddr = (bus_addr_t*) arg; 3075 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3076 *paddr = segs->ds_addr; 3077} 3078 3079/* 3080 * Allocate the descriptors and appropriate DMA tag/setup. 3081 * 3082 * For some situations (eg EDMA TX completion), there isn't a requirement 3083 * for the ath_buf entries to be allocated. 3084 */ 3085int 3086ath_descdma_alloc_desc(struct ath_softc *sc, 3087 struct ath_descdma *dd, ath_bufhead *head, 3088 const char *name, int ds_size, int ndesc) 3089{ 3090#define DS2PHYS(_dd, _ds) \ 3091 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3092#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 3093 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 3094 struct ifnet *ifp = sc->sc_ifp; 3095 int error; 3096 3097 dd->dd_descsize = ds_size; 3098 3099 DPRINTF(sc, ATH_DEBUG_RESET, 3100 "%s: %s DMA: %u desc, %d bytes per descriptor\n", 3101 __func__, name, ndesc, dd->dd_descsize); 3102 3103 dd->dd_name = name; 3104 dd->dd_desc_len = dd->dd_descsize * ndesc; 3105 3106 /* 3107 * Merlin work-around: 3108 * Descriptors that cross the 4KB boundary can't be used. 3109 * Assume one skipped descriptor per 4KB page. 3110 */ 3111 if (! ath_hal_split4ktrans(sc->sc_ah)) { 3112 int numpages = dd->dd_desc_len / 4096; 3113 dd->dd_desc_len += ds_size * numpages; 3114 } 3115 3116 /* 3117 * Setup DMA descriptor area. 3118 * 3119 * BUS_DMA_ALLOCNOW is not used; we never use bounce 3120 * buffers for the descriptors themselves. 3121 */ 3122 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3123 PAGE_SIZE, 0, /* alignment, bounds */ 3124 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3125 BUS_SPACE_MAXADDR, /* highaddr */ 3126 NULL, NULL, /* filter, filterarg */ 3127 dd->dd_desc_len, /* maxsize */ 3128 1, /* nsegments */ 3129 dd->dd_desc_len, /* maxsegsize */ 3130 0, /* flags */ 3131 NULL, /* lockfunc */ 3132 NULL, /* lockarg */ 3133 &dd->dd_dmat); 3134 if (error != 0) { 3135 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3136 return error; 3137 } 3138 3139 /* allocate descriptors */ 3140 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3141 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3142 &dd->dd_dmamap); 3143 if (error != 0) { 3144 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3145 "error %u\n", ndesc, dd->dd_name, error); 3146 goto fail1; 3147 } 3148 3149 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3150 dd->dd_desc, dd->dd_desc_len, 3151 ath_load_cb, &dd->dd_desc_paddr, 3152 BUS_DMA_NOWAIT); 3153 if (error != 0) { 3154 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3155 dd->dd_name, error); 3156 goto fail2; 3157 } 3158 3159 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3160 __func__, dd->dd_name, (uint8_t *) dd->dd_desc, 3161 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr, 3162 /*XXX*/ (u_long) dd->dd_desc_len); 3163 3164 return (0); 3165 3166fail2: 3167 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3168fail1: 3169 bus_dma_tag_destroy(dd->dd_dmat); 3170 memset(dd, 0, sizeof(*dd)); 3171 return error; 3172#undef DS2PHYS 3173#undef ATH_DESC_4KB_BOUND_CHECK 3174} 3175 3176int 3177ath_descdma_setup(struct ath_softc *sc, 3178 struct ath_descdma *dd, ath_bufhead *head, 3179 const char *name, int ds_size, int nbuf, int ndesc) 3180{ 3181#define DS2PHYS(_dd, _ds) \ 3182 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3183#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 3184 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 3185 struct ifnet *ifp = sc->sc_ifp; 3186 uint8_t *ds; 3187 struct ath_buf *bf; 3188 int i, bsize, error; 3189 3190 /* Allocate descriptors */ 3191 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size, 3192 nbuf * ndesc); 3193 3194 /* Assume any errors during allocation were dealt with */ 3195 if (error != 0) { 3196 return (error); 3197 } 3198 3199 ds = (uint8_t *) dd->dd_desc; 3200 3201 /* allocate rx buffers */ 3202 bsize = sizeof(struct ath_buf) * nbuf; 3203 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3204 if (bf == NULL) { 3205 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3206 dd->dd_name, bsize); 3207 goto fail3; 3208 } 3209 dd->dd_bufptr = bf; 3210 3211 TAILQ_INIT(head); 3212 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) { 3213 bf->bf_desc = (struct ath_desc *) ds; 3214 bf->bf_daddr = DS2PHYS(dd, ds); 3215 if (! ath_hal_split4ktrans(sc->sc_ah)) { 3216 /* 3217 * Merlin WAR: Skip descriptor addresses which 3218 * cause 4KB boundary crossing along any point 3219 * in the descriptor. 3220 */ 3221 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 3222 dd->dd_descsize)) { 3223 /* Start at the next page */ 3224 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 3225 bf->bf_desc = (struct ath_desc *) ds; 3226 bf->bf_daddr = DS2PHYS(dd, ds); 3227 } 3228 } 3229 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3230 &bf->bf_dmamap); 3231 if (error != 0) { 3232 if_printf(ifp, "unable to create dmamap for %s " 3233 "buffer %u, error %u\n", dd->dd_name, i, error); 3234 ath_descdma_cleanup(sc, dd, head); 3235 return error; 3236 } 3237 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 3238 TAILQ_INSERT_TAIL(head, bf, bf_list); 3239 } 3240 3241 /* 3242 * XXX TODO: ensure that ds doesn't overflow the descriptor 3243 * allocation otherwise weird stuff will occur and crash your 3244 * machine. 3245 */ 3246 return 0; 3247 /* XXX this should likely just call ath_descdma_cleanup() */ 3248fail3: 3249 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3250 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3251 bus_dma_tag_destroy(dd->dd_dmat); 3252 memset(dd, 0, sizeof(*dd)); 3253 return error; 3254#undef DS2PHYS 3255#undef ATH_DESC_4KB_BOUND_CHECK 3256} 3257 3258/* 3259 * Allocate ath_buf entries but no descriptor contents. 3260 * 3261 * This is for RX EDMA where the descriptors are the header part of 3262 * the RX buffer. 3263 */ 3264int 3265ath_descdma_setup_rx_edma(struct ath_softc *sc, 3266 struct ath_descdma *dd, ath_bufhead *head, 3267 const char *name, int nbuf, int rx_status_len) 3268{ 3269 struct ifnet *ifp = sc->sc_ifp; 3270 struct ath_buf *bf; 3271 int i, bsize, error; 3272 3273 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n", 3274 __func__, name, nbuf); 3275 3276 dd->dd_name = name; 3277 /* 3278 * This is (mostly) purely for show. We're not allocating any actual 3279 * descriptors here as EDMA RX has the descriptor be part 3280 * of the RX buffer. 3281 * 3282 * However, dd_desc_len is used by ath_descdma_free() to determine 3283 * whether we have already freed this DMA mapping. 3284 */ 3285 dd->dd_desc_len = rx_status_len * nbuf; 3286 dd->dd_descsize = rx_status_len; 3287 3288 /* allocate rx buffers */ 3289 bsize = sizeof(struct ath_buf) * nbuf; 3290 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3291 if (bf == NULL) { 3292 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3293 dd->dd_name, bsize); 3294 error = ENOMEM; 3295 goto fail3; 3296 } 3297 dd->dd_bufptr = bf; 3298 3299 TAILQ_INIT(head); 3300 for (i = 0; i < nbuf; i++, bf++) { 3301 bf->bf_desc = NULL; 3302 bf->bf_daddr = 0; 3303 bf->bf_lastds = NULL; /* Just an initial value */ 3304 3305 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3306 &bf->bf_dmamap); 3307 if (error != 0) { 3308 if_printf(ifp, "unable to create dmamap for %s " 3309 "buffer %u, error %u\n", dd->dd_name, i, error); 3310 ath_descdma_cleanup(sc, dd, head); 3311 return error; 3312 } 3313 TAILQ_INSERT_TAIL(head, bf, bf_list); 3314 } 3315 return 0; 3316fail3: 3317 memset(dd, 0, sizeof(*dd)); 3318 return error; 3319} 3320 3321void 3322ath_descdma_cleanup(struct ath_softc *sc, 3323 struct ath_descdma *dd, ath_bufhead *head) 3324{ 3325 struct ath_buf *bf; 3326 struct ieee80211_node *ni; 3327 int do_warning = 0; 3328 3329 if (dd->dd_dmamap != 0) { 3330 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3331 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3332 bus_dma_tag_destroy(dd->dd_dmat); 3333 } 3334 3335 if (head != NULL) { 3336 TAILQ_FOREACH(bf, head, bf_list) { 3337 if (bf->bf_m) { 3338 /* 3339 * XXX warn if there's buffers here. 3340 * XXX it should have been freed by the 3341 * owner! 3342 */ 3343 3344 if (do_warning == 0) { 3345 do_warning = 1; 3346 device_printf(sc->sc_dev, 3347 "%s: %s: mbuf should've been" 3348 " unmapped/freed!\n", 3349 __func__, 3350 dd->dd_name); 3351 } 3352 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3353 BUS_DMASYNC_POSTREAD); 3354 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3355 m_freem(bf->bf_m); 3356 bf->bf_m = NULL; 3357 } 3358 if (bf->bf_dmamap != NULL) { 3359 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3360 bf->bf_dmamap = NULL; 3361 } 3362 ni = bf->bf_node; 3363 bf->bf_node = NULL; 3364 if (ni != NULL) { 3365 /* 3366 * Reclaim node reference. 3367 */ 3368 ieee80211_free_node(ni); 3369 } 3370 } 3371 } 3372 3373 if (head != NULL) 3374 TAILQ_INIT(head); 3375 3376 if (dd->dd_bufptr != NULL) 3377 free(dd->dd_bufptr, M_ATHDEV); 3378 memset(dd, 0, sizeof(*dd)); 3379} 3380 3381static int 3382ath_desc_alloc(struct ath_softc *sc) 3383{ 3384 int error; 3385 3386 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3387 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER); 3388 if (error != 0) { 3389 return error; 3390 } 3391 sc->sc_txbuf_cnt = ath_txbuf; 3392 3393 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt, 3394 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt, 3395 ATH_TXDESC); 3396 if (error != 0) { 3397 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3398 return error; 3399 } 3400 3401 /* 3402 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the 3403 * flag doesn't have to be set in ath_getbuf_locked(). 3404 */ 3405 3406 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3407 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1); 3408 if (error != 0) { 3409 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3410 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3411 &sc->sc_txbuf_mgmt); 3412 return error; 3413 } 3414 return 0; 3415} 3416 3417static void 3418ath_desc_free(struct ath_softc *sc) 3419{ 3420 3421 if (sc->sc_bdma.dd_desc_len != 0) 3422 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3423 if (sc->sc_txdma.dd_desc_len != 0) 3424 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3425 if (sc->sc_txdma_mgmt.dd_desc_len != 0) 3426 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3427 &sc->sc_txbuf_mgmt); 3428} 3429 3430static struct ieee80211_node * 3431ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3432{ 3433 struct ieee80211com *ic = vap->iv_ic; 3434 struct ath_softc *sc = ic->ic_ifp->if_softc; 3435 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3436 struct ath_node *an; 3437 3438 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3439 if (an == NULL) { 3440 /* XXX stat+msg */ 3441 return NULL; 3442 } 3443 ath_rate_node_init(sc, an); 3444 3445 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3446 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3447 device_get_nameunit(sc->sc_dev), an); 3448 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3449 3450 /* XXX setup ath_tid */ 3451 ath_tx_tid_init(sc, an); 3452 3453 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3454 return &an->an_node; 3455} 3456 3457static void 3458ath_node_cleanup(struct ieee80211_node *ni) 3459{ 3460 struct ieee80211com *ic = ni->ni_ic; 3461 struct ath_softc *sc = ic->ic_ifp->if_softc; 3462 3463 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3464 ath_tx_node_flush(sc, ATH_NODE(ni)); 3465 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3466 sc->sc_node_cleanup(ni); 3467} 3468 3469static void 3470ath_node_free(struct ieee80211_node *ni) 3471{ 3472 struct ieee80211com *ic = ni->ni_ic; 3473 struct ath_softc *sc = ic->ic_ifp->if_softc; 3474 3475 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3476 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3477 sc->sc_node_free(ni); 3478} 3479 3480static void 3481ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3482{ 3483 struct ieee80211com *ic = ni->ni_ic; 3484 struct ath_softc *sc = ic->ic_ifp->if_softc; 3485 struct ath_hal *ah = sc->sc_ah; 3486 3487 *rssi = ic->ic_node_getrssi(ni); 3488 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3489 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3490 else 3491 *noise = -95; /* nominally correct */ 3492} 3493 3494/* 3495 * Set the default antenna. 3496 */ 3497void 3498ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3499{ 3500 struct ath_hal *ah = sc->sc_ah; 3501 3502 /* XXX block beacon interrupts */ 3503 ath_hal_setdefantenna(ah, antenna); 3504 if (sc->sc_defant != antenna) 3505 sc->sc_stats.ast_ant_defswitch++; 3506 sc->sc_defant = antenna; 3507 sc->sc_rxotherant = 0; 3508} 3509 3510static void 3511ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3512{ 3513 txq->axq_qnum = qnum; 3514 txq->axq_ac = 0; 3515 txq->axq_depth = 0; 3516 txq->axq_aggr_depth = 0; 3517 txq->axq_intrcnt = 0; 3518 txq->axq_link = NULL; 3519 txq->axq_softc = sc; 3520 TAILQ_INIT(&txq->axq_q); 3521 TAILQ_INIT(&txq->axq_tidq); 3522 TAILQ_INIT(&txq->fifo.axq_q); 3523 ATH_TXQ_LOCK_INIT(sc, txq); 3524} 3525 3526/* 3527 * Setup a h/w transmit queue. 3528 */ 3529static struct ath_txq * 3530ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3531{ 3532#define N(a) (sizeof(a)/sizeof(a[0])) 3533 struct ath_hal *ah = sc->sc_ah; 3534 HAL_TXQ_INFO qi; 3535 int qnum; 3536 3537 memset(&qi, 0, sizeof(qi)); 3538 qi.tqi_subtype = subtype; 3539 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3540 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3541 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3542 /* 3543 * Enable interrupts only for EOL and DESC conditions. 3544 * We mark tx descriptors to receive a DESC interrupt 3545 * when a tx queue gets deep; otherwise waiting for the 3546 * EOL to reap descriptors. Note that this is done to 3547 * reduce interrupt load and this only defers reaping 3548 * descriptors, never transmitting frames. Aside from 3549 * reducing interrupts this also permits more concurrency. 3550 * The only potential downside is if the tx queue backs 3551 * up in which case the top half of the kernel may backup 3552 * due to a lack of tx descriptors. 3553 */ 3554 if (sc->sc_isedma) 3555 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3556 HAL_TXQ_TXOKINT_ENABLE; 3557 else 3558 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3559 HAL_TXQ_TXDESCINT_ENABLE; 3560 3561 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3562 if (qnum == -1) { 3563 /* 3564 * NB: don't print a message, this happens 3565 * normally on parts with too few tx queues 3566 */ 3567 return NULL; 3568 } 3569 if (qnum >= N(sc->sc_txq)) { 3570 device_printf(sc->sc_dev, 3571 "hal qnum %u out of range, max %zu!\n", 3572 qnum, N(sc->sc_txq)); 3573 ath_hal_releasetxqueue(ah, qnum); 3574 return NULL; 3575 } 3576 if (!ATH_TXQ_SETUP(sc, qnum)) { 3577 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 3578 sc->sc_txqsetup |= 1<<qnum; 3579 } 3580 return &sc->sc_txq[qnum]; 3581#undef N 3582} 3583 3584/* 3585 * Setup a hardware data transmit queue for the specified 3586 * access control. The hal may not support all requested 3587 * queues in which case it will return a reference to a 3588 * previously setup queue. We record the mapping from ac's 3589 * to h/w queues for use by ath_tx_start and also track 3590 * the set of h/w queues being used to optimize work in the 3591 * transmit interrupt handler and related routines. 3592 */ 3593static int 3594ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3595{ 3596#define N(a) (sizeof(a)/sizeof(a[0])) 3597 struct ath_txq *txq; 3598 3599 if (ac >= N(sc->sc_ac2q)) { 3600 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3601 ac, N(sc->sc_ac2q)); 3602 return 0; 3603 } 3604 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3605 if (txq != NULL) { 3606 txq->axq_ac = ac; 3607 sc->sc_ac2q[ac] = txq; 3608 return 1; 3609 } else 3610 return 0; 3611#undef N 3612} 3613 3614/* 3615 * Update WME parameters for a transmit queue. 3616 */ 3617static int 3618ath_txq_update(struct ath_softc *sc, int ac) 3619{ 3620#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3621#define ATH_TXOP_TO_US(v) (v<<5) 3622 struct ifnet *ifp = sc->sc_ifp; 3623 struct ieee80211com *ic = ifp->if_l2com; 3624 struct ath_txq *txq = sc->sc_ac2q[ac]; 3625 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3626 struct ath_hal *ah = sc->sc_ah; 3627 HAL_TXQ_INFO qi; 3628 3629 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3630#ifdef IEEE80211_SUPPORT_TDMA 3631 if (sc->sc_tdma) { 3632 /* 3633 * AIFS is zero so there's no pre-transmit wait. The 3634 * burst time defines the slot duration and is configured 3635 * through net80211. The QCU is setup to not do post-xmit 3636 * back off, lockout all lower-priority QCU's, and fire 3637 * off the DMA beacon alert timer which is setup based 3638 * on the slot configuration. 3639 */ 3640 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3641 | HAL_TXQ_TXERRINT_ENABLE 3642 | HAL_TXQ_TXURNINT_ENABLE 3643 | HAL_TXQ_TXEOLINT_ENABLE 3644 | HAL_TXQ_DBA_GATED 3645 | HAL_TXQ_BACKOFF_DISABLE 3646 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 3647 ; 3648 qi.tqi_aifs = 0; 3649 /* XXX +dbaprep? */ 3650 qi.tqi_readyTime = sc->sc_tdmaslotlen; 3651 qi.tqi_burstTime = qi.tqi_readyTime; 3652 } else { 3653#endif 3654 /* 3655 * XXX shouldn't this just use the default flags 3656 * used in the previous queue setup? 3657 */ 3658 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3659 | HAL_TXQ_TXERRINT_ENABLE 3660 | HAL_TXQ_TXDESCINT_ENABLE 3661 | HAL_TXQ_TXURNINT_ENABLE 3662 | HAL_TXQ_TXEOLINT_ENABLE 3663 ; 3664 qi.tqi_aifs = wmep->wmep_aifsn; 3665 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3666 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3667 qi.tqi_readyTime = 0; 3668 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3669#ifdef IEEE80211_SUPPORT_TDMA 3670 } 3671#endif 3672 3673 DPRINTF(sc, ATH_DEBUG_RESET, 3674 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 3675 __func__, txq->axq_qnum, qi.tqi_qflags, 3676 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 3677 3678 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3679 if_printf(ifp, "unable to update hardware queue " 3680 "parameters for %s traffic!\n", 3681 ieee80211_wme_acnames[ac]); 3682 return 0; 3683 } else { 3684 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3685 return 1; 3686 } 3687#undef ATH_TXOP_TO_US 3688#undef ATH_EXPONENT_TO_VALUE 3689} 3690 3691/* 3692 * Callback from the 802.11 layer to update WME parameters. 3693 */ 3694int 3695ath_wme_update(struct ieee80211com *ic) 3696{ 3697 struct ath_softc *sc = ic->ic_ifp->if_softc; 3698 3699 return !ath_txq_update(sc, WME_AC_BE) || 3700 !ath_txq_update(sc, WME_AC_BK) || 3701 !ath_txq_update(sc, WME_AC_VI) || 3702 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3703} 3704 3705/* 3706 * Reclaim resources for a setup queue. 3707 */ 3708static void 3709ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3710{ 3711 3712 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3713 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3714 ATH_TXQ_LOCK_DESTROY(txq); 3715} 3716 3717/* 3718 * Reclaim all tx queue resources. 3719 */ 3720static void 3721ath_tx_cleanup(struct ath_softc *sc) 3722{ 3723 int i; 3724 3725 ATH_TXBUF_LOCK_DESTROY(sc); 3726 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3727 if (ATH_TXQ_SETUP(sc, i)) 3728 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3729} 3730 3731/* 3732 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 3733 * using the current rates in sc_rixmap. 3734 */ 3735int 3736ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 3737{ 3738 int rix = sc->sc_rixmap[rate]; 3739 /* NB: return lowest rix for invalid rate */ 3740 return (rix == 0xff ? 0 : rix); 3741} 3742 3743static void 3744ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 3745 struct ath_buf *bf) 3746{ 3747 struct ieee80211_node *ni = bf->bf_node; 3748 struct ifnet *ifp = sc->sc_ifp; 3749 struct ieee80211com *ic = ifp->if_l2com; 3750 int sr, lr, pri; 3751 3752 if (ts->ts_status == 0) { 3753 u_int8_t txant = ts->ts_antenna; 3754 sc->sc_stats.ast_ant_tx[txant]++; 3755 sc->sc_ant_tx[txant]++; 3756 if (ts->ts_finaltsi != 0) 3757 sc->sc_stats.ast_tx_altrate++; 3758 pri = M_WME_GETAC(bf->bf_m); 3759 if (pri >= WME_AC_VO) 3760 ic->ic_wme.wme_hipri_traffic++; 3761 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 3762 ni->ni_inact = ni->ni_inact_reload; 3763 } else { 3764 if (ts->ts_status & HAL_TXERR_XRETRY) 3765 sc->sc_stats.ast_tx_xretries++; 3766 if (ts->ts_status & HAL_TXERR_FIFO) 3767 sc->sc_stats.ast_tx_fifoerr++; 3768 if (ts->ts_status & HAL_TXERR_FILT) 3769 sc->sc_stats.ast_tx_filtered++; 3770 if (ts->ts_status & HAL_TXERR_XTXOP) 3771 sc->sc_stats.ast_tx_xtxop++; 3772 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 3773 sc->sc_stats.ast_tx_timerexpired++; 3774 3775 if (bf->bf_m->m_flags & M_FF) 3776 sc->sc_stats.ast_ff_txerr++; 3777 } 3778 /* XXX when is this valid? */ 3779 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR) 3780 sc->sc_stats.ast_tx_desccfgerr++; 3781 /* 3782 * This can be valid for successful frame transmission! 3783 * If there's a TX FIFO underrun during aggregate transmission, 3784 * the MAC will pad the rest of the aggregate with delimiters. 3785 * If a BA is returned, the frame is marked as "OK" and it's up 3786 * to the TX completion code to notice which frames weren't 3787 * successfully transmitted. 3788 */ 3789 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN) 3790 sc->sc_stats.ast_tx_data_underrun++; 3791 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN) 3792 sc->sc_stats.ast_tx_delim_underrun++; 3793 3794 sr = ts->ts_shortretry; 3795 lr = ts->ts_longretry; 3796 sc->sc_stats.ast_tx_shortretry += sr; 3797 sc->sc_stats.ast_tx_longretry += lr; 3798 3799} 3800 3801/* 3802 * The default completion. If fail is 1, this means 3803 * "please don't retry the frame, and just return -1 status 3804 * to the net80211 stack. 3805 */ 3806void 3807ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3808{ 3809 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3810 int st; 3811 3812 if (fail == 1) 3813 st = -1; 3814 else 3815 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 3816 ts->ts_status : HAL_TXERR_XRETRY; 3817 3818#if 0 3819 if (bf->bf_state.bfs_dobaw) 3820 device_printf(sc->sc_dev, 3821 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 3822 __func__, 3823 bf, 3824 SEQNO(bf->bf_state.bfs_seqno)); 3825#endif 3826 if (bf->bf_next != NULL) 3827 device_printf(sc->sc_dev, 3828 "%s: bf %p: seqno %d: bf_next not NULL!\n", 3829 __func__, 3830 bf, 3831 SEQNO(bf->bf_state.bfs_seqno)); 3832 3833 /* 3834 * Check if the node software queue is empty; if so 3835 * then clear the TIM. 3836 * 3837 * This needs to be done before the buffer is freed as 3838 * otherwise the node reference will have been released 3839 * and the node may not actually exist any longer. 3840 * 3841 * XXX I don't like this belonging here, but it's cleaner 3842 * to do it here right now then all the other places 3843 * where ath_tx_default_comp() is called. 3844 * 3845 * XXX TODO: during drain, ensure that the callback is 3846 * being called so we get a chance to update the TIM. 3847 */ 3848 if (bf->bf_node) 3849 ath_tx_update_tim(sc, bf->bf_node, 0); 3850 3851 /* 3852 * Do any tx complete callback. Note this must 3853 * be done before releasing the node reference. 3854 * This will free the mbuf, release the net80211 3855 * node and recycle the ath_buf. 3856 */ 3857 ath_tx_freebuf(sc, bf, st); 3858} 3859 3860/* 3861 * Update rate control with the given completion status. 3862 */ 3863void 3864ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 3865 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 3866 int nframes, int nbad) 3867{ 3868 struct ath_node *an; 3869 3870 /* Only for unicast frames */ 3871 if (ni == NULL) 3872 return; 3873 3874 an = ATH_NODE(ni); 3875 ATH_NODE_UNLOCK_ASSERT(an); 3876 3877 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 3878 ATH_NODE_LOCK(an); 3879 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 3880 ATH_NODE_UNLOCK(an); 3881 } 3882} 3883 3884/* 3885 * Process the completion of the given buffer. 3886 * 3887 * This calls the rate control update and then the buffer completion. 3888 * This will either free the buffer or requeue it. In any case, the 3889 * bf pointer should be treated as invalid after this function is called. 3890 */ 3891void 3892ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq, 3893 struct ath_tx_status *ts, struct ath_buf *bf) 3894{ 3895 struct ieee80211_node *ni = bf->bf_node; 3896 struct ath_node *an = NULL; 3897 3898 ATH_TX_UNLOCK_ASSERT(sc); 3899 3900 /* If unicast frame, update general statistics */ 3901 if (ni != NULL) { 3902 an = ATH_NODE(ni); 3903 /* update statistics */ 3904 ath_tx_update_stats(sc, ts, bf); 3905 } 3906 3907 /* 3908 * Call the completion handler. 3909 * The completion handler is responsible for 3910 * calling the rate control code. 3911 * 3912 * Frames with no completion handler get the 3913 * rate control code called here. 3914 */ 3915 if (bf->bf_comp == NULL) { 3916 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 3917 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 3918 /* 3919 * XXX assume this isn't an aggregate 3920 * frame. 3921 */ 3922 ath_tx_update_ratectrl(sc, ni, 3923 bf->bf_state.bfs_rc, ts, 3924 bf->bf_state.bfs_pktlen, 1, 3925 (ts->ts_status == 0 ? 0 : 1)); 3926 } 3927 ath_tx_default_comp(sc, bf, 0); 3928 } else 3929 bf->bf_comp(sc, bf, 0); 3930} 3931 3932 3933 3934/* 3935 * Process completed xmit descriptors from the specified queue. 3936 * Kick the packet scheduler if needed. This can occur from this 3937 * particular task. 3938 */ 3939static int 3940ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 3941{ 3942 struct ath_hal *ah = sc->sc_ah; 3943 struct ath_buf *bf; 3944 struct ath_desc *ds; 3945 struct ath_tx_status *ts; 3946 struct ieee80211_node *ni; 3947#ifdef IEEE80211_SUPPORT_SUPERG 3948 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3949#endif /* IEEE80211_SUPPORT_SUPERG */ 3950 int nacked; 3951 HAL_STATUS status; 3952 3953 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3954 __func__, txq->axq_qnum, 3955 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3956 txq->axq_link); 3957 3958 ATH_KTR(sc, ATH_KTR_TXCOMP, 4, 3959 "ath_tx_processq: txq=%u head %p link %p depth %p", 3960 txq->axq_qnum, 3961 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3962 txq->axq_link, 3963 txq->axq_depth); 3964 3965 nacked = 0; 3966 for (;;) { 3967 ATH_TXQ_LOCK(txq); 3968 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3969 bf = TAILQ_FIRST(&txq->axq_q); 3970 if (bf == NULL) { 3971 ATH_TXQ_UNLOCK(txq); 3972 break; 3973 } 3974 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 3975 ts = &bf->bf_status.ds_txstat; 3976 3977 status = ath_hal_txprocdesc(ah, ds, ts); 3978#ifdef ATH_DEBUG 3979 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3980 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3981 status == HAL_OK); 3982 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) 3983 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3984 status == HAL_OK); 3985#endif 3986#ifdef ATH_DEBUG_ALQ 3987 if (if_ath_alq_checkdebug(&sc->sc_alq, 3988 ATH_ALQ_EDMA_TXSTATUS)) { 3989 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 3990 sc->sc_tx_statuslen, 3991 (char *) ds); 3992 } 3993#endif 3994 3995 if (status == HAL_EINPROGRESS) { 3996 ATH_KTR(sc, ATH_KTR_TXCOMP, 3, 3997 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS", 3998 txq->axq_qnum, bf, ds); 3999 ATH_TXQ_UNLOCK(txq); 4000 break; 4001 } 4002 ATH_TXQ_REMOVE(txq, bf, bf_list); 4003 4004 /* 4005 * Always mark the last buffer in this list as busy. 4006 * 4007 * The hardware may re-read the holding descriptor 4008 * even if we hit the end of the list and try writing 4009 * a new TxDP. 4010 * 4011 * If there's no holding descriptor then this is the 4012 * last buffer in the list of buffers after a fresh 4013 * reset; it'll soon become the holding buffer. 4014 */ 4015 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4016 4017 if (bf->bf_state.bfs_aggr) 4018 txq->axq_aggr_depth--; 4019 4020 ni = bf->bf_node; 4021 4022 ATH_KTR(sc, ATH_KTR_TXCOMP, 5, 4023 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x", 4024 txq->axq_qnum, bf, ds, ni, ts->ts_status); 4025 /* 4026 * If unicast frame was ack'd update RSSI, 4027 * including the last rx time used to 4028 * workaround phantom bmiss interrupts. 4029 */ 4030 if (ni != NULL && ts->ts_status == 0 && 4031 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 4032 nacked++; 4033 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4034 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4035 ts->ts_rssi); 4036 } 4037 ATH_TXQ_UNLOCK(txq); 4038 4039 /* 4040 * Update statistics and call completion 4041 */ 4042 ath_tx_process_buf_completion(sc, txq, ts, bf); 4043 4044 /* XXX at this point, bf and ni may be totally invalid */ 4045 } 4046#ifdef IEEE80211_SUPPORT_SUPERG 4047 /* 4048 * Flush fast-frame staging queue when traffic slows. 4049 */ 4050 if (txq->axq_depth <= 1) 4051 ieee80211_ff_flush(ic, txq->axq_ac); 4052#endif 4053 4054 /* Kick the software TXQ scheduler */ 4055 if (dosched) { 4056 ATH_TX_LOCK(sc); 4057 ath_txq_sched(sc, txq); 4058 ATH_TX_UNLOCK(sc); 4059 } 4060 4061 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4062 "ath_tx_processq: txq=%u: done", 4063 txq->axq_qnum); 4064 4065 return nacked; 4066} 4067 4068#define TXQACTIVE(t, q) ( (t) & (1 << (q))) 4069 4070/* 4071 * Deferred processing of transmit interrupt; special-cased 4072 * for a single hardware transmit queue (e.g. 5210 and 5211). 4073 */ 4074static void 4075ath_tx_proc_q0(void *arg, int npending) 4076{ 4077 struct ath_softc *sc = arg; 4078 struct ifnet *ifp = sc->sc_ifp; 4079 uint32_t txqs; 4080 4081 ATH_PCU_LOCK(sc); 4082 sc->sc_txproc_cnt++; 4083 txqs = sc->sc_txq_active; 4084 sc->sc_txq_active &= ~txqs; 4085 ATH_PCU_UNLOCK(sc); 4086 4087 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4088 "ath_tx_proc_q0: txqs=0x%08x", txqs); 4089 4090 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 4091 /* XXX why is lastrx updated in tx code? */ 4092 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4093 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4094 ath_tx_processq(sc, sc->sc_cabq, 1); 4095 IF_LOCK(&ifp->if_snd); 4096 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4097 IF_UNLOCK(&ifp->if_snd); 4098 sc->sc_wd_timer = 0; 4099 4100 if (sc->sc_softled) 4101 ath_led_event(sc, sc->sc_txrix); 4102 4103 ATH_PCU_LOCK(sc); 4104 sc->sc_txproc_cnt--; 4105 ATH_PCU_UNLOCK(sc); 4106 4107 ath_tx_kick(sc); 4108} 4109 4110/* 4111 * Deferred processing of transmit interrupt; special-cased 4112 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4113 */ 4114static void 4115ath_tx_proc_q0123(void *arg, int npending) 4116{ 4117 struct ath_softc *sc = arg; 4118 struct ifnet *ifp = sc->sc_ifp; 4119 int nacked; 4120 uint32_t txqs; 4121 4122 ATH_PCU_LOCK(sc); 4123 sc->sc_txproc_cnt++; 4124 txqs = sc->sc_txq_active; 4125 sc->sc_txq_active &= ~txqs; 4126 ATH_PCU_UNLOCK(sc); 4127 4128 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4129 "ath_tx_proc_q0123: txqs=0x%08x", txqs); 4130 4131 /* 4132 * Process each active queue. 4133 */ 4134 nacked = 0; 4135 if (TXQACTIVE(txqs, 0)) 4136 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 4137 if (TXQACTIVE(txqs, 1)) 4138 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 4139 if (TXQACTIVE(txqs, 2)) 4140 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 4141 if (TXQACTIVE(txqs, 3)) 4142 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 4143 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4144 ath_tx_processq(sc, sc->sc_cabq, 1); 4145 if (nacked) 4146 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4147 4148 IF_LOCK(&ifp->if_snd); 4149 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4150 IF_UNLOCK(&ifp->if_snd); 4151 sc->sc_wd_timer = 0; 4152 4153 if (sc->sc_softled) 4154 ath_led_event(sc, sc->sc_txrix); 4155 4156 ATH_PCU_LOCK(sc); 4157 sc->sc_txproc_cnt--; 4158 ATH_PCU_UNLOCK(sc); 4159 4160 ath_tx_kick(sc); 4161} 4162 4163/* 4164 * Deferred processing of transmit interrupt. 4165 */ 4166static void 4167ath_tx_proc(void *arg, int npending) 4168{ 4169 struct ath_softc *sc = arg; 4170 struct ifnet *ifp = sc->sc_ifp; 4171 int i, nacked; 4172 uint32_t txqs; 4173 4174 ATH_PCU_LOCK(sc); 4175 sc->sc_txproc_cnt++; 4176 txqs = sc->sc_txq_active; 4177 sc->sc_txq_active &= ~txqs; 4178 ATH_PCU_UNLOCK(sc); 4179 4180 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs); 4181 4182 /* 4183 * Process each active queue. 4184 */ 4185 nacked = 0; 4186 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4187 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 4188 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 4189 if (nacked) 4190 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4191 4192 /* XXX check this inside of IF_LOCK? */ 4193 IF_LOCK(&ifp->if_snd); 4194 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4195 IF_UNLOCK(&ifp->if_snd); 4196 sc->sc_wd_timer = 0; 4197 4198 if (sc->sc_softled) 4199 ath_led_event(sc, sc->sc_txrix); 4200 4201 ATH_PCU_LOCK(sc); 4202 sc->sc_txproc_cnt--; 4203 ATH_PCU_UNLOCK(sc); 4204 4205 ath_tx_kick(sc); 4206} 4207#undef TXQACTIVE 4208 4209/* 4210 * Deferred processing of TXQ rescheduling. 4211 */ 4212static void 4213ath_txq_sched_tasklet(void *arg, int npending) 4214{ 4215 struct ath_softc *sc = arg; 4216 int i; 4217 4218 /* XXX is skipping ok? */ 4219 ATH_PCU_LOCK(sc); 4220#if 0 4221 if (sc->sc_inreset_cnt > 0) { 4222 device_printf(sc->sc_dev, 4223 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 4224 ATH_PCU_UNLOCK(sc); 4225 return; 4226 } 4227#endif 4228 sc->sc_txproc_cnt++; 4229 ATH_PCU_UNLOCK(sc); 4230 4231 ATH_TX_LOCK(sc); 4232 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4233 if (ATH_TXQ_SETUP(sc, i)) { 4234 ath_txq_sched(sc, &sc->sc_txq[i]); 4235 } 4236 } 4237 ATH_TX_UNLOCK(sc); 4238 4239 ATH_PCU_LOCK(sc); 4240 sc->sc_txproc_cnt--; 4241 ATH_PCU_UNLOCK(sc); 4242} 4243 4244void 4245ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf) 4246{ 4247 4248 ATH_TXBUF_LOCK_ASSERT(sc); 4249 4250 if (bf->bf_flags & ATH_BUF_MGMT) 4251 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list); 4252 else { 4253 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4254 sc->sc_txbuf_cnt++; 4255 if (sc->sc_txbuf_cnt > ath_txbuf) { 4256 device_printf(sc->sc_dev, 4257 "%s: sc_txbuf_cnt > %d?\n", 4258 __func__, 4259 ath_txbuf); 4260 sc->sc_txbuf_cnt = ath_txbuf; 4261 } 4262 } 4263} 4264 4265void 4266ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf) 4267{ 4268 4269 ATH_TXBUF_LOCK_ASSERT(sc); 4270 4271 if (bf->bf_flags & ATH_BUF_MGMT) 4272 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list); 4273 else { 4274 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 4275 sc->sc_txbuf_cnt++; 4276 if (sc->sc_txbuf_cnt > ATH_TXBUF) { 4277 device_printf(sc->sc_dev, 4278 "%s: sc_txbuf_cnt > %d?\n", 4279 __func__, 4280 ATH_TXBUF); 4281 sc->sc_txbuf_cnt = ATH_TXBUF; 4282 } 4283 } 4284} 4285 4286/* 4287 * Free the holding buffer if it exists 4288 */ 4289void 4290ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq) 4291{ 4292 ATH_TXBUF_LOCK_ASSERT(sc); 4293 4294 if (txq->axq_holdingbf == NULL) 4295 return; 4296 4297 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY; 4298 ath_returnbuf_tail(sc, txq->axq_holdingbf); 4299 txq->axq_holdingbf = NULL; 4300} 4301 4302/* 4303 * Add this buffer to the holding queue, freeing the previous 4304 * one if it exists. 4305 */ 4306static void 4307ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf) 4308{ 4309 struct ath_txq *txq; 4310 4311 ATH_TXBUF_LOCK_ASSERT(sc); 4312 4313 /* XXX assert ATH_BUF_BUSY is set */ 4314 4315 /* XXX assert the tx queue is under the max number */ 4316 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) { 4317 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n", 4318 __func__, 4319 bf, 4320 bf->bf_state.bfs_tx_queue); 4321 bf->bf_flags &= ~ATH_BUF_BUSY; 4322 ath_returnbuf_tail(sc, bf); 4323 return; 4324 } 4325 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4326 ath_txq_freeholdingbuf(sc, txq); 4327 txq->axq_holdingbf = bf; 4328} 4329 4330/* 4331 * Return a buffer to the pool and update the 'busy' flag on the 4332 * previous 'tail' entry. 4333 * 4334 * This _must_ only be called when the buffer is involved in a completed 4335 * TX. The logic is that if it was part of an active TX, the previous 4336 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4337 * for restart (eg for TDMA.) 4338 * 4339 * The caller must free the mbuf and recycle the node reference. 4340 */ 4341void 4342ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4343{ 4344 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4345 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4346 4347 /* 4348 * If this buffer is busy, push it onto the holding queue 4349 */ 4350 if (bf->bf_flags & ATH_BUF_BUSY) { 4351 ATH_TXBUF_LOCK(sc); 4352 ath_txq_addholdingbuf(sc, bf); 4353 ATH_TXBUF_UNLOCK(sc); 4354 return; 4355 } 4356 4357 /* 4358 * Not a busy buffer, so free normally 4359 */ 4360 ATH_TXBUF_LOCK(sc); 4361 ath_returnbuf_tail(sc, bf); 4362 ATH_TXBUF_UNLOCK(sc); 4363} 4364 4365/* 4366 * This is currently used by ath_tx_draintxq() and 4367 * ath_tx_tid_free_pkts(). 4368 * 4369 * It recycles a single ath_buf. 4370 */ 4371void 4372ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4373{ 4374 struct ieee80211_node *ni = bf->bf_node; 4375 struct mbuf *m0 = bf->bf_m; 4376 4377 /* 4378 * Make sure that we only sync/unload if there's an mbuf. 4379 * If not (eg we cloned a buffer), the unload will have already 4380 * occured. 4381 */ 4382 if (bf->bf_m != NULL) { 4383 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4384 BUS_DMASYNC_POSTWRITE); 4385 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4386 } 4387 4388 bf->bf_node = NULL; 4389 bf->bf_m = NULL; 4390 4391 /* Free the buffer, it's not needed any longer */ 4392 ath_freebuf(sc, bf); 4393 4394 if (ni != NULL) { 4395 /* 4396 * Do any callback and reclaim the node reference. 4397 */ 4398 if (m0->m_flags & M_TXCB) 4399 ieee80211_process_callback(ni, m0, status); 4400 ieee80211_free_node(ni); 4401 } 4402 4403 /* Finally, we don't need this mbuf any longer */ 4404 m_freem(m0); 4405} 4406 4407static struct ath_buf * 4408ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq) 4409{ 4410 struct ath_buf *bf; 4411 4412 ATH_TXQ_LOCK_ASSERT(txq); 4413 4414 /* 4415 * Drain the FIFO queue first, then if it's 4416 * empty, move to the normal frame queue. 4417 */ 4418 bf = TAILQ_FIRST(&txq->fifo.axq_q); 4419 if (bf != NULL) { 4420 /* 4421 * Is it the last buffer in this set? 4422 * Decrement the FIFO counter. 4423 */ 4424 if (bf->bf_flags & ATH_BUF_FIFOEND) { 4425 if (txq->axq_fifo_depth == 0) { 4426 device_printf(sc->sc_dev, 4427 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n", 4428 __func__, 4429 txq->axq_qnum, 4430 txq->fifo.axq_depth); 4431 } else 4432 txq->axq_fifo_depth--; 4433 } 4434 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list); 4435 return (bf); 4436 } 4437 4438 /* 4439 * Debugging! 4440 */ 4441 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) { 4442 device_printf(sc->sc_dev, 4443 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n", 4444 __func__, 4445 txq->axq_qnum, 4446 txq->axq_fifo_depth, 4447 txq->fifo.axq_depth); 4448 } 4449 4450 /* 4451 * Now drain the pending queue. 4452 */ 4453 bf = TAILQ_FIRST(&txq->axq_q); 4454 if (bf == NULL) { 4455 txq->axq_link = NULL; 4456 return (NULL); 4457 } 4458 ATH_TXQ_REMOVE(txq, bf, bf_list); 4459 return (bf); 4460} 4461 4462void 4463ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4464{ 4465#ifdef ATH_DEBUG 4466 struct ath_hal *ah = sc->sc_ah; 4467#endif 4468 struct ath_buf *bf; 4469 u_int ix; 4470 4471 /* 4472 * NB: this assumes output has been stopped and 4473 * we do not need to block ath_tx_proc 4474 */ 4475 for (ix = 0;; ix++) { 4476 ATH_TXQ_LOCK(txq); 4477 bf = ath_tx_draintxq_get_one(sc, txq); 4478 if (bf == NULL) { 4479 ATH_TXQ_UNLOCK(txq); 4480 break; 4481 } 4482 if (bf->bf_state.bfs_aggr) 4483 txq->axq_aggr_depth--; 4484#ifdef ATH_DEBUG 4485 if (sc->sc_debug & ATH_DEBUG_RESET) { 4486 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 4487 int status = 0; 4488 4489 /* 4490 * EDMA operation has a TX completion FIFO 4491 * separate from the TX descriptor, so this 4492 * method of checking the "completion" status 4493 * is wrong. 4494 */ 4495 if (! sc->sc_isedma) { 4496 status = (ath_hal_txprocdesc(ah, 4497 bf->bf_lastds, 4498 &bf->bf_status.ds_txstat) == HAL_OK); 4499 } 4500 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status); 4501 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 4502 bf->bf_m->m_len, 0, -1); 4503 } 4504#endif /* ATH_DEBUG */ 4505 /* 4506 * Since we're now doing magic in the completion 4507 * functions, we -must- call it for aggregation 4508 * destinations or BAW tracking will get upset. 4509 */ 4510 /* 4511 * Clear ATH_BUF_BUSY; the completion handler 4512 * will free the buffer. 4513 */ 4514 ATH_TXQ_UNLOCK(txq); 4515 bf->bf_flags &= ~ATH_BUF_BUSY; 4516 if (bf->bf_comp) 4517 bf->bf_comp(sc, bf, 1); 4518 else 4519 ath_tx_default_comp(sc, bf, 1); 4520 } 4521 4522 /* 4523 * Free the holding buffer if it exists 4524 */ 4525 ATH_TXBUF_LOCK(sc); 4526 ath_txq_freeholdingbuf(sc, txq); 4527 ATH_TXBUF_UNLOCK(sc); 4528 4529 /* 4530 * Drain software queued frames which are on 4531 * active TIDs. 4532 */ 4533 ath_tx_txq_drain(sc, txq); 4534} 4535 4536static void 4537ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4538{ 4539 struct ath_hal *ah = sc->sc_ah; 4540 4541 DPRINTF(sc, ATH_DEBUG_RESET, 4542 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, link %p\n", 4543 __func__, 4544 txq->axq_qnum, 4545 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4546 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)), 4547 (int) ath_hal_numtxpending(ah, txq->axq_qnum), 4548 txq->axq_flags, 4549 txq->axq_link); 4550 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4551} 4552 4553int 4554ath_stoptxdma(struct ath_softc *sc) 4555{ 4556 struct ath_hal *ah = sc->sc_ah; 4557 int i; 4558 4559 /* XXX return value */ 4560 if (sc->sc_invalid) 4561 return 0; 4562 4563 if (!sc->sc_invalid) { 4564 /* don't touch the hardware if marked invalid */ 4565 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4566 __func__, sc->sc_bhalq, 4567 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4568 NULL); 4569 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4570 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4571 if (ATH_TXQ_SETUP(sc, i)) 4572 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4573 } 4574 4575 return 1; 4576} 4577 4578#ifdef ATH_DEBUG 4579static void 4580ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq) 4581{ 4582 struct ath_hal *ah = sc->sc_ah; 4583 struct ath_buf *bf; 4584 int i = 0; 4585 4586 if (! (sc->sc_debug & ATH_DEBUG_RESET)) 4587 return; 4588 4589 device_printf(sc->sc_dev, "%s: Q%d: begin\n", 4590 __func__, txq->axq_qnum); 4591 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 4592 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 4593 ath_hal_txprocdesc(ah, bf->bf_lastds, 4594 &bf->bf_status.ds_txstat) == HAL_OK); 4595 i++; 4596 } 4597 device_printf(sc->sc_dev, "%s: Q%d: end\n", 4598 __func__, txq->axq_qnum); 4599} 4600#endif /* ATH_DEBUG */ 4601 4602/* 4603 * Drain the transmit queues and reclaim resources. 4604 */ 4605void 4606ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 4607{ 4608#ifdef ATH_DEBUG 4609 struct ath_hal *ah = sc->sc_ah; 4610#endif 4611 struct ifnet *ifp = sc->sc_ifp; 4612 int i; 4613 4614 (void) ath_stoptxdma(sc); 4615 4616 /* 4617 * Dump the queue contents 4618 */ 4619 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4620 /* 4621 * XXX TODO: should we just handle the completed TX frames 4622 * here, whether or not the reset is a full one or not? 4623 */ 4624 if (ATH_TXQ_SETUP(sc, i)) { 4625#ifdef ATH_DEBUG 4626 if (sc->sc_debug & ATH_DEBUG_RESET) 4627 ath_tx_dump(sc, &sc->sc_txq[i]); 4628#endif /* ATH_DEBUG */ 4629 if (reset_type == ATH_RESET_NOLOSS) 4630 ath_tx_processq(sc, &sc->sc_txq[i], 0); 4631 else 4632 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4633 } 4634 } 4635#ifdef ATH_DEBUG 4636 if (sc->sc_debug & ATH_DEBUG_RESET) { 4637 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 4638 if (bf != NULL && bf->bf_m != NULL) { 4639 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 4640 ath_hal_txprocdesc(ah, bf->bf_lastds, 4641 &bf->bf_status.ds_txstat) == HAL_OK); 4642 ieee80211_dump_pkt(ifp->if_l2com, 4643 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 4644 0, -1); 4645 } 4646 } 4647#endif /* ATH_DEBUG */ 4648 IF_LOCK(&ifp->if_snd); 4649 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4650 IF_UNLOCK(&ifp->if_snd); 4651 sc->sc_wd_timer = 0; 4652} 4653 4654/* 4655 * Update internal state after a channel change. 4656 */ 4657static void 4658ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4659{ 4660 enum ieee80211_phymode mode; 4661 4662 /* 4663 * Change channels and update the h/w rate map 4664 * if we're switching; e.g. 11a to 11b/g. 4665 */ 4666 mode = ieee80211_chan2mode(chan); 4667 if (mode != sc->sc_curmode) 4668 ath_setcurmode(sc, mode); 4669 sc->sc_curchan = chan; 4670} 4671 4672/* 4673 * Set/change channels. If the channel is really being changed, 4674 * it's done by resetting the chip. To accomplish this we must 4675 * first cleanup any pending DMA, then restart stuff after a la 4676 * ath_init. 4677 */ 4678static int 4679ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4680{ 4681 struct ifnet *ifp = sc->sc_ifp; 4682 struct ieee80211com *ic = ifp->if_l2com; 4683 struct ath_hal *ah = sc->sc_ah; 4684 int ret = 0; 4685 4686 /* Treat this as an interface reset */ 4687 ATH_PCU_UNLOCK_ASSERT(sc); 4688 ATH_UNLOCK_ASSERT(sc); 4689 4690 /* (Try to) stop TX/RX from occuring */ 4691 taskqueue_block(sc->sc_tq); 4692 4693 ATH_PCU_LOCK(sc); 4694 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */ 4695 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */ 4696 if (ath_reset_grablock(sc, 1) == 0) { 4697 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 4698 __func__); 4699 } 4700 ATH_PCU_UNLOCK(sc); 4701 4702 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 4703 __func__, ieee80211_chan2ieee(ic, chan), 4704 chan->ic_freq, chan->ic_flags); 4705 if (chan != sc->sc_curchan) { 4706 HAL_STATUS status; 4707 /* 4708 * To switch channels clear any pending DMA operations; 4709 * wait long enough for the RX fifo to drain, reset the 4710 * hardware at the new frequency, and then re-enable 4711 * the relevant bits of the h/w. 4712 */ 4713#if 0 4714 ath_hal_intrset(ah, 0); /* disable interrupts */ 4715#endif 4716 ath_stoprecv(sc, 1); /* turn off frame recv */ 4717 /* 4718 * First, handle completed TX/RX frames. 4719 */ 4720 ath_rx_flush(sc); 4721 ath_draintxq(sc, ATH_RESET_NOLOSS); 4722 /* 4723 * Next, flush the non-scheduled frames. 4724 */ 4725 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 4726 4727 ath_update_chainmasks(sc, chan); 4728 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 4729 sc->sc_cur_rxchainmask); 4730 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 4731 if_printf(ifp, "%s: unable to reset " 4732 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 4733 __func__, ieee80211_chan2ieee(ic, chan), 4734 chan->ic_freq, chan->ic_flags, status); 4735 ret = EIO; 4736 goto finish; 4737 } 4738 sc->sc_diversity = ath_hal_getdiversity(ah); 4739 4740 /* Let DFS at it in case it's a DFS channel */ 4741 ath_dfs_radar_enable(sc, chan); 4742 4743 /* Let spectral at in case spectral is enabled */ 4744 ath_spectral_enable(sc, chan); 4745 4746 /* 4747 * Re-enable rx framework. 4748 */ 4749 if (ath_startrecv(sc) != 0) { 4750 if_printf(ifp, "%s: unable to restart recv logic\n", 4751 __func__); 4752 ret = EIO; 4753 goto finish; 4754 } 4755 4756 /* 4757 * Change channels and update the h/w rate map 4758 * if we're switching; e.g. 11a to 11b/g. 4759 */ 4760 ath_chan_change(sc, chan); 4761 4762 /* 4763 * Reset clears the beacon timers; reset them 4764 * here if needed. 4765 */ 4766 if (sc->sc_beacons) { /* restart beacons */ 4767#ifdef IEEE80211_SUPPORT_TDMA 4768 if (sc->sc_tdma) 4769 ath_tdma_config(sc, NULL); 4770 else 4771#endif 4772 ath_beacon_config(sc, NULL); 4773 } 4774 4775 /* 4776 * Re-enable interrupts. 4777 */ 4778#if 0 4779 ath_hal_intrset(ah, sc->sc_imask); 4780#endif 4781 } 4782 4783finish: 4784 ATH_PCU_LOCK(sc); 4785 sc->sc_inreset_cnt--; 4786 /* XXX only do this if sc_inreset_cnt == 0? */ 4787 ath_hal_intrset(ah, sc->sc_imask); 4788 ATH_PCU_UNLOCK(sc); 4789 4790 IF_LOCK(&ifp->if_snd); 4791 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4792 IF_UNLOCK(&ifp->if_snd); 4793 ath_txrx_start(sc); 4794 /* XXX ath_start? */ 4795 4796 return ret; 4797} 4798 4799/* 4800 * Periodically recalibrate the PHY to account 4801 * for temperature/environment changes. 4802 */ 4803static void 4804ath_calibrate(void *arg) 4805{ 4806 struct ath_softc *sc = arg; 4807 struct ath_hal *ah = sc->sc_ah; 4808 struct ifnet *ifp = sc->sc_ifp; 4809 struct ieee80211com *ic = ifp->if_l2com; 4810 HAL_BOOL longCal, isCalDone = AH_TRUE; 4811 HAL_BOOL aniCal, shortCal = AH_FALSE; 4812 int nextcal; 4813 4814 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 4815 goto restart; 4816 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 4817 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 4818 if (sc->sc_doresetcal) 4819 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 4820 4821 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 4822 if (aniCal) { 4823 sc->sc_stats.ast_ani_cal++; 4824 sc->sc_lastani = ticks; 4825 ath_hal_ani_poll(ah, sc->sc_curchan); 4826 } 4827 4828 if (longCal) { 4829 sc->sc_stats.ast_per_cal++; 4830 sc->sc_lastlongcal = ticks; 4831 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4832 /* 4833 * Rfgain is out of bounds, reset the chip 4834 * to load new gain values. 4835 */ 4836 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4837 "%s: rfgain change\n", __func__); 4838 sc->sc_stats.ast_per_rfgain++; 4839 sc->sc_resetcal = 0; 4840 sc->sc_doresetcal = AH_TRUE; 4841 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 4842 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 4843 return; 4844 } 4845 /* 4846 * If this long cal is after an idle period, then 4847 * reset the data collection state so we start fresh. 4848 */ 4849 if (sc->sc_resetcal) { 4850 (void) ath_hal_calreset(ah, sc->sc_curchan); 4851 sc->sc_lastcalreset = ticks; 4852 sc->sc_lastshortcal = ticks; 4853 sc->sc_resetcal = 0; 4854 sc->sc_doresetcal = AH_TRUE; 4855 } 4856 } 4857 4858 /* Only call if we're doing a short/long cal, not for ANI calibration */ 4859 if (shortCal || longCal) { 4860 isCalDone = AH_FALSE; 4861 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 4862 if (longCal) { 4863 /* 4864 * Calibrate noise floor data again in case of change. 4865 */ 4866 ath_hal_process_noisefloor(ah); 4867 } 4868 } else { 4869 DPRINTF(sc, ATH_DEBUG_ANY, 4870 "%s: calibration of channel %u failed\n", 4871 __func__, sc->sc_curchan->ic_freq); 4872 sc->sc_stats.ast_per_calfail++; 4873 } 4874 if (shortCal) 4875 sc->sc_lastshortcal = ticks; 4876 } 4877 if (!isCalDone) { 4878restart: 4879 /* 4880 * Use a shorter interval to potentially collect multiple 4881 * data samples required to complete calibration. Once 4882 * we're told the work is done we drop back to a longer 4883 * interval between requests. We're more aggressive doing 4884 * work when operating as an AP to improve operation right 4885 * after startup. 4886 */ 4887 sc->sc_lastshortcal = ticks; 4888 nextcal = ath_shortcalinterval*hz/1000; 4889 if (sc->sc_opmode != HAL_M_HOSTAP) 4890 nextcal *= 10; 4891 sc->sc_doresetcal = AH_TRUE; 4892 } else { 4893 /* nextcal should be the shortest time for next event */ 4894 nextcal = ath_longcalinterval*hz; 4895 if (sc->sc_lastcalreset == 0) 4896 sc->sc_lastcalreset = sc->sc_lastlongcal; 4897 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 4898 sc->sc_resetcal = 1; /* setup reset next trip */ 4899 sc->sc_doresetcal = AH_FALSE; 4900 } 4901 /* ANI calibration may occur more often than short/long/resetcal */ 4902 if (ath_anicalinterval > 0) 4903 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 4904 4905 if (nextcal != 0) { 4906 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 4907 __func__, nextcal, isCalDone ? "" : "!"); 4908 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 4909 } else { 4910 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 4911 __func__); 4912 /* NB: don't rearm timer */ 4913 } 4914} 4915 4916static void 4917ath_scan_start(struct ieee80211com *ic) 4918{ 4919 struct ifnet *ifp = ic->ic_ifp; 4920 struct ath_softc *sc = ifp->if_softc; 4921 struct ath_hal *ah = sc->sc_ah; 4922 u_int32_t rfilt; 4923 4924 /* XXX calibration timer? */ 4925 4926 ATH_LOCK(sc); 4927 sc->sc_scanning = 1; 4928 sc->sc_syncbeacon = 0; 4929 rfilt = ath_calcrxfilter(sc); 4930 ATH_UNLOCK(sc); 4931 4932 ATH_PCU_LOCK(sc); 4933 ath_hal_setrxfilter(ah, rfilt); 4934 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 4935 ATH_PCU_UNLOCK(sc); 4936 4937 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 4938 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 4939} 4940 4941static void 4942ath_scan_end(struct ieee80211com *ic) 4943{ 4944 struct ifnet *ifp = ic->ic_ifp; 4945 struct ath_softc *sc = ifp->if_softc; 4946 struct ath_hal *ah = sc->sc_ah; 4947 u_int32_t rfilt; 4948 4949 ATH_LOCK(sc); 4950 sc->sc_scanning = 0; 4951 rfilt = ath_calcrxfilter(sc); 4952 ATH_UNLOCK(sc); 4953 4954 ATH_PCU_LOCK(sc); 4955 ath_hal_setrxfilter(ah, rfilt); 4956 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4957 4958 ath_hal_process_noisefloor(ah); 4959 ATH_PCU_UNLOCK(sc); 4960 4961 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4962 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 4963 sc->sc_curaid); 4964} 4965 4966#ifdef ATH_ENABLE_11N 4967/* 4968 * For now, just do a channel change. 4969 * 4970 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 4971 * control state and resetting the hardware without dropping frames out 4972 * of the queue. 4973 * 4974 * The unfortunate trouble here is making absolutely sure that the 4975 * channel width change has propagated enough so the hardware 4976 * absolutely isn't handed bogus frames for it's current operating 4977 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 4978 * does occur in parallel, we need to make certain we've blocked 4979 * any further ongoing TX (and RX, that can cause raw TX) 4980 * before we do this. 4981 */ 4982static void 4983ath_update_chw(struct ieee80211com *ic) 4984{ 4985 struct ifnet *ifp = ic->ic_ifp; 4986 struct ath_softc *sc = ifp->if_softc; 4987 4988 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 4989 ath_set_channel(ic); 4990} 4991#endif /* ATH_ENABLE_11N */ 4992 4993static void 4994ath_set_channel(struct ieee80211com *ic) 4995{ 4996 struct ifnet *ifp = ic->ic_ifp; 4997 struct ath_softc *sc = ifp->if_softc; 4998 4999 (void) ath_chan_set(sc, ic->ic_curchan); 5000 /* 5001 * If we are returning to our bss channel then mark state 5002 * so the next recv'd beacon's tsf will be used to sync the 5003 * beacon timers. Note that since we only hear beacons in 5004 * sta/ibss mode this has no effect in other operating modes. 5005 */ 5006 ATH_LOCK(sc); 5007 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5008 sc->sc_syncbeacon = 1; 5009 ATH_UNLOCK(sc); 5010} 5011 5012/* 5013 * Walk the vap list and check if there any vap's in RUN state. 5014 */ 5015static int 5016ath_isanyrunningvaps(struct ieee80211vap *this) 5017{ 5018 struct ieee80211com *ic = this->iv_ic; 5019 struct ieee80211vap *vap; 5020 5021 IEEE80211_LOCK_ASSERT(ic); 5022 5023 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5024 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5025 return 1; 5026 } 5027 return 0; 5028} 5029 5030static int 5031ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5032{ 5033 struct ieee80211com *ic = vap->iv_ic; 5034 struct ath_softc *sc = ic->ic_ifp->if_softc; 5035 struct ath_vap *avp = ATH_VAP(vap); 5036 struct ath_hal *ah = sc->sc_ah; 5037 struct ieee80211_node *ni = NULL; 5038 int i, error, stamode; 5039 u_int32_t rfilt; 5040 int csa_run_transition = 0; 5041 5042 static const HAL_LED_STATE leds[] = { 5043 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5044 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5045 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5046 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5047 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5048 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5049 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5050 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5051 }; 5052 5053 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5054 ieee80211_state_name[vap->iv_state], 5055 ieee80211_state_name[nstate]); 5056 5057 /* 5058 * net80211 _should_ have the comlock asserted at this point. 5059 * There are some comments around the calls to vap->iv_newstate 5060 * which indicate that it (newstate) may end up dropping the 5061 * lock. This and the subsequent lock assert check after newstate 5062 * are an attempt to catch these and figure out how/why. 5063 */ 5064 IEEE80211_LOCK_ASSERT(ic); 5065 5066 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 5067 csa_run_transition = 1; 5068 5069 callout_drain(&sc->sc_cal_ch); 5070 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5071 5072 if (nstate == IEEE80211_S_SCAN) { 5073 /* 5074 * Scanning: turn off beacon miss and don't beacon. 5075 * Mark beacon state so when we reach RUN state we'll 5076 * [re]setup beacons. Unblock the task q thread so 5077 * deferred interrupt processing is done. 5078 */ 5079 ath_hal_intrset(ah, 5080 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5081 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5082 sc->sc_beacons = 0; 5083 taskqueue_unblock(sc->sc_tq); 5084 } 5085 5086 ni = ieee80211_ref_node(vap->iv_bss); 5087 rfilt = ath_calcrxfilter(sc); 5088 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5089 vap->iv_opmode == IEEE80211_M_AHDEMO || 5090 vap->iv_opmode == IEEE80211_M_IBSS); 5091 if (stamode && nstate == IEEE80211_S_RUN) { 5092 sc->sc_curaid = ni->ni_associd; 5093 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5094 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5095 } 5096 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5097 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5098 ath_hal_setrxfilter(ah, rfilt); 5099 5100 /* XXX is this to restore keycache on resume? */ 5101 if (vap->iv_opmode != IEEE80211_M_STA && 5102 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5103 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5104 if (ath_hal_keyisvalid(ah, i)) 5105 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5106 } 5107 5108 /* 5109 * Invoke the parent method to do net80211 work. 5110 */ 5111 error = avp->av_newstate(vap, nstate, arg); 5112 if (error != 0) 5113 goto bad; 5114 5115 /* 5116 * See above: ensure av_newstate() doesn't drop the lock 5117 * on us. 5118 */ 5119 IEEE80211_LOCK_ASSERT(ic); 5120 5121 if (nstate == IEEE80211_S_RUN) { 5122 /* NB: collect bss node again, it may have changed */ 5123 ieee80211_free_node(ni); 5124 ni = ieee80211_ref_node(vap->iv_bss); 5125 5126 DPRINTF(sc, ATH_DEBUG_STATE, 5127 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5128 "capinfo 0x%04x chan %d\n", __func__, 5129 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5130 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5131 5132 switch (vap->iv_opmode) { 5133#ifdef IEEE80211_SUPPORT_TDMA 5134 case IEEE80211_M_AHDEMO: 5135 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5136 break; 5137 /* fall thru... */ 5138#endif 5139 case IEEE80211_M_HOSTAP: 5140 case IEEE80211_M_IBSS: 5141 case IEEE80211_M_MBSS: 5142 /* 5143 * Allocate and setup the beacon frame. 5144 * 5145 * Stop any previous beacon DMA. This may be 5146 * necessary, for example, when an ibss merge 5147 * causes reconfiguration; there will be a state 5148 * transition from RUN->RUN that means we may 5149 * be called with beacon transmission active. 5150 */ 5151 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5152 5153 error = ath_beacon_alloc(sc, ni); 5154 if (error != 0) 5155 goto bad; 5156 /* 5157 * If joining an adhoc network defer beacon timer 5158 * configuration to the next beacon frame so we 5159 * have a current TSF to use. Otherwise we're 5160 * starting an ibss/bss so there's no need to delay; 5161 * if this is the first vap moving to RUN state, then 5162 * beacon state needs to be [re]configured. 5163 */ 5164 if (vap->iv_opmode == IEEE80211_M_IBSS && 5165 ni->ni_tstamp.tsf != 0) { 5166 sc->sc_syncbeacon = 1; 5167 } else if (!sc->sc_beacons) { 5168#ifdef IEEE80211_SUPPORT_TDMA 5169 if (vap->iv_caps & IEEE80211_C_TDMA) 5170 ath_tdma_config(sc, vap); 5171 else 5172#endif 5173 ath_beacon_config(sc, vap); 5174 sc->sc_beacons = 1; 5175 } 5176 break; 5177 case IEEE80211_M_STA: 5178 /* 5179 * Defer beacon timer configuration to the next 5180 * beacon frame so we have a current TSF to use 5181 * (any TSF collected when scanning is likely old). 5182 * However if it's due to a CSA -> RUN transition, 5183 * force a beacon update so we pick up a lack of 5184 * beacons from an AP in CAC and thus force a 5185 * scan. 5186 * 5187 * And, there's also corner cases here where 5188 * after a scan, the AP may have disappeared. 5189 * In that case, we may not receive an actual 5190 * beacon to update the beacon timer and thus we 5191 * won't get notified of the missing beacons. 5192 */ 5193 sc->sc_syncbeacon = 1; 5194#if 0 5195 if (csa_run_transition) 5196#endif 5197 ath_beacon_config(sc, vap); 5198 5199 /* 5200 * PR: kern/175227 5201 * 5202 * Reconfigure beacons during reset; as otherwise 5203 * we won't get the beacon timers reprogrammed 5204 * after a reset and thus we won't pick up a 5205 * beacon miss interrupt. 5206 * 5207 * Hopefully we'll see a beacon before the BMISS 5208 * timer fires (too often), leading to a STA 5209 * disassociation. 5210 */ 5211 sc->sc_beacons = 1; 5212 break; 5213 case IEEE80211_M_MONITOR: 5214 /* 5215 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5216 * transitions so we must re-enable interrupts here to 5217 * handle the case of a single monitor mode vap. 5218 */ 5219 ath_hal_intrset(ah, sc->sc_imask); 5220 break; 5221 case IEEE80211_M_WDS: 5222 break; 5223 default: 5224 break; 5225 } 5226 /* 5227 * Let the hal process statistics collected during a 5228 * scan so it can provide calibrated noise floor data. 5229 */ 5230 ath_hal_process_noisefloor(ah); 5231 /* 5232 * Reset rssi stats; maybe not the best place... 5233 */ 5234 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5235 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5236 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5237 /* 5238 * Finally, start any timers and the task q thread 5239 * (in case we didn't go through SCAN state). 5240 */ 5241 if (ath_longcalinterval != 0) { 5242 /* start periodic recalibration timer */ 5243 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5244 } else { 5245 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5246 "%s: calibration disabled\n", __func__); 5247 } 5248 taskqueue_unblock(sc->sc_tq); 5249 } else if (nstate == IEEE80211_S_INIT) { 5250 /* 5251 * If there are no vaps left in RUN state then 5252 * shutdown host/driver operation: 5253 * o disable interrupts 5254 * o disable the task queue thread 5255 * o mark beacon processing as stopped 5256 */ 5257 if (!ath_isanyrunningvaps(vap)) { 5258 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5259 /* disable interrupts */ 5260 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5261 taskqueue_block(sc->sc_tq); 5262 sc->sc_beacons = 0; 5263 } 5264#ifdef IEEE80211_SUPPORT_TDMA 5265 ath_hal_setcca(ah, AH_TRUE); 5266#endif 5267 } 5268bad: 5269 ieee80211_free_node(ni); 5270 return error; 5271} 5272 5273/* 5274 * Allocate a key cache slot to the station so we can 5275 * setup a mapping from key index to node. The key cache 5276 * slot is needed for managing antenna state and for 5277 * compression when stations do not use crypto. We do 5278 * it uniliaterally here; if crypto is employed this slot 5279 * will be reassigned. 5280 */ 5281static void 5282ath_setup_stationkey(struct ieee80211_node *ni) 5283{ 5284 struct ieee80211vap *vap = ni->ni_vap; 5285 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5286 ieee80211_keyix keyix, rxkeyix; 5287 5288 /* XXX should take a locked ref to vap->iv_bss */ 5289 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5290 /* 5291 * Key cache is full; we'll fall back to doing 5292 * the more expensive lookup in software. Note 5293 * this also means no h/w compression. 5294 */ 5295 /* XXX msg+statistic */ 5296 } else { 5297 /* XXX locking? */ 5298 ni->ni_ucastkey.wk_keyix = keyix; 5299 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5300 /* NB: must mark device key to get called back on delete */ 5301 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5302 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5303 /* NB: this will create a pass-thru key entry */ 5304 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 5305 } 5306} 5307 5308/* 5309 * Setup driver-specific state for a newly associated node. 5310 * Note that we're called also on a re-associate, the isnew 5311 * param tells us if this is the first time or not. 5312 */ 5313static void 5314ath_newassoc(struct ieee80211_node *ni, int isnew) 5315{ 5316 struct ath_node *an = ATH_NODE(ni); 5317 struct ieee80211vap *vap = ni->ni_vap; 5318 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5319 const struct ieee80211_txparam *tp = ni->ni_txparms; 5320 5321 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5322 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5323 5324 ath_rate_newassoc(sc, an, isnew); 5325 if (isnew && 5326 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5327 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5328 ath_setup_stationkey(ni); 5329} 5330 5331static int 5332ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5333 int nchans, struct ieee80211_channel chans[]) 5334{ 5335 struct ath_softc *sc = ic->ic_ifp->if_softc; 5336 struct ath_hal *ah = sc->sc_ah; 5337 HAL_STATUS status; 5338 5339 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5340 "%s: rd %u cc %u location %c%s\n", 5341 __func__, reg->regdomain, reg->country, reg->location, 5342 reg->ecm ? " ecm" : ""); 5343 5344 status = ath_hal_set_channels(ah, chans, nchans, 5345 reg->country, reg->regdomain); 5346 if (status != HAL_OK) { 5347 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5348 __func__, status); 5349 return EINVAL; /* XXX */ 5350 } 5351 5352 return 0; 5353} 5354 5355static void 5356ath_getradiocaps(struct ieee80211com *ic, 5357 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5358{ 5359 struct ath_softc *sc = ic->ic_ifp->if_softc; 5360 struct ath_hal *ah = sc->sc_ah; 5361 5362 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5363 __func__, SKU_DEBUG, CTRY_DEFAULT); 5364 5365 /* XXX check return */ 5366 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5367 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5368 5369} 5370 5371static int 5372ath_getchannels(struct ath_softc *sc) 5373{ 5374 struct ifnet *ifp = sc->sc_ifp; 5375 struct ieee80211com *ic = ifp->if_l2com; 5376 struct ath_hal *ah = sc->sc_ah; 5377 HAL_STATUS status; 5378 5379 /* 5380 * Collect channel set based on EEPROM contents. 5381 */ 5382 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5383 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5384 if (status != HAL_OK) { 5385 if_printf(ifp, "%s: unable to collect channel list from hal, " 5386 "status %d\n", __func__, status); 5387 return EINVAL; 5388 } 5389 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5390 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5391 /* XXX map Atheros sku's to net80211 SKU's */ 5392 /* XXX net80211 types too small */ 5393 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5394 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5395 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5396 ic->ic_regdomain.isocc[1] = ' '; 5397 5398 ic->ic_regdomain.ecm = 1; 5399 ic->ic_regdomain.location = 'I'; 5400 5401 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5402 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5403 __func__, sc->sc_eerd, sc->sc_eecc, 5404 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5405 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5406 return 0; 5407} 5408 5409static int 5410ath_rate_setup(struct ath_softc *sc, u_int mode) 5411{ 5412 struct ath_hal *ah = sc->sc_ah; 5413 const HAL_RATE_TABLE *rt; 5414 5415 switch (mode) { 5416 case IEEE80211_MODE_11A: 5417 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5418 break; 5419 case IEEE80211_MODE_HALF: 5420 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5421 break; 5422 case IEEE80211_MODE_QUARTER: 5423 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5424 break; 5425 case IEEE80211_MODE_11B: 5426 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5427 break; 5428 case IEEE80211_MODE_11G: 5429 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5430 break; 5431 case IEEE80211_MODE_TURBO_A: 5432 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5433 break; 5434 case IEEE80211_MODE_TURBO_G: 5435 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5436 break; 5437 case IEEE80211_MODE_STURBO_A: 5438 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5439 break; 5440 case IEEE80211_MODE_11NA: 5441 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5442 break; 5443 case IEEE80211_MODE_11NG: 5444 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5445 break; 5446 default: 5447 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5448 __func__, mode); 5449 return 0; 5450 } 5451 sc->sc_rates[mode] = rt; 5452 return (rt != NULL); 5453} 5454 5455static void 5456ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5457{ 5458#define N(a) (sizeof(a)/sizeof(a[0])) 5459 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5460 static const struct { 5461 u_int rate; /* tx/rx 802.11 rate */ 5462 u_int16_t timeOn; /* LED on time (ms) */ 5463 u_int16_t timeOff; /* LED off time (ms) */ 5464 } blinkrates[] = { 5465 { 108, 40, 10 }, 5466 { 96, 44, 11 }, 5467 { 72, 50, 13 }, 5468 { 48, 57, 14 }, 5469 { 36, 67, 16 }, 5470 { 24, 80, 20 }, 5471 { 22, 100, 25 }, 5472 { 18, 133, 34 }, 5473 { 12, 160, 40 }, 5474 { 10, 200, 50 }, 5475 { 6, 240, 58 }, 5476 { 4, 267, 66 }, 5477 { 2, 400, 100 }, 5478 { 0, 500, 130 }, 5479 /* XXX half/quarter rates */ 5480 }; 5481 const HAL_RATE_TABLE *rt; 5482 int i, j; 5483 5484 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5485 rt = sc->sc_rates[mode]; 5486 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5487 for (i = 0; i < rt->rateCount; i++) { 5488 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5489 if (rt->info[i].phy != IEEE80211_T_HT) 5490 sc->sc_rixmap[ieeerate] = i; 5491 else 5492 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 5493 } 5494 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5495 for (i = 0; i < N(sc->sc_hwmap); i++) { 5496 if (i >= rt->rateCount) { 5497 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5498 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5499 continue; 5500 } 5501 sc->sc_hwmap[i].ieeerate = 5502 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5503 if (rt->info[i].phy == IEEE80211_T_HT) 5504 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 5505 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5506 if (rt->info[i].shortPreamble || 5507 rt->info[i].phy == IEEE80211_T_OFDM) 5508 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5509 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 5510 for (j = 0; j < N(blinkrates)-1; j++) 5511 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5512 break; 5513 /* NB: this uses the last entry if the rate isn't found */ 5514 /* XXX beware of overlow */ 5515 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5516 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5517 } 5518 sc->sc_currates = rt; 5519 sc->sc_curmode = mode; 5520 /* 5521 * All protection frames are transmited at 2Mb/s for 5522 * 11g, otherwise at 1Mb/s. 5523 */ 5524 if (mode == IEEE80211_MODE_11G) 5525 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 5526 else 5527 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 5528 /* NB: caller is responsible for resetting rate control state */ 5529#undef N 5530} 5531 5532static void 5533ath_watchdog(void *arg) 5534{ 5535 struct ath_softc *sc = arg; 5536 int do_reset = 0; 5537 5538 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 5539 struct ifnet *ifp = sc->sc_ifp; 5540 uint32_t hangs; 5541 5542 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 5543 hangs != 0) { 5544 if_printf(ifp, "%s hang detected (0x%x)\n", 5545 hangs & 0xff ? "bb" : "mac", hangs); 5546 } else 5547 if_printf(ifp, "device timeout\n"); 5548 do_reset = 1; 5549 ifp->if_oerrors++; 5550 sc->sc_stats.ast_watchdog++; 5551 } 5552 5553 /* 5554 * We can't hold the lock across the ath_reset() call. 5555 * 5556 * And since this routine can't hold a lock and sleep, 5557 * do the reset deferred. 5558 */ 5559 if (do_reset) { 5560 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 5561 } 5562 5563 callout_schedule(&sc->sc_wd_ch, hz); 5564} 5565 5566/* 5567 * Fetch the rate control statistics for the given node. 5568 */ 5569static int 5570ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs) 5571{ 5572 struct ath_node *an; 5573 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5574 struct ieee80211_node *ni; 5575 int error = 0; 5576 5577 /* Perform a lookup on the given node */ 5578 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr); 5579 if (ni == NULL) { 5580 error = EINVAL; 5581 goto bad; 5582 } 5583 5584 /* Lock the ath_node */ 5585 an = ATH_NODE(ni); 5586 ATH_NODE_LOCK(an); 5587 5588 /* Fetch the rate control stats for this node */ 5589 error = ath_rate_fetch_node_stats(sc, an, rs); 5590 5591 /* No matter what happens here, just drop through */ 5592 5593 /* Unlock the ath_node */ 5594 ATH_NODE_UNLOCK(an); 5595 5596 /* Unref the node */ 5597 ieee80211_node_decref(ni); 5598 5599bad: 5600 return (error); 5601} 5602 5603#ifdef ATH_DIAGAPI 5604/* 5605 * Diagnostic interface to the HAL. This is used by various 5606 * tools to do things like retrieve register contents for 5607 * debugging. The mechanism is intentionally opaque so that 5608 * it can change frequently w/o concern for compatiblity. 5609 */ 5610static int 5611ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5612{ 5613 struct ath_hal *ah = sc->sc_ah; 5614 u_int id = ad->ad_id & ATH_DIAG_ID; 5615 void *indata = NULL; 5616 void *outdata = NULL; 5617 u_int32_t insize = ad->ad_in_size; 5618 u_int32_t outsize = ad->ad_out_size; 5619 int error = 0; 5620 5621 if (ad->ad_id & ATH_DIAG_IN) { 5622 /* 5623 * Copy in data. 5624 */ 5625 indata = malloc(insize, M_TEMP, M_NOWAIT); 5626 if (indata == NULL) { 5627 error = ENOMEM; 5628 goto bad; 5629 } 5630 error = copyin(ad->ad_in_data, indata, insize); 5631 if (error) 5632 goto bad; 5633 } 5634 if (ad->ad_id & ATH_DIAG_DYN) { 5635 /* 5636 * Allocate a buffer for the results (otherwise the HAL 5637 * returns a pointer to a buffer where we can read the 5638 * results). Note that we depend on the HAL leaving this 5639 * pointer for us to use below in reclaiming the buffer; 5640 * may want to be more defensive. 5641 */ 5642 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5643 if (outdata == NULL) { 5644 error = ENOMEM; 5645 goto bad; 5646 } 5647 } 5648 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5649 if (outsize < ad->ad_out_size) 5650 ad->ad_out_size = outsize; 5651 if (outdata != NULL) 5652 error = copyout(outdata, ad->ad_out_data, 5653 ad->ad_out_size); 5654 } else { 5655 error = EINVAL; 5656 } 5657bad: 5658 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5659 free(indata, M_TEMP); 5660 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5661 free(outdata, M_TEMP); 5662 return error; 5663} 5664#endif /* ATH_DIAGAPI */ 5665 5666static int 5667ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5668{ 5669#define IS_RUNNING(ifp) \ 5670 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5671 struct ath_softc *sc = ifp->if_softc; 5672 struct ieee80211com *ic = ifp->if_l2com; 5673 struct ifreq *ifr = (struct ifreq *)data; 5674 const HAL_RATE_TABLE *rt; 5675 int error = 0; 5676 5677 switch (cmd) { 5678 case SIOCSIFFLAGS: 5679 ATH_LOCK(sc); 5680 if (IS_RUNNING(ifp)) { 5681 /* 5682 * To avoid rescanning another access point, 5683 * do not call ath_init() here. Instead, 5684 * only reflect promisc mode settings. 5685 */ 5686 ath_mode_init(sc); 5687 } else if (ifp->if_flags & IFF_UP) { 5688 /* 5689 * Beware of being called during attach/detach 5690 * to reset promiscuous mode. In that case we 5691 * will still be marked UP but not RUNNING. 5692 * However trying to re-init the interface 5693 * is the wrong thing to do as we've already 5694 * torn down much of our state. There's 5695 * probably a better way to deal with this. 5696 */ 5697 if (!sc->sc_invalid) 5698 ath_init(sc); /* XXX lose error */ 5699 } else { 5700 ath_stop_locked(ifp); 5701#ifdef notyet 5702 /* XXX must wakeup in places like ath_vap_delete */ 5703 if (!sc->sc_invalid) 5704 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 5705#endif 5706 } 5707 ATH_UNLOCK(sc); 5708 break; 5709 case SIOCGIFMEDIA: 5710 case SIOCSIFMEDIA: 5711 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 5712 break; 5713 case SIOCGATHSTATS: 5714 /* NB: embed these numbers to get a consistent view */ 5715 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5716 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5717 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 5718 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 5719#ifdef IEEE80211_SUPPORT_TDMA 5720 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 5721 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 5722#endif 5723 rt = sc->sc_currates; 5724 sc->sc_stats.ast_tx_rate = 5725 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 5726 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT) 5727 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS; 5728 return copyout(&sc->sc_stats, 5729 ifr->ifr_data, sizeof (sc->sc_stats)); 5730 case SIOCGATHAGSTATS: 5731 return copyout(&sc->sc_aggr_stats, 5732 ifr->ifr_data, sizeof (sc->sc_aggr_stats)); 5733 case SIOCZATHSTATS: 5734 error = priv_check(curthread, PRIV_DRIVER); 5735 if (error == 0) { 5736 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 5737 memset(&sc->sc_aggr_stats, 0, 5738 sizeof(sc->sc_aggr_stats)); 5739 memset(&sc->sc_intr_stats, 0, 5740 sizeof(sc->sc_intr_stats)); 5741 } 5742 break; 5743#ifdef ATH_DIAGAPI 5744 case SIOCGATHDIAG: 5745 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5746 break; 5747 case SIOCGATHPHYERR: 5748 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr); 5749 break; 5750#endif 5751 case SIOCGATHSPECTRAL: 5752 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr); 5753 break; 5754 case SIOCGATHNODERATESTATS: 5755 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr); 5756 break; 5757 case SIOCGIFADDR: 5758 error = ether_ioctl(ifp, cmd, data); 5759 break; 5760 default: 5761 error = EINVAL; 5762 break; 5763 } 5764 return error; 5765#undef IS_RUNNING 5766} 5767 5768/* 5769 * Announce various information on device/driver attach. 5770 */ 5771static void 5772ath_announce(struct ath_softc *sc) 5773{ 5774 struct ifnet *ifp = sc->sc_ifp; 5775 struct ath_hal *ah = sc->sc_ah; 5776 5777 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 5778 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 5779 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5780 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 5781 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 5782 if (bootverbose) { 5783 int i; 5784 for (i = 0; i <= WME_AC_VO; i++) { 5785 struct ath_txq *txq = sc->sc_ac2q[i]; 5786 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5787 txq->axq_qnum, ieee80211_wme_acnames[i]); 5788 } 5789 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5790 sc->sc_cabq->axq_qnum); 5791 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5792 } 5793 if (ath_rxbuf != ATH_RXBUF) 5794 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5795 if (ath_txbuf != ATH_TXBUF) 5796 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5797 if (sc->sc_mcastkey && bootverbose) 5798 if_printf(ifp, "using multicast key search\n"); 5799} 5800 5801static void 5802ath_dfs_tasklet(void *p, int npending) 5803{ 5804 struct ath_softc *sc = (struct ath_softc *) p; 5805 struct ifnet *ifp = sc->sc_ifp; 5806 struct ieee80211com *ic = ifp->if_l2com; 5807 5808 /* 5809 * If previous processing has found a radar event, 5810 * signal this to the net80211 layer to begin DFS 5811 * processing. 5812 */ 5813 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 5814 /* DFS event found, initiate channel change */ 5815 /* 5816 * XXX doesn't currently tell us whether the event 5817 * XXX was found in the primary or extension 5818 * XXX channel! 5819 */ 5820 IEEE80211_LOCK(ic); 5821 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 5822 IEEE80211_UNLOCK(ic); 5823 } 5824} 5825 5826/* 5827 * Enable/disable power save. This must be called with 5828 * no TX driver locks currently held, so it should only 5829 * be called from the RX path (which doesn't hold any 5830 * TX driver locks.) 5831 */ 5832static void 5833ath_node_powersave(struct ieee80211_node *ni, int enable) 5834{ 5835#ifdef ATH_SW_PSQ 5836 struct ath_node *an = ATH_NODE(ni); 5837 struct ieee80211com *ic = ni->ni_ic; 5838 struct ath_softc *sc = ic->ic_ifp->if_softc; 5839 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5840 5841 ATH_NODE_UNLOCK_ASSERT(an); 5842 /* XXX and no TXQ locks should be held here */ 5843 5844 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: ni=%p, enable=%d\n", 5845 __func__, ni, enable); 5846 5847 /* Suspend or resume software queue handling */ 5848 if (enable) 5849 ath_tx_node_sleep(sc, an); 5850 else 5851 ath_tx_node_wakeup(sc, an); 5852 5853 /* Update net80211 state */ 5854 avp->av_node_ps(ni, enable); 5855#else 5856 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5857 5858 /* Update net80211 state */ 5859 avp->av_node_ps(ni, enable); 5860#endif/* ATH_SW_PSQ */ 5861} 5862 5863/* 5864 * Notification from net80211 that the powersave queue state has 5865 * changed. 5866 * 5867 * Since the software queue also may have some frames: 5868 * 5869 * + if the node software queue has frames and the TID state 5870 * is 0, we set the TIM; 5871 * + if the node and the stack are both empty, we clear the TIM bit. 5872 * + If the stack tries to set the bit, always set it. 5873 * + If the stack tries to clear the bit, only clear it if the 5874 * software queue in question is also cleared. 5875 * 5876 * TODO: this is called during node teardown; so let's ensure this 5877 * is all correctly handled and that the TIM bit is cleared. 5878 * It may be that the node flush is called _AFTER_ the net80211 5879 * stack clears the TIM. 5880 * 5881 * Here is the racy part. Since it's possible >1 concurrent, 5882 * overlapping TXes will appear complete with a TX completion in 5883 * another thread, it's possible that the concurrent TIM calls will 5884 * clash. We can't hold the node lock here because setting the 5885 * TIM grabs the net80211 comlock and this may cause a LOR. 5886 * The solution is either to totally serialise _everything_ at 5887 * this point (ie, all TX, completion and any reset/flush go into 5888 * one taskqueue) or a new "ath TIM lock" needs to be created that 5889 * just wraps the driver state change and this call to avp->av_set_tim(). 5890 * 5891 * The same race exists in the net80211 power save queue handling 5892 * as well. Since multiple transmitting threads may queue frames 5893 * into the driver, as well as ps-poll and the driver transmitting 5894 * frames (and thus clearing the psq), it's quite possible that 5895 * a packet entering the PSQ and a ps-poll being handled will 5896 * race, causing the TIM to be cleared and not re-set. 5897 */ 5898static int 5899ath_node_set_tim(struct ieee80211_node *ni, int enable) 5900{ 5901#ifdef ATH_SW_PSQ 5902 struct ieee80211com *ic = ni->ni_ic; 5903 struct ath_softc *sc = ic->ic_ifp->if_softc; 5904 struct ath_node *an = ATH_NODE(ni); 5905 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5906 int changed = 0; 5907 5908 ATH_NODE_UNLOCK_ASSERT(an); 5909 5910 /* 5911 * For now, just track and then update the TIM. 5912 */ 5913 ATH_NODE_LOCK(an); 5914 an->an_stack_psq = enable; 5915 5916 /* 5917 * This will get called for all operating modes, 5918 * even if avp->av_set_tim is unset. 5919 * It's currently set for hostap/ibss modes; but 5920 * the same infrastructure is used for both STA 5921 * and AP/IBSS node power save. 5922 */ 5923 if (avp->av_set_tim == NULL) { 5924 ATH_NODE_UNLOCK(an); 5925 return (0); 5926 } 5927 5928 /* 5929 * If setting the bit, always set it here. 5930 * If clearing the bit, only clear it if the 5931 * software queue is also empty. 5932 * 5933 * If the node has left power save, just clear the TIM 5934 * bit regardless of the state of the power save queue. 5935 * 5936 * XXX TODO: although atomics are used, it's quite possible 5937 * that a race will occur between this and setting/clearing 5938 * in another thread. TX completion will occur always in 5939 * one thread, however setting/clearing the TIM bit can come 5940 * from a variety of different process contexts! 5941 */ 5942 if (enable && an->an_tim_set == 1) { 5943 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5944 "%s: an=%p, enable=%d, tim_set=1, ignoring\n", 5945 __func__, an, enable); 5946 ATH_NODE_UNLOCK(an); 5947 } else if (enable) { 5948 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5949 "%s: an=%p, enable=%d, enabling TIM\n", 5950 __func__, an, enable); 5951 an->an_tim_set = 1; 5952 ATH_NODE_UNLOCK(an); 5953 changed = avp->av_set_tim(ni, enable); 5954 } else if (atomic_load_acq_int(&an->an_swq_depth) == 0) { 5955 /* disable */ 5956 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5957 "%s: an=%p, enable=%d, an_swq_depth == 0, disabling\n", 5958 __func__, an, enable); 5959 an->an_tim_set = 0; 5960 ATH_NODE_UNLOCK(an); 5961 changed = avp->av_set_tim(ni, enable); 5962 } else if (! an->an_is_powersave) { 5963 /* 5964 * disable regardless; the node isn't in powersave now 5965 */ 5966 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5967 "%s: an=%p, enable=%d, an_pwrsave=0, disabling\n", 5968 __func__, an, enable); 5969 an->an_tim_set = 0; 5970 ATH_NODE_UNLOCK(an); 5971 changed = avp->av_set_tim(ni, enable); 5972 } else { 5973 /* 5974 * psq disable, node is currently in powersave, node 5975 * software queue isn't empty, so don't clear the TIM bit 5976 * for now. 5977 */ 5978 ATH_NODE_UNLOCK(an); 5979 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5980 "%s: enable=%d, an_swq_depth > 0, ignoring\n", 5981 __func__, enable); 5982 changed = 0; 5983 } 5984 5985 return (changed); 5986#else 5987 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5988 5989 /* 5990 * Some operating modes don't set av_set_tim(), so don't 5991 * update it here. 5992 */ 5993 if (avp->av_set_tim == NULL) 5994 return (0); 5995 5996 return (avp->av_set_tim(ni, enable)); 5997#endif /* ATH_SW_PSQ */ 5998} 5999 6000/* 6001 * Set or update the TIM from the software queue. 6002 * 6003 * Check the software queue depth before attempting to do lock 6004 * anything; that avoids trying to obtain the lock. Then, 6005 * re-check afterwards to ensure nothing has changed in the 6006 * meantime. 6007 * 6008 * set: This is designed to be called from the TX path, after 6009 * a frame has been queued; to see if the swq > 0. 6010 * 6011 * clear: This is designed to be called from the buffer completion point 6012 * (right now it's ath_tx_default_comp()) where the state of 6013 * a software queue has changed. 6014 * 6015 * It makes sense to place it at buffer free / completion rather 6016 * than after each software queue operation, as there's no real 6017 * point in churning the TIM bit as the last frames in the software 6018 * queue are transmitted. If they fail and we retry them, we'd 6019 * just be setting the TIM bit again anyway. 6020 */ 6021void 6022ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni, 6023 int enable) 6024{ 6025#ifdef ATH_SW_PSQ 6026 struct ath_node *an; 6027 struct ath_vap *avp; 6028 6029 /* Don't do this for broadcast/etc frames */ 6030 if (ni == NULL) 6031 return; 6032 6033 an = ATH_NODE(ni); 6034 avp = ATH_VAP(ni->ni_vap); 6035 6036 /* 6037 * And for operating modes without the TIM handler set, let's 6038 * just skip those. 6039 */ 6040 if (avp->av_set_tim == NULL) 6041 return; 6042 6043 ATH_NODE_UNLOCK_ASSERT(an); 6044 6045 if (enable) { 6046 /* 6047 * Don't bother grabbing the lock unless the queue is not 6048 * empty. 6049 */ 6050 if (atomic_load_acq_int(&an->an_swq_depth) == 0) 6051 return; 6052 6053 ATH_NODE_LOCK(an); 6054 if (an->an_is_powersave && 6055 an->an_tim_set == 0 && 6056 atomic_load_acq_int(&an->an_swq_depth) != 0) { 6057 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6058 "%s: an=%p, swq_depth>0, tim_set=0, set!\n", 6059 __func__, an); 6060 an->an_tim_set = 1; 6061 ATH_NODE_UNLOCK(an); 6062 (void) avp->av_set_tim(ni, 1); 6063 } else { 6064 ATH_NODE_UNLOCK(an); 6065 } 6066 } else { 6067 /* 6068 * Don't bother grabbing the lock unless the queue is empty. 6069 */ 6070 if (atomic_load_acq_int(&an->an_swq_depth) != 0) 6071 return; 6072 6073 ATH_NODE_LOCK(an); 6074 if (an->an_is_powersave && 6075 an->an_stack_psq == 0 && 6076 an->an_tim_set == 1 && 6077 atomic_load_acq_int(&an->an_swq_depth) == 0) { 6078 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6079 "%s: an=%p, swq_depth=0, tim_set=1, psq_set=0," 6080 " clear!\n", 6081 __func__, an); 6082 an->an_tim_set = 0; 6083 ATH_NODE_UNLOCK(an); 6084 (void) avp->av_set_tim(ni, 0); 6085 } else { 6086 ATH_NODE_UNLOCK(an); 6087 } 6088 } 6089#else 6090 return; 6091#endif /* ATH_SW_PSQ */ 6092} 6093 6094MODULE_VERSION(if_ath, 1); 6095MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */ 6096#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) 6097MODULE_DEPEND(if_ath, alq, 1, 1, 1); 6098#endif 6099