if_ath.c revision 236599
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 236599 2012-06-05 06:03:55Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_beacon.h> 112#include <dev/ath/if_athdfs.h> 113 114#ifdef ATH_TX99_DIAG 115#include <dev/ath/ath_tx99/ath_tx99.h> 116#endif 117 118#define ATH_KTR_INTR KTR_SPARE4 119#define ATH_KTR_ERR KTR_SPARE3 120 121/* 122 * ATH_BCBUF determines the number of vap's that can transmit 123 * beacons and also (currently) the number of vap's that can 124 * have unique mac addresses/bssid. When staggering beacons 125 * 4 is probably a good max as otherwise the beacons become 126 * very closely spaced and there is limited time for cab q traffic 127 * to go out. You can burst beacons instead but that is not good 128 * for stations in power save and at some point you really want 129 * another radio (and channel). 130 * 131 * The limit on the number of mac addresses is tied to our use of 132 * the U/L bit and tracking addresses in a byte; it would be 133 * worthwhile to allow more for applications like proxy sta. 134 */ 135CTASSERT(ATH_BCBUF <= 8); 136 137static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 138 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 139 const uint8_t [IEEE80211_ADDR_LEN], 140 const uint8_t [IEEE80211_ADDR_LEN]); 141static void ath_vap_delete(struct ieee80211vap *); 142static void ath_init(void *); 143static void ath_stop_locked(struct ifnet *); 144static void ath_stop(struct ifnet *); 145static int ath_reset_vap(struct ieee80211vap *, u_long); 146static int ath_media_change(struct ifnet *); 147static void ath_watchdog(void *); 148static int ath_ioctl(struct ifnet *, u_long, caddr_t); 149static void ath_fatal_proc(void *, int); 150static void ath_bmiss_vap(struct ieee80211vap *); 151static void ath_bmiss_proc(void *, int); 152static void ath_key_update_begin(struct ieee80211vap *); 153static void ath_key_update_end(struct ieee80211vap *); 154static void ath_update_mcast(struct ifnet *); 155static void ath_update_promisc(struct ifnet *); 156static void ath_updateslot(struct ifnet *); 157static void ath_bstuck_proc(void *, int); 158static void ath_reset_proc(void *, int); 159static void ath_descdma_cleanup(struct ath_softc *sc, 160 struct ath_descdma *, ath_bufhead *); 161static int ath_desc_alloc(struct ath_softc *); 162static void ath_desc_free(struct ath_softc *); 163static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 164 const uint8_t [IEEE80211_ADDR_LEN]); 165static void ath_node_cleanup(struct ieee80211_node *); 166static void ath_node_free(struct ieee80211_node *); 167static void ath_node_getsignal(const struct ieee80211_node *, 168 int8_t *, int8_t *); 169static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 170static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 171static int ath_tx_setup(struct ath_softc *, int, int); 172static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 173static void ath_tx_cleanup(struct ath_softc *); 174static void ath_tx_proc_q0(void *, int); 175static void ath_tx_proc_q0123(void *, int); 176static void ath_tx_proc(void *, int); 177static void ath_txq_sched_tasklet(void *, int); 178static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 179static void ath_draintxq(struct ath_softc *, ATH_RESET_TYPE reset_type); 180static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 181static void ath_scan_start(struct ieee80211com *); 182static void ath_scan_end(struct ieee80211com *); 183static void ath_set_channel(struct ieee80211com *); 184#ifdef ATH_ENABLE_11N 185static void ath_update_chw(struct ieee80211com *); 186#endif /* ATH_ENABLE_11N */ 187static void ath_calibrate(void *); 188static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 189static void ath_setup_stationkey(struct ieee80211_node *); 190static void ath_newassoc(struct ieee80211_node *, int); 191static int ath_setregdomain(struct ieee80211com *, 192 struct ieee80211_regdomain *, int, 193 struct ieee80211_channel []); 194static void ath_getradiocaps(struct ieee80211com *, int, int *, 195 struct ieee80211_channel []); 196static int ath_getchannels(struct ath_softc *); 197 198static int ath_rate_setup(struct ath_softc *, u_int mode); 199static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 200 201static void ath_announce(struct ath_softc *); 202 203static void ath_dfs_tasklet(void *, int); 204 205#ifdef IEEE80211_SUPPORT_TDMA 206#include <dev/ath/if_ath_tdma.h> 207#endif 208 209#if 0 210#define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 211#define TDMA_LPF_LEN 6 212#define TDMA_DUMMY_MARKER 0x127 213#define TDMA_EP_MUL(x, mul) ((x) * (mul)) 214#define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 215#define TDMA_LPF(x, y, len) \ 216 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 217#define TDMA_SAMPLE(x, y) do { \ 218 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 219} while (0) 220#define TDMA_EP_RND(x,mul) \ 221 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 222#define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 223#endif /* IEEE80211_SUPPORT_TDMA */ 224 225SYSCTL_DECL(_hw_ath); 226 227/* XXX validate sysctl values */ 228static int ath_longcalinterval = 30; /* long cals every 30 secs */ 229SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 230 0, "long chip calibration interval (secs)"); 231static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 232SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 233 0, "short chip calibration interval (msecs)"); 234static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 235SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 236 0, "reset chip calibration results (secs)"); 237static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 238SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 239 0, "ANI calibration (msecs)"); 240 241static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 242SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 243 0, "rx buffers allocated"); 244TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 245static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 246SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 247 0, "tx buffers allocated"); 248TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 249 250int ath_bstuck_threshold = 4; /* max missed beacons */ 251SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 252 0, "max missed beacon xmits before chip reset"); 253 254MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 255 256#define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 257#define HAL_MODE_HT40 \ 258 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 259 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 260int 261ath_attach(u_int16_t devid, struct ath_softc *sc) 262{ 263 struct ifnet *ifp; 264 struct ieee80211com *ic; 265 struct ath_hal *ah = NULL; 266 HAL_STATUS status; 267 int error = 0, i; 268 u_int wmodes; 269 uint8_t macaddr[IEEE80211_ADDR_LEN]; 270 int rx_chainmask, tx_chainmask; 271 272 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 273 274 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 275 if (ifp == NULL) { 276 device_printf(sc->sc_dev, "can not if_alloc()\n"); 277 error = ENOSPC; 278 goto bad; 279 } 280 ic = ifp->if_l2com; 281 282 /* set these up early for if_printf use */ 283 if_initname(ifp, device_get_name(sc->sc_dev), 284 device_get_unit(sc->sc_dev)); 285 286 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 287 sc->sc_eepromdata, &status); 288 if (ah == NULL) { 289 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 290 status); 291 error = ENXIO; 292 goto bad; 293 } 294 sc->sc_ah = ah; 295 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 296#ifdef ATH_DEBUG 297 sc->sc_debug = ath_debug; 298#endif 299 300 /* 301 * Check if the MAC has multi-rate retry support. 302 * We do this by trying to setup a fake extended 303 * descriptor. MAC's that don't have support will 304 * return false w/o doing anything. MAC's that do 305 * support it will return true w/o doing anything. 306 */ 307 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 308 309 /* 310 * Check if the device has hardware counters for PHY 311 * errors. If so we need to enable the MIB interrupt 312 * so we can act on stat triggers. 313 */ 314 if (ath_hal_hwphycounters(ah)) 315 sc->sc_needmib = 1; 316 317 /* 318 * Get the hardware key cache size. 319 */ 320 sc->sc_keymax = ath_hal_keycachesize(ah); 321 if (sc->sc_keymax > ATH_KEYMAX) { 322 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 323 ATH_KEYMAX, sc->sc_keymax); 324 sc->sc_keymax = ATH_KEYMAX; 325 } 326 /* 327 * Reset the key cache since some parts do not 328 * reset the contents on initial power up. 329 */ 330 for (i = 0; i < sc->sc_keymax; i++) 331 ath_hal_keyreset(ah, i); 332 333 /* 334 * Collect the default channel list. 335 */ 336 error = ath_getchannels(sc); 337 if (error != 0) 338 goto bad; 339 340 /* 341 * Setup rate tables for all potential media types. 342 */ 343 ath_rate_setup(sc, IEEE80211_MODE_11A); 344 ath_rate_setup(sc, IEEE80211_MODE_11B); 345 ath_rate_setup(sc, IEEE80211_MODE_11G); 346 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 347 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 348 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 349 ath_rate_setup(sc, IEEE80211_MODE_11NA); 350 ath_rate_setup(sc, IEEE80211_MODE_11NG); 351 ath_rate_setup(sc, IEEE80211_MODE_HALF); 352 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 353 354 /* NB: setup here so ath_rate_update is happy */ 355 ath_setcurmode(sc, IEEE80211_MODE_11A); 356 357 /* 358 * Allocate tx+rx descriptors and populate the lists. 359 */ 360 error = ath_desc_alloc(sc); 361 if (error != 0) { 362 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 363 goto bad; 364 } 365 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 366 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 367 368 ATH_TXBUF_LOCK_INIT(sc); 369 370 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 371 taskqueue_thread_enqueue, &sc->sc_tq); 372 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 373 "%s taskq", ifp->if_xname); 374 375 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_tasklet, sc); 376 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 377 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 378 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 379 TASK_INIT(&sc->sc_txqtask,0, ath_txq_sched_tasklet, sc); 380 TASK_INIT(&sc->sc_fataltask,0, ath_fatal_proc, sc); 381 382 /* 383 * Allocate hardware transmit queues: one queue for 384 * beacon frames and one data queue for each QoS 385 * priority. Note that the hal handles resetting 386 * these queues at the needed time. 387 * 388 * XXX PS-Poll 389 */ 390 sc->sc_bhalq = ath_beaconq_setup(ah); 391 if (sc->sc_bhalq == (u_int) -1) { 392 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 393 error = EIO; 394 goto bad2; 395 } 396 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 397 if (sc->sc_cabq == NULL) { 398 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 399 error = EIO; 400 goto bad2; 401 } 402 /* NB: insure BK queue is the lowest priority h/w queue */ 403 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 404 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 405 ieee80211_wme_acnames[WME_AC_BK]); 406 error = EIO; 407 goto bad2; 408 } 409 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 410 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 411 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 412 /* 413 * Not enough hardware tx queues to properly do WME; 414 * just punt and assign them all to the same h/w queue. 415 * We could do a better job of this if, for example, 416 * we allocate queues when we switch from station to 417 * AP mode. 418 */ 419 if (sc->sc_ac2q[WME_AC_VI] != NULL) 420 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 421 if (sc->sc_ac2q[WME_AC_BE] != NULL) 422 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 423 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 424 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 425 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 426 } 427 428 /* 429 * Special case certain configurations. Note the 430 * CAB queue is handled by these specially so don't 431 * include them when checking the txq setup mask. 432 */ 433 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 434 case 0x01: 435 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 436 break; 437 case 0x0f: 438 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 439 break; 440 default: 441 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 442 break; 443 } 444 445 /* 446 * Setup rate control. Some rate control modules 447 * call back to change the anntena state so expose 448 * the necessary entry points. 449 * XXX maybe belongs in struct ath_ratectrl? 450 */ 451 sc->sc_setdefantenna = ath_setdefantenna; 452 sc->sc_rc = ath_rate_attach(sc); 453 if (sc->sc_rc == NULL) { 454 error = EIO; 455 goto bad2; 456 } 457 458 /* Attach DFS module */ 459 if (! ath_dfs_attach(sc)) { 460 device_printf(sc->sc_dev, 461 "%s: unable to attach DFS\n", __func__); 462 error = EIO; 463 goto bad2; 464 } 465 466 /* Start DFS processing tasklet */ 467 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 468 469 /* Configure LED state */ 470 sc->sc_blinking = 0; 471 sc->sc_ledstate = 1; 472 sc->sc_ledon = 0; /* low true */ 473 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 474 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 475 476 /* 477 * Don't setup hardware-based blinking. 478 * 479 * Although some NICs may have this configured in the 480 * default reset register values, the user may wish 481 * to alter which pins have which function. 482 * 483 * The reference driver attaches the MAC network LED to GPIO1 and 484 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 485 * NIC has these reversed. 486 */ 487 sc->sc_hardled = (1 == 0); 488 sc->sc_led_net_pin = -1; 489 sc->sc_led_pwr_pin = -1; 490 /* 491 * Auto-enable soft led processing for IBM cards and for 492 * 5211 minipci cards. Users can also manually enable/disable 493 * support with a sysctl. 494 */ 495 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 496 ath_led_config(sc); 497 ath_hal_setledstate(ah, HAL_LED_INIT); 498 499 ifp->if_softc = sc; 500 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 501 ifp->if_start = ath_start; 502 ifp->if_ioctl = ath_ioctl; 503 ifp->if_init = ath_init; 504 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 505 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 506 IFQ_SET_READY(&ifp->if_snd); 507 508 ic->ic_ifp = ifp; 509 /* XXX not right but it's not used anywhere important */ 510 ic->ic_phytype = IEEE80211_T_OFDM; 511 ic->ic_opmode = IEEE80211_M_STA; 512 ic->ic_caps = 513 IEEE80211_C_STA /* station mode */ 514 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 515 | IEEE80211_C_HOSTAP /* hostap mode */ 516 | IEEE80211_C_MONITOR /* monitor mode */ 517 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 518 | IEEE80211_C_WDS /* 4-address traffic works */ 519 | IEEE80211_C_MBSS /* mesh point link mode */ 520 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 521 | IEEE80211_C_SHSLOT /* short slot time supported */ 522 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 523 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 524 | IEEE80211_C_TXFRAG /* handle tx frags */ 525#ifdef ATH_ENABLE_DFS 526 | IEEE80211_C_DFS /* Enable radar detection */ 527#endif 528 ; 529 /* 530 * Query the hal to figure out h/w crypto support. 531 */ 532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 533 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 535 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 537 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 539 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 540 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 541 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 542 /* 543 * Check if h/w does the MIC and/or whether the 544 * separate key cache entries are required to 545 * handle both tx+rx MIC keys. 546 */ 547 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 548 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 549 /* 550 * If the h/w supports storing tx+rx MIC keys 551 * in one cache slot automatically enable use. 552 */ 553 if (ath_hal_hastkipsplit(ah) || 554 !ath_hal_settkipsplit(ah, AH_FALSE)) 555 sc->sc_splitmic = 1; 556 /* 557 * If the h/w can do TKIP MIC together with WME then 558 * we use it; otherwise we force the MIC to be done 559 * in software by the net80211 layer. 560 */ 561 if (ath_hal_haswmetkipmic(ah)) 562 sc->sc_wmetkipmic = 1; 563 } 564 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 565 /* 566 * Check for multicast key search support. 567 */ 568 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 569 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 570 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 571 } 572 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 573 /* 574 * Mark key cache slots associated with global keys 575 * as in use. If we knew TKIP was not to be used we 576 * could leave the +32, +64, and +32+64 slots free. 577 */ 578 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 579 setbit(sc->sc_keymap, i); 580 setbit(sc->sc_keymap, i+64); 581 if (sc->sc_splitmic) { 582 setbit(sc->sc_keymap, i+32); 583 setbit(sc->sc_keymap, i+32+64); 584 } 585 } 586 /* 587 * TPC support can be done either with a global cap or 588 * per-packet support. The latter is not available on 589 * all parts. We're a bit pedantic here as all parts 590 * support a global cap. 591 */ 592 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 593 ic->ic_caps |= IEEE80211_C_TXPMGT; 594 595 /* 596 * Mark WME capability only if we have sufficient 597 * hardware queues to do proper priority scheduling. 598 */ 599 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 600 ic->ic_caps |= IEEE80211_C_WME; 601 /* 602 * Check for misc other capabilities. 603 */ 604 if (ath_hal_hasbursting(ah)) 605 ic->ic_caps |= IEEE80211_C_BURST; 606 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 607 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 608 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 609 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 610 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah); 611 if (ath_hal_hasfastframes(ah)) 612 ic->ic_caps |= IEEE80211_C_FF; 613 wmodes = ath_hal_getwirelessmodes(ah); 614 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 615 ic->ic_caps |= IEEE80211_C_TURBOP; 616#ifdef IEEE80211_SUPPORT_TDMA 617 if (ath_hal_macversion(ah) > 0x78) { 618 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 619 ic->ic_tdma_update = ath_tdma_update; 620 } 621#endif 622 623 /* 624 * TODO: enforce that at least this many frames are available 625 * in the txbuf list before allowing data frames (raw or 626 * otherwise) to be transmitted. 627 */ 628 sc->sc_txq_data_minfree = 10; 629 /* 630 * Leave this as default to maintain legacy behaviour. 631 * Shortening the cabq/mcastq may end up causing some 632 * undesirable behaviour. 633 */ 634 sc->sc_txq_mcastq_maxdepth = ath_txbuf; 635 636 /* 637 * Allow the TX and RX chainmasks to be overridden by 638 * environment variables and/or device.hints. 639 * 640 * This must be done early - before the hardware is 641 * calibrated or before the 802.11n stream calculation 642 * is done. 643 */ 644 if (resource_int_value(device_get_name(sc->sc_dev), 645 device_get_unit(sc->sc_dev), "rx_chainmask", 646 &rx_chainmask) == 0) { 647 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 648 rx_chainmask); 649 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 650 } 651 if (resource_int_value(device_get_name(sc->sc_dev), 652 device_get_unit(sc->sc_dev), "tx_chainmask", 653 &tx_chainmask) == 0) { 654 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 655 tx_chainmask); 656 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 657 } 658 659 /* 660 * The if_ath 11n support is completely not ready for normal use. 661 * Enabling this option will likely break everything and everything. 662 * Don't think of doing that unless you know what you're doing. 663 */ 664 665#ifdef ATH_ENABLE_11N 666 /* 667 * Query HT capabilities 668 */ 669 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 670 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 671 int rxs, txs; 672 673 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 674 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 675 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 676 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 677 | IEEE80211_HTCAP_MAXAMSDU_3839 678 /* max A-MSDU length */ 679 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 680 ; 681 682 /* 683 * Enable short-GI for HT20 only if the hardware 684 * advertises support. 685 * Notably, anything earlier than the AR9287 doesn't. 686 */ 687 if ((ath_hal_getcapability(ah, 688 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 689 (wmodes & HAL_MODE_HT20)) { 690 device_printf(sc->sc_dev, 691 "[HT] enabling short-GI in 20MHz mode\n"); 692 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 693 } 694 695 if (wmodes & HAL_MODE_HT40) 696 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 697 | IEEE80211_HTCAP_SHORTGI40; 698 699 /* 700 * TX/RX streams need to be taken into account when 701 * negotiating which MCS rates it'll receive and 702 * what MCS rates are available for TX. 703 */ 704 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 705 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 706 707 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 708 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 709 710 ic->ic_txstream = txs; 711 ic->ic_rxstream = rxs; 712 713 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 714 &sc->sc_rts_aggr_limit); 715 if (sc->sc_rts_aggr_limit != (64 * 1024)) 716 device_printf(sc->sc_dev, 717 "[HT] RTS aggregates limited to %d KiB\n", 718 sc->sc_rts_aggr_limit / 1024); 719 720 device_printf(sc->sc_dev, 721 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 722 } 723#endif 724 725 /* 726 * Check if the hardware requires PCI register serialisation. 727 * Some of the Owl based MACs require this. 728 */ 729 if (mp_ncpus > 1 && 730 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 731 0, NULL) == HAL_OK) { 732 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 733 device_printf(sc->sc_dev, 734 "Enabling register serialisation\n"); 735 } 736 737 /* 738 * Indicate we need the 802.11 header padded to a 739 * 32-bit boundary for 4-address and QoS frames. 740 */ 741 ic->ic_flags |= IEEE80211_F_DATAPAD; 742 743 /* 744 * Query the hal about antenna support. 745 */ 746 sc->sc_defant = ath_hal_getdefantenna(ah); 747 748 /* 749 * Not all chips have the VEOL support we want to 750 * use with IBSS beacons; check here for it. 751 */ 752 sc->sc_hasveol = ath_hal_hasveol(ah); 753 754 /* get mac address from hardware */ 755 ath_hal_getmac(ah, macaddr); 756 if (sc->sc_hasbmask) 757 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 758 759 /* NB: used to size node table key mapping array */ 760 ic->ic_max_keyix = sc->sc_keymax; 761 /* call MI attach routine. */ 762 ieee80211_ifattach(ic, macaddr); 763 ic->ic_setregdomain = ath_setregdomain; 764 ic->ic_getradiocaps = ath_getradiocaps; 765 sc->sc_opmode = HAL_M_STA; 766 767 /* override default methods */ 768 ic->ic_newassoc = ath_newassoc; 769 ic->ic_updateslot = ath_updateslot; 770 ic->ic_wme.wme_update = ath_wme_update; 771 ic->ic_vap_create = ath_vap_create; 772 ic->ic_vap_delete = ath_vap_delete; 773 ic->ic_raw_xmit = ath_raw_xmit; 774 ic->ic_update_mcast = ath_update_mcast; 775 ic->ic_update_promisc = ath_update_promisc; 776 ic->ic_node_alloc = ath_node_alloc; 777 sc->sc_node_free = ic->ic_node_free; 778 ic->ic_node_free = ath_node_free; 779 sc->sc_node_cleanup = ic->ic_node_cleanup; 780 ic->ic_node_cleanup = ath_node_cleanup; 781 ic->ic_node_getsignal = ath_node_getsignal; 782 ic->ic_scan_start = ath_scan_start; 783 ic->ic_scan_end = ath_scan_end; 784 ic->ic_set_channel = ath_set_channel; 785#ifdef ATH_ENABLE_11N 786 /* 802.11n specific - but just override anyway */ 787 sc->sc_addba_request = ic->ic_addba_request; 788 sc->sc_addba_response = ic->ic_addba_response; 789 sc->sc_addba_stop = ic->ic_addba_stop; 790 sc->sc_bar_response = ic->ic_bar_response; 791 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 792 793 ic->ic_addba_request = ath_addba_request; 794 ic->ic_addba_response = ath_addba_response; 795 ic->ic_addba_response_timeout = ath_addba_response_timeout; 796 ic->ic_addba_stop = ath_addba_stop; 797 ic->ic_bar_response = ath_bar_response; 798 799 ic->ic_update_chw = ath_update_chw; 800#endif /* ATH_ENABLE_11N */ 801 802 ieee80211_radiotap_attach(ic, 803 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 804 ATH_TX_RADIOTAP_PRESENT, 805 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 806 ATH_RX_RADIOTAP_PRESENT); 807 808 /* 809 * Setup dynamic sysctl's now that country code and 810 * regdomain are available from the hal. 811 */ 812 ath_sysctlattach(sc); 813 ath_sysctl_stats_attach(sc); 814 ath_sysctl_hal_attach(sc); 815 816 if (bootverbose) 817 ieee80211_announce(ic); 818 ath_announce(sc); 819 return 0; 820bad2: 821 ath_tx_cleanup(sc); 822 ath_desc_free(sc); 823bad: 824 if (ah) 825 ath_hal_detach(ah); 826 if (ifp != NULL) 827 if_free(ifp); 828 sc->sc_invalid = 1; 829 return error; 830} 831 832int 833ath_detach(struct ath_softc *sc) 834{ 835 struct ifnet *ifp = sc->sc_ifp; 836 837 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 838 __func__, ifp->if_flags); 839 840 /* 841 * NB: the order of these is important: 842 * o stop the chip so no more interrupts will fire 843 * o call the 802.11 layer before detaching the hal to 844 * insure callbacks into the driver to delete global 845 * key cache entries can be handled 846 * o free the taskqueue which drains any pending tasks 847 * o reclaim the tx queue data structures after calling 848 * the 802.11 layer as we'll get called back to reclaim 849 * node state and potentially want to use them 850 * o to cleanup the tx queues the hal is called, so detach 851 * it last 852 * Other than that, it's straightforward... 853 */ 854 ath_stop(ifp); 855 ieee80211_ifdetach(ifp->if_l2com); 856 taskqueue_free(sc->sc_tq); 857#ifdef ATH_TX99_DIAG 858 if (sc->sc_tx99 != NULL) 859 sc->sc_tx99->detach(sc->sc_tx99); 860#endif 861 ath_rate_detach(sc->sc_rc); 862 863 ath_dfs_detach(sc); 864 ath_desc_free(sc); 865 ath_tx_cleanup(sc); 866 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 867 if_free(ifp); 868 869 return 0; 870} 871 872/* 873 * MAC address handling for multiple BSS on the same radio. 874 * The first vap uses the MAC address from the EEPROM. For 875 * subsequent vap's we set the U/L bit (bit 1) in the MAC 876 * address and use the next six bits as an index. 877 */ 878static void 879assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 880{ 881 int i; 882 883 if (clone && sc->sc_hasbmask) { 884 /* NB: we only do this if h/w supports multiple bssid */ 885 for (i = 0; i < 8; i++) 886 if ((sc->sc_bssidmask & (1<<i)) == 0) 887 break; 888 if (i != 0) 889 mac[0] |= (i << 2)|0x2; 890 } else 891 i = 0; 892 sc->sc_bssidmask |= 1<<i; 893 sc->sc_hwbssidmask[0] &= ~mac[0]; 894 if (i == 0) 895 sc->sc_nbssid0++; 896} 897 898static void 899reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 900{ 901 int i = mac[0] >> 2; 902 uint8_t mask; 903 904 if (i != 0 || --sc->sc_nbssid0 == 0) { 905 sc->sc_bssidmask &= ~(1<<i); 906 /* recalculate bssid mask from remaining addresses */ 907 mask = 0xff; 908 for (i = 1; i < 8; i++) 909 if (sc->sc_bssidmask & (1<<i)) 910 mask &= ~((i<<2)|0x2); 911 sc->sc_hwbssidmask[0] |= mask; 912 } 913} 914 915/* 916 * Assign a beacon xmit slot. We try to space out 917 * assignments so when beacons are staggered the 918 * traffic coming out of the cab q has maximal time 919 * to go out before the next beacon is scheduled. 920 */ 921static int 922assign_bslot(struct ath_softc *sc) 923{ 924 u_int slot, free; 925 926 free = 0; 927 for (slot = 0; slot < ATH_BCBUF; slot++) 928 if (sc->sc_bslot[slot] == NULL) { 929 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 930 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 931 return slot; 932 free = slot; 933 /* NB: keep looking for a double slot */ 934 } 935 return free; 936} 937 938static struct ieee80211vap * 939ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 940 enum ieee80211_opmode opmode, int flags, 941 const uint8_t bssid[IEEE80211_ADDR_LEN], 942 const uint8_t mac0[IEEE80211_ADDR_LEN]) 943{ 944 struct ath_softc *sc = ic->ic_ifp->if_softc; 945 struct ath_vap *avp; 946 struct ieee80211vap *vap; 947 uint8_t mac[IEEE80211_ADDR_LEN]; 948 int needbeacon, error; 949 enum ieee80211_opmode ic_opmode; 950 951 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 952 M_80211_VAP, M_WAITOK | M_ZERO); 953 needbeacon = 0; 954 IEEE80211_ADDR_COPY(mac, mac0); 955 956 ATH_LOCK(sc); 957 ic_opmode = opmode; /* default to opmode of new vap */ 958 switch (opmode) { 959 case IEEE80211_M_STA: 960 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 961 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 962 goto bad; 963 } 964 if (sc->sc_nvaps) { 965 /* 966 * With multiple vaps we must fall back 967 * to s/w beacon miss handling. 968 */ 969 flags |= IEEE80211_CLONE_NOBEACONS; 970 } 971 if (flags & IEEE80211_CLONE_NOBEACONS) { 972 /* 973 * Station mode w/o beacons are implemented w/ AP mode. 974 */ 975 ic_opmode = IEEE80211_M_HOSTAP; 976 } 977 break; 978 case IEEE80211_M_IBSS: 979 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 980 device_printf(sc->sc_dev, 981 "only 1 ibss vap supported\n"); 982 goto bad; 983 } 984 needbeacon = 1; 985 break; 986 case IEEE80211_M_AHDEMO: 987#ifdef IEEE80211_SUPPORT_TDMA 988 if (flags & IEEE80211_CLONE_TDMA) { 989 if (sc->sc_nvaps != 0) { 990 device_printf(sc->sc_dev, 991 "only 1 tdma vap supported\n"); 992 goto bad; 993 } 994 needbeacon = 1; 995 flags |= IEEE80211_CLONE_NOBEACONS; 996 } 997 /* fall thru... */ 998#endif 999 case IEEE80211_M_MONITOR: 1000 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1001 /* 1002 * Adopt existing mode. Adding a monitor or ahdemo 1003 * vap to an existing configuration is of dubious 1004 * value but should be ok. 1005 */ 1006 /* XXX not right for monitor mode */ 1007 ic_opmode = ic->ic_opmode; 1008 } 1009 break; 1010 case IEEE80211_M_HOSTAP: 1011 case IEEE80211_M_MBSS: 1012 needbeacon = 1; 1013 break; 1014 case IEEE80211_M_WDS: 1015 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1016 device_printf(sc->sc_dev, 1017 "wds not supported in sta mode\n"); 1018 goto bad; 1019 } 1020 /* 1021 * Silently remove any request for a unique 1022 * bssid; WDS vap's always share the local 1023 * mac address. 1024 */ 1025 flags &= ~IEEE80211_CLONE_BSSID; 1026 if (sc->sc_nvaps == 0) 1027 ic_opmode = IEEE80211_M_HOSTAP; 1028 else 1029 ic_opmode = ic->ic_opmode; 1030 break; 1031 default: 1032 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1033 goto bad; 1034 } 1035 /* 1036 * Check that a beacon buffer is available; the code below assumes it. 1037 */ 1038 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1039 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1040 goto bad; 1041 } 1042 1043 /* STA, AHDEMO? */ 1044 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 1045 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1046 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1047 } 1048 1049 vap = &avp->av_vap; 1050 /* XXX can't hold mutex across if_alloc */ 1051 ATH_UNLOCK(sc); 1052 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 1053 bssid, mac); 1054 ATH_LOCK(sc); 1055 if (error != 0) { 1056 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1057 __func__, error); 1058 goto bad2; 1059 } 1060 1061 /* h/w crypto support */ 1062 vap->iv_key_alloc = ath_key_alloc; 1063 vap->iv_key_delete = ath_key_delete; 1064 vap->iv_key_set = ath_key_set; 1065 vap->iv_key_update_begin = ath_key_update_begin; 1066 vap->iv_key_update_end = ath_key_update_end; 1067 1068 /* override various methods */ 1069 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1070 vap->iv_recv_mgmt = ath_recv_mgmt; 1071 vap->iv_reset = ath_reset_vap; 1072 vap->iv_update_beacon = ath_beacon_update; 1073 avp->av_newstate = vap->iv_newstate; 1074 vap->iv_newstate = ath_newstate; 1075 avp->av_bmiss = vap->iv_bmiss; 1076 vap->iv_bmiss = ath_bmiss_vap; 1077 1078 /* Set default parameters */ 1079 1080 /* 1081 * Anything earlier than some AR9300 series MACs don't 1082 * support a smaller MPDU density. 1083 */ 1084 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1085 /* 1086 * All NICs can handle the maximum size, however 1087 * AR5416 based MACs can only TX aggregates w/ RTS 1088 * protection when the total aggregate size is <= 8k. 1089 * However, for now that's enforced by the TX path. 1090 */ 1091 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1092 1093 avp->av_bslot = -1; 1094 if (needbeacon) { 1095 /* 1096 * Allocate beacon state and setup the q for buffered 1097 * multicast frames. We know a beacon buffer is 1098 * available because we checked above. 1099 */ 1100 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1101 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1102 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1103 /* 1104 * Assign the vap to a beacon xmit slot. As above 1105 * this cannot fail to find a free one. 1106 */ 1107 avp->av_bslot = assign_bslot(sc); 1108 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1109 ("beacon slot %u not empty", avp->av_bslot)); 1110 sc->sc_bslot[avp->av_bslot] = vap; 1111 sc->sc_nbcnvaps++; 1112 } 1113 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1114 /* 1115 * Multple vaps are to transmit beacons and we 1116 * have h/w support for TSF adjusting; enable 1117 * use of staggered beacons. 1118 */ 1119 sc->sc_stagbeacons = 1; 1120 } 1121 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1122 } 1123 1124 ic->ic_opmode = ic_opmode; 1125 if (opmode != IEEE80211_M_WDS) { 1126 sc->sc_nvaps++; 1127 if (opmode == IEEE80211_M_STA) 1128 sc->sc_nstavaps++; 1129 if (opmode == IEEE80211_M_MBSS) 1130 sc->sc_nmeshvaps++; 1131 } 1132 switch (ic_opmode) { 1133 case IEEE80211_M_IBSS: 1134 sc->sc_opmode = HAL_M_IBSS; 1135 break; 1136 case IEEE80211_M_STA: 1137 sc->sc_opmode = HAL_M_STA; 1138 break; 1139 case IEEE80211_M_AHDEMO: 1140#ifdef IEEE80211_SUPPORT_TDMA 1141 if (vap->iv_caps & IEEE80211_C_TDMA) { 1142 sc->sc_tdma = 1; 1143 /* NB: disable tsf adjust */ 1144 sc->sc_stagbeacons = 0; 1145 } 1146 /* 1147 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1148 * just ap mode. 1149 */ 1150 /* fall thru... */ 1151#endif 1152 case IEEE80211_M_HOSTAP: 1153 case IEEE80211_M_MBSS: 1154 sc->sc_opmode = HAL_M_HOSTAP; 1155 break; 1156 case IEEE80211_M_MONITOR: 1157 sc->sc_opmode = HAL_M_MONITOR; 1158 break; 1159 default: 1160 /* XXX should not happen */ 1161 break; 1162 } 1163 if (sc->sc_hastsfadd) { 1164 /* 1165 * Configure whether or not TSF adjust should be done. 1166 */ 1167 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1168 } 1169 if (flags & IEEE80211_CLONE_NOBEACONS) { 1170 /* 1171 * Enable s/w beacon miss handling. 1172 */ 1173 sc->sc_swbmiss = 1; 1174 } 1175 ATH_UNLOCK(sc); 1176 1177 /* complete setup */ 1178 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1179 return vap; 1180bad2: 1181 reclaim_address(sc, mac); 1182 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1183bad: 1184 free(avp, M_80211_VAP); 1185 ATH_UNLOCK(sc); 1186 return NULL; 1187} 1188 1189static void 1190ath_vap_delete(struct ieee80211vap *vap) 1191{ 1192 struct ieee80211com *ic = vap->iv_ic; 1193 struct ifnet *ifp = ic->ic_ifp; 1194 struct ath_softc *sc = ifp->if_softc; 1195 struct ath_hal *ah = sc->sc_ah; 1196 struct ath_vap *avp = ATH_VAP(vap); 1197 1198 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1199 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1200 /* 1201 * Quiesce the hardware while we remove the vap. In 1202 * particular we need to reclaim all references to 1203 * the vap state by any frames pending on the tx queues. 1204 */ 1205 ath_hal_intrset(ah, 0); /* disable interrupts */ 1206 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1207 /* XXX Do all frames from all vaps/nodes need draining here? */ 1208 ath_stoprecv(sc, 1); /* stop recv side */ 1209 } 1210 1211 ieee80211_vap_detach(vap); 1212 1213 /* 1214 * XXX Danger Will Robinson! Danger! 1215 * 1216 * Because ieee80211_vap_detach() can queue a frame (the station 1217 * diassociate message?) after we've drained the TXQ and 1218 * flushed the software TXQ, we will end up with a frame queued 1219 * to a node whose vap is about to be freed. 1220 * 1221 * To work around this, flush the hardware/software again. 1222 * This may be racy - the ath task may be running and the packet 1223 * may be being scheduled between sw->hw txq. Tsk. 1224 * 1225 * TODO: figure out why a new node gets allocated somewhere around 1226 * here (after the ath_tx_swq() call; and after an ath_stop_locked() 1227 * call!) 1228 */ 1229 1230 ath_draintxq(sc, ATH_RESET_DEFAULT); 1231 1232 ATH_LOCK(sc); 1233 /* 1234 * Reclaim beacon state. Note this must be done before 1235 * the vap instance is reclaimed as we may have a reference 1236 * to it in the buffer for the beacon frame. 1237 */ 1238 if (avp->av_bcbuf != NULL) { 1239 if (avp->av_bslot != -1) { 1240 sc->sc_bslot[avp->av_bslot] = NULL; 1241 sc->sc_nbcnvaps--; 1242 } 1243 ath_beacon_return(sc, avp->av_bcbuf); 1244 avp->av_bcbuf = NULL; 1245 if (sc->sc_nbcnvaps == 0) { 1246 sc->sc_stagbeacons = 0; 1247 if (sc->sc_hastsfadd) 1248 ath_hal_settsfadjust(sc->sc_ah, 0); 1249 } 1250 /* 1251 * Reclaim any pending mcast frames for the vap. 1252 */ 1253 ath_tx_draintxq(sc, &avp->av_mcastq); 1254 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1255 } 1256 /* 1257 * Update bookkeeping. 1258 */ 1259 if (vap->iv_opmode == IEEE80211_M_STA) { 1260 sc->sc_nstavaps--; 1261 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1262 sc->sc_swbmiss = 0; 1263 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1264 vap->iv_opmode == IEEE80211_M_MBSS) { 1265 reclaim_address(sc, vap->iv_myaddr); 1266 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1267 if (vap->iv_opmode == IEEE80211_M_MBSS) 1268 sc->sc_nmeshvaps--; 1269 } 1270 if (vap->iv_opmode != IEEE80211_M_WDS) 1271 sc->sc_nvaps--; 1272#ifdef IEEE80211_SUPPORT_TDMA 1273 /* TDMA operation ceases when the last vap is destroyed */ 1274 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1275 sc->sc_tdma = 0; 1276 sc->sc_swbmiss = 0; 1277 } 1278#endif 1279 free(avp, M_80211_VAP); 1280 1281 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1282 /* 1283 * Restart rx+tx machines if still running (RUNNING will 1284 * be reset if we just destroyed the last vap). 1285 */ 1286 if (ath_startrecv(sc) != 0) 1287 if_printf(ifp, "%s: unable to restart recv logic\n", 1288 __func__); 1289 if (sc->sc_beacons) { /* restart beacons */ 1290#ifdef IEEE80211_SUPPORT_TDMA 1291 if (sc->sc_tdma) 1292 ath_tdma_config(sc, NULL); 1293 else 1294#endif 1295 ath_beacon_config(sc, NULL); 1296 } 1297 ath_hal_intrset(ah, sc->sc_imask); 1298 } 1299 ATH_UNLOCK(sc); 1300} 1301 1302void 1303ath_suspend(struct ath_softc *sc) 1304{ 1305 struct ifnet *ifp = sc->sc_ifp; 1306 struct ieee80211com *ic = ifp->if_l2com; 1307 1308 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1309 __func__, ifp->if_flags); 1310 1311 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1312 if (ic->ic_opmode == IEEE80211_M_STA) 1313 ath_stop(ifp); 1314 else 1315 ieee80211_suspend_all(ic); 1316 /* 1317 * NB: don't worry about putting the chip in low power 1318 * mode; pci will power off our socket on suspend and 1319 * CardBus detaches the device. 1320 */ 1321 1322 /* 1323 * XXX ensure none of the taskqueues are running 1324 * XXX ensure sc_invalid is 1 1325 * XXX ensure the calibration callout is disabled 1326 */ 1327 1328 /* Disable the PCIe PHY, complete with workarounds */ 1329 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1330} 1331 1332/* 1333 * Reset the key cache since some parts do not reset the 1334 * contents on resume. First we clear all entries, then 1335 * re-load keys that the 802.11 layer assumes are setup 1336 * in h/w. 1337 */ 1338static void 1339ath_reset_keycache(struct ath_softc *sc) 1340{ 1341 struct ifnet *ifp = sc->sc_ifp; 1342 struct ieee80211com *ic = ifp->if_l2com; 1343 struct ath_hal *ah = sc->sc_ah; 1344 int i; 1345 1346 for (i = 0; i < sc->sc_keymax; i++) 1347 ath_hal_keyreset(ah, i); 1348 ieee80211_crypto_reload_keys(ic); 1349} 1350 1351void 1352ath_resume(struct ath_softc *sc) 1353{ 1354 struct ifnet *ifp = sc->sc_ifp; 1355 struct ieee80211com *ic = ifp->if_l2com; 1356 struct ath_hal *ah = sc->sc_ah; 1357 HAL_STATUS status; 1358 1359 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1360 __func__, ifp->if_flags); 1361 1362 /* Re-enable PCIe, re-enable the PCIe bus */ 1363 ath_hal_enablepcie(ah, 0, 0); 1364 1365 /* 1366 * Must reset the chip before we reload the 1367 * keycache as we were powered down on suspend. 1368 */ 1369 ath_hal_reset(ah, sc->sc_opmode, 1370 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1371 AH_FALSE, &status); 1372 ath_reset_keycache(sc); 1373 1374 /* Let DFS at it in case it's a DFS channel */ 1375 ath_dfs_radar_enable(sc, ic->ic_curchan); 1376 1377 /* Restore the LED configuration */ 1378 ath_led_config(sc); 1379 ath_hal_setledstate(ah, HAL_LED_INIT); 1380 1381 if (sc->sc_resume_up) { 1382 if (ic->ic_opmode == IEEE80211_M_STA) { 1383 ath_init(sc); 1384 ath_hal_setledstate(ah, HAL_LED_RUN); 1385 /* 1386 * Program the beacon registers using the last rx'd 1387 * beacon frame and enable sync on the next beacon 1388 * we see. This should handle the case where we 1389 * wakeup and find the same AP and also the case where 1390 * we wakeup and need to roam. For the latter we 1391 * should get bmiss events that trigger a roam. 1392 */ 1393 ath_beacon_config(sc, NULL); 1394 sc->sc_syncbeacon = 1; 1395 } else 1396 ieee80211_resume_all(ic); 1397 } 1398 1399 /* XXX beacons ? */ 1400} 1401 1402void 1403ath_shutdown(struct ath_softc *sc) 1404{ 1405 struct ifnet *ifp = sc->sc_ifp; 1406 1407 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1408 __func__, ifp->if_flags); 1409 1410 ath_stop(ifp); 1411 /* NB: no point powering down chip as we're about to reboot */ 1412} 1413 1414/* 1415 * Interrupt handler. Most of the actual processing is deferred. 1416 */ 1417void 1418ath_intr(void *arg) 1419{ 1420 struct ath_softc *sc = arg; 1421 struct ifnet *ifp = sc->sc_ifp; 1422 struct ath_hal *ah = sc->sc_ah; 1423 HAL_INT status = 0; 1424 uint32_t txqs; 1425 1426 /* 1427 * If we're inside a reset path, just print a warning and 1428 * clear the ISR. The reset routine will finish it for us. 1429 */ 1430 ATH_PCU_LOCK(sc); 1431 if (sc->sc_inreset_cnt) { 1432 HAL_INT status; 1433 ath_hal_getisr(ah, &status); /* clear ISR */ 1434 ath_hal_intrset(ah, 0); /* disable further intr's */ 1435 DPRINTF(sc, ATH_DEBUG_ANY, 1436 "%s: in reset, ignoring: status=0x%x\n", 1437 __func__, status); 1438 ATH_PCU_UNLOCK(sc); 1439 return; 1440 } 1441 1442 if (sc->sc_invalid) { 1443 /* 1444 * The hardware is not ready/present, don't touch anything. 1445 * Note this can happen early on if the IRQ is shared. 1446 */ 1447 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1448 ATH_PCU_UNLOCK(sc); 1449 return; 1450 } 1451 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 1452 ATH_PCU_UNLOCK(sc); 1453 return; 1454 } 1455 1456 if ((ifp->if_flags & IFF_UP) == 0 || 1457 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1458 HAL_INT status; 1459 1460 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1461 __func__, ifp->if_flags); 1462 ath_hal_getisr(ah, &status); /* clear ISR */ 1463 ath_hal_intrset(ah, 0); /* disable further intr's */ 1464 ATH_PCU_UNLOCK(sc); 1465 return; 1466 } 1467 1468 /* 1469 * Figure out the reason(s) for the interrupt. Note 1470 * that the hal returns a pseudo-ISR that may include 1471 * bits we haven't explicitly enabled so we mask the 1472 * value to insure we only process bits we requested. 1473 */ 1474 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1475 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1476 CTR1(ATH_KTR_INTR, "ath_intr: mask=0x%.8x", status); 1477#ifdef ATH_KTR_INTR_DEBUG 1478 CTR5(ATH_KTR_INTR, 1479 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 1480 ah->ah_intrstate[0], 1481 ah->ah_intrstate[1], 1482 ah->ah_intrstate[2], 1483 ah->ah_intrstate[3], 1484 ah->ah_intrstate[6]); 1485#endif 1486 1487 /* Squirrel away SYNC interrupt debugging */ 1488 if (ah->ah_syncstate != 0) { 1489 int i; 1490 for (i = 0; i < 32; i++) 1491 if (ah->ah_syncstate & (i << i)) 1492 sc->sc_intr_stats.sync_intr[i]++; 1493 } 1494 1495 status &= sc->sc_imask; /* discard unasked for bits */ 1496 1497 /* Short-circuit un-handled interrupts */ 1498 if (status == 0x0) { 1499 ATH_PCU_UNLOCK(sc); 1500 return; 1501 } 1502 1503 /* 1504 * Take a note that we're inside the interrupt handler, so 1505 * the reset routines know to wait. 1506 */ 1507 sc->sc_intr_cnt++; 1508 ATH_PCU_UNLOCK(sc); 1509 1510 /* 1511 * Handle the interrupt. We won't run concurrent with the reset 1512 * or channel change routines as they'll wait for sc_intr_cnt 1513 * to be 0 before continuing. 1514 */ 1515 if (status & HAL_INT_FATAL) { 1516 sc->sc_stats.ast_hardware++; 1517 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1518 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 1519 } else { 1520 if (status & HAL_INT_SWBA) { 1521 /* 1522 * Software beacon alert--time to send a beacon. 1523 * Handle beacon transmission directly; deferring 1524 * this is too slow to meet timing constraints 1525 * under load. 1526 */ 1527#ifdef IEEE80211_SUPPORT_TDMA 1528 if (sc->sc_tdma) { 1529 if (sc->sc_tdmaswba == 0) { 1530 struct ieee80211com *ic = ifp->if_l2com; 1531 struct ieee80211vap *vap = 1532 TAILQ_FIRST(&ic->ic_vaps); 1533 ath_tdma_beacon_send(sc, vap); 1534 sc->sc_tdmaswba = 1535 vap->iv_tdma->tdma_bintval; 1536 } else 1537 sc->sc_tdmaswba--; 1538 } else 1539#endif 1540 { 1541 ath_beacon_proc(sc, 0); 1542#ifdef IEEE80211_SUPPORT_SUPERG 1543 /* 1544 * Schedule the rx taskq in case there's no 1545 * traffic so any frames held on the staging 1546 * queue are aged and potentially flushed. 1547 */ 1548 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1549#endif 1550 } 1551 } 1552 if (status & HAL_INT_RXEOL) { 1553 int imask; 1554 CTR0(ATH_KTR_ERR, "ath_intr: RXEOL"); 1555 ATH_PCU_LOCK(sc); 1556 /* 1557 * NB: the hardware should re-read the link when 1558 * RXE bit is written, but it doesn't work at 1559 * least on older hardware revs. 1560 */ 1561 sc->sc_stats.ast_rxeol++; 1562 /* 1563 * Disable RXEOL/RXORN - prevent an interrupt 1564 * storm until the PCU logic can be reset. 1565 * In case the interface is reset some other 1566 * way before "sc_kickpcu" is called, don't 1567 * modify sc_imask - that way if it is reset 1568 * by a call to ath_reset() somehow, the 1569 * interrupt mask will be correctly reprogrammed. 1570 */ 1571 imask = sc->sc_imask; 1572 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 1573 ath_hal_intrset(ah, imask); 1574 /* 1575 * Only blank sc_rxlink if we've not yet kicked 1576 * the PCU. 1577 * 1578 * This isn't entirely correct - the correct solution 1579 * would be to have a PCU lock and engage that for 1580 * the duration of the PCU fiddling; which would include 1581 * running the RX process. Otherwise we could end up 1582 * messing up the RX descriptor chain and making the 1583 * RX desc list much shorter. 1584 */ 1585 if (! sc->sc_kickpcu) 1586 sc->sc_rxlink = NULL; 1587 sc->sc_kickpcu = 1; 1588 /* 1589 * Enqueue an RX proc, to handled whatever 1590 * is in the RX queue. 1591 * This will then kick the PCU. 1592 */ 1593 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1594 ATH_PCU_UNLOCK(sc); 1595 } 1596 if (status & HAL_INT_TXURN) { 1597 sc->sc_stats.ast_txurn++; 1598 /* bump tx trigger level */ 1599 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1600 } 1601 if (status & HAL_INT_RX) { 1602 sc->sc_stats.ast_rx_intr++; 1603 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1604 } 1605 if (status & HAL_INT_TX) { 1606 sc->sc_stats.ast_tx_intr++; 1607 /* 1608 * Grab all the currently set bits in the HAL txq bitmap 1609 * and blank them. This is the only place we should be 1610 * doing this. 1611 */ 1612 ATH_PCU_LOCK(sc); 1613 txqs = 0xffffffff; 1614 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 1615 sc->sc_txq_active |= txqs; 1616 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1617 ATH_PCU_UNLOCK(sc); 1618 } 1619 if (status & HAL_INT_BMISS) { 1620 sc->sc_stats.ast_bmiss++; 1621 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1622 } 1623 if (status & HAL_INT_GTT) 1624 sc->sc_stats.ast_tx_timeout++; 1625 if (status & HAL_INT_CST) 1626 sc->sc_stats.ast_tx_cst++; 1627 if (status & HAL_INT_MIB) { 1628 sc->sc_stats.ast_mib++; 1629 ATH_PCU_LOCK(sc); 1630 /* 1631 * Disable interrupts until we service the MIB 1632 * interrupt; otherwise it will continue to fire. 1633 */ 1634 ath_hal_intrset(ah, 0); 1635 /* 1636 * Let the hal handle the event. We assume it will 1637 * clear whatever condition caused the interrupt. 1638 */ 1639 ath_hal_mibevent(ah, &sc->sc_halstats); 1640 /* 1641 * Don't reset the interrupt if we've just 1642 * kicked the PCU, or we may get a nested 1643 * RXEOL before the rxproc has had a chance 1644 * to run. 1645 */ 1646 if (sc->sc_kickpcu == 0) 1647 ath_hal_intrset(ah, sc->sc_imask); 1648 ATH_PCU_UNLOCK(sc); 1649 } 1650 if (status & HAL_INT_RXORN) { 1651 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1652 CTR0(ATH_KTR_ERR, "ath_intr: RXORN"); 1653 sc->sc_stats.ast_rxorn++; 1654 } 1655 } 1656 ATH_PCU_LOCK(sc); 1657 sc->sc_intr_cnt--; 1658 ATH_PCU_UNLOCK(sc); 1659} 1660 1661static void 1662ath_fatal_proc(void *arg, int pending) 1663{ 1664 struct ath_softc *sc = arg; 1665 struct ifnet *ifp = sc->sc_ifp; 1666 u_int32_t *state; 1667 u_int32_t len; 1668 void *sp; 1669 1670 if_printf(ifp, "hardware error; resetting\n"); 1671 /* 1672 * Fatal errors are unrecoverable. Typically these 1673 * are caused by DMA errors. Collect h/w state from 1674 * the hal so we can diagnose what's going on. 1675 */ 1676 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1677 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1678 state = sp; 1679 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1680 state[0], state[1] , state[2], state[3], 1681 state[4], state[5]); 1682 } 1683 ath_reset(ifp, ATH_RESET_NOLOSS); 1684} 1685 1686static void 1687ath_bmiss_vap(struct ieee80211vap *vap) 1688{ 1689 /* 1690 * Workaround phantom bmiss interrupts by sanity-checking 1691 * the time of our last rx'd frame. If it is within the 1692 * beacon miss interval then ignore the interrupt. If it's 1693 * truly a bmiss we'll get another interrupt soon and that'll 1694 * be dispatched up for processing. Note this applies only 1695 * for h/w beacon miss events. 1696 */ 1697 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1698 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1699 struct ath_softc *sc = ifp->if_softc; 1700 u_int64_t lastrx = sc->sc_lastrx; 1701 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1702 /* XXX should take a locked ref to iv_bss */ 1703 u_int bmisstimeout = 1704 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1705 1706 DPRINTF(sc, ATH_DEBUG_BEACON, 1707 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1708 __func__, (unsigned long long) tsf, 1709 (unsigned long long)(tsf - lastrx), 1710 (unsigned long long) lastrx, bmisstimeout); 1711 1712 if (tsf - lastrx <= bmisstimeout) { 1713 sc->sc_stats.ast_bmiss_phantom++; 1714 return; 1715 } 1716 } 1717 ATH_VAP(vap)->av_bmiss(vap); 1718} 1719 1720static int 1721ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1722{ 1723 uint32_t rsize; 1724 void *sp; 1725 1726 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 1727 return 0; 1728 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1729 *hangs = *(uint32_t *)sp; 1730 return 1; 1731} 1732 1733static void 1734ath_bmiss_proc(void *arg, int pending) 1735{ 1736 struct ath_softc *sc = arg; 1737 struct ifnet *ifp = sc->sc_ifp; 1738 uint32_t hangs; 1739 1740 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1741 1742 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1743 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs); 1744 ath_reset(ifp, ATH_RESET_NOLOSS); 1745 } else 1746 ieee80211_beacon_miss(ifp->if_l2com); 1747} 1748 1749/* 1750 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1751 * calcs together with WME. If necessary disable the crypto 1752 * hardware and mark the 802.11 state so keys will be setup 1753 * with the MIC work done in software. 1754 */ 1755static void 1756ath_settkipmic(struct ath_softc *sc) 1757{ 1758 struct ifnet *ifp = sc->sc_ifp; 1759 struct ieee80211com *ic = ifp->if_l2com; 1760 1761 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1762 if (ic->ic_flags & IEEE80211_F_WME) { 1763 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1764 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1765 } else { 1766 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1767 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1768 } 1769 } 1770} 1771 1772static void 1773ath_init(void *arg) 1774{ 1775 struct ath_softc *sc = (struct ath_softc *) arg; 1776 struct ifnet *ifp = sc->sc_ifp; 1777 struct ieee80211com *ic = ifp->if_l2com; 1778 struct ath_hal *ah = sc->sc_ah; 1779 HAL_STATUS status; 1780 1781 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1782 __func__, ifp->if_flags); 1783 1784 ATH_LOCK(sc); 1785 /* 1786 * Stop anything previously setup. This is safe 1787 * whether this is the first time through or not. 1788 */ 1789 ath_stop_locked(ifp); 1790 1791 /* 1792 * The basic interface to setting the hardware in a good 1793 * state is ``reset''. On return the hardware is known to 1794 * be powered up and with interrupts disabled. This must 1795 * be followed by initialization of the appropriate bits 1796 * and then setup of the interrupt mask. 1797 */ 1798 ath_settkipmic(sc); 1799 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1800 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1801 status); 1802 ATH_UNLOCK(sc); 1803 return; 1804 } 1805 ath_chan_change(sc, ic->ic_curchan); 1806 1807 /* Let DFS at it in case it's a DFS channel */ 1808 ath_dfs_radar_enable(sc, ic->ic_curchan); 1809 1810 /* 1811 * Likewise this is set during reset so update 1812 * state cached in the driver. 1813 */ 1814 sc->sc_diversity = ath_hal_getdiversity(ah); 1815 sc->sc_lastlongcal = 0; 1816 sc->sc_resetcal = 1; 1817 sc->sc_lastcalreset = 0; 1818 sc->sc_lastani = 0; 1819 sc->sc_lastshortcal = 0; 1820 sc->sc_doresetcal = AH_FALSE; 1821 /* 1822 * Beacon timers were cleared here; give ath_newstate() 1823 * a hint that the beacon timers should be poked when 1824 * things transition to the RUN state. 1825 */ 1826 sc->sc_beacons = 0; 1827 1828 /* 1829 * Initial aggregation settings. 1830 */ 1831 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; 1832 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 1833 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 1834 1835 /* 1836 * Setup the hardware after reset: the key cache 1837 * is filled as needed and the receive engine is 1838 * set going. Frame transmit is handled entirely 1839 * in the frame output path; there's nothing to do 1840 * here except setup the interrupt mask. 1841 */ 1842 if (ath_startrecv(sc) != 0) { 1843 if_printf(ifp, "unable to start recv logic\n"); 1844 ATH_UNLOCK(sc); 1845 return; 1846 } 1847 1848 /* 1849 * Enable interrupts. 1850 */ 1851 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1852 | HAL_INT_RXEOL | HAL_INT_RXORN 1853 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1854 /* 1855 * Enable MIB interrupts when there are hardware phy counters. 1856 * Note we only do this (at the moment) for station mode. 1857 */ 1858 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1859 sc->sc_imask |= HAL_INT_MIB; 1860 1861 /* Enable global TX timeout and carrier sense timeout if available */ 1862 if (ath_hal_gtxto_supported(ah)) 1863 sc->sc_imask |= HAL_INT_GTT; 1864 1865 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 1866 __func__, sc->sc_imask); 1867 1868 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1869 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1870 ath_hal_intrset(ah, sc->sc_imask); 1871 1872 ATH_UNLOCK(sc); 1873 1874#ifdef ATH_TX99_DIAG 1875 if (sc->sc_tx99 != NULL) 1876 sc->sc_tx99->start(sc->sc_tx99); 1877 else 1878#endif 1879 ieee80211_start_all(ic); /* start all vap's */ 1880} 1881 1882static void 1883ath_stop_locked(struct ifnet *ifp) 1884{ 1885 struct ath_softc *sc = ifp->if_softc; 1886 struct ath_hal *ah = sc->sc_ah; 1887 1888 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1889 __func__, sc->sc_invalid, ifp->if_flags); 1890 1891 ATH_LOCK_ASSERT(sc); 1892 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1893 /* 1894 * Shutdown the hardware and driver: 1895 * reset 802.11 state machine 1896 * turn off timers 1897 * disable interrupts 1898 * turn off the radio 1899 * clear transmit machinery 1900 * clear receive machinery 1901 * drain and release tx queues 1902 * reclaim beacon resources 1903 * power down hardware 1904 * 1905 * Note that some of this work is not possible if the 1906 * hardware is gone (invalid). 1907 */ 1908#ifdef ATH_TX99_DIAG 1909 if (sc->sc_tx99 != NULL) 1910 sc->sc_tx99->stop(sc->sc_tx99); 1911#endif 1912 callout_stop(&sc->sc_wd_ch); 1913 sc->sc_wd_timer = 0; 1914 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1915 if (!sc->sc_invalid) { 1916 if (sc->sc_softled) { 1917 callout_stop(&sc->sc_ledtimer); 1918 ath_hal_gpioset(ah, sc->sc_ledpin, 1919 !sc->sc_ledon); 1920 sc->sc_blinking = 0; 1921 } 1922 ath_hal_intrset(ah, 0); 1923 } 1924 ath_draintxq(sc, ATH_RESET_DEFAULT); 1925 if (!sc->sc_invalid) { 1926 ath_stoprecv(sc, 1); 1927 ath_hal_phydisable(ah); 1928 } else 1929 sc->sc_rxlink = NULL; 1930 ath_beacon_free(sc); /* XXX not needed */ 1931 } 1932} 1933 1934#define MAX_TXRX_ITERATIONS 1000 1935static void 1936ath_txrx_stop_locked(struct ath_softc *sc) 1937{ 1938 int i = MAX_TXRX_ITERATIONS; 1939 1940 ATH_UNLOCK_ASSERT(sc); 1941 ATH_PCU_LOCK_ASSERT(sc); 1942 1943 /* 1944 * Sleep until all the pending operations have completed. 1945 * 1946 * The caller must ensure that reset has been incremented 1947 * or the pending operations may continue being queued. 1948 */ 1949 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 1950 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 1951 if (i <= 0) 1952 break; 1953 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1); 1954 i--; 1955 } 1956 1957 if (i <= 0) 1958 device_printf(sc->sc_dev, 1959 "%s: didn't finish after %d iterations\n", 1960 __func__, MAX_TXRX_ITERATIONS); 1961} 1962#undef MAX_TXRX_ITERATIONS 1963 1964#if 0 1965static void 1966ath_txrx_stop(struct ath_softc *sc) 1967{ 1968 ATH_UNLOCK_ASSERT(sc); 1969 ATH_PCU_UNLOCK_ASSERT(sc); 1970 1971 ATH_PCU_LOCK(sc); 1972 ath_txrx_stop_locked(sc); 1973 ATH_PCU_UNLOCK(sc); 1974} 1975#endif 1976 1977static void 1978ath_txrx_start(struct ath_softc *sc) 1979{ 1980 1981 taskqueue_unblock(sc->sc_tq); 1982} 1983 1984/* 1985 * Grab the reset lock, and wait around until noone else 1986 * is trying to do anything with it. 1987 * 1988 * This is totally horrible but we can't hold this lock for 1989 * long enough to do TX/RX or we end up with net80211/ip stack 1990 * LORs and eventual deadlock. 1991 * 1992 * "dowait" signals whether to spin, waiting for the reset 1993 * lock count to reach 0. This should (for now) only be used 1994 * during the reset path, as the rest of the code may not 1995 * be locking-reentrant enough to behave correctly. 1996 * 1997 * Another, cleaner way should be found to serialise all of 1998 * these operations. 1999 */ 2000#define MAX_RESET_ITERATIONS 10 2001static int 2002ath_reset_grablock(struct ath_softc *sc, int dowait) 2003{ 2004 int w = 0; 2005 int i = MAX_RESET_ITERATIONS; 2006 2007 ATH_PCU_LOCK_ASSERT(sc); 2008 do { 2009 if (sc->sc_inreset_cnt == 0) { 2010 w = 1; 2011 break; 2012 } 2013 if (dowait == 0) { 2014 w = 0; 2015 break; 2016 } 2017 ATH_PCU_UNLOCK(sc); 2018 pause("ath_reset_grablock", 1); 2019 i--; 2020 ATH_PCU_LOCK(sc); 2021 } while (i > 0); 2022 2023 /* 2024 * We always increment the refcounter, regardless 2025 * of whether we succeeded to get it in an exclusive 2026 * way. 2027 */ 2028 sc->sc_inreset_cnt++; 2029 2030 if (i <= 0) 2031 device_printf(sc->sc_dev, 2032 "%s: didn't finish after %d iterations\n", 2033 __func__, MAX_RESET_ITERATIONS); 2034 2035 if (w == 0) 2036 device_printf(sc->sc_dev, 2037 "%s: warning, recursive reset path!\n", 2038 __func__); 2039 2040 return w; 2041} 2042#undef MAX_RESET_ITERATIONS 2043 2044/* 2045 * XXX TODO: write ath_reset_releaselock 2046 */ 2047 2048static void 2049ath_stop(struct ifnet *ifp) 2050{ 2051 struct ath_softc *sc = ifp->if_softc; 2052 2053 ATH_LOCK(sc); 2054 ath_stop_locked(ifp); 2055 ATH_UNLOCK(sc); 2056} 2057 2058/* 2059 * Reset the hardware w/o losing operational state. This is 2060 * basically a more efficient way of doing ath_stop, ath_init, 2061 * followed by state transitions to the current 802.11 2062 * operational state. Used to recover from various errors and 2063 * to reset or reload hardware state. 2064 */ 2065int 2066ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type) 2067{ 2068 struct ath_softc *sc = ifp->if_softc; 2069 struct ieee80211com *ic = ifp->if_l2com; 2070 struct ath_hal *ah = sc->sc_ah; 2071 HAL_STATUS status; 2072 int i; 2073 2074 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2075 2076 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2077 ATH_PCU_UNLOCK_ASSERT(sc); 2078 ATH_UNLOCK_ASSERT(sc); 2079 2080 /* Try to (stop any further TX/RX from occuring */ 2081 taskqueue_block(sc->sc_tq); 2082 2083 ATH_PCU_LOCK(sc); 2084 ath_hal_intrset(ah, 0); /* disable interrupts */ 2085 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */ 2086 if (ath_reset_grablock(sc, 1) == 0) { 2087 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2088 __func__); 2089 } 2090 ATH_PCU_UNLOCK(sc); 2091 2092 /* 2093 * Should now wait for pending TX/RX to complete 2094 * and block future ones from occuring. This needs to be 2095 * done before the TX queue is drained. 2096 */ 2097 ath_draintxq(sc, reset_type); /* stop xmit side */ 2098 2099 /* 2100 * Regardless of whether we're doing a no-loss flush or 2101 * not, stop the PCU and handle what's in the RX queue. 2102 * That way frames aren't dropped which shouldn't be. 2103 */ 2104 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2105 ath_rx_proc(sc, 0); 2106 2107 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2108 /* NB: indicate channel change so we do a full reset */ 2109 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 2110 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 2111 __func__, status); 2112 sc->sc_diversity = ath_hal_getdiversity(ah); 2113 2114 /* Let DFS at it in case it's a DFS channel */ 2115 ath_dfs_radar_enable(sc, ic->ic_curchan); 2116 2117 if (ath_startrecv(sc) != 0) /* restart recv */ 2118 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 2119 /* 2120 * We may be doing a reset in response to an ioctl 2121 * that changes the channel so update any state that 2122 * might change as a result. 2123 */ 2124 ath_chan_change(sc, ic->ic_curchan); 2125 if (sc->sc_beacons) { /* restart beacons */ 2126#ifdef IEEE80211_SUPPORT_TDMA 2127 if (sc->sc_tdma) 2128 ath_tdma_config(sc, NULL); 2129 else 2130#endif 2131 ath_beacon_config(sc, NULL); 2132 } 2133 2134 /* 2135 * Release the reset lock and re-enable interrupts here. 2136 * If an interrupt was being processed in ath_intr(), 2137 * it would disable interrupts at this point. So we have 2138 * to atomically enable interrupts and decrement the 2139 * reset counter - this way ath_intr() doesn't end up 2140 * disabling interrupts without a corresponding enable 2141 * in the rest or channel change path. 2142 */ 2143 ATH_PCU_LOCK(sc); 2144 sc->sc_inreset_cnt--; 2145 /* XXX only do this if sc_inreset_cnt == 0? */ 2146 ath_hal_intrset(ah, sc->sc_imask); 2147 ATH_PCU_UNLOCK(sc); 2148 2149 /* 2150 * TX and RX can be started here. If it were started with 2151 * sc_inreset_cnt > 0, the TX and RX path would abort. 2152 * Thus if this is a nested call through the reset or 2153 * channel change code, TX completion will occur but 2154 * RX completion and ath_start / ath_tx_start will not 2155 * run. 2156 */ 2157 2158 /* Restart TX/RX as needed */ 2159 ath_txrx_start(sc); 2160 2161 /* XXX Restart TX completion and pending TX */ 2162 if (reset_type == ATH_RESET_NOLOSS) { 2163 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2164 if (ATH_TXQ_SETUP(sc, i)) { 2165 ATH_TXQ_LOCK(&sc->sc_txq[i]); 2166 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 2167 ath_txq_sched(sc, &sc->sc_txq[i]); 2168 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 2169 } 2170 } 2171 } 2172 2173 /* 2174 * This may have been set during an ath_start() call which 2175 * set this once it detected a concurrent TX was going on. 2176 * So, clear it. 2177 */ 2178 IF_LOCK(&ifp->if_snd); 2179 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2180 IF_UNLOCK(&ifp->if_snd); 2181 2182 /* Handle any frames in the TX queue */ 2183 /* 2184 * XXX should this be done by the caller, rather than 2185 * ath_reset() ? 2186 */ 2187 ath_start(ifp); /* restart xmit */ 2188 return 0; 2189} 2190 2191static int 2192ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 2193{ 2194 struct ieee80211com *ic = vap->iv_ic; 2195 struct ifnet *ifp = ic->ic_ifp; 2196 struct ath_softc *sc = ifp->if_softc; 2197 struct ath_hal *ah = sc->sc_ah; 2198 2199 switch (cmd) { 2200 case IEEE80211_IOC_TXPOWER: 2201 /* 2202 * If per-packet TPC is enabled, then we have nothing 2203 * to do; otherwise we need to force the global limit. 2204 * All this can happen directly; no need to reset. 2205 */ 2206 if (!ath_hal_gettpc(ah)) 2207 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 2208 return 0; 2209 } 2210 /* XXX? Full or NOLOSS? */ 2211 return ath_reset(ifp, ATH_RESET_FULL); 2212} 2213 2214struct ath_buf * 2215_ath_getbuf_locked(struct ath_softc *sc) 2216{ 2217 struct ath_buf *bf; 2218 2219 ATH_TXBUF_LOCK_ASSERT(sc); 2220 2221 bf = TAILQ_FIRST(&sc->sc_txbuf); 2222 if (bf == NULL) { 2223 sc->sc_stats.ast_tx_getnobuf++; 2224 } else { 2225 if (bf->bf_flags & ATH_BUF_BUSY) { 2226 sc->sc_stats.ast_tx_getbusybuf++; 2227 bf = NULL; 2228 } 2229 } 2230 2231 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 2232 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 2233 else 2234 bf = NULL; 2235 2236 if (bf == NULL) { 2237 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 2238 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 2239 "out of xmit buffers" : "xmit buffer busy"); 2240 return NULL; 2241 } 2242 2243 /* Valid bf here; clear some basic fields */ 2244 bf->bf_next = NULL; /* XXX just to be sure */ 2245 bf->bf_last = NULL; /* XXX again, just to be sure */ 2246 bf->bf_comp = NULL; /* XXX again, just to be sure */ 2247 bzero(&bf->bf_state, sizeof(bf->bf_state)); 2248 2249 return bf; 2250} 2251 2252/* 2253 * When retrying a software frame, buffers marked ATH_BUF_BUSY 2254 * can't be thrown back on the queue as they could still be 2255 * in use by the hardware. 2256 * 2257 * This duplicates the buffer, or returns NULL. 2258 * 2259 * The descriptor is also copied but the link pointers and 2260 * the DMA segments aren't copied; this frame should thus 2261 * be again passed through the descriptor setup/chain routines 2262 * so the link is correct. 2263 * 2264 * The caller must free the buffer using ath_freebuf(). 2265 * 2266 * XXX TODO: this call shouldn't fail as it'll cause packet loss 2267 * XXX in the TX pathway when retries are needed. 2268 * XXX Figure out how to keep some buffers free, or factor the 2269 * XXX number of busy buffers into the xmit path (ath_start()) 2270 * XXX so we don't over-commit. 2271 */ 2272struct ath_buf * 2273ath_buf_clone(struct ath_softc *sc, const struct ath_buf *bf) 2274{ 2275 struct ath_buf *tbf; 2276 2277 tbf = ath_getbuf(sc); 2278 if (tbf == NULL) 2279 return NULL; /* XXX failure? Why? */ 2280 2281 /* Copy basics */ 2282 tbf->bf_next = NULL; 2283 tbf->bf_nseg = bf->bf_nseg; 2284 tbf->bf_flags = bf->bf_flags & ~ATH_BUF_BUSY; 2285 tbf->bf_status = bf->bf_status; 2286 tbf->bf_m = bf->bf_m; 2287 tbf->bf_node = bf->bf_node; 2288 /* will be setup by the chain/setup function */ 2289 tbf->bf_lastds = NULL; 2290 /* for now, last == self */ 2291 tbf->bf_last = tbf; 2292 tbf->bf_comp = bf->bf_comp; 2293 2294 /* NOTE: DMA segments will be setup by the setup/chain functions */ 2295 2296 /* The caller has to re-init the descriptor + links */ 2297 2298 /* Copy state */ 2299 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 2300 2301 return tbf; 2302} 2303 2304struct ath_buf * 2305ath_getbuf(struct ath_softc *sc) 2306{ 2307 struct ath_buf *bf; 2308 2309 ATH_TXBUF_LOCK(sc); 2310 bf = _ath_getbuf_locked(sc); 2311 ATH_TXBUF_UNLOCK(sc); 2312 if (bf == NULL) { 2313 struct ifnet *ifp = sc->sc_ifp; 2314 2315 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 2316 sc->sc_stats.ast_tx_qstop++; 2317 IF_LOCK(&ifp->if_snd); 2318 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2319 IF_UNLOCK(&ifp->if_snd); 2320 } 2321 return bf; 2322} 2323 2324void 2325ath_start(struct ifnet *ifp) 2326{ 2327 struct ath_softc *sc = ifp->if_softc; 2328 struct ieee80211_node *ni; 2329 struct ath_buf *bf; 2330 struct mbuf *m, *next; 2331 ath_bufhead frags; 2332 2333 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 2334 return; 2335 2336 /* XXX is it ok to hold the ATH_LOCK here? */ 2337 ATH_PCU_LOCK(sc); 2338 if (sc->sc_inreset_cnt > 0) { 2339 device_printf(sc->sc_dev, 2340 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 2341 ATH_PCU_UNLOCK(sc); 2342 IF_LOCK(&ifp->if_snd); 2343 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2344 IF_UNLOCK(&ifp->if_snd); 2345 return; 2346 } 2347 sc->sc_txstart_cnt++; 2348 ATH_PCU_UNLOCK(sc); 2349 2350 for (;;) { 2351 /* 2352 * Grab a TX buffer and associated resources. 2353 */ 2354 bf = ath_getbuf(sc); 2355 if (bf == NULL) 2356 break; 2357 2358 IFQ_DEQUEUE(&ifp->if_snd, m); 2359 if (m == NULL) { 2360 ATH_TXBUF_LOCK(sc); 2361 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2362 ATH_TXBUF_UNLOCK(sc); 2363 break; 2364 } 2365 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 2366 /* 2367 * Check for fragmentation. If this frame 2368 * has been broken up verify we have enough 2369 * buffers to send all the fragments so all 2370 * go out or none... 2371 */ 2372 TAILQ_INIT(&frags); 2373 if ((m->m_flags & M_FRAG) && 2374 !ath_txfrag_setup(sc, &frags, m, ni)) { 2375 DPRINTF(sc, ATH_DEBUG_XMIT, 2376 "%s: out of txfrag buffers\n", __func__); 2377 sc->sc_stats.ast_tx_nofrag++; 2378 ifp->if_oerrors++; 2379 ath_freetx(m); 2380 goto bad; 2381 } 2382 ifp->if_opackets++; 2383 nextfrag: 2384 /* 2385 * Pass the frame to the h/w for transmission. 2386 * Fragmented frames have each frag chained together 2387 * with m_nextpkt. We know there are sufficient ath_buf's 2388 * to send all the frags because of work done by 2389 * ath_txfrag_setup. We leave m_nextpkt set while 2390 * calling ath_tx_start so it can use it to extend the 2391 * the tx duration to cover the subsequent frag and 2392 * so it can reclaim all the mbufs in case of an error; 2393 * ath_tx_start clears m_nextpkt once it commits to 2394 * handing the frame to the hardware. 2395 */ 2396 next = m->m_nextpkt; 2397 if (ath_tx_start(sc, ni, bf, m)) { 2398 bad: 2399 ifp->if_oerrors++; 2400 reclaim: 2401 bf->bf_m = NULL; 2402 bf->bf_node = NULL; 2403 ATH_TXBUF_LOCK(sc); 2404 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2405 ath_txfrag_cleanup(sc, &frags, ni); 2406 ATH_TXBUF_UNLOCK(sc); 2407 if (ni != NULL) 2408 ieee80211_free_node(ni); 2409 continue; 2410 } 2411 if (next != NULL) { 2412 /* 2413 * Beware of state changing between frags. 2414 * XXX check sta power-save state? 2415 */ 2416 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2417 DPRINTF(sc, ATH_DEBUG_XMIT, 2418 "%s: flush fragmented packet, state %s\n", 2419 __func__, 2420 ieee80211_state_name[ni->ni_vap->iv_state]); 2421 ath_freetx(next); 2422 goto reclaim; 2423 } 2424 m = next; 2425 bf = TAILQ_FIRST(&frags); 2426 KASSERT(bf != NULL, ("no buf for txfrag")); 2427 TAILQ_REMOVE(&frags, bf, bf_list); 2428 goto nextfrag; 2429 } 2430 2431 sc->sc_wd_timer = 5; 2432 } 2433 2434 ATH_PCU_LOCK(sc); 2435 sc->sc_txstart_cnt--; 2436 ATH_PCU_UNLOCK(sc); 2437} 2438 2439static int 2440ath_media_change(struct ifnet *ifp) 2441{ 2442 int error = ieee80211_media_change(ifp); 2443 /* NB: only the fixed rate can change and that doesn't need a reset */ 2444 return (error == ENETRESET ? 0 : error); 2445} 2446 2447/* 2448 * Block/unblock tx+rx processing while a key change is done. 2449 * We assume the caller serializes key management operations 2450 * so we only need to worry about synchronization with other 2451 * uses that originate in the driver. 2452 */ 2453static void 2454ath_key_update_begin(struct ieee80211vap *vap) 2455{ 2456 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2457 struct ath_softc *sc = ifp->if_softc; 2458 2459 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2460 taskqueue_block(sc->sc_tq); 2461 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2462} 2463 2464static void 2465ath_key_update_end(struct ieee80211vap *vap) 2466{ 2467 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2468 struct ath_softc *sc = ifp->if_softc; 2469 2470 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2471 IF_UNLOCK(&ifp->if_snd); 2472 taskqueue_unblock(sc->sc_tq); 2473} 2474 2475static void 2476ath_update_promisc(struct ifnet *ifp) 2477{ 2478 struct ath_softc *sc = ifp->if_softc; 2479 u_int32_t rfilt; 2480 2481 /* configure rx filter */ 2482 rfilt = ath_calcrxfilter(sc); 2483 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2484 2485 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2486} 2487 2488static void 2489ath_update_mcast(struct ifnet *ifp) 2490{ 2491 struct ath_softc *sc = ifp->if_softc; 2492 u_int32_t mfilt[2]; 2493 2494 /* calculate and install multicast filter */ 2495 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2496 struct ifmultiaddr *ifma; 2497 /* 2498 * Merge multicast addresses to form the hardware filter. 2499 */ 2500 mfilt[0] = mfilt[1] = 0; 2501 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2502 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2503 caddr_t dl; 2504 u_int32_t val; 2505 u_int8_t pos; 2506 2507 /* calculate XOR of eight 6bit values */ 2508 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2509 val = LE_READ_4(dl + 0); 2510 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2511 val = LE_READ_4(dl + 3); 2512 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2513 pos &= 0x3f; 2514 mfilt[pos / 32] |= (1 << (pos % 32)); 2515 } 2516 if_maddr_runlock(ifp); 2517 } else 2518 mfilt[0] = mfilt[1] = ~0; 2519 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2520 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2521 __func__, mfilt[0], mfilt[1]); 2522} 2523 2524void 2525ath_mode_init(struct ath_softc *sc) 2526{ 2527 struct ifnet *ifp = sc->sc_ifp; 2528 struct ath_hal *ah = sc->sc_ah; 2529 u_int32_t rfilt; 2530 2531 /* configure rx filter */ 2532 rfilt = ath_calcrxfilter(sc); 2533 ath_hal_setrxfilter(ah, rfilt); 2534 2535 /* configure operational mode */ 2536 ath_hal_setopmode(ah); 2537 2538 /* handle any link-level address change */ 2539 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2540 2541 /* calculate and install multicast filter */ 2542 ath_update_mcast(ifp); 2543} 2544 2545/* 2546 * Set the slot time based on the current setting. 2547 */ 2548void 2549ath_setslottime(struct ath_softc *sc) 2550{ 2551 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2552 struct ath_hal *ah = sc->sc_ah; 2553 u_int usec; 2554 2555 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2556 usec = 13; 2557 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2558 usec = 21; 2559 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2560 /* honor short/long slot time only in 11g */ 2561 /* XXX shouldn't honor on pure g or turbo g channel */ 2562 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2563 usec = HAL_SLOT_TIME_9; 2564 else 2565 usec = HAL_SLOT_TIME_20; 2566 } else 2567 usec = HAL_SLOT_TIME_9; 2568 2569 DPRINTF(sc, ATH_DEBUG_RESET, 2570 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2571 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2572 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2573 2574 ath_hal_setslottime(ah, usec); 2575 sc->sc_updateslot = OK; 2576} 2577 2578/* 2579 * Callback from the 802.11 layer to update the 2580 * slot time based on the current setting. 2581 */ 2582static void 2583ath_updateslot(struct ifnet *ifp) 2584{ 2585 struct ath_softc *sc = ifp->if_softc; 2586 struct ieee80211com *ic = ifp->if_l2com; 2587 2588 /* 2589 * When not coordinating the BSS, change the hardware 2590 * immediately. For other operation we defer the change 2591 * until beacon updates have propagated to the stations. 2592 */ 2593 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2594 ic->ic_opmode == IEEE80211_M_MBSS) 2595 sc->sc_updateslot = UPDATE; 2596 else 2597 ath_setslottime(sc); 2598} 2599 2600/* 2601 * Append the contents of src to dst; both queues 2602 * are assumed to be locked. 2603 */ 2604void 2605ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2606{ 2607 2608 ATH_TXQ_LOCK_ASSERT(dst); 2609 ATH_TXQ_LOCK_ASSERT(src); 2610 2611 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 2612 dst->axq_link = src->axq_link; 2613 src->axq_link = NULL; 2614 dst->axq_depth += src->axq_depth; 2615 dst->axq_aggr_depth += src->axq_aggr_depth; 2616 src->axq_depth = 0; 2617 src->axq_aggr_depth = 0; 2618} 2619 2620/* 2621 * Reset the hardware, with no loss. 2622 * 2623 * This can't be used for a general case reset. 2624 */ 2625static void 2626ath_reset_proc(void *arg, int pending) 2627{ 2628 struct ath_softc *sc = arg; 2629 struct ifnet *ifp = sc->sc_ifp; 2630 2631#if 0 2632 if_printf(ifp, "%s: resetting\n", __func__); 2633#endif 2634 ath_reset(ifp, ATH_RESET_NOLOSS); 2635} 2636 2637/* 2638 * Reset the hardware after detecting beacons have stopped. 2639 */ 2640static void 2641ath_bstuck_proc(void *arg, int pending) 2642{ 2643 struct ath_softc *sc = arg; 2644 struct ifnet *ifp = sc->sc_ifp; 2645 uint32_t hangs = 0; 2646 2647 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 2648 if_printf(ifp, "bb hang detected (0x%x)\n", hangs); 2649 2650 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2651 sc->sc_bmisscount); 2652 sc->sc_stats.ast_bstuck++; 2653 /* 2654 * This assumes that there's no simultaneous channel mode change 2655 * occuring. 2656 */ 2657 ath_reset(ifp, ATH_RESET_NOLOSS); 2658} 2659 2660static void 2661ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2662{ 2663 bus_addr_t *paddr = (bus_addr_t*) arg; 2664 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2665 *paddr = segs->ds_addr; 2666} 2667 2668static int 2669ath_descdma_setup(struct ath_softc *sc, 2670 struct ath_descdma *dd, ath_bufhead *head, 2671 const char *name, int nbuf, int ndesc) 2672{ 2673#define DS2PHYS(_dd, _ds) \ 2674 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2675#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 2676 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 2677 struct ifnet *ifp = sc->sc_ifp; 2678 uint8_t *ds; 2679 struct ath_buf *bf; 2680 int i, bsize, error; 2681 int desc_len; 2682 2683 desc_len = sizeof(struct ath_desc); 2684 2685 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2686 __func__, name, nbuf, ndesc); 2687 2688 dd->dd_name = name; 2689 dd->dd_desc_len = desc_len * nbuf * ndesc; 2690 2691 /* 2692 * Merlin work-around: 2693 * Descriptors that cross the 4KB boundary can't be used. 2694 * Assume one skipped descriptor per 4KB page. 2695 */ 2696 if (! ath_hal_split4ktrans(sc->sc_ah)) { 2697 int numdescpage = 4096 / (desc_len * ndesc); 2698 dd->dd_desc_len = (nbuf / numdescpage + 1) * 4096; 2699 } 2700 2701 /* 2702 * Setup DMA descriptor area. 2703 */ 2704 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 2705 PAGE_SIZE, 0, /* alignment, bounds */ 2706 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2707 BUS_SPACE_MAXADDR, /* highaddr */ 2708 NULL, NULL, /* filter, filterarg */ 2709 dd->dd_desc_len, /* maxsize */ 2710 1, /* nsegments */ 2711 dd->dd_desc_len, /* maxsegsize */ 2712 BUS_DMA_ALLOCNOW, /* flags */ 2713 NULL, /* lockfunc */ 2714 NULL, /* lockarg */ 2715 &dd->dd_dmat); 2716 if (error != 0) { 2717 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2718 return error; 2719 } 2720 2721 /* allocate descriptors */ 2722 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2723 if (error != 0) { 2724 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2725 "error %u\n", dd->dd_name, error); 2726 goto fail0; 2727 } 2728 2729 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2730 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2731 &dd->dd_dmamap); 2732 if (error != 0) { 2733 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2734 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2735 goto fail1; 2736 } 2737 2738 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2739 dd->dd_desc, dd->dd_desc_len, 2740 ath_load_cb, &dd->dd_desc_paddr, 2741 BUS_DMA_NOWAIT); 2742 if (error != 0) { 2743 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2744 dd->dd_name, error); 2745 goto fail2; 2746 } 2747 2748 ds = (uint8_t *) dd->dd_desc; 2749 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2750 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2751 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2752 2753 /* allocate rx buffers */ 2754 bsize = sizeof(struct ath_buf) * nbuf; 2755 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2756 if (bf == NULL) { 2757 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2758 dd->dd_name, bsize); 2759 goto fail3; 2760 } 2761 dd->dd_bufptr = bf; 2762 2763 TAILQ_INIT(head); 2764 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * desc_len)) { 2765 bf->bf_desc = (struct ath_desc *) ds; 2766 bf->bf_daddr = DS2PHYS(dd, ds); 2767 if (! ath_hal_split4ktrans(sc->sc_ah)) { 2768 /* 2769 * Merlin WAR: Skip descriptor addresses which 2770 * cause 4KB boundary crossing along any point 2771 * in the descriptor. 2772 */ 2773 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 2774 desc_len * ndesc)) { 2775 /* Start at the next page */ 2776 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 2777 bf->bf_desc = (struct ath_desc *) ds; 2778 bf->bf_daddr = DS2PHYS(dd, ds); 2779 } 2780 } 2781 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2782 &bf->bf_dmamap); 2783 if (error != 0) { 2784 if_printf(ifp, "unable to create dmamap for %s " 2785 "buffer %u, error %u\n", dd->dd_name, i, error); 2786 ath_descdma_cleanup(sc, dd, head); 2787 return error; 2788 } 2789 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 2790 TAILQ_INSERT_TAIL(head, bf, bf_list); 2791 } 2792 return 0; 2793fail3: 2794 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2795fail2: 2796 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2797fail1: 2798 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2799fail0: 2800 bus_dma_tag_destroy(dd->dd_dmat); 2801 memset(dd, 0, sizeof(*dd)); 2802 return error; 2803#undef DS2PHYS 2804#undef ATH_DESC_4KB_BOUND_CHECK 2805} 2806 2807static void 2808ath_descdma_cleanup(struct ath_softc *sc, 2809 struct ath_descdma *dd, ath_bufhead *head) 2810{ 2811 struct ath_buf *bf; 2812 struct ieee80211_node *ni; 2813 2814 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2815 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2816 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2817 bus_dma_tag_destroy(dd->dd_dmat); 2818 2819 TAILQ_FOREACH(bf, head, bf_list) { 2820 if (bf->bf_m) { 2821 m_freem(bf->bf_m); 2822 bf->bf_m = NULL; 2823 } 2824 if (bf->bf_dmamap != NULL) { 2825 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2826 bf->bf_dmamap = NULL; 2827 } 2828 ni = bf->bf_node; 2829 bf->bf_node = NULL; 2830 if (ni != NULL) { 2831 /* 2832 * Reclaim node reference. 2833 */ 2834 ieee80211_free_node(ni); 2835 } 2836 } 2837 2838 TAILQ_INIT(head); 2839 free(dd->dd_bufptr, M_ATHDEV); 2840 memset(dd, 0, sizeof(*dd)); 2841} 2842 2843static int 2844ath_desc_alloc(struct ath_softc *sc) 2845{ 2846 int error; 2847 2848 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2849 "rx", ath_rxbuf, 1); 2850 if (error != 0) 2851 return error; 2852 2853 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2854 "tx", ath_txbuf, ATH_TXDESC); 2855 if (error != 0) { 2856 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2857 return error; 2858 } 2859 2860 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2861 "beacon", ATH_BCBUF, 1); 2862 if (error != 0) { 2863 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2864 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2865 return error; 2866 } 2867 return 0; 2868} 2869 2870static void 2871ath_desc_free(struct ath_softc *sc) 2872{ 2873 2874 if (sc->sc_bdma.dd_desc_len != 0) 2875 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2876 if (sc->sc_txdma.dd_desc_len != 0) 2877 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2878 if (sc->sc_rxdma.dd_desc_len != 0) 2879 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2880} 2881 2882static struct ieee80211_node * 2883ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2884{ 2885 struct ieee80211com *ic = vap->iv_ic; 2886 struct ath_softc *sc = ic->ic_ifp->if_softc; 2887 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2888 struct ath_node *an; 2889 2890 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2891 if (an == NULL) { 2892 /* XXX stat+msg */ 2893 return NULL; 2894 } 2895 ath_rate_node_init(sc, an); 2896 2897 /* Setup the mutex - there's no associd yet so set the name to NULL */ 2898 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 2899 device_get_nameunit(sc->sc_dev), an); 2900 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 2901 2902 /* XXX setup ath_tid */ 2903 ath_tx_tid_init(sc, an); 2904 2905 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2906 return &an->an_node; 2907} 2908 2909static void 2910ath_node_cleanup(struct ieee80211_node *ni) 2911{ 2912 struct ieee80211com *ic = ni->ni_ic; 2913 struct ath_softc *sc = ic->ic_ifp->if_softc; 2914 2915 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 2916 ath_tx_node_flush(sc, ATH_NODE(ni)); 2917 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2918 sc->sc_node_cleanup(ni); 2919} 2920 2921static void 2922ath_node_free(struct ieee80211_node *ni) 2923{ 2924 struct ieee80211com *ic = ni->ni_ic; 2925 struct ath_softc *sc = ic->ic_ifp->if_softc; 2926 2927 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2928 mtx_destroy(&ATH_NODE(ni)->an_mtx); 2929 sc->sc_node_free(ni); 2930} 2931 2932static void 2933ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 2934{ 2935 struct ieee80211com *ic = ni->ni_ic; 2936 struct ath_softc *sc = ic->ic_ifp->if_softc; 2937 struct ath_hal *ah = sc->sc_ah; 2938 2939 *rssi = ic->ic_node_getrssi(ni); 2940 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 2941 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 2942 else 2943 *noise = -95; /* nominally correct */ 2944} 2945 2946/* 2947 * Set the default antenna. 2948 */ 2949void 2950ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2951{ 2952 struct ath_hal *ah = sc->sc_ah; 2953 2954 /* XXX block beacon interrupts */ 2955 ath_hal_setdefantenna(ah, antenna); 2956 if (sc->sc_defant != antenna) 2957 sc->sc_stats.ast_ant_defswitch++; 2958 sc->sc_defant = antenna; 2959 sc->sc_rxotherant = 0; 2960} 2961 2962static void 2963ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 2964{ 2965 txq->axq_qnum = qnum; 2966 txq->axq_ac = 0; 2967 txq->axq_depth = 0; 2968 txq->axq_aggr_depth = 0; 2969 txq->axq_intrcnt = 0; 2970 txq->axq_link = NULL; 2971 txq->axq_softc = sc; 2972 TAILQ_INIT(&txq->axq_q); 2973 TAILQ_INIT(&txq->axq_tidq); 2974 ATH_TXQ_LOCK_INIT(sc, txq); 2975} 2976 2977/* 2978 * Setup a h/w transmit queue. 2979 */ 2980static struct ath_txq * 2981ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 2982{ 2983#define N(a) (sizeof(a)/sizeof(a[0])) 2984 struct ath_hal *ah = sc->sc_ah; 2985 HAL_TXQ_INFO qi; 2986 int qnum; 2987 2988 memset(&qi, 0, sizeof(qi)); 2989 qi.tqi_subtype = subtype; 2990 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2991 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2992 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2993 /* 2994 * Enable interrupts only for EOL and DESC conditions. 2995 * We mark tx descriptors to receive a DESC interrupt 2996 * when a tx queue gets deep; otherwise waiting for the 2997 * EOL to reap descriptors. Note that this is done to 2998 * reduce interrupt load and this only defers reaping 2999 * descriptors, never transmitting frames. Aside from 3000 * reducing interrupts this also permits more concurrency. 3001 * The only potential downside is if the tx queue backs 3002 * up in which case the top half of the kernel may backup 3003 * due to a lack of tx descriptors. 3004 */ 3005 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3006 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3007 if (qnum == -1) { 3008 /* 3009 * NB: don't print a message, this happens 3010 * normally on parts with too few tx queues 3011 */ 3012 return NULL; 3013 } 3014 if (qnum >= N(sc->sc_txq)) { 3015 device_printf(sc->sc_dev, 3016 "hal qnum %u out of range, max %zu!\n", 3017 qnum, N(sc->sc_txq)); 3018 ath_hal_releasetxqueue(ah, qnum); 3019 return NULL; 3020 } 3021 if (!ATH_TXQ_SETUP(sc, qnum)) { 3022 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 3023 sc->sc_txqsetup |= 1<<qnum; 3024 } 3025 return &sc->sc_txq[qnum]; 3026#undef N 3027} 3028 3029/* 3030 * Setup a hardware data transmit queue for the specified 3031 * access control. The hal may not support all requested 3032 * queues in which case it will return a reference to a 3033 * previously setup queue. We record the mapping from ac's 3034 * to h/w queues for use by ath_tx_start and also track 3035 * the set of h/w queues being used to optimize work in the 3036 * transmit interrupt handler and related routines. 3037 */ 3038static int 3039ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3040{ 3041#define N(a) (sizeof(a)/sizeof(a[0])) 3042 struct ath_txq *txq; 3043 3044 if (ac >= N(sc->sc_ac2q)) { 3045 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3046 ac, N(sc->sc_ac2q)); 3047 return 0; 3048 } 3049 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3050 if (txq != NULL) { 3051 txq->axq_ac = ac; 3052 sc->sc_ac2q[ac] = txq; 3053 return 1; 3054 } else 3055 return 0; 3056#undef N 3057} 3058 3059/* 3060 * Update WME parameters for a transmit queue. 3061 */ 3062static int 3063ath_txq_update(struct ath_softc *sc, int ac) 3064{ 3065#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3066#define ATH_TXOP_TO_US(v) (v<<5) 3067 struct ifnet *ifp = sc->sc_ifp; 3068 struct ieee80211com *ic = ifp->if_l2com; 3069 struct ath_txq *txq = sc->sc_ac2q[ac]; 3070 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3071 struct ath_hal *ah = sc->sc_ah; 3072 HAL_TXQ_INFO qi; 3073 3074 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3075#ifdef IEEE80211_SUPPORT_TDMA 3076 if (sc->sc_tdma) { 3077 /* 3078 * AIFS is zero so there's no pre-transmit wait. The 3079 * burst time defines the slot duration and is configured 3080 * through net80211. The QCU is setup to not do post-xmit 3081 * back off, lockout all lower-priority QCU's, and fire 3082 * off the DMA beacon alert timer which is setup based 3083 * on the slot configuration. 3084 */ 3085 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3086 | HAL_TXQ_TXERRINT_ENABLE 3087 | HAL_TXQ_TXURNINT_ENABLE 3088 | HAL_TXQ_TXEOLINT_ENABLE 3089 | HAL_TXQ_DBA_GATED 3090 | HAL_TXQ_BACKOFF_DISABLE 3091 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 3092 ; 3093 qi.tqi_aifs = 0; 3094 /* XXX +dbaprep? */ 3095 qi.tqi_readyTime = sc->sc_tdmaslotlen; 3096 qi.tqi_burstTime = qi.tqi_readyTime; 3097 } else { 3098#endif 3099 /* 3100 * XXX shouldn't this just use the default flags 3101 * used in the previous queue setup? 3102 */ 3103 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3104 | HAL_TXQ_TXERRINT_ENABLE 3105 | HAL_TXQ_TXDESCINT_ENABLE 3106 | HAL_TXQ_TXURNINT_ENABLE 3107 | HAL_TXQ_TXEOLINT_ENABLE 3108 ; 3109 qi.tqi_aifs = wmep->wmep_aifsn; 3110 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3111 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3112 qi.tqi_readyTime = 0; 3113 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3114#ifdef IEEE80211_SUPPORT_TDMA 3115 } 3116#endif 3117 3118 DPRINTF(sc, ATH_DEBUG_RESET, 3119 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 3120 __func__, txq->axq_qnum, qi.tqi_qflags, 3121 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 3122 3123 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3124 if_printf(ifp, "unable to update hardware queue " 3125 "parameters for %s traffic!\n", 3126 ieee80211_wme_acnames[ac]); 3127 return 0; 3128 } else { 3129 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3130 return 1; 3131 } 3132#undef ATH_TXOP_TO_US 3133#undef ATH_EXPONENT_TO_VALUE 3134} 3135 3136/* 3137 * Callback from the 802.11 layer to update WME parameters. 3138 */ 3139int 3140ath_wme_update(struct ieee80211com *ic) 3141{ 3142 struct ath_softc *sc = ic->ic_ifp->if_softc; 3143 3144 return !ath_txq_update(sc, WME_AC_BE) || 3145 !ath_txq_update(sc, WME_AC_BK) || 3146 !ath_txq_update(sc, WME_AC_VI) || 3147 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3148} 3149 3150/* 3151 * Reclaim resources for a setup queue. 3152 */ 3153static void 3154ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3155{ 3156 3157 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3158 ATH_TXQ_LOCK_DESTROY(txq); 3159 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3160} 3161 3162/* 3163 * Reclaim all tx queue resources. 3164 */ 3165static void 3166ath_tx_cleanup(struct ath_softc *sc) 3167{ 3168 int i; 3169 3170 ATH_TXBUF_LOCK_DESTROY(sc); 3171 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3172 if (ATH_TXQ_SETUP(sc, i)) 3173 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3174} 3175 3176/* 3177 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 3178 * using the current rates in sc_rixmap. 3179 */ 3180int 3181ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 3182{ 3183 int rix = sc->sc_rixmap[rate]; 3184 /* NB: return lowest rix for invalid rate */ 3185 return (rix == 0xff ? 0 : rix); 3186} 3187 3188static void 3189ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 3190 struct ath_buf *bf) 3191{ 3192 struct ieee80211_node *ni = bf->bf_node; 3193 struct ifnet *ifp = sc->sc_ifp; 3194 struct ieee80211com *ic = ifp->if_l2com; 3195 int sr, lr, pri; 3196 3197 if (ts->ts_status == 0) { 3198 u_int8_t txant = ts->ts_antenna; 3199 sc->sc_stats.ast_ant_tx[txant]++; 3200 sc->sc_ant_tx[txant]++; 3201 if (ts->ts_finaltsi != 0) 3202 sc->sc_stats.ast_tx_altrate++; 3203 pri = M_WME_GETAC(bf->bf_m); 3204 if (pri >= WME_AC_VO) 3205 ic->ic_wme.wme_hipri_traffic++; 3206 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 3207 ni->ni_inact = ni->ni_inact_reload; 3208 } else { 3209 if (ts->ts_status & HAL_TXERR_XRETRY) 3210 sc->sc_stats.ast_tx_xretries++; 3211 if (ts->ts_status & HAL_TXERR_FIFO) 3212 sc->sc_stats.ast_tx_fifoerr++; 3213 if (ts->ts_status & HAL_TXERR_FILT) 3214 sc->sc_stats.ast_tx_filtered++; 3215 if (ts->ts_status & HAL_TXERR_XTXOP) 3216 sc->sc_stats.ast_tx_xtxop++; 3217 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 3218 sc->sc_stats.ast_tx_timerexpired++; 3219 3220 if (ts->ts_status & HAL_TX_DATA_UNDERRUN) 3221 sc->sc_stats.ast_tx_data_underrun++; 3222 if (ts->ts_status & HAL_TX_DELIM_UNDERRUN) 3223 sc->sc_stats.ast_tx_delim_underrun++; 3224 3225 if (bf->bf_m->m_flags & M_FF) 3226 sc->sc_stats.ast_ff_txerr++; 3227 } 3228 /* XXX when is this valid? */ 3229 if (ts->ts_status & HAL_TX_DESC_CFG_ERR) 3230 sc->sc_stats.ast_tx_desccfgerr++; 3231 3232 sr = ts->ts_shortretry; 3233 lr = ts->ts_longretry; 3234 sc->sc_stats.ast_tx_shortretry += sr; 3235 sc->sc_stats.ast_tx_longretry += lr; 3236 3237} 3238 3239/* 3240 * The default completion. If fail is 1, this means 3241 * "please don't retry the frame, and just return -1 status 3242 * to the net80211 stack. 3243 */ 3244void 3245ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3246{ 3247 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3248 int st; 3249 3250 if (fail == 1) 3251 st = -1; 3252 else 3253 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 3254 ts->ts_status : HAL_TXERR_XRETRY; 3255 3256 if (bf->bf_state.bfs_dobaw) 3257 device_printf(sc->sc_dev, 3258 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 3259 __func__, 3260 bf, 3261 SEQNO(bf->bf_state.bfs_seqno)); 3262 if (bf->bf_next != NULL) 3263 device_printf(sc->sc_dev, 3264 "%s: bf %p: seqno %d: bf_next not NULL!\n", 3265 __func__, 3266 bf, 3267 SEQNO(bf->bf_state.bfs_seqno)); 3268 3269 /* 3270 * Do any tx complete callback. Note this must 3271 * be done before releasing the node reference. 3272 * This will free the mbuf, release the net80211 3273 * node and recycle the ath_buf. 3274 */ 3275 ath_tx_freebuf(sc, bf, st); 3276} 3277 3278/* 3279 * Update rate control with the given completion status. 3280 */ 3281void 3282ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 3283 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 3284 int nframes, int nbad) 3285{ 3286 struct ath_node *an; 3287 3288 /* Only for unicast frames */ 3289 if (ni == NULL) 3290 return; 3291 3292 an = ATH_NODE(ni); 3293 3294 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 3295 ATH_NODE_LOCK(an); 3296 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 3297 ATH_NODE_UNLOCK(an); 3298 } 3299} 3300 3301/* 3302 * Update the busy status of the last frame on the free list. 3303 * When doing TDMA, the busy flag tracks whether the hardware 3304 * currently points to this buffer or not, and thus gated DMA 3305 * may restart by re-reading the last descriptor in this 3306 * buffer. 3307 * 3308 * This should be called in the completion function once one 3309 * of the buffers has been used. 3310 */ 3311static void 3312ath_tx_update_busy(struct ath_softc *sc) 3313{ 3314 struct ath_buf *last; 3315 3316 /* 3317 * Since the last frame may still be marked 3318 * as ATH_BUF_BUSY, unmark it here before 3319 * finishing the frame processing. 3320 * Since we've completed a frame (aggregate 3321 * or otherwise), the hardware has moved on 3322 * and is no longer referencing the previous 3323 * descriptor. 3324 */ 3325 ATH_TXBUF_LOCK_ASSERT(sc); 3326 last = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 3327 if (last != NULL) 3328 last->bf_flags &= ~ATH_BUF_BUSY; 3329} 3330 3331 3332/* 3333 * Process completed xmit descriptors from the specified queue. 3334 * Kick the packet scheduler if needed. This can occur from this 3335 * particular task. 3336 */ 3337static int 3338ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 3339{ 3340 struct ath_hal *ah = sc->sc_ah; 3341 struct ath_buf *bf; 3342 struct ath_desc *ds; 3343 struct ath_tx_status *ts; 3344 struct ieee80211_node *ni; 3345 struct ath_node *an; 3346#ifdef IEEE80211_SUPPORT_SUPERG 3347 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3348#endif /* IEEE80211_SUPPORT_SUPERG */ 3349 int nacked; 3350 HAL_STATUS status; 3351 3352 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3353 __func__, txq->axq_qnum, 3354 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3355 txq->axq_link); 3356 nacked = 0; 3357 for (;;) { 3358 ATH_TXQ_LOCK(txq); 3359 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3360 bf = TAILQ_FIRST(&txq->axq_q); 3361 if (bf == NULL) { 3362 ATH_TXQ_UNLOCK(txq); 3363 break; 3364 } 3365 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 3366 ts = &bf->bf_status.ds_txstat; 3367 status = ath_hal_txprocdesc(ah, ds, ts); 3368#ifdef ATH_DEBUG 3369 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3370 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3371 status == HAL_OK); 3372 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) { 3373 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3374 status == HAL_OK); 3375 } 3376#endif 3377 if (status == HAL_EINPROGRESS) { 3378 ATH_TXQ_UNLOCK(txq); 3379 break; 3380 } 3381 ATH_TXQ_REMOVE(txq, bf, bf_list); 3382#ifdef IEEE80211_SUPPORT_TDMA 3383 if (txq->axq_depth > 0) { 3384 /* 3385 * More frames follow. Mark the buffer busy 3386 * so it's not re-used while the hardware may 3387 * still re-read the link field in the descriptor. 3388 * 3389 * Use the last buffer in an aggregate as that 3390 * is where the hardware may be - intermediate 3391 * descriptors won't be "busy". 3392 */ 3393 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 3394 } else 3395#else 3396 if (txq->axq_depth == 0) 3397#endif 3398 txq->axq_link = NULL; 3399 if (bf->bf_state.bfs_aggr) 3400 txq->axq_aggr_depth--; 3401 3402 ni = bf->bf_node; 3403 /* 3404 * If unicast frame was ack'd update RSSI, 3405 * including the last rx time used to 3406 * workaround phantom bmiss interrupts. 3407 */ 3408 if (ni != NULL && ts->ts_status == 0 && 3409 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 3410 nacked++; 3411 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 3412 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3413 ts->ts_rssi); 3414 } 3415 ATH_TXQ_UNLOCK(txq); 3416 3417 /* If unicast frame, update general statistics */ 3418 if (ni != NULL) { 3419 an = ATH_NODE(ni); 3420 /* update statistics */ 3421 ath_tx_update_stats(sc, ts, bf); 3422 } 3423 3424 /* 3425 * Call the completion handler. 3426 * The completion handler is responsible for 3427 * calling the rate control code. 3428 * 3429 * Frames with no completion handler get the 3430 * rate control code called here. 3431 */ 3432 if (bf->bf_comp == NULL) { 3433 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 3434 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 3435 /* 3436 * XXX assume this isn't an aggregate 3437 * frame. 3438 */ 3439 ath_tx_update_ratectrl(sc, ni, 3440 bf->bf_state.bfs_rc, ts, 3441 bf->bf_state.bfs_pktlen, 1, 3442 (ts->ts_status == 0 ? 0 : 1)); 3443 } 3444 ath_tx_default_comp(sc, bf, 0); 3445 } else 3446 bf->bf_comp(sc, bf, 0); 3447 } 3448#ifdef IEEE80211_SUPPORT_SUPERG 3449 /* 3450 * Flush fast-frame staging queue when traffic slows. 3451 */ 3452 if (txq->axq_depth <= 1) 3453 ieee80211_ff_flush(ic, txq->axq_ac); 3454#endif 3455 3456 /* Kick the TXQ scheduler */ 3457 if (dosched) { 3458 ATH_TXQ_LOCK(txq); 3459 ath_txq_sched(sc, txq); 3460 ATH_TXQ_UNLOCK(txq); 3461 } 3462 3463 return nacked; 3464} 3465 3466#define TXQACTIVE(t, q) ( (t) & (1 << (q))) 3467 3468/* 3469 * Deferred processing of transmit interrupt; special-cased 3470 * for a single hardware transmit queue (e.g. 5210 and 5211). 3471 */ 3472static void 3473ath_tx_proc_q0(void *arg, int npending) 3474{ 3475 struct ath_softc *sc = arg; 3476 struct ifnet *ifp = sc->sc_ifp; 3477 uint32_t txqs; 3478 3479 ATH_PCU_LOCK(sc); 3480 sc->sc_txproc_cnt++; 3481 txqs = sc->sc_txq_active; 3482 sc->sc_txq_active &= ~txqs; 3483 ATH_PCU_UNLOCK(sc); 3484 3485 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 3486 /* XXX why is lastrx updated in tx code? */ 3487 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3488 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 3489 ath_tx_processq(sc, sc->sc_cabq, 1); 3490 IF_LOCK(&ifp->if_snd); 3491 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3492 IF_UNLOCK(&ifp->if_snd); 3493 sc->sc_wd_timer = 0; 3494 3495 if (sc->sc_softled) 3496 ath_led_event(sc, sc->sc_txrix); 3497 3498 ATH_PCU_LOCK(sc); 3499 sc->sc_txproc_cnt--; 3500 ATH_PCU_UNLOCK(sc); 3501 3502 ath_tx_kick(sc); 3503} 3504 3505/* 3506 * Deferred processing of transmit interrupt; special-cased 3507 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3508 */ 3509static void 3510ath_tx_proc_q0123(void *arg, int npending) 3511{ 3512 struct ath_softc *sc = arg; 3513 struct ifnet *ifp = sc->sc_ifp; 3514 int nacked; 3515 uint32_t txqs; 3516 3517 ATH_PCU_LOCK(sc); 3518 sc->sc_txproc_cnt++; 3519 txqs = sc->sc_txq_active; 3520 sc->sc_txq_active &= ~txqs; 3521 ATH_PCU_UNLOCK(sc); 3522 3523 /* 3524 * Process each active queue. 3525 */ 3526 nacked = 0; 3527 if (TXQACTIVE(txqs, 0)) 3528 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 3529 if (TXQACTIVE(txqs, 1)) 3530 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 3531 if (TXQACTIVE(txqs, 2)) 3532 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 3533 if (TXQACTIVE(txqs, 3)) 3534 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 3535 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 3536 ath_tx_processq(sc, sc->sc_cabq, 1); 3537 if (nacked) 3538 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3539 3540 IF_LOCK(&ifp->if_snd); 3541 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3542 IF_UNLOCK(&ifp->if_snd); 3543 sc->sc_wd_timer = 0; 3544 3545 if (sc->sc_softled) 3546 ath_led_event(sc, sc->sc_txrix); 3547 3548 ATH_PCU_LOCK(sc); 3549 sc->sc_txproc_cnt--; 3550 ATH_PCU_UNLOCK(sc); 3551 3552 ath_tx_kick(sc); 3553} 3554 3555/* 3556 * Deferred processing of transmit interrupt. 3557 */ 3558static void 3559ath_tx_proc(void *arg, int npending) 3560{ 3561 struct ath_softc *sc = arg; 3562 struct ifnet *ifp = sc->sc_ifp; 3563 int i, nacked; 3564 uint32_t txqs; 3565 3566 ATH_PCU_LOCK(sc); 3567 sc->sc_txproc_cnt++; 3568 txqs = sc->sc_txq_active; 3569 sc->sc_txq_active &= ~txqs; 3570 ATH_PCU_UNLOCK(sc); 3571 3572 /* 3573 * Process each active queue. 3574 */ 3575 nacked = 0; 3576 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3577 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 3578 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 3579 if (nacked) 3580 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3581 3582 /* XXX check this inside of IF_LOCK? */ 3583 IF_LOCK(&ifp->if_snd); 3584 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3585 IF_UNLOCK(&ifp->if_snd); 3586 sc->sc_wd_timer = 0; 3587 3588 if (sc->sc_softled) 3589 ath_led_event(sc, sc->sc_txrix); 3590 3591 ATH_PCU_LOCK(sc); 3592 sc->sc_txproc_cnt--; 3593 ATH_PCU_UNLOCK(sc); 3594 3595 ath_tx_kick(sc); 3596} 3597#undef TXQACTIVE 3598 3599/* 3600 * Deferred processing of TXQ rescheduling. 3601 */ 3602static void 3603ath_txq_sched_tasklet(void *arg, int npending) 3604{ 3605 struct ath_softc *sc = arg; 3606 int i; 3607 3608 /* XXX is skipping ok? */ 3609 ATH_PCU_LOCK(sc); 3610#if 0 3611 if (sc->sc_inreset_cnt > 0) { 3612 device_printf(sc->sc_dev, 3613 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 3614 ATH_PCU_UNLOCK(sc); 3615 return; 3616 } 3617#endif 3618 sc->sc_txproc_cnt++; 3619 ATH_PCU_UNLOCK(sc); 3620 3621 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 3622 if (ATH_TXQ_SETUP(sc, i)) { 3623 ATH_TXQ_LOCK(&sc->sc_txq[i]); 3624 ath_txq_sched(sc, &sc->sc_txq[i]); 3625 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 3626 } 3627 } 3628 3629 ATH_PCU_LOCK(sc); 3630 sc->sc_txproc_cnt--; 3631 ATH_PCU_UNLOCK(sc); 3632} 3633 3634/* 3635 * Return a buffer to the pool and update the 'busy' flag on the 3636 * previous 'tail' entry. 3637 * 3638 * This _must_ only be called when the buffer is involved in a completed 3639 * TX. The logic is that if it was part of an active TX, the previous 3640 * buffer on the list is now not involved in a halted TX DMA queue, waiting 3641 * for restart (eg for TDMA.) 3642 * 3643 * The caller must free the mbuf and recycle the node reference. 3644 */ 3645void 3646ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 3647{ 3648 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3649 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTWRITE); 3650 3651 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 3652 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 3653 3654 ATH_TXBUF_LOCK(sc); 3655 ath_tx_update_busy(sc); 3656 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3657 ATH_TXBUF_UNLOCK(sc); 3658} 3659 3660/* 3661 * This is currently used by ath_tx_draintxq() and 3662 * ath_tx_tid_free_pkts(). 3663 * 3664 * It recycles a single ath_buf. 3665 */ 3666void 3667ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 3668{ 3669 struct ieee80211_node *ni = bf->bf_node; 3670 struct mbuf *m0 = bf->bf_m; 3671 3672 bf->bf_node = NULL; 3673 bf->bf_m = NULL; 3674 3675 /* Free the buffer, it's not needed any longer */ 3676 ath_freebuf(sc, bf); 3677 3678 if (ni != NULL) { 3679 /* 3680 * Do any callback and reclaim the node reference. 3681 */ 3682 if (m0->m_flags & M_TXCB) 3683 ieee80211_process_callback(ni, m0, status); 3684 ieee80211_free_node(ni); 3685 } 3686 m_freem(m0); 3687 3688 /* 3689 * XXX the buffer used to be freed -after-, but the DMA map was 3690 * freed where ath_freebuf() now is. I've no idea what this 3691 * will do. 3692 */ 3693} 3694 3695void 3696ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3697{ 3698#ifdef ATH_DEBUG 3699 struct ath_hal *ah = sc->sc_ah; 3700#endif 3701 struct ath_buf *bf; 3702 u_int ix; 3703 3704 /* 3705 * NB: this assumes output has been stopped and 3706 * we do not need to block ath_tx_proc 3707 */ 3708 ATH_TXBUF_LOCK(sc); 3709 bf = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 3710 if (bf != NULL) 3711 bf->bf_flags &= ~ATH_BUF_BUSY; 3712 ATH_TXBUF_UNLOCK(sc); 3713 3714 for (ix = 0;; ix++) { 3715 ATH_TXQ_LOCK(txq); 3716 bf = TAILQ_FIRST(&txq->axq_q); 3717 if (bf == NULL) { 3718 txq->axq_link = NULL; 3719 ATH_TXQ_UNLOCK(txq); 3720 break; 3721 } 3722 ATH_TXQ_REMOVE(txq, bf, bf_list); 3723 if (bf->bf_state.bfs_aggr) 3724 txq->axq_aggr_depth--; 3725#ifdef ATH_DEBUG 3726 if (sc->sc_debug & ATH_DEBUG_RESET) { 3727 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3728 3729 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 3730 ath_hal_txprocdesc(ah, bf->bf_lastds, 3731 &bf->bf_status.ds_txstat) == HAL_OK); 3732 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 3733 bf->bf_m->m_len, 0, -1); 3734 } 3735#endif /* ATH_DEBUG */ 3736 /* 3737 * Since we're now doing magic in the completion 3738 * functions, we -must- call it for aggregation 3739 * destinations or BAW tracking will get upset. 3740 */ 3741 /* 3742 * Clear ATH_BUF_BUSY; the completion handler 3743 * will free the buffer. 3744 */ 3745 ATH_TXQ_UNLOCK(txq); 3746 bf->bf_flags &= ~ATH_BUF_BUSY; 3747 if (bf->bf_comp) 3748 bf->bf_comp(sc, bf, 1); 3749 else 3750 ath_tx_default_comp(sc, bf, 1); 3751 } 3752 3753 /* 3754 * Drain software queued frames which are on 3755 * active TIDs. 3756 */ 3757 ath_tx_txq_drain(sc, txq); 3758} 3759 3760static void 3761ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3762{ 3763 struct ath_hal *ah = sc->sc_ah; 3764 3765 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3766 __func__, txq->axq_qnum, 3767 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 3768 txq->axq_link); 3769 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 3770} 3771 3772static int 3773ath_stoptxdma(struct ath_softc *sc) 3774{ 3775 struct ath_hal *ah = sc->sc_ah; 3776 int i; 3777 3778 /* XXX return value */ 3779 if (sc->sc_invalid) 3780 return 0; 3781 3782 if (!sc->sc_invalid) { 3783 /* don't touch the hardware if marked invalid */ 3784 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3785 __func__, sc->sc_bhalq, 3786 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 3787 NULL); 3788 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 3789 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3790 if (ATH_TXQ_SETUP(sc, i)) 3791 ath_tx_stopdma(sc, &sc->sc_txq[i]); 3792 } 3793 3794 return 1; 3795} 3796 3797/* 3798 * Drain the transmit queues and reclaim resources. 3799 */ 3800static void 3801ath_draintxq(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 3802{ 3803#ifdef ATH_DEBUG 3804 struct ath_hal *ah = sc->sc_ah; 3805#endif 3806 struct ifnet *ifp = sc->sc_ifp; 3807 int i; 3808 3809 (void) ath_stoptxdma(sc); 3810 3811 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 3812 /* 3813 * XXX TODO: should we just handle the completed TX frames 3814 * here, whether or not the reset is a full one or not? 3815 */ 3816 if (ATH_TXQ_SETUP(sc, i)) { 3817 if (reset_type == ATH_RESET_NOLOSS) 3818 ath_tx_processq(sc, &sc->sc_txq[i], 0); 3819 else 3820 ath_tx_draintxq(sc, &sc->sc_txq[i]); 3821 } 3822 } 3823#ifdef ATH_DEBUG 3824 if (sc->sc_debug & ATH_DEBUG_RESET) { 3825 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 3826 if (bf != NULL && bf->bf_m != NULL) { 3827 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 3828 ath_hal_txprocdesc(ah, bf->bf_lastds, 3829 &bf->bf_status.ds_txstat) == HAL_OK); 3830 ieee80211_dump_pkt(ifp->if_l2com, 3831 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 3832 0, -1); 3833 } 3834 } 3835#endif /* ATH_DEBUG */ 3836 IF_LOCK(&ifp->if_snd); 3837 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3838 IF_UNLOCK(&ifp->if_snd); 3839 sc->sc_wd_timer = 0; 3840} 3841 3842/* 3843 * Update internal state after a channel change. 3844 */ 3845static void 3846ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 3847{ 3848 enum ieee80211_phymode mode; 3849 3850 /* 3851 * Change channels and update the h/w rate map 3852 * if we're switching; e.g. 11a to 11b/g. 3853 */ 3854 mode = ieee80211_chan2mode(chan); 3855 if (mode != sc->sc_curmode) 3856 ath_setcurmode(sc, mode); 3857 sc->sc_curchan = chan; 3858} 3859 3860/* 3861 * Set/change channels. If the channel is really being changed, 3862 * it's done by resetting the chip. To accomplish this we must 3863 * first cleanup any pending DMA, then restart stuff after a la 3864 * ath_init. 3865 */ 3866static int 3867ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 3868{ 3869 struct ifnet *ifp = sc->sc_ifp; 3870 struct ieee80211com *ic = ifp->if_l2com; 3871 struct ath_hal *ah = sc->sc_ah; 3872 int ret = 0; 3873 3874 /* Treat this as an interface reset */ 3875 ATH_PCU_UNLOCK_ASSERT(sc); 3876 ATH_UNLOCK_ASSERT(sc); 3877 3878 /* (Try to) stop TX/RX from occuring */ 3879 taskqueue_block(sc->sc_tq); 3880 3881 ATH_PCU_LOCK(sc); 3882 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */ 3883 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */ 3884 if (ath_reset_grablock(sc, 1) == 0) { 3885 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 3886 __func__); 3887 } 3888 ATH_PCU_UNLOCK(sc); 3889 3890 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 3891 __func__, ieee80211_chan2ieee(ic, chan), 3892 chan->ic_freq, chan->ic_flags); 3893 if (chan != sc->sc_curchan) { 3894 HAL_STATUS status; 3895 /* 3896 * To switch channels clear any pending DMA operations; 3897 * wait long enough for the RX fifo to drain, reset the 3898 * hardware at the new frequency, and then re-enable 3899 * the relevant bits of the h/w. 3900 */ 3901#if 0 3902 ath_hal_intrset(ah, 0); /* disable interrupts */ 3903#endif 3904 ath_stoprecv(sc, 1); /* turn off frame recv */ 3905 /* 3906 * First, handle completed TX/RX frames. 3907 */ 3908 ath_rx_proc(sc, 0); 3909 ath_draintxq(sc, ATH_RESET_NOLOSS); 3910 /* 3911 * Next, flush the non-scheduled frames. 3912 */ 3913 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 3914 3915 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 3916 if_printf(ifp, "%s: unable to reset " 3917 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 3918 __func__, ieee80211_chan2ieee(ic, chan), 3919 chan->ic_freq, chan->ic_flags, status); 3920 ret = EIO; 3921 goto finish; 3922 } 3923 sc->sc_diversity = ath_hal_getdiversity(ah); 3924 3925 /* Let DFS at it in case it's a DFS channel */ 3926 ath_dfs_radar_enable(sc, chan); 3927 3928 /* 3929 * Re-enable rx framework. 3930 */ 3931 if (ath_startrecv(sc) != 0) { 3932 if_printf(ifp, "%s: unable to restart recv logic\n", 3933 __func__); 3934 ret = EIO; 3935 goto finish; 3936 } 3937 3938 /* 3939 * Change channels and update the h/w rate map 3940 * if we're switching; e.g. 11a to 11b/g. 3941 */ 3942 ath_chan_change(sc, chan); 3943 3944 /* 3945 * Reset clears the beacon timers; reset them 3946 * here if needed. 3947 */ 3948 if (sc->sc_beacons) { /* restart beacons */ 3949#ifdef IEEE80211_SUPPORT_TDMA 3950 if (sc->sc_tdma) 3951 ath_tdma_config(sc, NULL); 3952 else 3953#endif 3954 ath_beacon_config(sc, NULL); 3955 } 3956 3957 /* 3958 * Re-enable interrupts. 3959 */ 3960#if 0 3961 ath_hal_intrset(ah, sc->sc_imask); 3962#endif 3963 } 3964 3965finish: 3966 ATH_PCU_LOCK(sc); 3967 sc->sc_inreset_cnt--; 3968 /* XXX only do this if sc_inreset_cnt == 0? */ 3969 ath_hal_intrset(ah, sc->sc_imask); 3970 ATH_PCU_UNLOCK(sc); 3971 3972 IF_LOCK(&ifp->if_snd); 3973 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3974 IF_UNLOCK(&ifp->if_snd); 3975 ath_txrx_start(sc); 3976 /* XXX ath_start? */ 3977 3978 return ret; 3979} 3980 3981/* 3982 * Periodically recalibrate the PHY to account 3983 * for temperature/environment changes. 3984 */ 3985static void 3986ath_calibrate(void *arg) 3987{ 3988 struct ath_softc *sc = arg; 3989 struct ath_hal *ah = sc->sc_ah; 3990 struct ifnet *ifp = sc->sc_ifp; 3991 struct ieee80211com *ic = ifp->if_l2com; 3992 HAL_BOOL longCal, isCalDone; 3993 HAL_BOOL aniCal, shortCal = AH_FALSE; 3994 int nextcal; 3995 3996 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 3997 goto restart; 3998 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 3999 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 4000 if (sc->sc_doresetcal) 4001 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 4002 4003 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 4004 if (aniCal) { 4005 sc->sc_stats.ast_ani_cal++; 4006 sc->sc_lastani = ticks; 4007 ath_hal_ani_poll(ah, sc->sc_curchan); 4008 } 4009 4010 if (longCal) { 4011 sc->sc_stats.ast_per_cal++; 4012 sc->sc_lastlongcal = ticks; 4013 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4014 /* 4015 * Rfgain is out of bounds, reset the chip 4016 * to load new gain values. 4017 */ 4018 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4019 "%s: rfgain change\n", __func__); 4020 sc->sc_stats.ast_per_rfgain++; 4021 sc->sc_resetcal = 0; 4022 sc->sc_doresetcal = AH_TRUE; 4023 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 4024 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 4025 return; 4026 } 4027 /* 4028 * If this long cal is after an idle period, then 4029 * reset the data collection state so we start fresh. 4030 */ 4031 if (sc->sc_resetcal) { 4032 (void) ath_hal_calreset(ah, sc->sc_curchan); 4033 sc->sc_lastcalreset = ticks; 4034 sc->sc_lastshortcal = ticks; 4035 sc->sc_resetcal = 0; 4036 sc->sc_doresetcal = AH_TRUE; 4037 } 4038 } 4039 4040 /* Only call if we're doing a short/long cal, not for ANI calibration */ 4041 if (shortCal || longCal) { 4042 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 4043 if (longCal) { 4044 /* 4045 * Calibrate noise floor data again in case of change. 4046 */ 4047 ath_hal_process_noisefloor(ah); 4048 } 4049 } else { 4050 DPRINTF(sc, ATH_DEBUG_ANY, 4051 "%s: calibration of channel %u failed\n", 4052 __func__, sc->sc_curchan->ic_freq); 4053 sc->sc_stats.ast_per_calfail++; 4054 } 4055 if (shortCal) 4056 sc->sc_lastshortcal = ticks; 4057 } 4058 if (!isCalDone) { 4059restart: 4060 /* 4061 * Use a shorter interval to potentially collect multiple 4062 * data samples required to complete calibration. Once 4063 * we're told the work is done we drop back to a longer 4064 * interval between requests. We're more aggressive doing 4065 * work when operating as an AP to improve operation right 4066 * after startup. 4067 */ 4068 sc->sc_lastshortcal = ticks; 4069 nextcal = ath_shortcalinterval*hz/1000; 4070 if (sc->sc_opmode != HAL_M_HOSTAP) 4071 nextcal *= 10; 4072 sc->sc_doresetcal = AH_TRUE; 4073 } else { 4074 /* nextcal should be the shortest time for next event */ 4075 nextcal = ath_longcalinterval*hz; 4076 if (sc->sc_lastcalreset == 0) 4077 sc->sc_lastcalreset = sc->sc_lastlongcal; 4078 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 4079 sc->sc_resetcal = 1; /* setup reset next trip */ 4080 sc->sc_doresetcal = AH_FALSE; 4081 } 4082 /* ANI calibration may occur more often than short/long/resetcal */ 4083 if (ath_anicalinterval > 0) 4084 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 4085 4086 if (nextcal != 0) { 4087 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 4088 __func__, nextcal, isCalDone ? "" : "!"); 4089 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 4090 } else { 4091 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 4092 __func__); 4093 /* NB: don't rearm timer */ 4094 } 4095} 4096 4097static void 4098ath_scan_start(struct ieee80211com *ic) 4099{ 4100 struct ifnet *ifp = ic->ic_ifp; 4101 struct ath_softc *sc = ifp->if_softc; 4102 struct ath_hal *ah = sc->sc_ah; 4103 u_int32_t rfilt; 4104 4105 /* XXX calibration timer? */ 4106 4107 ATH_LOCK(sc); 4108 sc->sc_scanning = 1; 4109 sc->sc_syncbeacon = 0; 4110 rfilt = ath_calcrxfilter(sc); 4111 ATH_UNLOCK(sc); 4112 4113 ATH_PCU_LOCK(sc); 4114 ath_hal_setrxfilter(ah, rfilt); 4115 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 4116 ATH_PCU_UNLOCK(sc); 4117 4118 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 4119 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 4120} 4121 4122static void 4123ath_scan_end(struct ieee80211com *ic) 4124{ 4125 struct ifnet *ifp = ic->ic_ifp; 4126 struct ath_softc *sc = ifp->if_softc; 4127 struct ath_hal *ah = sc->sc_ah; 4128 u_int32_t rfilt; 4129 4130 ATH_LOCK(sc); 4131 sc->sc_scanning = 0; 4132 rfilt = ath_calcrxfilter(sc); 4133 ATH_UNLOCK(sc); 4134 4135 ATH_PCU_LOCK(sc); 4136 ath_hal_setrxfilter(ah, rfilt); 4137 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4138 4139 ath_hal_process_noisefloor(ah); 4140 ATH_PCU_UNLOCK(sc); 4141 4142 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4143 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 4144 sc->sc_curaid); 4145} 4146 4147#ifdef ATH_ENABLE_11N 4148/* 4149 * For now, just do a channel change. 4150 * 4151 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 4152 * control state and resetting the hardware without dropping frames out 4153 * of the queue. 4154 * 4155 * The unfortunate trouble here is making absolutely sure that the 4156 * channel width change has propagated enough so the hardware 4157 * absolutely isn't handed bogus frames for it's current operating 4158 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 4159 * does occur in parallel, we need to make certain we've blocked 4160 * any further ongoing TX (and RX, that can cause raw TX) 4161 * before we do this. 4162 */ 4163static void 4164ath_update_chw(struct ieee80211com *ic) 4165{ 4166 struct ifnet *ifp = ic->ic_ifp; 4167 struct ath_softc *sc = ifp->if_softc; 4168 4169 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 4170 ath_set_channel(ic); 4171} 4172#endif /* ATH_ENABLE_11N */ 4173 4174static void 4175ath_set_channel(struct ieee80211com *ic) 4176{ 4177 struct ifnet *ifp = ic->ic_ifp; 4178 struct ath_softc *sc = ifp->if_softc; 4179 4180 (void) ath_chan_set(sc, ic->ic_curchan); 4181 /* 4182 * If we are returning to our bss channel then mark state 4183 * so the next recv'd beacon's tsf will be used to sync the 4184 * beacon timers. Note that since we only hear beacons in 4185 * sta/ibss mode this has no effect in other operating modes. 4186 */ 4187 ATH_LOCK(sc); 4188 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 4189 sc->sc_syncbeacon = 1; 4190 ATH_UNLOCK(sc); 4191} 4192 4193/* 4194 * Walk the vap list and check if there any vap's in RUN state. 4195 */ 4196static int 4197ath_isanyrunningvaps(struct ieee80211vap *this) 4198{ 4199 struct ieee80211com *ic = this->iv_ic; 4200 struct ieee80211vap *vap; 4201 4202 IEEE80211_LOCK_ASSERT(ic); 4203 4204 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4205 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 4206 return 1; 4207 } 4208 return 0; 4209} 4210 4211static int 4212ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4213{ 4214 struct ieee80211com *ic = vap->iv_ic; 4215 struct ath_softc *sc = ic->ic_ifp->if_softc; 4216 struct ath_vap *avp = ATH_VAP(vap); 4217 struct ath_hal *ah = sc->sc_ah; 4218 struct ieee80211_node *ni = NULL; 4219 int i, error, stamode; 4220 u_int32_t rfilt; 4221 int csa_run_transition = 0; 4222 static const HAL_LED_STATE leds[] = { 4223 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4224 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4225 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4226 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4227 HAL_LED_RUN, /* IEEE80211_S_CAC */ 4228 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4229 HAL_LED_RUN, /* IEEE80211_S_CSA */ 4230 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 4231 }; 4232 4233 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4234 ieee80211_state_name[vap->iv_state], 4235 ieee80211_state_name[nstate]); 4236 4237 /* 4238 * net80211 _should_ have the comlock asserted at this point. 4239 * There are some comments around the calls to vap->iv_newstate 4240 * which indicate that it (newstate) may end up dropping the 4241 * lock. This and the subsequent lock assert check after newstate 4242 * are an attempt to catch these and figure out how/why. 4243 */ 4244 IEEE80211_LOCK_ASSERT(ic); 4245 4246 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 4247 csa_run_transition = 1; 4248 4249 callout_drain(&sc->sc_cal_ch); 4250 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4251 4252 if (nstate == IEEE80211_S_SCAN) { 4253 /* 4254 * Scanning: turn off beacon miss and don't beacon. 4255 * Mark beacon state so when we reach RUN state we'll 4256 * [re]setup beacons. Unblock the task q thread so 4257 * deferred interrupt processing is done. 4258 */ 4259 ath_hal_intrset(ah, 4260 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4261 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4262 sc->sc_beacons = 0; 4263 taskqueue_unblock(sc->sc_tq); 4264 } 4265 4266 ni = ieee80211_ref_node(vap->iv_bss); 4267 rfilt = ath_calcrxfilter(sc); 4268 stamode = (vap->iv_opmode == IEEE80211_M_STA || 4269 vap->iv_opmode == IEEE80211_M_AHDEMO || 4270 vap->iv_opmode == IEEE80211_M_IBSS); 4271 if (stamode && nstate == IEEE80211_S_RUN) { 4272 sc->sc_curaid = ni->ni_associd; 4273 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 4274 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4275 } 4276 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4277 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 4278 ath_hal_setrxfilter(ah, rfilt); 4279 4280 /* XXX is this to restore keycache on resume? */ 4281 if (vap->iv_opmode != IEEE80211_M_STA && 4282 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 4283 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4284 if (ath_hal_keyisvalid(ah, i)) 4285 ath_hal_keysetmac(ah, i, ni->ni_bssid); 4286 } 4287 4288 /* 4289 * Invoke the parent method to do net80211 work. 4290 */ 4291 error = avp->av_newstate(vap, nstate, arg); 4292 if (error != 0) 4293 goto bad; 4294 4295 /* 4296 * See above: ensure av_newstate() doesn't drop the lock 4297 * on us. 4298 */ 4299 IEEE80211_LOCK_ASSERT(ic); 4300 4301 if (nstate == IEEE80211_S_RUN) { 4302 /* NB: collect bss node again, it may have changed */ 4303 ieee80211_free_node(ni); 4304 ni = ieee80211_ref_node(vap->iv_bss); 4305 4306 DPRINTF(sc, ATH_DEBUG_STATE, 4307 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 4308 "capinfo 0x%04x chan %d\n", __func__, 4309 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 4310 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 4311 4312 switch (vap->iv_opmode) { 4313#ifdef IEEE80211_SUPPORT_TDMA 4314 case IEEE80211_M_AHDEMO: 4315 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 4316 break; 4317 /* fall thru... */ 4318#endif 4319 case IEEE80211_M_HOSTAP: 4320 case IEEE80211_M_IBSS: 4321 case IEEE80211_M_MBSS: 4322 /* 4323 * Allocate and setup the beacon frame. 4324 * 4325 * Stop any previous beacon DMA. This may be 4326 * necessary, for example, when an ibss merge 4327 * causes reconfiguration; there will be a state 4328 * transition from RUN->RUN that means we may 4329 * be called with beacon transmission active. 4330 */ 4331 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4332 4333 error = ath_beacon_alloc(sc, ni); 4334 if (error != 0) 4335 goto bad; 4336 /* 4337 * If joining an adhoc network defer beacon timer 4338 * configuration to the next beacon frame so we 4339 * have a current TSF to use. Otherwise we're 4340 * starting an ibss/bss so there's no need to delay; 4341 * if this is the first vap moving to RUN state, then 4342 * beacon state needs to be [re]configured. 4343 */ 4344 if (vap->iv_opmode == IEEE80211_M_IBSS && 4345 ni->ni_tstamp.tsf != 0) { 4346 sc->sc_syncbeacon = 1; 4347 } else if (!sc->sc_beacons) { 4348#ifdef IEEE80211_SUPPORT_TDMA 4349 if (vap->iv_caps & IEEE80211_C_TDMA) 4350 ath_tdma_config(sc, vap); 4351 else 4352#endif 4353 ath_beacon_config(sc, vap); 4354 sc->sc_beacons = 1; 4355 } 4356 break; 4357 case IEEE80211_M_STA: 4358 /* 4359 * Defer beacon timer configuration to the next 4360 * beacon frame so we have a current TSF to use 4361 * (any TSF collected when scanning is likely old). 4362 * However if it's due to a CSA -> RUN transition, 4363 * force a beacon update so we pick up a lack of 4364 * beacons from an AP in CAC and thus force a 4365 * scan. 4366 */ 4367 sc->sc_syncbeacon = 1; 4368 if (csa_run_transition) 4369 ath_beacon_config(sc, vap); 4370 break; 4371 case IEEE80211_M_MONITOR: 4372 /* 4373 * Monitor mode vaps have only INIT->RUN and RUN->RUN 4374 * transitions so we must re-enable interrupts here to 4375 * handle the case of a single monitor mode vap. 4376 */ 4377 ath_hal_intrset(ah, sc->sc_imask); 4378 break; 4379 case IEEE80211_M_WDS: 4380 break; 4381 default: 4382 break; 4383 } 4384 /* 4385 * Let the hal process statistics collected during a 4386 * scan so it can provide calibrated noise floor data. 4387 */ 4388 ath_hal_process_noisefloor(ah); 4389 /* 4390 * Reset rssi stats; maybe not the best place... 4391 */ 4392 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4393 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4394 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4395 /* 4396 * Finally, start any timers and the task q thread 4397 * (in case we didn't go through SCAN state). 4398 */ 4399 if (ath_longcalinterval != 0) { 4400 /* start periodic recalibration timer */ 4401 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 4402 } else { 4403 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4404 "%s: calibration disabled\n", __func__); 4405 } 4406 taskqueue_unblock(sc->sc_tq); 4407 } else if (nstate == IEEE80211_S_INIT) { 4408 /* 4409 * If there are no vaps left in RUN state then 4410 * shutdown host/driver operation: 4411 * o disable interrupts 4412 * o disable the task queue thread 4413 * o mark beacon processing as stopped 4414 */ 4415 if (!ath_isanyrunningvaps(vap)) { 4416 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4417 /* disable interrupts */ 4418 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4419 taskqueue_block(sc->sc_tq); 4420 sc->sc_beacons = 0; 4421 } 4422#ifdef IEEE80211_SUPPORT_TDMA 4423 ath_hal_setcca(ah, AH_TRUE); 4424#endif 4425 } 4426bad: 4427 ieee80211_free_node(ni); 4428 return error; 4429} 4430 4431/* 4432 * Allocate a key cache slot to the station so we can 4433 * setup a mapping from key index to node. The key cache 4434 * slot is needed for managing antenna state and for 4435 * compression when stations do not use crypto. We do 4436 * it uniliaterally here; if crypto is employed this slot 4437 * will be reassigned. 4438 */ 4439static void 4440ath_setup_stationkey(struct ieee80211_node *ni) 4441{ 4442 struct ieee80211vap *vap = ni->ni_vap; 4443 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 4444 ieee80211_keyix keyix, rxkeyix; 4445 4446 /* XXX should take a locked ref to vap->iv_bss */ 4447 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4448 /* 4449 * Key cache is full; we'll fall back to doing 4450 * the more expensive lookup in software. Note 4451 * this also means no h/w compression. 4452 */ 4453 /* XXX msg+statistic */ 4454 } else { 4455 /* XXX locking? */ 4456 ni->ni_ucastkey.wk_keyix = keyix; 4457 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4458 /* NB: must mark device key to get called back on delete */ 4459 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 4460 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 4461 /* NB: this will create a pass-thru key entry */ 4462 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 4463 } 4464} 4465 4466/* 4467 * Setup driver-specific state for a newly associated node. 4468 * Note that we're called also on a re-associate, the isnew 4469 * param tells us if this is the first time or not. 4470 */ 4471static void 4472ath_newassoc(struct ieee80211_node *ni, int isnew) 4473{ 4474 struct ath_node *an = ATH_NODE(ni); 4475 struct ieee80211vap *vap = ni->ni_vap; 4476 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 4477 const struct ieee80211_txparam *tp = ni->ni_txparms; 4478 4479 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 4480 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 4481 4482 ath_rate_newassoc(sc, an, isnew); 4483 if (isnew && 4484 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 4485 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4486 ath_setup_stationkey(ni); 4487} 4488 4489static int 4490ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 4491 int nchans, struct ieee80211_channel chans[]) 4492{ 4493 struct ath_softc *sc = ic->ic_ifp->if_softc; 4494 struct ath_hal *ah = sc->sc_ah; 4495 HAL_STATUS status; 4496 4497 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 4498 "%s: rd %u cc %u location %c%s\n", 4499 __func__, reg->regdomain, reg->country, reg->location, 4500 reg->ecm ? " ecm" : ""); 4501 4502 status = ath_hal_set_channels(ah, chans, nchans, 4503 reg->country, reg->regdomain); 4504 if (status != HAL_OK) { 4505 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 4506 __func__, status); 4507 return EINVAL; /* XXX */ 4508 } 4509 4510 return 0; 4511} 4512 4513static void 4514ath_getradiocaps(struct ieee80211com *ic, 4515 int maxchans, int *nchans, struct ieee80211_channel chans[]) 4516{ 4517 struct ath_softc *sc = ic->ic_ifp->if_softc; 4518 struct ath_hal *ah = sc->sc_ah; 4519 4520 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 4521 __func__, SKU_DEBUG, CTRY_DEFAULT); 4522 4523 /* XXX check return */ 4524 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 4525 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 4526 4527} 4528 4529static int 4530ath_getchannels(struct ath_softc *sc) 4531{ 4532 struct ifnet *ifp = sc->sc_ifp; 4533 struct ieee80211com *ic = ifp->if_l2com; 4534 struct ath_hal *ah = sc->sc_ah; 4535 HAL_STATUS status; 4536 4537 /* 4538 * Collect channel set based on EEPROM contents. 4539 */ 4540 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 4541 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 4542 if (status != HAL_OK) { 4543 if_printf(ifp, "%s: unable to collect channel list from hal, " 4544 "status %d\n", __func__, status); 4545 return EINVAL; 4546 } 4547 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 4548 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 4549 /* XXX map Atheros sku's to net80211 SKU's */ 4550 /* XXX net80211 types too small */ 4551 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 4552 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 4553 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 4554 ic->ic_regdomain.isocc[1] = ' '; 4555 4556 ic->ic_regdomain.ecm = 1; 4557 ic->ic_regdomain.location = 'I'; 4558 4559 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 4560 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 4561 __func__, sc->sc_eerd, sc->sc_eecc, 4562 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 4563 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 4564 return 0; 4565} 4566 4567static int 4568ath_rate_setup(struct ath_softc *sc, u_int mode) 4569{ 4570 struct ath_hal *ah = sc->sc_ah; 4571 const HAL_RATE_TABLE *rt; 4572 4573 switch (mode) { 4574 case IEEE80211_MODE_11A: 4575 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4576 break; 4577 case IEEE80211_MODE_HALF: 4578 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 4579 break; 4580 case IEEE80211_MODE_QUARTER: 4581 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 4582 break; 4583 case IEEE80211_MODE_11B: 4584 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4585 break; 4586 case IEEE80211_MODE_11G: 4587 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4588 break; 4589 case IEEE80211_MODE_TURBO_A: 4590 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 4591 break; 4592 case IEEE80211_MODE_TURBO_G: 4593 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4594 break; 4595 case IEEE80211_MODE_STURBO_A: 4596 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4597 break; 4598 case IEEE80211_MODE_11NA: 4599 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 4600 break; 4601 case IEEE80211_MODE_11NG: 4602 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 4603 break; 4604 default: 4605 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4606 __func__, mode); 4607 return 0; 4608 } 4609 sc->sc_rates[mode] = rt; 4610 return (rt != NULL); 4611} 4612 4613static void 4614ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4615{ 4616#define N(a) (sizeof(a)/sizeof(a[0])) 4617 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4618 static const struct { 4619 u_int rate; /* tx/rx 802.11 rate */ 4620 u_int16_t timeOn; /* LED on time (ms) */ 4621 u_int16_t timeOff; /* LED off time (ms) */ 4622 } blinkrates[] = { 4623 { 108, 40, 10 }, 4624 { 96, 44, 11 }, 4625 { 72, 50, 13 }, 4626 { 48, 57, 14 }, 4627 { 36, 67, 16 }, 4628 { 24, 80, 20 }, 4629 { 22, 100, 25 }, 4630 { 18, 133, 34 }, 4631 { 12, 160, 40 }, 4632 { 10, 200, 50 }, 4633 { 6, 240, 58 }, 4634 { 4, 267, 66 }, 4635 { 2, 400, 100 }, 4636 { 0, 500, 130 }, 4637 /* XXX half/quarter rates */ 4638 }; 4639 const HAL_RATE_TABLE *rt; 4640 int i, j; 4641 4642 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4643 rt = sc->sc_rates[mode]; 4644 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4645 for (i = 0; i < rt->rateCount; i++) { 4646 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 4647 if (rt->info[i].phy != IEEE80211_T_HT) 4648 sc->sc_rixmap[ieeerate] = i; 4649 else 4650 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 4651 } 4652 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4653 for (i = 0; i < N(sc->sc_hwmap); i++) { 4654 if (i >= rt->rateCount) { 4655 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4656 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4657 continue; 4658 } 4659 sc->sc_hwmap[i].ieeerate = 4660 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 4661 if (rt->info[i].phy == IEEE80211_T_HT) 4662 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 4663 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4664 if (rt->info[i].shortPreamble || 4665 rt->info[i].phy == IEEE80211_T_OFDM) 4666 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4667 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 4668 for (j = 0; j < N(blinkrates)-1; j++) 4669 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4670 break; 4671 /* NB: this uses the last entry if the rate isn't found */ 4672 /* XXX beware of overlow */ 4673 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4674 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4675 } 4676 sc->sc_currates = rt; 4677 sc->sc_curmode = mode; 4678 /* 4679 * All protection frames are transmited at 2Mb/s for 4680 * 11g, otherwise at 1Mb/s. 4681 */ 4682 if (mode == IEEE80211_MODE_11G) 4683 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 4684 else 4685 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 4686 /* NB: caller is responsible for resetting rate control state */ 4687#undef N 4688} 4689 4690static void 4691ath_watchdog(void *arg) 4692{ 4693 struct ath_softc *sc = arg; 4694 int do_reset = 0; 4695 4696 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 4697 struct ifnet *ifp = sc->sc_ifp; 4698 uint32_t hangs; 4699 4700 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 4701 hangs != 0) { 4702 if_printf(ifp, "%s hang detected (0x%x)\n", 4703 hangs & 0xff ? "bb" : "mac", hangs); 4704 } else 4705 if_printf(ifp, "device timeout\n"); 4706 do_reset = 1; 4707 ifp->if_oerrors++; 4708 sc->sc_stats.ast_watchdog++; 4709 } 4710 4711 /* 4712 * We can't hold the lock across the ath_reset() call. 4713 * 4714 * And since this routine can't hold a lock and sleep, 4715 * do the reset deferred. 4716 */ 4717 if (do_reset) { 4718 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 4719 } 4720 4721 callout_schedule(&sc->sc_wd_ch, hz); 4722} 4723 4724#ifdef ATH_DIAGAPI 4725/* 4726 * Diagnostic interface to the HAL. This is used by various 4727 * tools to do things like retrieve register contents for 4728 * debugging. The mechanism is intentionally opaque so that 4729 * it can change frequently w/o concern for compatiblity. 4730 */ 4731static int 4732ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4733{ 4734 struct ath_hal *ah = sc->sc_ah; 4735 u_int id = ad->ad_id & ATH_DIAG_ID; 4736 void *indata = NULL; 4737 void *outdata = NULL; 4738 u_int32_t insize = ad->ad_in_size; 4739 u_int32_t outsize = ad->ad_out_size; 4740 int error = 0; 4741 4742 if (ad->ad_id & ATH_DIAG_IN) { 4743 /* 4744 * Copy in data. 4745 */ 4746 indata = malloc(insize, M_TEMP, M_NOWAIT); 4747 if (indata == NULL) { 4748 error = ENOMEM; 4749 goto bad; 4750 } 4751 error = copyin(ad->ad_in_data, indata, insize); 4752 if (error) 4753 goto bad; 4754 } 4755 if (ad->ad_id & ATH_DIAG_DYN) { 4756 /* 4757 * Allocate a buffer for the results (otherwise the HAL 4758 * returns a pointer to a buffer where we can read the 4759 * results). Note that we depend on the HAL leaving this 4760 * pointer for us to use below in reclaiming the buffer; 4761 * may want to be more defensive. 4762 */ 4763 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4764 if (outdata == NULL) { 4765 error = ENOMEM; 4766 goto bad; 4767 } 4768 } 4769 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4770 if (outsize < ad->ad_out_size) 4771 ad->ad_out_size = outsize; 4772 if (outdata != NULL) 4773 error = copyout(outdata, ad->ad_out_data, 4774 ad->ad_out_size); 4775 } else { 4776 error = EINVAL; 4777 } 4778bad: 4779 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4780 free(indata, M_TEMP); 4781 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4782 free(outdata, M_TEMP); 4783 return error; 4784} 4785#endif /* ATH_DIAGAPI */ 4786 4787static int 4788ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4789{ 4790#define IS_RUNNING(ifp) \ 4791 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 4792 struct ath_softc *sc = ifp->if_softc; 4793 struct ieee80211com *ic = ifp->if_l2com; 4794 struct ifreq *ifr = (struct ifreq *)data; 4795 const HAL_RATE_TABLE *rt; 4796 int error = 0; 4797 4798 switch (cmd) { 4799 case SIOCSIFFLAGS: 4800 ATH_LOCK(sc); 4801 if (IS_RUNNING(ifp)) { 4802 /* 4803 * To avoid rescanning another access point, 4804 * do not call ath_init() here. Instead, 4805 * only reflect promisc mode settings. 4806 */ 4807 ath_mode_init(sc); 4808 } else if (ifp->if_flags & IFF_UP) { 4809 /* 4810 * Beware of being called during attach/detach 4811 * to reset promiscuous mode. In that case we 4812 * will still be marked UP but not RUNNING. 4813 * However trying to re-init the interface 4814 * is the wrong thing to do as we've already 4815 * torn down much of our state. There's 4816 * probably a better way to deal with this. 4817 */ 4818 if (!sc->sc_invalid) 4819 ath_init(sc); /* XXX lose error */ 4820 } else { 4821 ath_stop_locked(ifp); 4822#ifdef notyet 4823 /* XXX must wakeup in places like ath_vap_delete */ 4824 if (!sc->sc_invalid) 4825 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 4826#endif 4827 } 4828 ATH_UNLOCK(sc); 4829 break; 4830 case SIOCGIFMEDIA: 4831 case SIOCSIFMEDIA: 4832 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 4833 break; 4834 case SIOCGATHSTATS: 4835 /* NB: embed these numbers to get a consistent view */ 4836 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4837 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4838 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 4839 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 4840#ifdef IEEE80211_SUPPORT_TDMA 4841 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 4842 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 4843#endif 4844 rt = sc->sc_currates; 4845 sc->sc_stats.ast_tx_rate = 4846 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 4847 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT) 4848 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS; 4849 return copyout(&sc->sc_stats, 4850 ifr->ifr_data, sizeof (sc->sc_stats)); 4851 case SIOCZATHSTATS: 4852 error = priv_check(curthread, PRIV_DRIVER); 4853 if (error == 0) { 4854 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 4855 memset(&sc->sc_aggr_stats, 0, 4856 sizeof(sc->sc_aggr_stats)); 4857 memset(&sc->sc_intr_stats, 0, 4858 sizeof(sc->sc_intr_stats)); 4859 } 4860 break; 4861#ifdef ATH_DIAGAPI 4862 case SIOCGATHDIAG: 4863 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4864 break; 4865 case SIOCGATHPHYERR: 4866 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr); 4867 break; 4868#endif 4869 case SIOCGIFADDR: 4870 error = ether_ioctl(ifp, cmd, data); 4871 break; 4872 default: 4873 error = EINVAL; 4874 break; 4875 } 4876 return error; 4877#undef IS_RUNNING 4878} 4879 4880/* 4881 * Announce various information on device/driver attach. 4882 */ 4883static void 4884ath_announce(struct ath_softc *sc) 4885{ 4886 struct ifnet *ifp = sc->sc_ifp; 4887 struct ath_hal *ah = sc->sc_ah; 4888 4889 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 4890 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 4891 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4892 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 4893 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 4894 if (bootverbose) { 4895 int i; 4896 for (i = 0; i <= WME_AC_VO; i++) { 4897 struct ath_txq *txq = sc->sc_ac2q[i]; 4898 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4899 txq->axq_qnum, ieee80211_wme_acnames[i]); 4900 } 4901 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4902 sc->sc_cabq->axq_qnum); 4903 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4904 } 4905 if (ath_rxbuf != ATH_RXBUF) 4906 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 4907 if (ath_txbuf != ATH_TXBUF) 4908 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 4909 if (sc->sc_mcastkey && bootverbose) 4910 if_printf(ifp, "using multicast key search\n"); 4911} 4912 4913static void 4914ath_dfs_tasklet(void *p, int npending) 4915{ 4916 struct ath_softc *sc = (struct ath_softc *) p; 4917 struct ifnet *ifp = sc->sc_ifp; 4918 struct ieee80211com *ic = ifp->if_l2com; 4919 4920 /* 4921 * If previous processing has found a radar event, 4922 * signal this to the net80211 layer to begin DFS 4923 * processing. 4924 */ 4925 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 4926 /* DFS event found, initiate channel change */ 4927 /* 4928 * XXX doesn't currently tell us whether the event 4929 * XXX was found in the primary or extension 4930 * XXX channel! 4931 */ 4932 IEEE80211_LOCK(ic); 4933 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 4934 IEEE80211_UNLOCK(ic); 4935 } 4936} 4937 4938MODULE_VERSION(if_ath, 1); 4939MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */ 4940#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) 4941MODULE_DEPEND(if_ath, alq, 1, 1, 1); 4942#endif 4943