if_ath.c revision 189605
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 189605 2009-03-09 23:10:19Z sam $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sysctl.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/kernel.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/errno.h> 54#include <sys/callout.h> 55#include <sys/bus.h> 56#include <sys/endian.h> 57#include <sys/kthread.h> 58#include <sys/taskqueue.h> 59#include <sys/priv.h> 60 61#include <machine/bus.h> 62 63#include <net/if.h> 64#include <net/if_dl.h> 65#include <net/if_media.h> 66#include <net/if_types.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_llc.h> 70 71#include <net80211/ieee80211_var.h> 72#include <net80211/ieee80211_regdomain.h> 73#ifdef ATH_SUPPORT_TDMA 74#include <net80211/ieee80211_tdma.h> 75#endif 76 77#include <net/bpf.h> 78 79#ifdef INET 80#include <netinet/in.h> 81#include <netinet/if_ether.h> 82#endif 83 84#include <dev/ath/if_athvar.h> 85#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 86 87#ifdef ATH_TX99_DIAG 88#include <dev/ath/ath_tx99/ath_tx99.h> 89#endif 90 91/* 92 * We require a HAL w/ the changes for split tx/rx MIC. 93 */ 94CTASSERT(HAL_ABI_VERSION > 0x06052200); 95 96/* 97 * ATH_BCBUF determines the number of vap's that can transmit 98 * beacons and also (currently) the number of vap's that can 99 * have unique mac addresses/bssid. When staggering beacons 100 * 4 is probably a good max as otherwise the beacons become 101 * very closely spaced and there is limited time for cab q traffic 102 * to go out. You can burst beacons instead but that is not good 103 * for stations in power save and at some point you really want 104 * another radio (and channel). 105 * 106 * The limit on the number of mac addresses is tied to our use of 107 * the U/L bit and tracking addresses in a byte; it would be 108 * worthwhile to allow more for applications like proxy sta. 109 */ 110CTASSERT(ATH_BCBUF <= 8); 111 112/* unaligned little endian access */ 113#define LE_READ_2(p) \ 114 ((u_int16_t) \ 115 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 116#define LE_READ_4(p) \ 117 ((u_int32_t) \ 118 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 119 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 120 121static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 122 const char name[IFNAMSIZ], int unit, int opmode, 123 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 124 const uint8_t mac[IEEE80211_ADDR_LEN]); 125static void ath_vap_delete(struct ieee80211vap *); 126static void ath_init(void *); 127static void ath_stop_locked(struct ifnet *); 128static void ath_stop(struct ifnet *); 129static void ath_start(struct ifnet *); 130static int ath_reset(struct ifnet *); 131static int ath_reset_vap(struct ieee80211vap *, u_long); 132static int ath_media_change(struct ifnet *); 133static void ath_watchdog(void *); 134static int ath_ioctl(struct ifnet *, u_long, caddr_t); 135static void ath_fatal_proc(void *, int); 136static void ath_bmiss_vap(struct ieee80211vap *); 137static void ath_bmiss_proc(void *, int); 138static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 139 struct ieee80211_node *); 140static int ath_key_alloc(struct ieee80211vap *, 141 struct ieee80211_key *, 142 ieee80211_keyix *, ieee80211_keyix *); 143static int ath_key_delete(struct ieee80211vap *, 144 const struct ieee80211_key *); 145static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 146 const u_int8_t mac[IEEE80211_ADDR_LEN]); 147static void ath_key_update_begin(struct ieee80211vap *); 148static void ath_key_update_end(struct ieee80211vap *); 149static void ath_update_mcast(struct ifnet *); 150static void ath_update_promisc(struct ifnet *); 151static void ath_mode_init(struct ath_softc *); 152static void ath_setslottime(struct ath_softc *); 153static void ath_updateslot(struct ifnet *); 154static int ath_beaconq_setup(struct ath_hal *); 155static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 156static void ath_beacon_update(struct ieee80211vap *, int item); 157static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 158static void ath_beacon_proc(void *, int); 159static struct ath_buf *ath_beacon_generate(struct ath_softc *, 160 struct ieee80211vap *); 161static void ath_bstuck_proc(void *, int); 162static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 163static void ath_beacon_free(struct ath_softc *); 164static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 165static void ath_descdma_cleanup(struct ath_softc *sc, 166 struct ath_descdma *, ath_bufhead *); 167static int ath_desc_alloc(struct ath_softc *); 168static void ath_desc_free(struct ath_softc *); 169static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 170 const uint8_t [IEEE80211_ADDR_LEN]); 171static void ath_node_free(struct ieee80211_node *); 172static void ath_node_getsignal(const struct ieee80211_node *, 173 int8_t *, int8_t *); 174static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 175static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 176 int subtype, int rssi, int noise, u_int32_t rstamp); 177static void ath_setdefantenna(struct ath_softc *, u_int); 178static void ath_rx_proc(void *, int); 179static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 180static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 181static int ath_tx_setup(struct ath_softc *, int, int); 182static int ath_wme_update(struct ieee80211com *); 183static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 184static void ath_tx_cleanup(struct ath_softc *); 185static void ath_freetx(struct mbuf *); 186static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 187 struct ath_buf *, struct mbuf *); 188static void ath_tx_proc_q0(void *, int); 189static void ath_tx_proc_q0123(void *, int); 190static void ath_tx_proc(void *, int); 191static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 192static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 193static void ath_draintxq(struct ath_softc *); 194static void ath_stoprecv(struct ath_softc *); 195static int ath_startrecv(struct ath_softc *); 196static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 197static void ath_scan_start(struct ieee80211com *); 198static void ath_scan_end(struct ieee80211com *); 199static void ath_set_channel(struct ieee80211com *); 200static void ath_calibrate(void *); 201static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 202static void ath_setup_stationkey(struct ieee80211_node *); 203static void ath_newassoc(struct ieee80211_node *, int); 204static int ath_setregdomain(struct ieee80211com *, 205 struct ieee80211_regdomain *, int, 206 struct ieee80211_channel []); 207static void ath_getradiocaps(struct ieee80211com *, int, int *, 208 struct ieee80211_channel []); 209static int ath_getchannels(struct ath_softc *); 210static void ath_led_event(struct ath_softc *, int); 211 212static int ath_rate_setup(struct ath_softc *, u_int mode); 213static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 214 215static void ath_sysctlattach(struct ath_softc *); 216static int ath_raw_xmit(struct ieee80211_node *, 217 struct mbuf *, const struct ieee80211_bpf_params *); 218static void ath_bpfattach(struct ath_softc *); 219static void ath_announce(struct ath_softc *); 220 221#ifdef ATH_SUPPORT_TDMA 222static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 223 u_int32_t bintval); 224static void ath_tdma_bintvalsetup(struct ath_softc *sc, 225 const struct ieee80211_tdma_state *tdma); 226static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 227static void ath_tdma_update(struct ieee80211_node *ni, 228 const struct ieee80211_tdma_param *tdma); 229static void ath_tdma_beacon_send(struct ath_softc *sc, 230 struct ieee80211vap *vap); 231 232static __inline void 233ath_hal_setcca(struct ath_hal *ah, int ena) 234{ 235 /* 236 * NB: fill me in; this is not provided by default because disabling 237 * CCA in most locales violates regulatory. 238 */ 239} 240 241static __inline int 242ath_hal_getcca(struct ath_hal *ah) 243{ 244 u_int32_t diag; 245 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 246 return 1; 247 return ((diag & 0x500000) == 0); 248} 249 250#define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 251#define TDMA_LPF_LEN 6 252#define TDMA_DUMMY_MARKER 0x127 253#define TDMA_EP_MUL(x, mul) ((x) * (mul)) 254#define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 255#define TDMA_LPF(x, y, len) \ 256 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 257#define TDMA_SAMPLE(x, y) do { \ 258 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 259} while (0) 260#define TDMA_EP_RND(x,mul) \ 261 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 262#define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 263#endif /* ATH_SUPPORT_TDMA */ 264 265SYSCTL_DECL(_hw_ath); 266 267/* XXX validate sysctl values */ 268static int ath_longcalinterval = 30; /* long cals every 30 secs */ 269SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 270 0, "long chip calibration interval (secs)"); 271static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 272SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 273 0, "short chip calibration interval (msecs)"); 274static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 275SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 276 0, "reset chip calibration results (secs)"); 277 278static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 279SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 280 0, "rx buffers allocated"); 281TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 282static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 283SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 284 0, "tx buffers allocated"); 285TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 286 287static int ath_bstuck_threshold = 4; /* max missed beacons */ 288SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 289 0, "max missed beacon xmits before chip reset"); 290 291#ifdef ATH_DEBUG 292enum { 293 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 294 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 295 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 296 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 297 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 298 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 299 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 300 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 301 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 302 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 303 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 304 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 305 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 306 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 307 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 308 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 309 ATH_DEBUG_NODE = 0x00080000, /* node management */ 310 ATH_DEBUG_LED = 0x00100000, /* led management */ 311 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 312 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 313 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */ 314 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */ 315 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 316 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 317 ATH_DEBUG_ANY = 0xffffffff 318}; 319static int ath_debug = 0; 320SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 321 0, "control debugging printfs"); 322TUNABLE_INT("hw.ath.debug", &ath_debug); 323 324#define IFF_DUMPPKTS(sc, m) \ 325 ((sc->sc_debug & (m)) || \ 326 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 327#define DPRINTF(sc, m, fmt, ...) do { \ 328 if (sc->sc_debug & (m)) \ 329 printf(fmt, __VA_ARGS__); \ 330} while (0) 331#define KEYPRINTF(sc, ix, hk, mac) do { \ 332 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 333 ath_keyprint(sc, __func__, ix, hk, mac); \ 334} while (0) 335static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 336 u_int ix, int); 337static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 338 u_int qnum, u_int ix, int done); 339#else 340#define IFF_DUMPPKTS(sc, m) \ 341 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 342#define DPRINTF(sc, m, fmt, ...) do { \ 343 (void) sc; \ 344} while (0) 345#define KEYPRINTF(sc, k, ix, mac) do { \ 346 (void) sc; \ 347} while (0) 348#endif 349 350MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 351 352int 353ath_attach(u_int16_t devid, struct ath_softc *sc) 354{ 355 struct ifnet *ifp; 356 struct ieee80211com *ic; 357 struct ath_hal *ah = NULL; 358 HAL_STATUS status; 359 int error = 0, i; 360 u_int wmodes; 361 362 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 363 364 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 365 if (ifp == NULL) { 366 device_printf(sc->sc_dev, "can not if_alloc()\n"); 367 error = ENOSPC; 368 goto bad; 369 } 370 ic = ifp->if_l2com; 371 372 /* set these up early for if_printf use */ 373 if_initname(ifp, device_get_name(sc->sc_dev), 374 device_get_unit(sc->sc_dev)); 375 376 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 377 if (ah == NULL) { 378 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 379 status); 380 error = ENXIO; 381 goto bad; 382 } 383 if (ah->ah_abi != HAL_ABI_VERSION) { 384 if_printf(ifp, "HAL ABI mismatch detected " 385 "(HAL:0x%x != driver:0x%x)\n", 386 ah->ah_abi, HAL_ABI_VERSION); 387 error = ENXIO; 388 goto bad; 389 } 390 sc->sc_ah = ah; 391 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 392#ifdef ATH_DEBUG 393 sc->sc_debug = ath_debug; 394#endif 395 396 /* 397 * Check if the MAC has multi-rate retry support. 398 * We do this by trying to setup a fake extended 399 * descriptor. MAC's that don't have support will 400 * return false w/o doing anything. MAC's that do 401 * support it will return true w/o doing anything. 402 */ 403 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 404 405 /* 406 * Check if the device has hardware counters for PHY 407 * errors. If so we need to enable the MIB interrupt 408 * so we can act on stat triggers. 409 */ 410 if (ath_hal_hwphycounters(ah)) 411 sc->sc_needmib = 1; 412 413 /* 414 * Get the hardware key cache size. 415 */ 416 sc->sc_keymax = ath_hal_keycachesize(ah); 417 if (sc->sc_keymax > ATH_KEYMAX) { 418 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 419 ATH_KEYMAX, sc->sc_keymax); 420 sc->sc_keymax = ATH_KEYMAX; 421 } 422 /* 423 * Reset the key cache since some parts do not 424 * reset the contents on initial power up. 425 */ 426 for (i = 0; i < sc->sc_keymax; i++) 427 ath_hal_keyreset(ah, i); 428 429 /* 430 * Collect the default channel list. 431 */ 432 error = ath_getchannels(sc); 433 if (error != 0) 434 goto bad; 435 436 /* 437 * Setup rate tables for all potential media types. 438 */ 439 ath_rate_setup(sc, IEEE80211_MODE_11A); 440 ath_rate_setup(sc, IEEE80211_MODE_11B); 441 ath_rate_setup(sc, IEEE80211_MODE_11G); 442 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 443 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 444 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 445 ath_rate_setup(sc, IEEE80211_MODE_11NA); 446 ath_rate_setup(sc, IEEE80211_MODE_11NG); 447 ath_rate_setup(sc, IEEE80211_MODE_HALF); 448 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 449 450 /* NB: setup here so ath_rate_update is happy */ 451 ath_setcurmode(sc, IEEE80211_MODE_11A); 452 453 /* 454 * Allocate tx+rx descriptors and populate the lists. 455 */ 456 error = ath_desc_alloc(sc); 457 if (error != 0) { 458 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 459 goto bad; 460 } 461 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 462 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 463 464 ATH_TXBUF_LOCK_INIT(sc); 465 466 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 467 taskqueue_thread_enqueue, &sc->sc_tq); 468 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 469 "%s taskq", ifp->if_xname); 470 471 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 472 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 473 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 474 475 /* 476 * Allocate hardware transmit queues: one queue for 477 * beacon frames and one data queue for each QoS 478 * priority. Note that the hal handles reseting 479 * these queues at the needed time. 480 * 481 * XXX PS-Poll 482 */ 483 sc->sc_bhalq = ath_beaconq_setup(ah); 484 if (sc->sc_bhalq == (u_int) -1) { 485 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 486 error = EIO; 487 goto bad2; 488 } 489 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 490 if (sc->sc_cabq == NULL) { 491 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 492 error = EIO; 493 goto bad2; 494 } 495 /* NB: insure BK queue is the lowest priority h/w queue */ 496 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 497 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 498 ieee80211_wme_acnames[WME_AC_BK]); 499 error = EIO; 500 goto bad2; 501 } 502 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 503 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 504 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 505 /* 506 * Not enough hardware tx queues to properly do WME; 507 * just punt and assign them all to the same h/w queue. 508 * We could do a better job of this if, for example, 509 * we allocate queues when we switch from station to 510 * AP mode. 511 */ 512 if (sc->sc_ac2q[WME_AC_VI] != NULL) 513 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 514 if (sc->sc_ac2q[WME_AC_BE] != NULL) 515 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 516 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 517 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 518 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 519 } 520 521 /* 522 * Special case certain configurations. Note the 523 * CAB queue is handled by these specially so don't 524 * include them when checking the txq setup mask. 525 */ 526 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 527 case 0x01: 528 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 529 break; 530 case 0x0f: 531 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 532 break; 533 default: 534 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 535 break; 536 } 537 538 /* 539 * Setup rate control. Some rate control modules 540 * call back to change the anntena state so expose 541 * the necessary entry points. 542 * XXX maybe belongs in struct ath_ratectrl? 543 */ 544 sc->sc_setdefantenna = ath_setdefantenna; 545 sc->sc_rc = ath_rate_attach(sc); 546 if (sc->sc_rc == NULL) { 547 error = EIO; 548 goto bad2; 549 } 550 551 sc->sc_blinking = 0; 552 sc->sc_ledstate = 1; 553 sc->sc_ledon = 0; /* low true */ 554 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 555 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 556 /* 557 * Auto-enable soft led processing for IBM cards and for 558 * 5211 minipci cards. Users can also manually enable/disable 559 * support with a sysctl. 560 */ 561 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 562 if (sc->sc_softled) { 563 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 564 HAL_GPIO_MUX_MAC_NETWORK_LED); 565 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 566 } 567 568 ifp->if_softc = sc; 569 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 570 ifp->if_start = ath_start; 571 ifp->if_watchdog = NULL; 572 ifp->if_ioctl = ath_ioctl; 573 ifp->if_init = ath_init; 574 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 575 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 576 IFQ_SET_READY(&ifp->if_snd); 577 578 ic->ic_ifp = ifp; 579 /* XXX not right but it's not used anywhere important */ 580 ic->ic_phytype = IEEE80211_T_OFDM; 581 ic->ic_opmode = IEEE80211_M_STA; 582 ic->ic_caps = 583 IEEE80211_C_STA /* station mode */ 584 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 585 | IEEE80211_C_HOSTAP /* hostap mode */ 586 | IEEE80211_C_MONITOR /* monitor mode */ 587 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 588 | IEEE80211_C_WDS /* 4-address traffic works */ 589 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 590 | IEEE80211_C_SHSLOT /* short slot time supported */ 591 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 592 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 593 | IEEE80211_C_TXFRAG /* handle tx frags */ 594 ; 595 /* 596 * Query the hal to figure out h/w crypto support. 597 */ 598 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 599 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 600 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 601 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 602 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 603 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 604 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 605 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 606 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 607 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 608 /* 609 * Check if h/w does the MIC and/or whether the 610 * separate key cache entries are required to 611 * handle both tx+rx MIC keys. 612 */ 613 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 614 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 615 /* 616 * If the h/w supports storing tx+rx MIC keys 617 * in one cache slot automatically enable use. 618 */ 619 if (ath_hal_hastkipsplit(ah) || 620 !ath_hal_settkipsplit(ah, AH_FALSE)) 621 sc->sc_splitmic = 1; 622 /* 623 * If the h/w can do TKIP MIC together with WME then 624 * we use it; otherwise we force the MIC to be done 625 * in software by the net80211 layer. 626 */ 627 if (ath_hal_haswmetkipmic(ah)) 628 sc->sc_wmetkipmic = 1; 629 } 630 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 631 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 632 /* 633 * Mark key cache slots associated with global keys 634 * as in use. If we knew TKIP was not to be used we 635 * could leave the +32, +64, and +32+64 slots free. 636 */ 637 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 638 setbit(sc->sc_keymap, i); 639 setbit(sc->sc_keymap, i+64); 640 if (sc->sc_splitmic) { 641 setbit(sc->sc_keymap, i+32); 642 setbit(sc->sc_keymap, i+32+64); 643 } 644 } 645 /* 646 * TPC support can be done either with a global cap or 647 * per-packet support. The latter is not available on 648 * all parts. We're a bit pedantic here as all parts 649 * support a global cap. 650 */ 651 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 652 ic->ic_caps |= IEEE80211_C_TXPMGT; 653 654 /* 655 * Mark WME capability only if we have sufficient 656 * hardware queues to do proper priority scheduling. 657 */ 658 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 659 ic->ic_caps |= IEEE80211_C_WME; 660 /* 661 * Check for misc other capabilities. 662 */ 663 if (ath_hal_hasbursting(ah)) 664 ic->ic_caps |= IEEE80211_C_BURST; 665 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 666 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 667 if (ath_hal_hasfastframes(ah)) 668 ic->ic_caps |= IEEE80211_C_FF; 669 wmodes = ath_hal_getwirelessmodes(ah); 670 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 671 ic->ic_caps |= IEEE80211_C_TURBOP; 672#ifdef ATH_SUPPORT_TDMA 673 if (ath_hal_macversion(ah) > 0x78) { 674 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 675 ic->ic_tdma_update = ath_tdma_update; 676 } 677#endif 678 /* 679 * Indicate we need the 802.11 header padded to a 680 * 32-bit boundary for 4-address and QoS frames. 681 */ 682 ic->ic_flags |= IEEE80211_F_DATAPAD; 683 684 /* 685 * Query the hal about antenna support. 686 */ 687 sc->sc_defant = ath_hal_getdefantenna(ah); 688 689 /* 690 * Not all chips have the VEOL support we want to 691 * use with IBSS beacons; check here for it. 692 */ 693 sc->sc_hasveol = ath_hal_hasveol(ah); 694 695 /* get mac address from hardware */ 696 ath_hal_getmac(ah, ic->ic_myaddr); 697 if (sc->sc_hasbmask) 698 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 699 700 /* NB: used to size node table key mapping array */ 701 ic->ic_max_keyix = sc->sc_keymax; 702 /* call MI attach routine. */ 703 ieee80211_ifattach(ic); 704 ic->ic_setregdomain = ath_setregdomain; 705 ic->ic_getradiocaps = ath_getradiocaps; 706 sc->sc_opmode = HAL_M_STA; 707 708 /* override default methods */ 709 ic->ic_newassoc = ath_newassoc; 710 ic->ic_updateslot = ath_updateslot; 711 ic->ic_wme.wme_update = ath_wme_update; 712 ic->ic_vap_create = ath_vap_create; 713 ic->ic_vap_delete = ath_vap_delete; 714 ic->ic_raw_xmit = ath_raw_xmit; 715 ic->ic_update_mcast = ath_update_mcast; 716 ic->ic_update_promisc = ath_update_promisc; 717 ic->ic_node_alloc = ath_node_alloc; 718 sc->sc_node_free = ic->ic_node_free; 719 ic->ic_node_free = ath_node_free; 720 ic->ic_node_getsignal = ath_node_getsignal; 721 ic->ic_scan_start = ath_scan_start; 722 ic->ic_scan_end = ath_scan_end; 723 ic->ic_set_channel = ath_set_channel; 724 725 ath_bpfattach(sc); 726 /* 727 * Setup dynamic sysctl's now that country code and 728 * regdomain are available from the hal. 729 */ 730 ath_sysctlattach(sc); 731 732 if (bootverbose) 733 ieee80211_announce(ic); 734 ath_announce(sc); 735 return 0; 736bad2: 737 ath_tx_cleanup(sc); 738 ath_desc_free(sc); 739bad: 740 if (ah) 741 ath_hal_detach(ah); 742 if (ifp != NULL) 743 if_free(ifp); 744 sc->sc_invalid = 1; 745 return error; 746} 747 748int 749ath_detach(struct ath_softc *sc) 750{ 751 struct ifnet *ifp = sc->sc_ifp; 752 753 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 754 __func__, ifp->if_flags); 755 756 /* 757 * NB: the order of these is important: 758 * o stop the chip so no more interrupts will fire 759 * o call the 802.11 layer before detaching the hal to 760 * insure callbacks into the driver to delete global 761 * key cache entries can be handled 762 * o free the taskqueue which drains any pending tasks 763 * o reclaim the bpf tap now that we know nothing will use 764 * it (e.g. rx processing from the task q thread) 765 * o reclaim the tx queue data structures after calling 766 * the 802.11 layer as we'll get called back to reclaim 767 * node state and potentially want to use them 768 * o to cleanup the tx queues the hal is called, so detach 769 * it last 770 * Other than that, it's straightforward... 771 */ 772 ath_stop(ifp); 773 ieee80211_ifdetach(ifp->if_l2com); 774 taskqueue_free(sc->sc_tq); 775 bpfdetach(ifp); 776#ifdef ATH_TX99_DIAG 777 if (sc->sc_tx99 != NULL) 778 sc->sc_tx99->detach(sc->sc_tx99); 779#endif 780 ath_rate_detach(sc->sc_rc); 781 ath_desc_free(sc); 782 ath_tx_cleanup(sc); 783 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 784 if_free(ifp); 785 786 return 0; 787} 788 789/* 790 * MAC address handling for multiple BSS on the same radio. 791 * The first vap uses the MAC address from the EEPROM. For 792 * subsequent vap's we set the U/L bit (bit 1) in the MAC 793 * address and use the next six bits as an index. 794 */ 795static void 796assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 797{ 798 int i; 799 800 if (clone && sc->sc_hasbmask) { 801 /* NB: we only do this if h/w supports multiple bssid */ 802 for (i = 0; i < 8; i++) 803 if ((sc->sc_bssidmask & (1<<i)) == 0) 804 break; 805 if (i != 0) 806 mac[0] |= (i << 2)|0x2; 807 } else 808 i = 0; 809 sc->sc_bssidmask |= 1<<i; 810 sc->sc_hwbssidmask[0] &= ~mac[0]; 811 if (i == 0) 812 sc->sc_nbssid0++; 813} 814 815static void 816reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 817{ 818 int i = mac[0] >> 2; 819 uint8_t mask; 820 821 if (i != 0 || --sc->sc_nbssid0 == 0) { 822 sc->sc_bssidmask &= ~(1<<i); 823 /* recalculate bssid mask from remaining addresses */ 824 mask = 0xff; 825 for (i = 1; i < 8; i++) 826 if (sc->sc_bssidmask & (1<<i)) 827 mask &= ~((i<<2)|0x2); 828 sc->sc_hwbssidmask[0] |= mask; 829 } 830} 831 832/* 833 * Assign a beacon xmit slot. We try to space out 834 * assignments so when beacons are staggered the 835 * traffic coming out of the cab q has maximal time 836 * to go out before the next beacon is scheduled. 837 */ 838static int 839assign_bslot(struct ath_softc *sc) 840{ 841 u_int slot, free; 842 843 free = 0; 844 for (slot = 0; slot < ATH_BCBUF; slot++) 845 if (sc->sc_bslot[slot] == NULL) { 846 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 847 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 848 return slot; 849 free = slot; 850 /* NB: keep looking for a double slot */ 851 } 852 return free; 853} 854 855static struct ieee80211vap * 856ath_vap_create(struct ieee80211com *ic, 857 const char name[IFNAMSIZ], int unit, int opmode, int flags, 858 const uint8_t bssid[IEEE80211_ADDR_LEN], 859 const uint8_t mac0[IEEE80211_ADDR_LEN]) 860{ 861 struct ath_softc *sc = ic->ic_ifp->if_softc; 862 struct ath_vap *avp; 863 struct ieee80211vap *vap; 864 uint8_t mac[IEEE80211_ADDR_LEN]; 865 int ic_opmode, needbeacon, error; 866 867 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 868 M_80211_VAP, M_WAITOK | M_ZERO); 869 needbeacon = 0; 870 IEEE80211_ADDR_COPY(mac, mac0); 871 872 ATH_LOCK(sc); 873 switch (opmode) { 874 case IEEE80211_M_STA: 875 if (sc->sc_nstavaps != 0) { /* XXX only 1 sta for now */ 876 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 877 goto bad; 878 } 879 if (sc->sc_nvaps) { 880 /* 881 * When there are multiple vaps we must fall 882 * back to s/w beacon miss handling. 883 */ 884 flags |= IEEE80211_CLONE_NOBEACONS; 885 } 886 if (flags & IEEE80211_CLONE_NOBEACONS) 887 ic_opmode = IEEE80211_M_HOSTAP; 888 else 889 ic_opmode = opmode; 890 break; 891 case IEEE80211_M_IBSS: 892 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 893 device_printf(sc->sc_dev, 894 "only 1 ibss vap supported\n"); 895 goto bad; 896 } 897 ic_opmode = opmode; 898 needbeacon = 1; 899 break; 900 case IEEE80211_M_AHDEMO: 901#ifdef ATH_SUPPORT_TDMA 902 if (flags & IEEE80211_CLONE_TDMA) { 903 needbeacon = 1; 904 flags |= IEEE80211_CLONE_NOBEACONS; 905 } 906 /* fall thru... */ 907#endif 908 case IEEE80211_M_MONITOR: 909 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 910 /* XXX not right for monitor mode */ 911 ic_opmode = ic->ic_opmode; 912 } else 913 ic_opmode = opmode; 914 break; 915 case IEEE80211_M_HOSTAP: 916 needbeacon = 1; 917 /* fall thru... */ 918 case IEEE80211_M_WDS: 919 if (sc->sc_nvaps && ic->ic_opmode == IEEE80211_M_STA) { 920 device_printf(sc->sc_dev, 921 "wds not supported in sta mode\n"); 922 goto bad; 923 } 924 if (opmode == IEEE80211_M_WDS) { 925 /* 926 * Silently remove any request for a unique 927 * bssid; WDS vap's always share the local 928 * mac address. 929 */ 930 flags &= ~IEEE80211_CLONE_BSSID; 931 } 932 ic_opmode = IEEE80211_M_HOSTAP; 933 break; 934 default: 935 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 936 goto bad; 937 } 938 /* 939 * Check that a beacon buffer is available; the code below assumes it. 940 */ 941 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 942 device_printf(sc->sc_dev, "no beacon buffer available\n"); 943 goto bad; 944 } 945 946 /* STA, AHDEMO? */ 947 if (opmode == IEEE80211_M_HOSTAP) { 948 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 949 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 950 } 951 952 vap = &avp->av_vap; 953 /* XXX can't hold mutex across if_alloc */ 954 ATH_UNLOCK(sc); 955 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 956 bssid, mac); 957 ATH_LOCK(sc); 958 if (error != 0) { 959 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 960 __func__, error); 961 goto bad2; 962 } 963 964 /* h/w crypto support */ 965 vap->iv_key_alloc = ath_key_alloc; 966 vap->iv_key_delete = ath_key_delete; 967 vap->iv_key_set = ath_key_set; 968 vap->iv_key_update_begin = ath_key_update_begin; 969 vap->iv_key_update_end = ath_key_update_end; 970 971 /* override various methods */ 972 avp->av_recv_mgmt = vap->iv_recv_mgmt; 973 vap->iv_recv_mgmt = ath_recv_mgmt; 974 vap->iv_reset = ath_reset_vap; 975 vap->iv_update_beacon = ath_beacon_update; 976 avp->av_newstate = vap->iv_newstate; 977 vap->iv_newstate = ath_newstate; 978 avp->av_bmiss = vap->iv_bmiss; 979 vap->iv_bmiss = ath_bmiss_vap; 980 981 avp->av_bslot = -1; 982 if (needbeacon) { 983 /* 984 * Allocate beacon state and setup the q for buffered 985 * multicast frames. We know a beacon buffer is 986 * available because we checked above. 987 */ 988 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 989 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 990 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 991 /* 992 * Assign the vap to a beacon xmit slot. As above 993 * this cannot fail to find a free one. 994 */ 995 avp->av_bslot = assign_bslot(sc); 996 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 997 ("beacon slot %u not empty", avp->av_bslot)); 998 sc->sc_bslot[avp->av_bslot] = vap; 999 sc->sc_nbcnvaps++; 1000 } 1001 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1002 /* 1003 * Multple vaps are to transmit beacons and we 1004 * have h/w support for TSF adjusting; enable 1005 * use of staggered beacons. 1006 */ 1007 sc->sc_stagbeacons = 1; 1008 } 1009 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1010 } 1011 1012 ic->ic_opmode = ic_opmode; 1013 if (opmode != IEEE80211_M_WDS) { 1014 sc->sc_nvaps++; 1015 if (opmode == IEEE80211_M_STA) 1016 sc->sc_nstavaps++; 1017 } 1018 switch (ic_opmode) { 1019 case IEEE80211_M_IBSS: 1020 sc->sc_opmode = HAL_M_IBSS; 1021 break; 1022 case IEEE80211_M_STA: 1023 sc->sc_opmode = HAL_M_STA; 1024 break; 1025 case IEEE80211_M_AHDEMO: 1026#ifdef ATH_SUPPORT_TDMA 1027 if (vap->iv_caps & IEEE80211_C_TDMA) { 1028 sc->sc_tdma = 1; 1029 /* NB: disable tsf adjust */ 1030 sc->sc_stagbeacons = 0; 1031 } 1032 /* 1033 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1034 * just ap mode. 1035 */ 1036 /* fall thru... */ 1037#endif 1038 case IEEE80211_M_HOSTAP: 1039 sc->sc_opmode = HAL_M_HOSTAP; 1040 break; 1041 case IEEE80211_M_MONITOR: 1042 sc->sc_opmode = HAL_M_MONITOR; 1043 break; 1044 default: 1045 /* XXX should not happen */ 1046 break; 1047 } 1048 if (sc->sc_hastsfadd) { 1049 /* 1050 * Configure whether or not TSF adjust should be done. 1051 */ 1052 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1053 } 1054 if (flags & IEEE80211_CLONE_NOBEACONS) { 1055 /* 1056 * Enable s/w beacon miss handling. 1057 */ 1058 sc->sc_swbmiss = 1; 1059 } 1060 ATH_UNLOCK(sc); 1061 1062 /* complete setup */ 1063 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1064 return vap; 1065bad2: 1066 reclaim_address(sc, mac); 1067 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1068bad: 1069 free(avp, M_80211_VAP); 1070 ATH_UNLOCK(sc); 1071 return NULL; 1072} 1073 1074static void 1075ath_vap_delete(struct ieee80211vap *vap) 1076{ 1077 struct ieee80211com *ic = vap->iv_ic; 1078 struct ifnet *ifp = ic->ic_ifp; 1079 struct ath_softc *sc = ifp->if_softc; 1080 struct ath_hal *ah = sc->sc_ah; 1081 struct ath_vap *avp = ATH_VAP(vap); 1082 1083 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1084 /* 1085 * Quiesce the hardware while we remove the vap. In 1086 * particular we need to reclaim all references to 1087 * the vap state by any frames pending on the tx queues. 1088 */ 1089 ath_hal_intrset(ah, 0); /* disable interrupts */ 1090 ath_draintxq(sc); /* stop xmit side */ 1091 ath_stoprecv(sc); /* stop recv side */ 1092 } 1093 1094 ieee80211_vap_detach(vap); 1095 ATH_LOCK(sc); 1096 /* 1097 * Reclaim beacon state. Note this must be done before 1098 * the vap instance is reclaimed as we may have a reference 1099 * to it in the buffer for the beacon frame. 1100 */ 1101 if (avp->av_bcbuf != NULL) { 1102 if (avp->av_bslot != -1) { 1103 sc->sc_bslot[avp->av_bslot] = NULL; 1104 sc->sc_nbcnvaps--; 1105 } 1106 ath_beacon_return(sc, avp->av_bcbuf); 1107 avp->av_bcbuf = NULL; 1108 if (sc->sc_nbcnvaps == 0) { 1109 sc->sc_stagbeacons = 0; 1110 if (sc->sc_hastsfadd) 1111 ath_hal_settsfadjust(sc->sc_ah, 0); 1112 } 1113 /* 1114 * Reclaim any pending mcast frames for the vap. 1115 */ 1116 ath_tx_draintxq(sc, &avp->av_mcastq); 1117 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1118 } 1119 /* 1120 * Update bookkeeping. 1121 */ 1122 if (vap->iv_opmode == IEEE80211_M_STA) { 1123 sc->sc_nstavaps--; 1124 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1125 sc->sc_swbmiss = 0; 1126 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 1127 reclaim_address(sc, vap->iv_myaddr); 1128 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1129 } 1130 if (vap->iv_opmode != IEEE80211_M_WDS) 1131 sc->sc_nvaps--; 1132#ifdef ATH_SUPPORT_TDMA 1133 /* TDMA operation ceases when the last vap is destroyed */ 1134 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1135 sc->sc_tdma = 0; 1136 sc->sc_swbmiss = 0; 1137 } 1138#endif 1139 ATH_UNLOCK(sc); 1140 free(avp, M_80211_VAP); 1141 1142 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1143 /* 1144 * Restart rx+tx machines if still running (RUNNING will 1145 * be reset if we just destroyed the last vap). 1146 */ 1147 if (ath_startrecv(sc) != 0) 1148 if_printf(ifp, "%s: unable to restart recv logic\n", 1149 __func__); 1150 if (sc->sc_beacons) 1151 ath_beacon_config(sc, NULL); 1152 ath_hal_intrset(ah, sc->sc_imask); 1153 } 1154} 1155 1156void 1157ath_suspend(struct ath_softc *sc) 1158{ 1159 struct ifnet *ifp = sc->sc_ifp; 1160 struct ieee80211com *ic = ifp->if_l2com; 1161 1162 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1163 __func__, ifp->if_flags); 1164 1165 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1166 if (ic->ic_opmode == IEEE80211_M_STA) 1167 ath_stop(ifp); 1168 else 1169 ieee80211_suspend_all(ic); 1170 /* 1171 * NB: don't worry about putting the chip in low power 1172 * mode; pci will power off our socket on suspend and 1173 * cardbus detaches the device. 1174 */ 1175} 1176 1177/* 1178 * Reset the key cache since some parts do not reset the 1179 * contents on resume. First we clear all entries, then 1180 * re-load keys that the 802.11 layer assumes are setup 1181 * in h/w. 1182 */ 1183static void 1184ath_reset_keycache(struct ath_softc *sc) 1185{ 1186 struct ifnet *ifp = sc->sc_ifp; 1187 struct ieee80211com *ic = ifp->if_l2com; 1188 struct ath_hal *ah = sc->sc_ah; 1189 int i; 1190 1191 for (i = 0; i < sc->sc_keymax; i++) 1192 ath_hal_keyreset(ah, i); 1193 ieee80211_crypto_reload_keys(ic); 1194} 1195 1196void 1197ath_resume(struct ath_softc *sc) 1198{ 1199 struct ifnet *ifp = sc->sc_ifp; 1200 struct ieee80211com *ic = ifp->if_l2com; 1201 struct ath_hal *ah = sc->sc_ah; 1202 HAL_STATUS status; 1203 1204 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1205 __func__, ifp->if_flags); 1206 1207 /* 1208 * Must reset the chip before we reload the 1209 * keycache as we were powered down on suspend. 1210 */ 1211 ath_hal_reset(ah, sc->sc_opmode, 1212 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1213 AH_FALSE, &status); 1214 ath_reset_keycache(sc); 1215 if (sc->sc_resume_up) { 1216 if (ic->ic_opmode == IEEE80211_M_STA) { 1217 ath_init(sc); 1218 ieee80211_beacon_miss(ic); 1219 } else 1220 ieee80211_resume_all(ic); 1221 } 1222 if (sc->sc_softled) { 1223 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1224 HAL_GPIO_MUX_MAC_NETWORK_LED); 1225 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1226 } 1227} 1228 1229void 1230ath_shutdown(struct ath_softc *sc) 1231{ 1232 struct ifnet *ifp = sc->sc_ifp; 1233 1234 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1235 __func__, ifp->if_flags); 1236 1237 ath_stop(ifp); 1238 /* NB: no point powering down chip as we're about to reboot */ 1239} 1240 1241/* 1242 * Interrupt handler. Most of the actual processing is deferred. 1243 */ 1244void 1245ath_intr(void *arg) 1246{ 1247 struct ath_softc *sc = arg; 1248 struct ifnet *ifp = sc->sc_ifp; 1249 struct ath_hal *ah = sc->sc_ah; 1250 HAL_INT status; 1251 1252 if (sc->sc_invalid) { 1253 /* 1254 * The hardware is not ready/present, don't touch anything. 1255 * Note this can happen early on if the IRQ is shared. 1256 */ 1257 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1258 return; 1259 } 1260 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1261 return; 1262 if ((ifp->if_flags & IFF_UP) == 0 || 1263 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1264 HAL_INT status; 1265 1266 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1267 __func__, ifp->if_flags); 1268 ath_hal_getisr(ah, &status); /* clear ISR */ 1269 ath_hal_intrset(ah, 0); /* disable further intr's */ 1270 return; 1271 } 1272 /* 1273 * Figure out the reason(s) for the interrupt. Note 1274 * that the hal returns a pseudo-ISR that may include 1275 * bits we haven't explicitly enabled so we mask the 1276 * value to insure we only process bits we requested. 1277 */ 1278 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1279 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1280 status &= sc->sc_imask; /* discard unasked for bits */ 1281 if (status & HAL_INT_FATAL) { 1282 sc->sc_stats.ast_hardware++; 1283 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1284 ath_fatal_proc(sc, 0); 1285 } else { 1286 if (status & HAL_INT_SWBA) { 1287 /* 1288 * Software beacon alert--time to send a beacon. 1289 * Handle beacon transmission directly; deferring 1290 * this is too slow to meet timing constraints 1291 * under load. 1292 */ 1293#ifdef ATH_SUPPORT_TDMA 1294 if (sc->sc_tdma) { 1295 if (sc->sc_tdmaswba == 0) { 1296 struct ieee80211com *ic = ifp->if_l2com; 1297 struct ieee80211vap *vap = 1298 TAILQ_FIRST(&ic->ic_vaps); 1299 ath_tdma_beacon_send(sc, vap); 1300 sc->sc_tdmaswba = 1301 vap->iv_tdma->tdma_bintval; 1302 } else 1303 sc->sc_tdmaswba--; 1304 } else 1305#endif 1306 ath_beacon_proc(sc, 0); 1307 } 1308 if (status & HAL_INT_RXEOL) { 1309 /* 1310 * NB: the hardware should re-read the link when 1311 * RXE bit is written, but it doesn't work at 1312 * least on older hardware revs. 1313 */ 1314 sc->sc_stats.ast_rxeol++; 1315 sc->sc_rxlink = NULL; 1316 } 1317 if (status & HAL_INT_TXURN) { 1318 sc->sc_stats.ast_txurn++; 1319 /* bump tx trigger level */ 1320 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1321 } 1322 if (status & HAL_INT_RX) 1323 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1324 if (status & HAL_INT_TX) 1325 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1326 if (status & HAL_INT_BMISS) { 1327 sc->sc_stats.ast_bmiss++; 1328 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1329 } 1330 if (status & HAL_INT_MIB) { 1331 sc->sc_stats.ast_mib++; 1332 /* 1333 * Disable interrupts until we service the MIB 1334 * interrupt; otherwise it will continue to fire. 1335 */ 1336 ath_hal_intrset(ah, 0); 1337 /* 1338 * Let the hal handle the event. We assume it will 1339 * clear whatever condition caused the interrupt. 1340 */ 1341 ath_hal_mibevent(ah, &sc->sc_halstats); 1342 ath_hal_intrset(ah, sc->sc_imask); 1343 } 1344 if (status & HAL_INT_RXORN) { 1345 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1346 sc->sc_stats.ast_rxorn++; 1347 } 1348 } 1349} 1350 1351static void 1352ath_fatal_proc(void *arg, int pending) 1353{ 1354 struct ath_softc *sc = arg; 1355 struct ifnet *ifp = sc->sc_ifp; 1356 u_int32_t *state; 1357 u_int32_t len; 1358 void *sp; 1359 1360 if_printf(ifp, "hardware error; resetting\n"); 1361 /* 1362 * Fatal errors are unrecoverable. Typically these 1363 * are caused by DMA errors. Collect h/w state from 1364 * the hal so we can diagnose what's going on. 1365 */ 1366 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1367 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1368 state = sp; 1369 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1370 state[0], state[1] , state[2], state[3], 1371 state[4], state[5]); 1372 } 1373 ath_reset(ifp); 1374} 1375 1376static void 1377ath_bmiss_vap(struct ieee80211vap *vap) 1378{ 1379 /* 1380 * Workaround phantom bmiss interrupts by sanity-checking 1381 * the time of our last rx'd frame. If it is within the 1382 * beacon miss interval then ignore the interrupt. If it's 1383 * truly a bmiss we'll get another interrupt soon and that'll 1384 * be dispatched up for processing. Note this applies only 1385 * for h/w beacon miss events. 1386 */ 1387 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1388 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1389 struct ath_softc *sc = ifp->if_softc; 1390 u_int64_t lastrx = sc->sc_lastrx; 1391 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1392 u_int bmisstimeout = 1393 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1394 1395 DPRINTF(sc, ATH_DEBUG_BEACON, 1396 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1397 __func__, (unsigned long long) tsf, 1398 (unsigned long long)(tsf - lastrx), 1399 (unsigned long long) lastrx, bmisstimeout); 1400 1401 if (tsf - lastrx <= bmisstimeout) { 1402 sc->sc_stats.ast_bmiss_phantom++; 1403 return; 1404 } 1405 } 1406 ATH_VAP(vap)->av_bmiss(vap); 1407} 1408 1409static int 1410ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1411{ 1412 uint32_t rsize; 1413 void *sp; 1414 1415 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize)) 1416 return 0; 1417 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1418 *hangs = *(uint32_t *)sp; 1419 return 1; 1420} 1421 1422static void 1423ath_bmiss_proc(void *arg, int pending) 1424{ 1425 struct ath_softc *sc = arg; 1426 struct ifnet *ifp = sc->sc_ifp; 1427 uint32_t hangs; 1428 1429 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1430 1431 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1432 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs); 1433 ath_reset(ifp); 1434 } else 1435 ieee80211_beacon_miss(ifp->if_l2com); 1436} 1437 1438/* 1439 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1440 * calcs together with WME. If necessary disable the crypto 1441 * hardware and mark the 802.11 state so keys will be setup 1442 * with the MIC work done in software. 1443 */ 1444static void 1445ath_settkipmic(struct ath_softc *sc) 1446{ 1447 struct ifnet *ifp = sc->sc_ifp; 1448 struct ieee80211com *ic = ifp->if_l2com; 1449 1450 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1451 if (ic->ic_flags & IEEE80211_F_WME) { 1452 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1453 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1454 } else { 1455 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1456 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1457 } 1458 } 1459} 1460 1461static void 1462ath_init(void *arg) 1463{ 1464 struct ath_softc *sc = (struct ath_softc *) arg; 1465 struct ifnet *ifp = sc->sc_ifp; 1466 struct ieee80211com *ic = ifp->if_l2com; 1467 struct ath_hal *ah = sc->sc_ah; 1468 HAL_STATUS status; 1469 1470 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1471 __func__, ifp->if_flags); 1472 1473 ATH_LOCK(sc); 1474 /* 1475 * Stop anything previously setup. This is safe 1476 * whether this is the first time through or not. 1477 */ 1478 ath_stop_locked(ifp); 1479 1480 /* 1481 * The basic interface to setting the hardware in a good 1482 * state is ``reset''. On return the hardware is known to 1483 * be powered up and with interrupts disabled. This must 1484 * be followed by initialization of the appropriate bits 1485 * and then setup of the interrupt mask. 1486 */ 1487 ath_settkipmic(sc); 1488 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1489 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1490 status); 1491 ATH_UNLOCK(sc); 1492 return; 1493 } 1494 ath_chan_change(sc, ic->ic_curchan); 1495 1496 /* 1497 * Likewise this is set during reset so update 1498 * state cached in the driver. 1499 */ 1500 sc->sc_diversity = ath_hal_getdiversity(ah); 1501 sc->sc_lastlongcal = 0; 1502 sc->sc_resetcal = 1; 1503 sc->sc_lastcalreset = 0; 1504 1505 /* 1506 * Setup the hardware after reset: the key cache 1507 * is filled as needed and the receive engine is 1508 * set going. Frame transmit is handled entirely 1509 * in the frame output path; there's nothing to do 1510 * here except setup the interrupt mask. 1511 */ 1512 if (ath_startrecv(sc) != 0) { 1513 if_printf(ifp, "unable to start recv logic\n"); 1514 ATH_UNLOCK(sc); 1515 return; 1516 } 1517 1518 /* 1519 * Enable interrupts. 1520 */ 1521 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1522 | HAL_INT_RXEOL | HAL_INT_RXORN 1523 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1524 /* 1525 * Enable MIB interrupts when there are hardware phy counters. 1526 * Note we only do this (at the moment) for station mode. 1527 */ 1528 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1529 sc->sc_imask |= HAL_INT_MIB; 1530 1531 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1532 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1533 ath_hal_intrset(ah, sc->sc_imask); 1534 1535 ATH_UNLOCK(sc); 1536 1537#ifdef ATH_TX99_DIAG 1538 if (sc->sc_tx99 != NULL) 1539 sc->sc_tx99->start(sc->sc_tx99); 1540 else 1541#endif 1542 ieee80211_start_all(ic); /* start all vap's */ 1543} 1544 1545static void 1546ath_stop_locked(struct ifnet *ifp) 1547{ 1548 struct ath_softc *sc = ifp->if_softc; 1549 struct ath_hal *ah = sc->sc_ah; 1550 1551 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1552 __func__, sc->sc_invalid, ifp->if_flags); 1553 1554 ATH_LOCK_ASSERT(sc); 1555 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1556 /* 1557 * Shutdown the hardware and driver: 1558 * reset 802.11 state machine 1559 * turn off timers 1560 * disable interrupts 1561 * turn off the radio 1562 * clear transmit machinery 1563 * clear receive machinery 1564 * drain and release tx queues 1565 * reclaim beacon resources 1566 * power down hardware 1567 * 1568 * Note that some of this work is not possible if the 1569 * hardware is gone (invalid). 1570 */ 1571#ifdef ATH_TX99_DIAG 1572 if (sc->sc_tx99 != NULL) 1573 sc->sc_tx99->stop(sc->sc_tx99); 1574#endif 1575 callout_stop(&sc->sc_wd_ch); 1576 sc->sc_wd_timer = 0; 1577 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1578 if (!sc->sc_invalid) { 1579 if (sc->sc_softled) { 1580 callout_stop(&sc->sc_ledtimer); 1581 ath_hal_gpioset(ah, sc->sc_ledpin, 1582 !sc->sc_ledon); 1583 sc->sc_blinking = 0; 1584 } 1585 ath_hal_intrset(ah, 0); 1586 } 1587 ath_draintxq(sc); 1588 if (!sc->sc_invalid) { 1589 ath_stoprecv(sc); 1590 ath_hal_phydisable(ah); 1591 } else 1592 sc->sc_rxlink = NULL; 1593 ath_beacon_free(sc); /* XXX not needed */ 1594 } 1595} 1596 1597static void 1598ath_stop(struct ifnet *ifp) 1599{ 1600 struct ath_softc *sc = ifp->if_softc; 1601 1602 ATH_LOCK(sc); 1603 ath_stop_locked(ifp); 1604 ATH_UNLOCK(sc); 1605} 1606 1607/* 1608 * Reset the hardware w/o losing operational state. This is 1609 * basically a more efficient way of doing ath_stop, ath_init, 1610 * followed by state transitions to the current 802.11 1611 * operational state. Used to recover from various errors and 1612 * to reset or reload hardware state. 1613 */ 1614static int 1615ath_reset(struct ifnet *ifp) 1616{ 1617 struct ath_softc *sc = ifp->if_softc; 1618 struct ieee80211com *ic = ifp->if_l2com; 1619 struct ath_hal *ah = sc->sc_ah; 1620 HAL_STATUS status; 1621 1622 ath_hal_intrset(ah, 0); /* disable interrupts */ 1623 ath_draintxq(sc); /* stop xmit side */ 1624 ath_stoprecv(sc); /* stop recv side */ 1625 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1626 /* NB: indicate channel change so we do a full reset */ 1627 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1628 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1629 __func__, status); 1630 sc->sc_diversity = ath_hal_getdiversity(ah); 1631 if (ath_startrecv(sc) != 0) /* restart recv */ 1632 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1633 /* 1634 * We may be doing a reset in response to an ioctl 1635 * that changes the channel so update any state that 1636 * might change as a result. 1637 */ 1638 ath_chan_change(sc, ic->ic_curchan); 1639 if (sc->sc_beacons) { 1640#ifdef ATH_SUPPORT_TDMA 1641 if (sc->sc_tdma) 1642 ath_tdma_config(sc, NULL); 1643 else 1644#endif 1645 ath_beacon_config(sc, NULL); /* restart beacons */ 1646 } 1647 ath_hal_intrset(ah, sc->sc_imask); 1648 1649 ath_start(ifp); /* restart xmit */ 1650 return 0; 1651} 1652 1653static int 1654ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1655{ 1656 struct ieee80211com *ic = vap->iv_ic; 1657 struct ifnet *ifp = ic->ic_ifp; 1658 struct ath_softc *sc = ifp->if_softc; 1659 struct ath_hal *ah = sc->sc_ah; 1660 1661 switch (cmd) { 1662 case IEEE80211_IOC_TXPOWER: 1663 /* 1664 * If per-packet TPC is enabled, then we have nothing 1665 * to do; otherwise we need to force the global limit. 1666 * All this can happen directly; no need to reset. 1667 */ 1668 if (!ath_hal_gettpc(ah)) 1669 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1670 return 0; 1671 } 1672 return ath_reset(ifp); 1673} 1674 1675static int 1676ath_ff_always(struct ath_txq *txq, struct ath_buf *bf) 1677{ 1678 return 0; 1679} 1680 1681#if 0 1682static int 1683ath_ff_ageflushtestdone(struct ath_txq *txq, struct ath_buf *bf) 1684{ 1685 return (txq->axq_curage - bf->bf_age) < ATH_FF_STAGEMAX; 1686} 1687#endif 1688 1689/* 1690 * Flush FF staging queue. 1691 */ 1692static void 1693ath_ff_stageq_flush(struct ath_softc *sc, struct ath_txq *txq, 1694 int (*ath_ff_flushdonetest)(struct ath_txq *txq, struct ath_buf *bf)) 1695{ 1696 struct ath_buf *bf; 1697 struct ieee80211_node *ni; 1698 int pktlen, pri; 1699 1700 for (;;) { 1701 ATH_TXQ_LOCK(txq); 1702 /* 1703 * Go from the back (oldest) to front so we can 1704 * stop early based on the age of the entry. 1705 */ 1706 bf = TAILQ_LAST(&txq->axq_stageq, axq_headtype); 1707 if (bf == NULL || ath_ff_flushdonetest(txq, bf)) { 1708 ATH_TXQ_UNLOCK(txq); 1709 break; 1710 } 1711 1712 ni = bf->bf_node; 1713 pri = M_WME_GETAC(bf->bf_m); 1714 KASSERT(ATH_NODE(ni)->an_ff_buf[pri], 1715 ("no bf on staging queue %p", bf)); 1716 ATH_NODE(ni)->an_ff_buf[pri] = NULL; 1717 TAILQ_REMOVE(&txq->axq_stageq, bf, bf_stagelist); 1718 1719 ATH_TXQ_UNLOCK(txq); 1720 1721 DPRINTF(sc, ATH_DEBUG_FF, "%s: flush frame, age %u\n", 1722 __func__, bf->bf_age); 1723 1724 sc->sc_stats.ast_ff_flush++; 1725 1726 /* encap and xmit */ 1727 bf->bf_m = ieee80211_encap(ni, bf->bf_m); 1728 if (bf->bf_m == NULL) { 1729 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1730 "%s: discard, encapsulation failure\n", 1731 __func__); 1732 sc->sc_stats.ast_tx_encap++; 1733 goto bad; 1734 } 1735 pktlen = bf->bf_m->m_pkthdr.len; /* NB: don't reference below */ 1736 if (ath_tx_start(sc, ni, bf, bf->bf_m) == 0) { 1737#if 0 /*XXX*/ 1738 ifp->if_opackets++; 1739#endif 1740 continue; 1741 } 1742 bad: 1743 if (ni != NULL) 1744 ieee80211_free_node(ni); 1745 bf->bf_node = NULL; 1746 if (bf->bf_m != NULL) { 1747 m_freem(bf->bf_m); 1748 bf->bf_m = NULL; 1749 } 1750 1751 ATH_TXBUF_LOCK(sc); 1752 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1753 ATH_TXBUF_UNLOCK(sc); 1754 } 1755} 1756 1757static __inline u_int32_t 1758ath_ff_approx_txtime(struct ath_softc *sc, struct ath_node *an, struct mbuf *m) 1759{ 1760 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1761 u_int32_t framelen; 1762 struct ath_buf *bf; 1763 1764 /* 1765 * Approximate the frame length to be transmitted. A swag to add 1766 * the following maximal values to the skb payload: 1767 * - 32: 802.11 encap + CRC 1768 * - 24: encryption overhead (if wep bit) 1769 * - 4 + 6: fast-frame header and padding 1770 * - 16: 2 LLC FF tunnel headers 1771 * - 14: 1 802.3 FF tunnel header (skb already accounts for 2nd) 1772 */ 1773 framelen = m->m_pkthdr.len + 32 + 4 + 6 + 16 + 14; 1774 if (ic->ic_flags & IEEE80211_F_PRIVACY) 1775 framelen += 24; 1776 bf = an->an_ff_buf[M_WME_GETAC(m)]; 1777 if (bf != NULL) 1778 framelen += bf->bf_m->m_pkthdr.len; 1779 return ath_hal_computetxtime(sc->sc_ah, sc->sc_currates, framelen, 1780 sc->sc_lastdatarix, AH_FALSE); 1781} 1782 1783/* 1784 * Determine if a data frame may be aggregated via ff tunnelling. 1785 * Note the caller is responsible for checking if the destination 1786 * supports fast frames. 1787 * 1788 * NB: allowing EAPOL frames to be aggregated with other unicast traffic. 1789 * Do 802.1x EAPOL frames proceed in the clear? Then they couldn't 1790 * be aggregated with other types of frames when encryption is on? 1791 * 1792 * NB: assumes lock on an_ff_buf effectively held by txq lock mechanism. 1793 */ 1794static __inline int 1795ath_ff_can_aggregate(struct ath_softc *sc, 1796 struct ath_node *an, struct mbuf *m, int *flushq) 1797{ 1798 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1799 struct ath_txq *txq; 1800 u_int32_t txoplimit; 1801 u_int pri; 1802 1803 *flushq = 0; 1804 1805 /* 1806 * If there is no frame to combine with and the txq has 1807 * fewer frames than the minimum required; then do not 1808 * attempt to aggregate this frame. 1809 */ 1810 pri = M_WME_GETAC(m); 1811 txq = sc->sc_ac2q[pri]; 1812 if (an->an_ff_buf[pri] == NULL && txq->axq_depth < sc->sc_fftxqmin) 1813 return 0; 1814 /* 1815 * When not in station mode never aggregate a multicast 1816 * frame; this insures, for example, that a combined frame 1817 * does not require multiple encryption keys when using 1818 * 802.1x/WPA. 1819 */ 1820 if (ic->ic_opmode != IEEE80211_M_STA && 1821 ETHER_IS_MULTICAST(mtod(m, struct ether_header *)->ether_dhost)) 1822 return 0; 1823 /* 1824 * Consult the max bursting interval to insure a combined 1825 * frame fits within the TxOp window. 1826 */ 1827 txoplimit = IEEE80211_TXOP_TO_US( 1828 ic->ic_wme.wme_chanParams.cap_wmeParams[pri].wmep_txopLimit); 1829 if (txoplimit != 0 && ath_ff_approx_txtime(sc, an, m) > txoplimit) { 1830 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1831 "%s: FF TxOp violation\n", __func__); 1832 if (an->an_ff_buf[pri] != NULL) 1833 *flushq = 1; 1834 return 0; 1835 } 1836 return 1; /* try to aggregate */ 1837} 1838 1839/* 1840 * Check if the supplied frame can be partnered with an existing 1841 * or pending frame. Return a reference to any frame that should be 1842 * sent on return; otherwise return NULL. 1843 */ 1844static struct mbuf * 1845ath_ff_check(struct ath_softc *sc, struct ath_txq *txq, 1846 struct ath_buf *bf, struct mbuf *m, struct ieee80211_node *ni) 1847{ 1848 struct ath_node *an = ATH_NODE(ni); 1849 struct ath_buf *bfstaged; 1850 int ff_flush, pri; 1851 1852 /* 1853 * Check if the supplied frame can be aggregated. 1854 * 1855 * NB: we use the txq lock to protect references to 1856 * an->an_ff_txbuf in ath_ff_can_aggregate(). 1857 */ 1858 ATH_TXQ_LOCK(txq); 1859 pri = M_WME_GETAC(m); 1860 if (ath_ff_can_aggregate(sc, an, m, &ff_flush)) { 1861 struct ath_buf *bfstaged = an->an_ff_buf[pri]; 1862 if (bfstaged != NULL) { 1863 /* 1864 * A frame is available for partnering; remove 1865 * it, chain it to this one, and encapsulate. 1866 */ 1867 an->an_ff_buf[pri] = NULL; 1868 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1869 ATH_TXQ_UNLOCK(txq); 1870 1871 /* 1872 * Chain mbufs and add FF magic. 1873 */ 1874 DPRINTF(sc, ATH_DEBUG_FF, 1875 "[%s] aggregate fast-frame, age %u\n", 1876 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1877 m->m_nextpkt = NULL; 1878 bfstaged->bf_m->m_nextpkt = m; 1879 m = bfstaged->bf_m; 1880 bfstaged->bf_m = NULL; 1881 m->m_flags |= M_FF; 1882 /* 1883 * Release the node reference held while 1884 * the packet sat on an_ff_buf[] 1885 */ 1886 bfstaged->bf_node = NULL; 1887 ieee80211_free_node(ni); 1888 1889 /* 1890 * Return bfstaged to the free list. 1891 */ 1892 ATH_TXBUF_LOCK(sc); 1893 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bfstaged, bf_list); 1894 ATH_TXBUF_UNLOCK(sc); 1895 1896 return m; /* ready to go */ 1897 } else { 1898 /* 1899 * No frame available, queue this frame to wait 1900 * for a partner. Note that we hold the buffer 1901 * and a reference to the node; we need the 1902 * buffer in particular so we're certain we 1903 * can flush the frame at a later time. 1904 */ 1905 DPRINTF(sc, ATH_DEBUG_FF, 1906 "[%s] stage fast-frame, age %u\n", 1907 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1908 1909 bf->bf_m = m; 1910 bf->bf_node = ni; /* NB: held reference */ 1911 bf->bf_age = txq->axq_curage; 1912 an->an_ff_buf[pri] = bf; 1913 TAILQ_INSERT_HEAD(&txq->axq_stageq, bf, bf_stagelist); 1914 ATH_TXQ_UNLOCK(txq); 1915 1916 return NULL; /* consumed */ 1917 } 1918 } 1919 /* 1920 * Frame could not be aggregated, it needs to be returned 1921 * to the caller for immediate transmission. In addition 1922 * we check if we should first flush a frame from the 1923 * staging queue before sending this one. 1924 * 1925 * NB: ath_ff_can_aggregate only marks ff_flush if a frame 1926 * is present to flush. 1927 */ 1928 if (ff_flush) { 1929 int pktlen; 1930 1931 bfstaged = an->an_ff_buf[pri]; 1932 an->an_ff_buf[pri] = NULL; 1933 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1934 ATH_TXQ_UNLOCK(txq); 1935 1936 DPRINTF(sc, ATH_DEBUG_FF, "[%s] flush staged frame\n", 1937 ether_sprintf(an->an_node.ni_macaddr)); 1938 1939 /* encap and xmit */ 1940 bfstaged->bf_m = ieee80211_encap(ni, bfstaged->bf_m); 1941 if (bfstaged->bf_m == NULL) { 1942 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1943 "%s: discard, encap failure\n", __func__); 1944 sc->sc_stats.ast_tx_encap++; 1945 goto ff_flushbad; 1946 } 1947 pktlen = bfstaged->bf_m->m_pkthdr.len; 1948 if (ath_tx_start(sc, ni, bfstaged, bfstaged->bf_m)) { 1949 DPRINTF(sc, ATH_DEBUG_XMIT, 1950 "%s: discard, xmit failure\n", __func__); 1951 ff_flushbad: 1952 /* 1953 * Unable to transmit frame that was on the staging 1954 * queue. Reclaim the node reference and other 1955 * resources. 1956 */ 1957 if (ni != NULL) 1958 ieee80211_free_node(ni); 1959 bfstaged->bf_node = NULL; 1960 if (bfstaged->bf_m != NULL) { 1961 m_freem(bfstaged->bf_m); 1962 bfstaged->bf_m = NULL; 1963 } 1964 1965 ATH_TXBUF_LOCK(sc); 1966 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bfstaged, bf_list); 1967 ATH_TXBUF_UNLOCK(sc); 1968 } else { 1969#if 0 1970 ifp->if_opackets++; 1971#endif 1972 } 1973 } else { 1974 if (an->an_ff_buf[pri] != NULL) { 1975 /* 1976 * XXX: out-of-order condition only occurs for AP 1977 * mode and multicast. There may be no valid way 1978 * to get this condition. 1979 */ 1980 DPRINTF(sc, ATH_DEBUG_FF, "[%s] out-of-order frame\n", 1981 ether_sprintf(an->an_node.ni_macaddr)); 1982 /* XXX stat */ 1983 } 1984 ATH_TXQ_UNLOCK(txq); 1985 } 1986 return m; 1987} 1988 1989static struct ath_buf * 1990_ath_getbuf_locked(struct ath_softc *sc) 1991{ 1992 struct ath_buf *bf; 1993 1994 ATH_TXBUF_LOCK_ASSERT(sc); 1995 1996 bf = STAILQ_FIRST(&sc->sc_txbuf); 1997 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1998 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1999 else 2000 bf = NULL; 2001 if (bf == NULL) { 2002 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 2003 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 2004 "out of xmit buffers" : "xmit buffer busy"); 2005 sc->sc_stats.ast_tx_nobuf++; 2006 } 2007 return bf; 2008} 2009 2010static struct ath_buf * 2011ath_getbuf(struct ath_softc *sc) 2012{ 2013 struct ath_buf *bf; 2014 2015 ATH_TXBUF_LOCK(sc); 2016 bf = _ath_getbuf_locked(sc); 2017 if (bf == NULL) { 2018 struct ifnet *ifp = sc->sc_ifp; 2019 2020 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 2021 sc->sc_stats.ast_tx_qstop++; 2022 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2023 } 2024 ATH_TXBUF_UNLOCK(sc); 2025 return bf; 2026} 2027 2028/* 2029 * Cleanup driver resources when we run out of buffers 2030 * while processing fragments; return the tx buffers 2031 * allocated and drop node references. 2032 */ 2033static void 2034ath_txfrag_cleanup(struct ath_softc *sc, 2035 ath_bufhead *frags, struct ieee80211_node *ni) 2036{ 2037 struct ath_buf *bf, *next; 2038 2039 ATH_TXBUF_LOCK_ASSERT(sc); 2040 2041 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 2042 /* NB: bf assumed clean */ 2043 STAILQ_REMOVE_HEAD(frags, bf_list); 2044 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2045 ieee80211_node_decref(ni); 2046 } 2047} 2048 2049/* 2050 * Setup xmit of a fragmented frame. Allocate a buffer 2051 * for each frag and bump the node reference count to 2052 * reflect the held reference to be setup by ath_tx_start. 2053 */ 2054static int 2055ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 2056 struct mbuf *m0, struct ieee80211_node *ni) 2057{ 2058 struct mbuf *m; 2059 struct ath_buf *bf; 2060 2061 ATH_TXBUF_LOCK(sc); 2062 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 2063 bf = _ath_getbuf_locked(sc); 2064 if (bf == NULL) { /* out of buffers, cleanup */ 2065 ath_txfrag_cleanup(sc, frags, ni); 2066 break; 2067 } 2068 ieee80211_node_incref(ni); 2069 STAILQ_INSERT_TAIL(frags, bf, bf_list); 2070 } 2071 ATH_TXBUF_UNLOCK(sc); 2072 2073 return !STAILQ_EMPTY(frags); 2074} 2075 2076static void 2077ath_start(struct ifnet *ifp) 2078{ 2079 struct ath_softc *sc = ifp->if_softc; 2080 struct ieee80211_node *ni; 2081 struct ath_buf *bf; 2082 struct mbuf *m, *next; 2083 struct ath_txq *txq; 2084 ath_bufhead frags; 2085 int pri; 2086 2087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 2088 return; 2089 for (;;) { 2090 /* 2091 * Grab a TX buffer and associated resources. 2092 */ 2093 bf = ath_getbuf(sc); 2094 if (bf == NULL) 2095 break; 2096 2097 IFQ_DEQUEUE(&ifp->if_snd, m); 2098 if (m == NULL) { 2099 ATH_TXBUF_LOCK(sc); 2100 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2101 ATH_TXBUF_UNLOCK(sc); 2102 break; 2103 } 2104 STAILQ_INIT(&frags); 2105 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 2106 pri = M_WME_GETAC(m); 2107 txq = sc->sc_ac2q[pri]; 2108 if (IEEE80211_ATH_CAP(ni->ni_vap, ni, IEEE80211_NODE_FF)) { 2109 /* 2110 * Check queue length; if too deep drop this 2111 * frame (tail drop considered good). 2112 */ 2113 if (txq->axq_depth >= sc->sc_fftxqmax) { 2114 DPRINTF(sc, ATH_DEBUG_FF, 2115 "[%s] tail drop on q %u depth %u\n", 2116 ether_sprintf(ni->ni_macaddr), 2117 txq->axq_qnum, txq->axq_depth); 2118 sc->sc_stats.ast_tx_qfull++; 2119 m_freem(m); 2120 goto reclaim; 2121 } 2122 m = ath_ff_check(sc, txq, bf, m, ni); 2123 if (m == NULL) { 2124 /* NB: ni ref & bf held on stageq */ 2125 continue; 2126 } 2127 } 2128 ifp->if_opackets++; 2129 /* 2130 * Encapsulate the packet in prep for transmission. 2131 */ 2132 m = ieee80211_encap(ni, m); 2133 if (m == NULL) { 2134 DPRINTF(sc, ATH_DEBUG_XMIT, 2135 "%s: encapsulation failure\n", __func__); 2136 sc->sc_stats.ast_tx_encap++; 2137 goto bad; 2138 } 2139 /* 2140 * Check for fragmentation. If this frame 2141 * has been broken up verify we have enough 2142 * buffers to send all the fragments so all 2143 * go out or none... 2144 */ 2145 if ((m->m_flags & M_FRAG) && 2146 !ath_txfrag_setup(sc, &frags, m, ni)) { 2147 DPRINTF(sc, ATH_DEBUG_XMIT, 2148 "%s: out of txfrag buffers\n", __func__); 2149 sc->sc_stats.ast_tx_nofrag++; 2150 ath_freetx(m); 2151 goto bad; 2152 } 2153 nextfrag: 2154 /* 2155 * Pass the frame to the h/w for transmission. 2156 * Fragmented frames have each frag chained together 2157 * with m_nextpkt. We know there are sufficient ath_buf's 2158 * to send all the frags because of work done by 2159 * ath_txfrag_setup. We leave m_nextpkt set while 2160 * calling ath_tx_start so it can use it to extend the 2161 * the tx duration to cover the subsequent frag and 2162 * so it can reclaim all the mbufs in case of an error; 2163 * ath_tx_start clears m_nextpkt once it commits to 2164 * handing the frame to the hardware. 2165 */ 2166 next = m->m_nextpkt; 2167 if (ath_tx_start(sc, ni, bf, m)) { 2168 bad: 2169 ifp->if_oerrors++; 2170 reclaim: 2171 bf->bf_m = NULL; 2172 bf->bf_node = NULL; 2173 ATH_TXBUF_LOCK(sc); 2174 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2175 ath_txfrag_cleanup(sc, &frags, ni); 2176 ATH_TXBUF_UNLOCK(sc); 2177 if (ni != NULL) 2178 ieee80211_free_node(ni); 2179 continue; 2180 } 2181 if (next != NULL) { 2182 /* 2183 * Beware of state changing between frags. 2184 * XXX check sta power-save state? 2185 */ 2186 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2187 DPRINTF(sc, ATH_DEBUG_XMIT, 2188 "%s: flush fragmented packet, state %s\n", 2189 __func__, 2190 ieee80211_state_name[ni->ni_vap->iv_state]); 2191 ath_freetx(next); 2192 goto reclaim; 2193 } 2194 m = next; 2195 bf = STAILQ_FIRST(&frags); 2196 KASSERT(bf != NULL, ("no buf for txfrag")); 2197 STAILQ_REMOVE_HEAD(&frags, bf_list); 2198 goto nextfrag; 2199 } 2200 2201 sc->sc_wd_timer = 5; 2202#if 0 2203 /* 2204 * Flush stale frames from the fast-frame staging queue. 2205 */ 2206 if (ic->ic_opmode != IEEE80211_M_STA) 2207 ath_ff_stageq_flush(sc, txq, ath_ff_ageflushtestdone); 2208#endif 2209 } 2210} 2211 2212static int 2213ath_media_change(struct ifnet *ifp) 2214{ 2215 int error = ieee80211_media_change(ifp); 2216 /* NB: only the fixed rate can change and that doesn't need a reset */ 2217 return (error == ENETRESET ? 0 : error); 2218} 2219 2220#ifdef ATH_DEBUG 2221static void 2222ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 2223 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2224{ 2225 static const char *ciphers[] = { 2226 "WEP", 2227 "AES-OCB", 2228 "AES-CCM", 2229 "CKIP", 2230 "TKIP", 2231 "CLR", 2232 }; 2233 int i, n; 2234 2235 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 2236 for (i = 0, n = hk->kv_len; i < n; i++) 2237 printf("%02x", hk->kv_val[i]); 2238 printf(" mac %s", ether_sprintf(mac)); 2239 if (hk->kv_type == HAL_CIPHER_TKIP) { 2240 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 2241 for (i = 0; i < sizeof(hk->kv_mic); i++) 2242 printf("%02x", hk->kv_mic[i]); 2243 if (!sc->sc_splitmic) { 2244 printf(" txmic "); 2245 for (i = 0; i < sizeof(hk->kv_txmic); i++) 2246 printf("%02x", hk->kv_txmic[i]); 2247 } 2248 } 2249 printf("\n"); 2250} 2251#endif 2252 2253/* 2254 * Set a TKIP key into the hardware. This handles the 2255 * potential distribution of key state to multiple key 2256 * cache slots for TKIP. 2257 */ 2258static int 2259ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 2260 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2261{ 2262#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 2263 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 2264 struct ath_hal *ah = sc->sc_ah; 2265 2266 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 2267 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 2268 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 2269 if (sc->sc_splitmic) { 2270 /* 2271 * TX key goes at first index, RX key at the rx index. 2272 * The hal handles the MIC keys at index+64. 2273 */ 2274 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 2275 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 2276 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 2277 return 0; 2278 2279 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2280 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 2281 /* XXX delete tx key on failure? */ 2282 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 2283 } else { 2284 /* 2285 * Room for both TX+RX MIC keys in one key cache 2286 * slot, just set key at the first index; the hal 2287 * will handle the rest. 2288 */ 2289 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2290 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2291 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2292 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2293 } 2294 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 2295 if (sc->sc_splitmic) { 2296 /* 2297 * NB: must pass MIC key in expected location when 2298 * the keycache only holds one MIC key per entry. 2299 */ 2300 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 2301 } else 2302 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2303 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2304 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2305 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 2306 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2307 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2308 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2309 } 2310 return 0; 2311#undef IEEE80211_KEY_XR 2312} 2313 2314/* 2315 * Set a net80211 key into the hardware. This handles the 2316 * potential distribution of key state to multiple key 2317 * cache slots for TKIP with hardware MIC support. 2318 */ 2319static int 2320ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2321 struct ieee80211_node *bss) 2322{ 2323#define N(a) (sizeof(a)/sizeof(a[0])) 2324 static const u_int8_t ciphermap[] = { 2325 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2326 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2327 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2328 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2329 (u_int8_t) -1, /* 4 is not allocated */ 2330 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2331 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2332 }; 2333 struct ath_hal *ah = sc->sc_ah; 2334 const struct ieee80211_cipher *cip = k->wk_cipher; 2335 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2336 const u_int8_t *mac; 2337 HAL_KEYVAL hk; 2338 2339 memset(&hk, 0, sizeof(hk)); 2340 /* 2341 * Software crypto uses a "clear key" so non-crypto 2342 * state kept in the key cache are maintained and 2343 * so that rx frames have an entry to match. 2344 */ 2345 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2346 KASSERT(cip->ic_cipher < N(ciphermap), 2347 ("invalid cipher type %u", cip->ic_cipher)); 2348 hk.kv_type = ciphermap[cip->ic_cipher]; 2349 hk.kv_len = k->wk_keylen; 2350 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2351 } else 2352 hk.kv_type = HAL_CIPHER_CLR; 2353 2354 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2355 /* 2356 * Group keys on hardware that supports multicast frame 2357 * key search use a mac that is the sender's address with 2358 * the high bit set instead of the app-specified address. 2359 */ 2360 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2361 gmac[0] |= 0x80; 2362 mac = gmac; 2363 } else 2364 mac = k->wk_macaddr; 2365 2366 if (hk.kv_type == HAL_CIPHER_TKIP && 2367 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2368 return ath_keyset_tkip(sc, k, &hk, mac); 2369 } else { 2370 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2371 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2372 } 2373#undef N 2374} 2375 2376/* 2377 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2378 * each key, one for decrypt/encrypt and the other for the MIC. 2379 */ 2380static u_int16_t 2381key_alloc_2pair(struct ath_softc *sc, 2382 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2383{ 2384#define N(a) (sizeof(a)/sizeof(a[0])) 2385 u_int i, keyix; 2386 2387 KASSERT(sc->sc_splitmic, ("key cache !split")); 2388 /* XXX could optimize */ 2389 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2390 u_int8_t b = sc->sc_keymap[i]; 2391 if (b != 0xff) { 2392 /* 2393 * One or more slots in this byte are free. 2394 */ 2395 keyix = i*NBBY; 2396 while (b & 1) { 2397 again: 2398 keyix++; 2399 b >>= 1; 2400 } 2401 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2402 if (isset(sc->sc_keymap, keyix+32) || 2403 isset(sc->sc_keymap, keyix+64) || 2404 isset(sc->sc_keymap, keyix+32+64)) { 2405 /* full pair unavailable */ 2406 /* XXX statistic */ 2407 if (keyix == (i+1)*NBBY) { 2408 /* no slots were appropriate, advance */ 2409 continue; 2410 } 2411 goto again; 2412 } 2413 setbit(sc->sc_keymap, keyix); 2414 setbit(sc->sc_keymap, keyix+64); 2415 setbit(sc->sc_keymap, keyix+32); 2416 setbit(sc->sc_keymap, keyix+32+64); 2417 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2418 "%s: key pair %u,%u %u,%u\n", 2419 __func__, keyix, keyix+64, 2420 keyix+32, keyix+32+64); 2421 *txkeyix = keyix; 2422 *rxkeyix = keyix+32; 2423 return 1; 2424 } 2425 } 2426 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2427 return 0; 2428#undef N 2429} 2430 2431/* 2432 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2433 * each key, one for decrypt/encrypt and the other for the MIC. 2434 */ 2435static u_int16_t 2436key_alloc_pair(struct ath_softc *sc, 2437 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2438{ 2439#define N(a) (sizeof(a)/sizeof(a[0])) 2440 u_int i, keyix; 2441 2442 KASSERT(!sc->sc_splitmic, ("key cache split")); 2443 /* XXX could optimize */ 2444 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2445 u_int8_t b = sc->sc_keymap[i]; 2446 if (b != 0xff) { 2447 /* 2448 * One or more slots in this byte are free. 2449 */ 2450 keyix = i*NBBY; 2451 while (b & 1) { 2452 again: 2453 keyix++; 2454 b >>= 1; 2455 } 2456 if (isset(sc->sc_keymap, keyix+64)) { 2457 /* full pair unavailable */ 2458 /* XXX statistic */ 2459 if (keyix == (i+1)*NBBY) { 2460 /* no slots were appropriate, advance */ 2461 continue; 2462 } 2463 goto again; 2464 } 2465 setbit(sc->sc_keymap, keyix); 2466 setbit(sc->sc_keymap, keyix+64); 2467 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2468 "%s: key pair %u,%u\n", 2469 __func__, keyix, keyix+64); 2470 *txkeyix = *rxkeyix = keyix; 2471 return 1; 2472 } 2473 } 2474 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2475 return 0; 2476#undef N 2477} 2478 2479/* 2480 * Allocate a single key cache slot. 2481 */ 2482static int 2483key_alloc_single(struct ath_softc *sc, 2484 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2485{ 2486#define N(a) (sizeof(a)/sizeof(a[0])) 2487 u_int i, keyix; 2488 2489 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2490 for (i = 0; i < N(sc->sc_keymap); i++) { 2491 u_int8_t b = sc->sc_keymap[i]; 2492 if (b != 0xff) { 2493 /* 2494 * One or more slots are free. 2495 */ 2496 keyix = i*NBBY; 2497 while (b & 1) 2498 keyix++, b >>= 1; 2499 setbit(sc->sc_keymap, keyix); 2500 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2501 __func__, keyix); 2502 *txkeyix = *rxkeyix = keyix; 2503 return 1; 2504 } 2505 } 2506 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2507 return 0; 2508#undef N 2509} 2510 2511/* 2512 * Allocate one or more key cache slots for a uniacst key. The 2513 * key itself is needed only to identify the cipher. For hardware 2514 * TKIP with split cipher+MIC keys we allocate two key cache slot 2515 * pairs so that we can setup separate TX and RX MIC keys. Note 2516 * that the MIC key for a TKIP key at slot i is assumed by the 2517 * hardware to be at slot i+64. This limits TKIP keys to the first 2518 * 64 entries. 2519 */ 2520static int 2521ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2522 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2523{ 2524 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2525 2526 /* 2527 * Group key allocation must be handled specially for 2528 * parts that do not support multicast key cache search 2529 * functionality. For those parts the key id must match 2530 * the h/w key index so lookups find the right key. On 2531 * parts w/ the key search facility we install the sender's 2532 * mac address (with the high bit set) and let the hardware 2533 * find the key w/o using the key id. This is preferred as 2534 * it permits us to support multiple users for adhoc and/or 2535 * multi-station operation. 2536 */ 2537 if (k->wk_keyix != IEEE80211_KEYIX_NONE || /* global key */ 2538 ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey)) { 2539 if (!(&vap->iv_nw_keys[0] <= k && 2540 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2541 /* should not happen */ 2542 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2543 "%s: bogus group key\n", __func__); 2544 return 0; 2545 } 2546 /* 2547 * XXX we pre-allocate the global keys so 2548 * have no way to check if they've already been allocated. 2549 */ 2550 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2551 return 1; 2552 } 2553 2554 /* 2555 * We allocate two pair for TKIP when using the h/w to do 2556 * the MIC. For everything else, including software crypto, 2557 * we allocate a single entry. Note that s/w crypto requires 2558 * a pass-through slot on the 5211 and 5212. The 5210 does 2559 * not support pass-through cache entries and we map all 2560 * those requests to slot 0. 2561 */ 2562 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2563 return key_alloc_single(sc, keyix, rxkeyix); 2564 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2565 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2566 if (sc->sc_splitmic) 2567 return key_alloc_2pair(sc, keyix, rxkeyix); 2568 else 2569 return key_alloc_pair(sc, keyix, rxkeyix); 2570 } else { 2571 return key_alloc_single(sc, keyix, rxkeyix); 2572 } 2573} 2574 2575/* 2576 * Delete an entry in the key cache allocated by ath_key_alloc. 2577 */ 2578static int 2579ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2580{ 2581 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2582 struct ath_hal *ah = sc->sc_ah; 2583 const struct ieee80211_cipher *cip = k->wk_cipher; 2584 u_int keyix = k->wk_keyix; 2585 2586 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2587 2588 ath_hal_keyreset(ah, keyix); 2589 /* 2590 * Handle split tx/rx keying required for TKIP with h/w MIC. 2591 */ 2592 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2593 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2594 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2595 if (keyix >= IEEE80211_WEP_NKID) { 2596 /* 2597 * Don't touch keymap entries for global keys so 2598 * they are never considered for dynamic allocation. 2599 */ 2600 clrbit(sc->sc_keymap, keyix); 2601 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2602 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2603 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2604 if (sc->sc_splitmic) { 2605 /* +32 for RX key, +32+64 for RX key MIC */ 2606 clrbit(sc->sc_keymap, keyix+32); 2607 clrbit(sc->sc_keymap, keyix+32+64); 2608 } 2609 } 2610 } 2611 return 1; 2612} 2613 2614/* 2615 * Set the key cache contents for the specified key. Key cache 2616 * slot(s) must already have been allocated by ath_key_alloc. 2617 */ 2618static int 2619ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2620 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2621{ 2622 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2623 2624 return ath_keyset(sc, k, vap->iv_bss); 2625} 2626 2627/* 2628 * Block/unblock tx+rx processing while a key change is done. 2629 * We assume the caller serializes key management operations 2630 * so we only need to worry about synchronization with other 2631 * uses that originate in the driver. 2632 */ 2633static void 2634ath_key_update_begin(struct ieee80211vap *vap) 2635{ 2636 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2637 struct ath_softc *sc = ifp->if_softc; 2638 2639 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2640 taskqueue_block(sc->sc_tq); 2641 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2642} 2643 2644static void 2645ath_key_update_end(struct ieee80211vap *vap) 2646{ 2647 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2648 struct ath_softc *sc = ifp->if_softc; 2649 2650 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2651 IF_UNLOCK(&ifp->if_snd); 2652 taskqueue_unblock(sc->sc_tq); 2653} 2654 2655/* 2656 * Calculate the receive filter according to the 2657 * operating mode and state: 2658 * 2659 * o always accept unicast, broadcast, and multicast traffic 2660 * o accept PHY error frames when hardware doesn't have MIB support 2661 * to count and we need them for ANI (sta mode only until recently) 2662 * and we are not scanning (ANI is disabled) 2663 * NB: older hal's add rx filter bits out of sight and we need to 2664 * blindly preserve them 2665 * o probe request frames are accepted only when operating in 2666 * hostap, adhoc, or monitor modes 2667 * o enable promiscuous mode 2668 * - when in monitor mode 2669 * - if interface marked PROMISC (assumes bridge setting is filtered) 2670 * o accept beacons: 2671 * - when operating in station mode for collecting rssi data when 2672 * the station is otherwise quiet, or 2673 * - when operating in adhoc mode so the 802.11 layer creates 2674 * node table entries for peers, 2675 * - when scanning 2676 * - when doing s/w beacon miss (e.g. for ap+sta) 2677 * - when operating in ap mode in 11g to detect overlapping bss that 2678 * require protection 2679 * o accept control frames: 2680 * - when in monitor mode 2681 * XXX BAR frames for 11n 2682 * XXX HT protection for 11n 2683 */ 2684static u_int32_t 2685ath_calcrxfilter(struct ath_softc *sc) 2686{ 2687 struct ifnet *ifp = sc->sc_ifp; 2688 struct ieee80211com *ic = ifp->if_l2com; 2689 u_int32_t rfilt; 2690 2691 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2692#if HAL_ABI_VERSION < 0x08011600 2693 rfilt |= (ath_hal_getrxfilter(sc->sc_ah) & 2694 (HAL_RX_FILTER_PHYRADAR | HAL_RX_FILTER_PHYERR)); 2695#elif HAL_ABI_VERSION < 0x08060100 2696 if (ic->ic_opmode == IEEE80211_M_STA && 2697 !sc->sc_needmib && !sc->sc_scanning) 2698 rfilt |= HAL_RX_FILTER_PHYERR; 2699#else 2700 if (!sc->sc_needmib && !sc->sc_scanning) 2701 rfilt |= HAL_RX_FILTER_PHYERR; 2702#endif 2703 if (ic->ic_opmode != IEEE80211_M_STA) 2704 rfilt |= HAL_RX_FILTER_PROBEREQ; 2705 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2706 rfilt |= HAL_RX_FILTER_PROM; 2707 if (ic->ic_opmode == IEEE80211_M_STA || 2708 ic->ic_opmode == IEEE80211_M_IBSS || 2709 sc->sc_swbmiss || sc->sc_scanning) 2710 rfilt |= HAL_RX_FILTER_BEACON; 2711 /* 2712 * NB: We don't recalculate the rx filter when 2713 * ic_protmode changes; otherwise we could do 2714 * this only when ic_protmode != NONE. 2715 */ 2716 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2717 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2718 rfilt |= HAL_RX_FILTER_BEACON; 2719 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2720 rfilt |= HAL_RX_FILTER_CONTROL; 2721 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2722 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2723 return rfilt; 2724} 2725 2726static void 2727ath_update_promisc(struct ifnet *ifp) 2728{ 2729 struct ath_softc *sc = ifp->if_softc; 2730 u_int32_t rfilt; 2731 2732 /* configure rx filter */ 2733 rfilt = ath_calcrxfilter(sc); 2734 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2735 2736 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2737} 2738 2739static void 2740ath_update_mcast(struct ifnet *ifp) 2741{ 2742 struct ath_softc *sc = ifp->if_softc; 2743 u_int32_t mfilt[2]; 2744 2745 /* calculate and install multicast filter */ 2746 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2747 struct ifmultiaddr *ifma; 2748 /* 2749 * Merge multicast addresses to form the hardware filter. 2750 */ 2751 mfilt[0] = mfilt[1] = 0; 2752 IF_ADDR_LOCK(ifp); /* XXX need some fiddling to remove? */ 2753 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2754 caddr_t dl; 2755 u_int32_t val; 2756 u_int8_t pos; 2757 2758 /* calculate XOR of eight 6bit values */ 2759 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2760 val = LE_READ_4(dl + 0); 2761 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2762 val = LE_READ_4(dl + 3); 2763 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2764 pos &= 0x3f; 2765 mfilt[pos / 32] |= (1 << (pos % 32)); 2766 } 2767 IF_ADDR_UNLOCK(ifp); 2768 } else 2769 mfilt[0] = mfilt[1] = ~0; 2770 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2771 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2772 __func__, mfilt[0], mfilt[1]); 2773} 2774 2775static void 2776ath_mode_init(struct ath_softc *sc) 2777{ 2778 struct ifnet *ifp = sc->sc_ifp; 2779 struct ieee80211com *ic = ifp->if_l2com; 2780 struct ath_hal *ah = sc->sc_ah; 2781 u_int32_t rfilt; 2782 2783 /* configure rx filter */ 2784 rfilt = ath_calcrxfilter(sc); 2785 ath_hal_setrxfilter(ah, rfilt); 2786 2787 /* configure operational mode */ 2788 ath_hal_setopmode(ah); 2789 2790 /* 2791 * Handle any link-level address change. Note that we only 2792 * need to force ic_myaddr; any other addresses are handled 2793 * as a byproduct of the ifnet code marking the interface 2794 * down then up. 2795 * 2796 * XXX should get from lladdr instead of arpcom but that's more work 2797 */ 2798 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2799 ath_hal_setmac(ah, ic->ic_myaddr); 2800 2801 /* calculate and install multicast filter */ 2802 ath_update_mcast(ifp); 2803} 2804 2805/* 2806 * Set the slot time based on the current setting. 2807 */ 2808static void 2809ath_setslottime(struct ath_softc *sc) 2810{ 2811 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2812 struct ath_hal *ah = sc->sc_ah; 2813 u_int usec; 2814 2815 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2816 usec = 13; 2817 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2818 usec = 21; 2819 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2820 /* honor short/long slot time only in 11g */ 2821 /* XXX shouldn't honor on pure g or turbo g channel */ 2822 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2823 usec = HAL_SLOT_TIME_9; 2824 else 2825 usec = HAL_SLOT_TIME_20; 2826 } else 2827 usec = HAL_SLOT_TIME_9; 2828 2829 DPRINTF(sc, ATH_DEBUG_RESET, 2830 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2831 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2832 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2833 2834 ath_hal_setslottime(ah, usec); 2835 sc->sc_updateslot = OK; 2836} 2837 2838/* 2839 * Callback from the 802.11 layer to update the 2840 * slot time based on the current setting. 2841 */ 2842static void 2843ath_updateslot(struct ifnet *ifp) 2844{ 2845 struct ath_softc *sc = ifp->if_softc; 2846 struct ieee80211com *ic = ifp->if_l2com; 2847 2848 /* 2849 * When not coordinating the BSS, change the hardware 2850 * immediately. For other operation we defer the change 2851 * until beacon updates have propagated to the stations. 2852 */ 2853 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2854 sc->sc_updateslot = UPDATE; 2855 else 2856 ath_setslottime(sc); 2857} 2858 2859/* 2860 * Setup a h/w transmit queue for beacons. 2861 */ 2862static int 2863ath_beaconq_setup(struct ath_hal *ah) 2864{ 2865 HAL_TXQ_INFO qi; 2866 2867 memset(&qi, 0, sizeof(qi)); 2868 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2869 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2870 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2871 /* NB: for dynamic turbo, don't enable any other interrupts */ 2872 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2873 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2874} 2875 2876/* 2877 * Setup the transmit queue parameters for the beacon queue. 2878 */ 2879static int 2880ath_beaconq_config(struct ath_softc *sc) 2881{ 2882#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2883 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2884 struct ath_hal *ah = sc->sc_ah; 2885 HAL_TXQ_INFO qi; 2886 2887 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2888 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2889 /* 2890 * Always burst out beacon and CAB traffic. 2891 */ 2892 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2893 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2894 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2895 } else { 2896 struct wmeParams *wmep = 2897 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2898 /* 2899 * Adhoc mode; important thing is to use 2x cwmin. 2900 */ 2901 qi.tqi_aifs = wmep->wmep_aifsn; 2902 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2903 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2904 } 2905 2906 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2907 device_printf(sc->sc_dev, "unable to update parameters for " 2908 "beacon hardware queue!\n"); 2909 return 0; 2910 } else { 2911 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2912 return 1; 2913 } 2914#undef ATH_EXPONENT_TO_VALUE 2915} 2916 2917/* 2918 * Allocate and setup an initial beacon frame. 2919 */ 2920static int 2921ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2922{ 2923 struct ieee80211vap *vap = ni->ni_vap; 2924 struct ath_vap *avp = ATH_VAP(vap); 2925 struct ath_buf *bf; 2926 struct mbuf *m; 2927 int error; 2928 2929 bf = avp->av_bcbuf; 2930 if (bf->bf_m != NULL) { 2931 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2932 m_freem(bf->bf_m); 2933 bf->bf_m = NULL; 2934 } 2935 if (bf->bf_node != NULL) { 2936 ieee80211_free_node(bf->bf_node); 2937 bf->bf_node = NULL; 2938 } 2939 2940 /* 2941 * NB: the beacon data buffer must be 32-bit aligned; 2942 * we assume the mbuf routines will return us something 2943 * with this alignment (perhaps should assert). 2944 */ 2945 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2946 if (m == NULL) { 2947 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2948 sc->sc_stats.ast_be_nombuf++; 2949 return ENOMEM; 2950 } 2951 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2952 bf->bf_segs, &bf->bf_nseg, 2953 BUS_DMA_NOWAIT); 2954 if (error != 0) { 2955 device_printf(sc->sc_dev, 2956 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2957 __func__, error); 2958 m_freem(m); 2959 return error; 2960 } 2961 2962 /* 2963 * Calculate a TSF adjustment factor required for staggered 2964 * beacons. Note that we assume the format of the beacon 2965 * frame leaves the tstamp field immediately following the 2966 * header. 2967 */ 2968 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2969 uint64_t tsfadjust; 2970 struct ieee80211_frame *wh; 2971 2972 /* 2973 * The beacon interval is in TU's; the TSF is in usecs. 2974 * We figure out how many TU's to add to align the timestamp 2975 * then convert to TSF units and handle byte swapping before 2976 * inserting it in the frame. The hardware will then add this 2977 * each time a beacon frame is sent. Note that we align vap's 2978 * 1..N and leave vap 0 untouched. This means vap 0 has a 2979 * timestamp in one beacon interval while the others get a 2980 * timstamp aligned to the next interval. 2981 */ 2982 tsfadjust = ni->ni_intval * 2983 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2984 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2985 2986 DPRINTF(sc, ATH_DEBUG_BEACON, 2987 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2988 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2989 avp->av_bslot, ni->ni_intval, 2990 (long long unsigned) le64toh(tsfadjust)); 2991 2992 wh = mtod(m, struct ieee80211_frame *); 2993 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2994 } 2995 bf->bf_m = m; 2996 bf->bf_node = ieee80211_ref_node(ni); 2997 2998 return 0; 2999} 3000 3001/* 3002 * Setup the beacon frame for transmit. 3003 */ 3004static void 3005ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 3006{ 3007#define USE_SHPREAMBLE(_ic) \ 3008 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 3009 == IEEE80211_F_SHPREAMBLE) 3010 struct ieee80211_node *ni = bf->bf_node; 3011 struct ieee80211com *ic = ni->ni_ic; 3012 struct mbuf *m = bf->bf_m; 3013 struct ath_hal *ah = sc->sc_ah; 3014 struct ath_desc *ds; 3015 int flags, antenna; 3016 const HAL_RATE_TABLE *rt; 3017 u_int8_t rix, rate; 3018 3019 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 3020 __func__, m, m->m_len); 3021 3022 /* setup descriptors */ 3023 ds = bf->bf_desc; 3024 3025 flags = HAL_TXDESC_NOACK; 3026 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 3027 ds->ds_link = bf->bf_daddr; /* self-linked */ 3028 flags |= HAL_TXDESC_VEOL; 3029 /* 3030 * Let hardware handle antenna switching. 3031 */ 3032 antenna = sc->sc_txantenna; 3033 } else { 3034 ds->ds_link = 0; 3035 /* 3036 * Switch antenna every 4 beacons. 3037 * XXX assumes two antenna 3038 */ 3039 if (sc->sc_txantenna != 0) 3040 antenna = sc->sc_txantenna; 3041 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 3042 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 3043 else 3044 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 3045 } 3046 3047 KASSERT(bf->bf_nseg == 1, 3048 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 3049 ds->ds_data = bf->bf_segs[0].ds_addr; 3050 /* 3051 * Calculate rate code. 3052 * XXX everything at min xmit rate 3053 */ 3054 rix = 0; 3055 rt = sc->sc_currates; 3056 rate = rt->info[rix].rateCode; 3057 if (USE_SHPREAMBLE(ic)) 3058 rate |= rt->info[rix].shortPreamble; 3059 ath_hal_setuptxdesc(ah, ds 3060 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 3061 , sizeof(struct ieee80211_frame)/* header length */ 3062 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 3063 , ni->ni_txpower /* txpower XXX */ 3064 , rate, 1 /* series 0 rate/tries */ 3065 , HAL_TXKEYIX_INVALID /* no encryption */ 3066 , antenna /* antenna mode */ 3067 , flags /* no ack, veol for beacons */ 3068 , 0 /* rts/cts rate */ 3069 , 0 /* rts/cts duration */ 3070 ); 3071 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 3072 ath_hal_filltxdesc(ah, ds 3073 , roundup(m->m_len, 4) /* buffer length */ 3074 , AH_TRUE /* first segment */ 3075 , AH_TRUE /* last segment */ 3076 , ds /* first descriptor */ 3077 ); 3078#if 0 3079 ath_desc_swap(ds); 3080#endif 3081#undef USE_SHPREAMBLE 3082} 3083 3084static void 3085ath_beacon_update(struct ieee80211vap *vap, int item) 3086{ 3087 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 3088 3089 setbit(bo->bo_flags, item); 3090} 3091 3092/* 3093 * Append the contents of src to dst; both queues 3094 * are assumed to be locked. 3095 */ 3096static void 3097ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 3098{ 3099 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 3100 dst->axq_link = src->axq_link; 3101 src->axq_link = NULL; 3102 dst->axq_depth += src->axq_depth; 3103 src->axq_depth = 0; 3104} 3105 3106/* 3107 * Transmit a beacon frame at SWBA. Dynamic updates to the 3108 * frame contents are done as needed and the slot time is 3109 * also adjusted based on current state. 3110 */ 3111static void 3112ath_beacon_proc(void *arg, int pending) 3113{ 3114 struct ath_softc *sc = arg; 3115 struct ath_hal *ah = sc->sc_ah; 3116 struct ieee80211vap *vap; 3117 struct ath_buf *bf; 3118 int slot, otherant; 3119 uint32_t bfaddr; 3120 3121 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 3122 __func__, pending); 3123 /* 3124 * Check if the previous beacon has gone out. If 3125 * not don't try to post another, skip this period 3126 * and wait for the next. Missed beacons indicate 3127 * a problem and should not occur. If we miss too 3128 * many consecutive beacons reset the device. 3129 */ 3130 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 3131 sc->sc_bmisscount++; 3132 DPRINTF(sc, ATH_DEBUG_BEACON, 3133 "%s: missed %u consecutive beacons\n", 3134 __func__, sc->sc_bmisscount); 3135 if (sc->sc_bmisscount >= ath_bstuck_threshold) 3136 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 3137 return; 3138 } 3139 if (sc->sc_bmisscount != 0) { 3140 DPRINTF(sc, ATH_DEBUG_BEACON, 3141 "%s: resume beacon xmit after %u misses\n", 3142 __func__, sc->sc_bmisscount); 3143 sc->sc_bmisscount = 0; 3144 } 3145 3146 if (sc->sc_stagbeacons) { /* staggered beacons */ 3147 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3148 uint32_t tsftu; 3149 3150 tsftu = ath_hal_gettsf32(ah) >> 10; 3151 /* XXX lintval */ 3152 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 3153 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 3154 bfaddr = 0; 3155 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 3156 bf = ath_beacon_generate(sc, vap); 3157 if (bf != NULL) 3158 bfaddr = bf->bf_daddr; 3159 } 3160 } else { /* burst'd beacons */ 3161 uint32_t *bflink = &bfaddr; 3162 3163 for (slot = 0; slot < ATH_BCBUF; slot++) { 3164 vap = sc->sc_bslot[slot]; 3165 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 3166 bf = ath_beacon_generate(sc, vap); 3167 if (bf != NULL) { 3168 *bflink = bf->bf_daddr; 3169 bflink = &bf->bf_desc->ds_link; 3170 } 3171 } 3172 } 3173 *bflink = 0; /* terminate list */ 3174 } 3175 3176 /* 3177 * Handle slot time change when a non-ERP station joins/leaves 3178 * an 11g network. The 802.11 layer notifies us via callback, 3179 * we mark updateslot, then wait one beacon before effecting 3180 * the change. This gives associated stations at least one 3181 * beacon interval to note the state change. 3182 */ 3183 /* XXX locking */ 3184 if (sc->sc_updateslot == UPDATE) { 3185 sc->sc_updateslot = COMMIT; /* commit next beacon */ 3186 sc->sc_slotupdate = slot; 3187 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 3188 ath_setslottime(sc); /* commit change to h/w */ 3189 3190 /* 3191 * Check recent per-antenna transmit statistics and flip 3192 * the default antenna if noticeably more frames went out 3193 * on the non-default antenna. 3194 * XXX assumes 2 anntenae 3195 */ 3196 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 3197 otherant = sc->sc_defant & 1 ? 2 : 1; 3198 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 3199 ath_setdefantenna(sc, otherant); 3200 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 3201 } 3202 3203 if (bfaddr != 0) { 3204 /* 3205 * Stop any current dma and put the new frame on the queue. 3206 * This should never fail since we check above that no frames 3207 * are still pending on the queue. 3208 */ 3209 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 3210 DPRINTF(sc, ATH_DEBUG_ANY, 3211 "%s: beacon queue %u did not stop?\n", 3212 __func__, sc->sc_bhalq); 3213 } 3214 /* NB: cabq traffic should already be queued and primed */ 3215 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 3216 ath_hal_txstart(ah, sc->sc_bhalq); 3217 3218 sc->sc_stats.ast_be_xmit++; 3219 } 3220} 3221 3222static struct ath_buf * 3223ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 3224{ 3225 struct ath_vap *avp = ATH_VAP(vap); 3226 struct ath_txq *cabq = sc->sc_cabq; 3227 struct ath_buf *bf; 3228 struct mbuf *m; 3229 int nmcastq, error; 3230 3231 KASSERT(vap->iv_state == IEEE80211_S_RUN, 3232 ("not running, state %d", vap->iv_state)); 3233 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3234 3235 /* 3236 * Update dynamic beacon contents. If this returns 3237 * non-zero then we need to remap the memory because 3238 * the beacon frame changed size (probably because 3239 * of the TIM bitmap). 3240 */ 3241 bf = avp->av_bcbuf; 3242 m = bf->bf_m; 3243 nmcastq = avp->av_mcastq.axq_depth; 3244 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 3245 /* XXX too conservative? */ 3246 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3247 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3248 bf->bf_segs, &bf->bf_nseg, 3249 BUS_DMA_NOWAIT); 3250 if (error != 0) { 3251 if_printf(vap->iv_ifp, 3252 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3253 __func__, error); 3254 return NULL; 3255 } 3256 } 3257 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 3258 DPRINTF(sc, ATH_DEBUG_BEACON, 3259 "%s: cabq did not drain, mcastq %u cabq %u\n", 3260 __func__, nmcastq, cabq->axq_depth); 3261 sc->sc_stats.ast_cabq_busy++; 3262 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 3263 /* 3264 * CABQ traffic from a previous vap is still pending. 3265 * We must drain the q before this beacon frame goes 3266 * out as otherwise this vap's stations will get cab 3267 * frames from a different vap. 3268 * XXX could be slow causing us to miss DBA 3269 */ 3270 ath_tx_draintxq(sc, cabq); 3271 } 3272 } 3273 ath_beacon_setup(sc, bf); 3274 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3275 3276 /* 3277 * Enable the CAB queue before the beacon queue to 3278 * insure cab frames are triggered by this beacon. 3279 */ 3280 if (avp->av_boff.bo_tim[4] & 1) { 3281 struct ath_hal *ah = sc->sc_ah; 3282 3283 /* NB: only at DTIM */ 3284 ATH_TXQ_LOCK(cabq); 3285 ATH_TXQ_LOCK(&avp->av_mcastq); 3286 if (nmcastq) { 3287 struct ath_buf *bfm; 3288 3289 /* 3290 * Move frames from the s/w mcast q to the h/w cab q. 3291 * XXX MORE_DATA bit 3292 */ 3293 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 3294 if (cabq->axq_link != NULL) { 3295 *cabq->axq_link = bfm->bf_daddr; 3296 } else 3297 ath_hal_puttxbuf(ah, cabq->axq_qnum, 3298 bfm->bf_daddr); 3299 ath_txqmove(cabq, &avp->av_mcastq); 3300 3301 sc->sc_stats.ast_cabq_xmit += nmcastq; 3302 } 3303 /* NB: gated by beacon so safe to start here */ 3304 ath_hal_txstart(ah, cabq->axq_qnum); 3305 ATH_TXQ_UNLOCK(cabq); 3306 ATH_TXQ_UNLOCK(&avp->av_mcastq); 3307 } 3308 return bf; 3309} 3310 3311static void 3312ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3313{ 3314 struct ath_vap *avp = ATH_VAP(vap); 3315 struct ath_hal *ah = sc->sc_ah; 3316 struct ath_buf *bf; 3317 struct mbuf *m; 3318 int error; 3319 3320 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3321 3322 /* 3323 * Update dynamic beacon contents. If this returns 3324 * non-zero then we need to remap the memory because 3325 * the beacon frame changed size (probably because 3326 * of the TIM bitmap). 3327 */ 3328 bf = avp->av_bcbuf; 3329 m = bf->bf_m; 3330 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3331 /* XXX too conservative? */ 3332 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3333 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3334 bf->bf_segs, &bf->bf_nseg, 3335 BUS_DMA_NOWAIT); 3336 if (error != 0) { 3337 if_printf(vap->iv_ifp, 3338 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3339 __func__, error); 3340 return; 3341 } 3342 } 3343 ath_beacon_setup(sc, bf); 3344 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3345 3346 /* NB: caller is known to have already stopped tx dma */ 3347 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3348 ath_hal_txstart(ah, sc->sc_bhalq); 3349} 3350 3351/* 3352 * Reset the hardware after detecting beacons have stopped. 3353 */ 3354static void 3355ath_bstuck_proc(void *arg, int pending) 3356{ 3357 struct ath_softc *sc = arg; 3358 struct ifnet *ifp = sc->sc_ifp; 3359 3360 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3361 sc->sc_bmisscount); 3362 sc->sc_stats.ast_bstuck++; 3363 ath_reset(ifp); 3364} 3365 3366/* 3367 * Reclaim beacon resources and return buffer to the pool. 3368 */ 3369static void 3370ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3371{ 3372 3373 if (bf->bf_m != NULL) { 3374 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3375 m_freem(bf->bf_m); 3376 bf->bf_m = NULL; 3377 } 3378 if (bf->bf_node != NULL) { 3379 ieee80211_free_node(bf->bf_node); 3380 bf->bf_node = NULL; 3381 } 3382 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3383} 3384 3385/* 3386 * Reclaim beacon resources. 3387 */ 3388static void 3389ath_beacon_free(struct ath_softc *sc) 3390{ 3391 struct ath_buf *bf; 3392 3393 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3394 if (bf->bf_m != NULL) { 3395 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3396 m_freem(bf->bf_m); 3397 bf->bf_m = NULL; 3398 } 3399 if (bf->bf_node != NULL) { 3400 ieee80211_free_node(bf->bf_node); 3401 bf->bf_node = NULL; 3402 } 3403 } 3404} 3405 3406/* 3407 * Configure the beacon and sleep timers. 3408 * 3409 * When operating as an AP this resets the TSF and sets 3410 * up the hardware to notify us when we need to issue beacons. 3411 * 3412 * When operating in station mode this sets up the beacon 3413 * timers according to the timestamp of the last received 3414 * beacon and the current TSF, configures PCF and DTIM 3415 * handling, programs the sleep registers so the hardware 3416 * will wakeup in time to receive beacons, and configures 3417 * the beacon miss handling so we'll receive a BMISS 3418 * interrupt when we stop seeing beacons from the AP 3419 * we've associated with. 3420 */ 3421static void 3422ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3423{ 3424#define TSF_TO_TU(_h,_l) \ 3425 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3426#define FUDGE 2 3427 struct ath_hal *ah = sc->sc_ah; 3428 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3429 struct ieee80211_node *ni; 3430 u_int32_t nexttbtt, intval, tsftu; 3431 u_int64_t tsf; 3432 3433 if (vap == NULL) 3434 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3435 ni = vap->iv_bss; 3436 3437 /* extract tstamp from last beacon and convert to TU */ 3438 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3439 LE_READ_4(ni->ni_tstamp.data)); 3440 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3441 /* 3442 * For multi-bss ap support beacons are either staggered 3443 * evenly over N slots or burst together. For the former 3444 * arrange for the SWBA to be delivered for each slot. 3445 * Slots that are not occupied will generate nothing. 3446 */ 3447 /* NB: the beacon interval is kept internally in TU's */ 3448 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3449 if (sc->sc_stagbeacons) 3450 intval /= ATH_BCBUF; 3451 } else { 3452 /* NB: the beacon interval is kept internally in TU's */ 3453 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3454 } 3455 if (nexttbtt == 0) /* e.g. for ap mode */ 3456 nexttbtt = intval; 3457 else if (intval) /* NB: can be 0 for monitor mode */ 3458 nexttbtt = roundup(nexttbtt, intval); 3459 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3460 __func__, nexttbtt, intval, ni->ni_intval); 3461 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3462 HAL_BEACON_STATE bs; 3463 int dtimperiod, dtimcount; 3464 int cfpperiod, cfpcount; 3465 3466 /* 3467 * Setup dtim and cfp parameters according to 3468 * last beacon we received (which may be none). 3469 */ 3470 dtimperiod = ni->ni_dtim_period; 3471 if (dtimperiod <= 0) /* NB: 0 if not known */ 3472 dtimperiod = 1; 3473 dtimcount = ni->ni_dtim_count; 3474 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3475 dtimcount = 0; /* XXX? */ 3476 cfpperiod = 1; /* NB: no PCF support yet */ 3477 cfpcount = 0; 3478 /* 3479 * Pull nexttbtt forward to reflect the current 3480 * TSF and calculate dtim+cfp state for the result. 3481 */ 3482 tsf = ath_hal_gettsf64(ah); 3483 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3484 do { 3485 nexttbtt += intval; 3486 if (--dtimcount < 0) { 3487 dtimcount = dtimperiod - 1; 3488 if (--cfpcount < 0) 3489 cfpcount = cfpperiod - 1; 3490 } 3491 } while (nexttbtt < tsftu); 3492 memset(&bs, 0, sizeof(bs)); 3493 bs.bs_intval = intval; 3494 bs.bs_nexttbtt = nexttbtt; 3495 bs.bs_dtimperiod = dtimperiod*intval; 3496 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3497 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3498 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3499 bs.bs_cfpmaxduration = 0; 3500#if 0 3501 /* 3502 * The 802.11 layer records the offset to the DTIM 3503 * bitmap while receiving beacons; use it here to 3504 * enable h/w detection of our AID being marked in 3505 * the bitmap vector (to indicate frames for us are 3506 * pending at the AP). 3507 * XXX do DTIM handling in s/w to WAR old h/w bugs 3508 * XXX enable based on h/w rev for newer chips 3509 */ 3510 bs.bs_timoffset = ni->ni_timoff; 3511#endif 3512 /* 3513 * Calculate the number of consecutive beacons to miss 3514 * before taking a BMISS interrupt. 3515 * Note that we clamp the result to at most 10 beacons. 3516 */ 3517 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3518 if (bs.bs_bmissthreshold > 10) 3519 bs.bs_bmissthreshold = 10; 3520 else if (bs.bs_bmissthreshold <= 0) 3521 bs.bs_bmissthreshold = 1; 3522 3523 /* 3524 * Calculate sleep duration. The configuration is 3525 * given in ms. We insure a multiple of the beacon 3526 * period is used. Also, if the sleep duration is 3527 * greater than the DTIM period then it makes senses 3528 * to make it a multiple of that. 3529 * 3530 * XXX fixed at 100ms 3531 */ 3532 bs.bs_sleepduration = 3533 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3534 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3535 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3536 3537 DPRINTF(sc, ATH_DEBUG_BEACON, 3538 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3539 , __func__ 3540 , tsf, tsftu 3541 , bs.bs_intval 3542 , bs.bs_nexttbtt 3543 , bs.bs_dtimperiod 3544 , bs.bs_nextdtim 3545 , bs.bs_bmissthreshold 3546 , bs.bs_sleepduration 3547 , bs.bs_cfpperiod 3548 , bs.bs_cfpmaxduration 3549 , bs.bs_cfpnext 3550 , bs.bs_timoffset 3551 ); 3552 ath_hal_intrset(ah, 0); 3553 ath_hal_beacontimers(ah, &bs); 3554 sc->sc_imask |= HAL_INT_BMISS; 3555 ath_hal_intrset(ah, sc->sc_imask); 3556 } else { 3557 ath_hal_intrset(ah, 0); 3558 if (nexttbtt == intval) 3559 intval |= HAL_BEACON_RESET_TSF; 3560 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3561 /* 3562 * In IBSS mode enable the beacon timers but only 3563 * enable SWBA interrupts if we need to manually 3564 * prepare beacon frames. Otherwise we use a 3565 * self-linked tx descriptor and let the hardware 3566 * deal with things. 3567 */ 3568 intval |= HAL_BEACON_ENA; 3569 if (!sc->sc_hasveol) 3570 sc->sc_imask |= HAL_INT_SWBA; 3571 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3572 /* 3573 * Pull nexttbtt forward to reflect 3574 * the current TSF. 3575 */ 3576 tsf = ath_hal_gettsf64(ah); 3577 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3578 do { 3579 nexttbtt += intval; 3580 } while (nexttbtt < tsftu); 3581 } 3582 ath_beaconq_config(sc); 3583 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3584 /* 3585 * In AP mode we enable the beacon timers and 3586 * SWBA interrupts to prepare beacon frames. 3587 */ 3588 intval |= HAL_BEACON_ENA; 3589 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3590 ath_beaconq_config(sc); 3591 } 3592 ath_hal_beaconinit(ah, nexttbtt, intval); 3593 sc->sc_bmisscount = 0; 3594 ath_hal_intrset(ah, sc->sc_imask); 3595 /* 3596 * When using a self-linked beacon descriptor in 3597 * ibss mode load it once here. 3598 */ 3599 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3600 ath_beacon_start_adhoc(sc, vap); 3601 } 3602 sc->sc_syncbeacon = 0; 3603#undef FUDGE 3604#undef TSF_TO_TU 3605} 3606 3607static void 3608ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3609{ 3610 bus_addr_t *paddr = (bus_addr_t*) arg; 3611 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3612 *paddr = segs->ds_addr; 3613} 3614 3615static int 3616ath_descdma_setup(struct ath_softc *sc, 3617 struct ath_descdma *dd, ath_bufhead *head, 3618 const char *name, int nbuf, int ndesc) 3619{ 3620#define DS2PHYS(_dd, _ds) \ 3621 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3622 struct ifnet *ifp = sc->sc_ifp; 3623 struct ath_desc *ds; 3624 struct ath_buf *bf; 3625 int i, bsize, error; 3626 3627 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3628 __func__, name, nbuf, ndesc); 3629 3630 dd->dd_name = name; 3631 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3632 3633 /* 3634 * Setup DMA descriptor area. 3635 */ 3636 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3637 PAGE_SIZE, 0, /* alignment, bounds */ 3638 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3639 BUS_SPACE_MAXADDR, /* highaddr */ 3640 NULL, NULL, /* filter, filterarg */ 3641 dd->dd_desc_len, /* maxsize */ 3642 1, /* nsegments */ 3643 dd->dd_desc_len, /* maxsegsize */ 3644 BUS_DMA_ALLOCNOW, /* flags */ 3645 NULL, /* lockfunc */ 3646 NULL, /* lockarg */ 3647 &dd->dd_dmat); 3648 if (error != 0) { 3649 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3650 return error; 3651 } 3652 3653 /* allocate descriptors */ 3654 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3655 if (error != 0) { 3656 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3657 "error %u\n", dd->dd_name, error); 3658 goto fail0; 3659 } 3660 3661 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3662 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3663 &dd->dd_dmamap); 3664 if (error != 0) { 3665 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3666 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3667 goto fail1; 3668 } 3669 3670 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3671 dd->dd_desc, dd->dd_desc_len, 3672 ath_load_cb, &dd->dd_desc_paddr, 3673 BUS_DMA_NOWAIT); 3674 if (error != 0) { 3675 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3676 dd->dd_name, error); 3677 goto fail2; 3678 } 3679 3680 ds = dd->dd_desc; 3681 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3682 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3683 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3684 3685 /* allocate rx buffers */ 3686 bsize = sizeof(struct ath_buf) * nbuf; 3687 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3688 if (bf == NULL) { 3689 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3690 dd->dd_name, bsize); 3691 goto fail3; 3692 } 3693 dd->dd_bufptr = bf; 3694 3695 STAILQ_INIT(head); 3696 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3697 bf->bf_desc = ds; 3698 bf->bf_daddr = DS2PHYS(dd, ds); 3699 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3700 &bf->bf_dmamap); 3701 if (error != 0) { 3702 if_printf(ifp, "unable to create dmamap for %s " 3703 "buffer %u, error %u\n", dd->dd_name, i, error); 3704 ath_descdma_cleanup(sc, dd, head); 3705 return error; 3706 } 3707 STAILQ_INSERT_TAIL(head, bf, bf_list); 3708 } 3709 return 0; 3710fail3: 3711 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3712fail2: 3713 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3714fail1: 3715 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3716fail0: 3717 bus_dma_tag_destroy(dd->dd_dmat); 3718 memset(dd, 0, sizeof(*dd)); 3719 return error; 3720#undef DS2PHYS 3721} 3722 3723static void 3724ath_descdma_cleanup(struct ath_softc *sc, 3725 struct ath_descdma *dd, ath_bufhead *head) 3726{ 3727 struct ath_buf *bf; 3728 struct ieee80211_node *ni; 3729 3730 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3731 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3732 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3733 bus_dma_tag_destroy(dd->dd_dmat); 3734 3735 STAILQ_FOREACH(bf, head, bf_list) { 3736 if (bf->bf_m) { 3737 m_freem(bf->bf_m); 3738 bf->bf_m = NULL; 3739 } 3740 if (bf->bf_dmamap != NULL) { 3741 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3742 bf->bf_dmamap = NULL; 3743 } 3744 ni = bf->bf_node; 3745 bf->bf_node = NULL; 3746 if (ni != NULL) { 3747 /* 3748 * Reclaim node reference. 3749 */ 3750 ieee80211_free_node(ni); 3751 } 3752 } 3753 3754 STAILQ_INIT(head); 3755 free(dd->dd_bufptr, M_ATHDEV); 3756 memset(dd, 0, sizeof(*dd)); 3757} 3758 3759static int 3760ath_desc_alloc(struct ath_softc *sc) 3761{ 3762 int error; 3763 3764 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3765 "rx", ath_rxbuf, 1); 3766 if (error != 0) 3767 return error; 3768 3769 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3770 "tx", ath_txbuf, ATH_TXDESC); 3771 if (error != 0) { 3772 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3773 return error; 3774 } 3775 3776 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3777 "beacon", ATH_BCBUF, 1); 3778 if (error != 0) { 3779 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3780 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3781 return error; 3782 } 3783 return 0; 3784} 3785 3786static void 3787ath_desc_free(struct ath_softc *sc) 3788{ 3789 3790 if (sc->sc_bdma.dd_desc_len != 0) 3791 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3792 if (sc->sc_txdma.dd_desc_len != 0) 3793 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3794 if (sc->sc_rxdma.dd_desc_len != 0) 3795 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3796} 3797 3798static struct ieee80211_node * 3799ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3800{ 3801 struct ieee80211com *ic = vap->iv_ic; 3802 struct ath_softc *sc = ic->ic_ifp->if_softc; 3803 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3804 struct ath_node *an; 3805 3806 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3807 if (an == NULL) { 3808 /* XXX stat+msg */ 3809 return NULL; 3810 } 3811 ath_rate_node_init(sc, an); 3812 3813 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3814 return &an->an_node; 3815} 3816 3817static void 3818ath_node_free(struct ieee80211_node *ni) 3819{ 3820 struct ieee80211com *ic = ni->ni_ic; 3821 struct ath_softc *sc = ic->ic_ifp->if_softc; 3822 3823 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3824 3825 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3826 sc->sc_node_free(ni); 3827} 3828 3829static void 3830ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3831{ 3832 struct ieee80211com *ic = ni->ni_ic; 3833 struct ath_softc *sc = ic->ic_ifp->if_softc; 3834 struct ath_hal *ah = sc->sc_ah; 3835 3836 *rssi = ic->ic_node_getrssi(ni); 3837 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3838 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3839 else 3840 *noise = -95; /* nominally correct */ 3841} 3842 3843static int 3844ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3845{ 3846 struct ath_hal *ah = sc->sc_ah; 3847 int error; 3848 struct mbuf *m; 3849 struct ath_desc *ds; 3850 3851 m = bf->bf_m; 3852 if (m == NULL) { 3853 /* 3854 * NB: by assigning a page to the rx dma buffer we 3855 * implicitly satisfy the Atheros requirement that 3856 * this buffer be cache-line-aligned and sized to be 3857 * multiple of the cache line size. Not doing this 3858 * causes weird stuff to happen (for the 5210 at least). 3859 */ 3860 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3861 if (m == NULL) { 3862 DPRINTF(sc, ATH_DEBUG_ANY, 3863 "%s: no mbuf/cluster\n", __func__); 3864 sc->sc_stats.ast_rx_nombuf++; 3865 return ENOMEM; 3866 } 3867 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3868 3869 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3870 bf->bf_dmamap, m, 3871 bf->bf_segs, &bf->bf_nseg, 3872 BUS_DMA_NOWAIT); 3873 if (error != 0) { 3874 DPRINTF(sc, ATH_DEBUG_ANY, 3875 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3876 __func__, error); 3877 sc->sc_stats.ast_rx_busdma++; 3878 m_freem(m); 3879 return error; 3880 } 3881 KASSERT(bf->bf_nseg == 1, 3882 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3883 bf->bf_m = m; 3884 } 3885 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3886 3887 /* 3888 * Setup descriptors. For receive we always terminate 3889 * the descriptor list with a self-linked entry so we'll 3890 * not get overrun under high load (as can happen with a 3891 * 5212 when ANI processing enables PHY error frames). 3892 * 3893 * To insure the last descriptor is self-linked we create 3894 * each descriptor as self-linked and add it to the end. As 3895 * each additional descriptor is added the previous self-linked 3896 * entry is ``fixed'' naturally. This should be safe even 3897 * if DMA is happening. When processing RX interrupts we 3898 * never remove/process the last, self-linked, entry on the 3899 * descriptor list. This insures the hardware always has 3900 * someplace to write a new frame. 3901 */ 3902 ds = bf->bf_desc; 3903 ds->ds_link = bf->bf_daddr; /* link to self */ 3904 ds->ds_data = bf->bf_segs[0].ds_addr; 3905 ath_hal_setuprxdesc(ah, ds 3906 , m->m_len /* buffer size */ 3907 , 0 3908 ); 3909 3910 if (sc->sc_rxlink != NULL) 3911 *sc->sc_rxlink = bf->bf_daddr; 3912 sc->sc_rxlink = &ds->ds_link; 3913 return 0; 3914} 3915 3916/* 3917 * Extend 15-bit time stamp from rx descriptor to 3918 * a full 64-bit TSF using the specified TSF. 3919 */ 3920static __inline u_int64_t 3921ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3922{ 3923 if ((tsf & 0x7fff) < rstamp) 3924 tsf -= 0x8000; 3925 return ((tsf &~ 0x7fff) | rstamp); 3926} 3927 3928/* 3929 * Intercept management frames to collect beacon rssi data 3930 * and to do ibss merges. 3931 */ 3932static void 3933ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3934 int subtype, int rssi, int noise, u_int32_t rstamp) 3935{ 3936 struct ieee80211vap *vap = ni->ni_vap; 3937 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3938 3939 /* 3940 * Call up first so subsequent work can use information 3941 * potentially stored in the node (e.g. for ibss merge). 3942 */ 3943 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, noise, rstamp); 3944 switch (subtype) { 3945 case IEEE80211_FC0_SUBTYPE_BEACON: 3946 /* update rssi statistics for use by the hal */ 3947 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3948 if (sc->sc_syncbeacon && 3949 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3950 /* 3951 * Resync beacon timers using the tsf of the beacon 3952 * frame we just received. 3953 */ 3954 ath_beacon_config(sc, vap); 3955 } 3956 /* fall thru... */ 3957 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3958 if (vap->iv_opmode == IEEE80211_M_IBSS && 3959 vap->iv_state == IEEE80211_S_RUN) { 3960 u_int64_t tsf = ath_extend_tsf(rstamp, 3961 ath_hal_gettsf64(sc->sc_ah)); 3962 /* 3963 * Handle ibss merge as needed; check the tsf on the 3964 * frame before attempting the merge. The 802.11 spec 3965 * says the station should change it's bssid to match 3966 * the oldest station with the same ssid, where oldest 3967 * is determined by the tsf. Note that hardware 3968 * reconfiguration happens through callback to 3969 * ath_newstate as the state machine will go from 3970 * RUN -> RUN when this happens. 3971 */ 3972 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3973 DPRINTF(sc, ATH_DEBUG_STATE, 3974 "ibss merge, rstamp %u tsf %ju " 3975 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3976 (uintmax_t)ni->ni_tstamp.tsf); 3977 (void) ieee80211_ibss_merge(ni); 3978 } 3979 } 3980 break; 3981 } 3982} 3983 3984/* 3985 * Set the default antenna. 3986 */ 3987static void 3988ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3989{ 3990 struct ath_hal *ah = sc->sc_ah; 3991 3992 /* XXX block beacon interrupts */ 3993 ath_hal_setdefantenna(ah, antenna); 3994 if (sc->sc_defant != antenna) 3995 sc->sc_stats.ast_ant_defswitch++; 3996 sc->sc_defant = antenna; 3997 sc->sc_rxotherant = 0; 3998} 3999 4000static int 4001ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 4002 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 4003{ 4004#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 4005#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 4006#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 4007#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 4008 struct ath_softc *sc = ifp->if_softc; 4009 const HAL_RATE_TABLE *rt; 4010 uint8_t rix; 4011 4012 /* 4013 * Discard anything shorter than an ack or cts. 4014 */ 4015 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 4016 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 4017 __func__, m->m_pkthdr.len); 4018 sc->sc_stats.ast_rx_tooshort++; 4019 return 0; 4020 } 4021 rt = sc->sc_currates; 4022 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4023 rix = rt->rateCodeToIndex[rs->rs_rate]; 4024 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 4025 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 4026#ifdef AH_SUPPORT_AR5416 4027 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 4028 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 4029 struct ieee80211com *ic = ifp->if_l2com; 4030 4031 if ((rs->rs_flags & HAL_RX_2040) == 0) 4032 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 4033 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 4034 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 4035 else 4036 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 4037 if ((rs->rs_flags & HAL_RX_GI) == 0) 4038 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 4039 } 4040#endif 4041 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 4042 if (rs->rs_status & HAL_RXERR_CRC) 4043 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 4044 /* XXX propagate other error flags from descriptor */ 4045 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf; 4046 sc->sc_rx_th.wr_antnoise = nf; 4047 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 4048 4049 bpf_mtap2(ifp->if_bpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 4050 4051 return 1; 4052#undef CHAN_HT 4053#undef CHAN_HT20 4054#undef CHAN_HT40U 4055#undef CHAN_HT40D 4056} 4057 4058static void 4059ath_handle_micerror(struct ieee80211com *ic, 4060 struct ieee80211_frame *wh, int keyix) 4061{ 4062 struct ieee80211_node *ni; 4063 4064 /* XXX recheck MIC to deal w/ chips that lie */ 4065 /* XXX discard MIC errors on !data frames */ 4066 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 4067 if (ni != NULL) { 4068 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 4069 ieee80211_free_node(ni); 4070 } 4071} 4072 4073static void 4074ath_rx_proc(void *arg, int npending) 4075{ 4076#define PA2DESC(_sc, _pa) \ 4077 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4078 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4079 struct ath_softc *sc = arg; 4080 struct ath_buf *bf; 4081 struct ifnet *ifp = sc->sc_ifp; 4082 struct ieee80211com *ic = ifp->if_l2com; 4083 struct ath_hal *ah = sc->sc_ah; 4084 struct ath_desc *ds; 4085 struct ath_rx_status *rs; 4086 struct mbuf *m; 4087 struct ieee80211_node *ni; 4088 int len, type, ngood; 4089 u_int phyerr; 4090 HAL_STATUS status; 4091 int16_t nf; 4092 u_int64_t tsf; 4093 4094 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 4095 ngood = 0; 4096 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 4097 sc->sc_stats.ast_rx_noise = nf; 4098 tsf = ath_hal_gettsf64(ah); 4099 do { 4100 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4101 if (bf == NULL) { /* NB: shouldn't happen */ 4102 if_printf(ifp, "%s: no buffer!\n", __func__); 4103 break; 4104 } 4105 m = bf->bf_m; 4106 if (m == NULL) { /* NB: shouldn't happen */ 4107 /* 4108 * If mbuf allocation failed previously there 4109 * will be no mbuf; try again to re-populate it. 4110 */ 4111 /* XXX make debug msg */ 4112 if_printf(ifp, "%s: no mbuf!\n", __func__); 4113 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 4114 goto rx_next; 4115 } 4116 ds = bf->bf_desc; 4117 if (ds->ds_link == bf->bf_daddr) { 4118 /* NB: never process the self-linked entry at the end */ 4119 break; 4120 } 4121 /* XXX sync descriptor memory */ 4122 /* 4123 * Must provide the virtual address of the current 4124 * descriptor, the physical address, and the virtual 4125 * address of the next descriptor in the h/w chain. 4126 * This allows the HAL to look ahead to see if the 4127 * hardware is done with a descriptor by checking the 4128 * done bit in the following descriptor and the address 4129 * of the current descriptor the DMA engine is working 4130 * on. All this is necessary because of our use of 4131 * a self-linked list to avoid rx overruns. 4132 */ 4133 rs = &bf->bf_status.ds_rxstat; 4134 status = ath_hal_rxprocdesc(ah, ds, 4135 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 4136#ifdef ATH_DEBUG 4137 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 4138 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 4139#endif 4140 if (status == HAL_EINPROGRESS) 4141 break; 4142 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 4143 if (rs->rs_status != 0) { 4144 if (rs->rs_status & HAL_RXERR_CRC) 4145 sc->sc_stats.ast_rx_crcerr++; 4146 if (rs->rs_status & HAL_RXERR_FIFO) 4147 sc->sc_stats.ast_rx_fifoerr++; 4148 if (rs->rs_status & HAL_RXERR_PHY) { 4149 sc->sc_stats.ast_rx_phyerr++; 4150 phyerr = rs->rs_phyerr & 0x1f; 4151 sc->sc_stats.ast_rx_phy[phyerr]++; 4152 goto rx_error; /* NB: don't count in ierrors */ 4153 } 4154 if (rs->rs_status & HAL_RXERR_DECRYPT) { 4155 /* 4156 * Decrypt error. If the error occurred 4157 * because there was no hardware key, then 4158 * let the frame through so the upper layers 4159 * can process it. This is necessary for 5210 4160 * parts which have no way to setup a ``clear'' 4161 * key cache entry. 4162 * 4163 * XXX do key cache faulting 4164 */ 4165 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 4166 goto rx_accept; 4167 sc->sc_stats.ast_rx_badcrypt++; 4168 } 4169 if (rs->rs_status & HAL_RXERR_MIC) { 4170 sc->sc_stats.ast_rx_badmic++; 4171 /* 4172 * Do minimal work required to hand off 4173 * the 802.11 header for notifcation. 4174 */ 4175 /* XXX frag's and qos frames */ 4176 len = rs->rs_datalen; 4177 if (len >= sizeof (struct ieee80211_frame)) { 4178 bus_dmamap_sync(sc->sc_dmat, 4179 bf->bf_dmamap, 4180 BUS_DMASYNC_POSTREAD); 4181 ath_handle_micerror(ic, 4182 mtod(m, struct ieee80211_frame *), 4183 sc->sc_splitmic ? 4184 rs->rs_keyix-32 : rs->rs_keyix); 4185 } 4186 } 4187 ifp->if_ierrors++; 4188rx_error: 4189 /* 4190 * Cleanup any pending partial frame. 4191 */ 4192 if (sc->sc_rxpending != NULL) { 4193 m_freem(sc->sc_rxpending); 4194 sc->sc_rxpending = NULL; 4195 } 4196 /* 4197 * When a tap is present pass error frames 4198 * that have been requested. By default we 4199 * pass decrypt+mic errors but others may be 4200 * interesting (e.g. crc). 4201 */ 4202 if (bpf_peers_present(ifp->if_bpf) && 4203 (rs->rs_status & sc->sc_monpass)) { 4204 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4205 BUS_DMASYNC_POSTREAD); 4206 /* NB: bpf needs the mbuf length setup */ 4207 len = rs->rs_datalen; 4208 m->m_pkthdr.len = m->m_len = len; 4209 (void) ath_rx_tap(ifp, m, rs, tsf, nf); 4210 } 4211 /* XXX pass MIC errors up for s/w reclaculation */ 4212 goto rx_next; 4213 } 4214rx_accept: 4215 /* 4216 * Sync and unmap the frame. At this point we're 4217 * committed to passing the mbuf somewhere so clear 4218 * bf_m; this means a new mbuf must be allocated 4219 * when the rx descriptor is setup again to receive 4220 * another frame. 4221 */ 4222 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4223 BUS_DMASYNC_POSTREAD); 4224 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4225 bf->bf_m = NULL; 4226 4227 len = rs->rs_datalen; 4228 m->m_len = len; 4229 4230 if (rs->rs_more) { 4231 /* 4232 * Frame spans multiple descriptors; save 4233 * it for the next completed descriptor, it 4234 * will be used to construct a jumbogram. 4235 */ 4236 if (sc->sc_rxpending != NULL) { 4237 /* NB: max frame size is currently 2 clusters */ 4238 sc->sc_stats.ast_rx_toobig++; 4239 m_freem(sc->sc_rxpending); 4240 } 4241 m->m_pkthdr.rcvif = ifp; 4242 m->m_pkthdr.len = len; 4243 sc->sc_rxpending = m; 4244 goto rx_next; 4245 } else if (sc->sc_rxpending != NULL) { 4246 /* 4247 * This is the second part of a jumbogram, 4248 * chain it to the first mbuf, adjust the 4249 * frame length, and clear the rxpending state. 4250 */ 4251 sc->sc_rxpending->m_next = m; 4252 sc->sc_rxpending->m_pkthdr.len += len; 4253 m = sc->sc_rxpending; 4254 sc->sc_rxpending = NULL; 4255 } else { 4256 /* 4257 * Normal single-descriptor receive; setup 4258 * the rcvif and packet length. 4259 */ 4260 m->m_pkthdr.rcvif = ifp; 4261 m->m_pkthdr.len = len; 4262 } 4263 4264 ifp->if_ipackets++; 4265 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 4266 4267 if (bpf_peers_present(ifp->if_bpf) && 4268 !ath_rx_tap(ifp, m, rs, tsf, nf)) { 4269 m_freem(m); /* XXX reclaim */ 4270 goto rx_next; 4271 } 4272 4273 /* 4274 * From this point on we assume the frame is at least 4275 * as large as ieee80211_frame_min; verify that. 4276 */ 4277 if (len < IEEE80211_MIN_LEN) { 4278 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 4279 __func__, len); 4280 sc->sc_stats.ast_rx_tooshort++; 4281 m_freem(m); 4282 goto rx_next; 4283 } 4284 4285 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 4286 const HAL_RATE_TABLE *rt = sc->sc_currates; 4287 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 4288 4289 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 4290 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 4291 } 4292 4293 m_adj(m, -IEEE80211_CRC_LEN); 4294 4295 /* 4296 * Locate the node for sender, track state, and then 4297 * pass the (referenced) node up to the 802.11 layer 4298 * for its use. 4299 */ 4300 ni = ieee80211_find_rxnode_withkey(ic, 4301 mtod(m, const struct ieee80211_frame_min *), 4302 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4303 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4304 if (ni != NULL) { 4305 /* 4306 * Sending station is known, dispatch directly. 4307 */ 4308#ifdef ATH_SUPPORT_TDMA 4309 sc->sc_tdmars = rs; 4310#endif 4311 type = ieee80211_input(ni, m, 4312 rs->rs_rssi, nf, rs->rs_tstamp); 4313 ieee80211_free_node(ni); 4314 /* 4315 * Arrange to update the last rx timestamp only for 4316 * frames from our ap when operating in station mode. 4317 * This assumes the rx key is always setup when 4318 * associated. 4319 */ 4320 if (ic->ic_opmode == IEEE80211_M_STA && 4321 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4322 ngood++; 4323 } else { 4324 type = ieee80211_input_all(ic, m, 4325 rs->rs_rssi, nf, rs->rs_tstamp); 4326 } 4327 /* 4328 * Track rx rssi and do any rx antenna management. 4329 */ 4330 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4331 if (sc->sc_diversity) { 4332 /* 4333 * When using fast diversity, change the default rx 4334 * antenna if diversity chooses the other antenna 3 4335 * times in a row. 4336 */ 4337 if (sc->sc_defant != rs->rs_antenna) { 4338 if (++sc->sc_rxotherant >= 3) 4339 ath_setdefantenna(sc, rs->rs_antenna); 4340 } else 4341 sc->sc_rxotherant = 0; 4342 } 4343 if (sc->sc_softled) { 4344 /* 4345 * Blink for any data frame. Otherwise do a 4346 * heartbeat-style blink when idle. The latter 4347 * is mainly for station mode where we depend on 4348 * periodic beacon frames to trigger the poll event. 4349 */ 4350 if (type == IEEE80211_FC0_TYPE_DATA) { 4351 const HAL_RATE_TABLE *rt = sc->sc_currates; 4352 ath_led_event(sc, 4353 rt->rateCodeToIndex[rs->rs_rate]); 4354 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4355 ath_led_event(sc, 0); 4356 } 4357rx_next: 4358 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4359 } while (ath_rxbuf_init(sc, bf) == 0); 4360 4361 /* rx signal state monitoring */ 4362 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4363 if (ngood) 4364 sc->sc_lastrx = tsf; 4365 4366 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 4367 !IFQ_IS_EMPTY(&ifp->if_snd)) 4368 ath_start(ifp); 4369 4370#undef PA2DESC 4371} 4372 4373static void 4374ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4375{ 4376 txq->axq_qnum = qnum; 4377 txq->axq_depth = 0; 4378 txq->axq_intrcnt = 0; 4379 txq->axq_link = NULL; 4380 STAILQ_INIT(&txq->axq_q); 4381 ATH_TXQ_LOCK_INIT(sc, txq); 4382 TAILQ_INIT(&txq->axq_stageq); 4383 txq->axq_curage = 0; 4384} 4385 4386/* 4387 * Setup a h/w transmit queue. 4388 */ 4389static struct ath_txq * 4390ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4391{ 4392#define N(a) (sizeof(a)/sizeof(a[0])) 4393 struct ath_hal *ah = sc->sc_ah; 4394 HAL_TXQ_INFO qi; 4395 int qnum; 4396 4397 memset(&qi, 0, sizeof(qi)); 4398 qi.tqi_subtype = subtype; 4399 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4400 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4401 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4402 /* 4403 * Enable interrupts only for EOL and DESC conditions. 4404 * We mark tx descriptors to receive a DESC interrupt 4405 * when a tx queue gets deep; otherwise waiting for the 4406 * EOL to reap descriptors. Note that this is done to 4407 * reduce interrupt load and this only defers reaping 4408 * descriptors, never transmitting frames. Aside from 4409 * reducing interrupts this also permits more concurrency. 4410 * The only potential downside is if the tx queue backs 4411 * up in which case the top half of the kernel may backup 4412 * due to a lack of tx descriptors. 4413 */ 4414 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4415 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4416 if (qnum == -1) { 4417 /* 4418 * NB: don't print a message, this happens 4419 * normally on parts with too few tx queues 4420 */ 4421 return NULL; 4422 } 4423 if (qnum >= N(sc->sc_txq)) { 4424 device_printf(sc->sc_dev, 4425 "hal qnum %u out of range, max %zu!\n", 4426 qnum, N(sc->sc_txq)); 4427 ath_hal_releasetxqueue(ah, qnum); 4428 return NULL; 4429 } 4430 if (!ATH_TXQ_SETUP(sc, qnum)) { 4431 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4432 sc->sc_txqsetup |= 1<<qnum; 4433 } 4434 return &sc->sc_txq[qnum]; 4435#undef N 4436} 4437 4438/* 4439 * Setup a hardware data transmit queue for the specified 4440 * access control. The hal may not support all requested 4441 * queues in which case it will return a reference to a 4442 * previously setup queue. We record the mapping from ac's 4443 * to h/w queues for use by ath_tx_start and also track 4444 * the set of h/w queues being used to optimize work in the 4445 * transmit interrupt handler and related routines. 4446 */ 4447static int 4448ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4449{ 4450#define N(a) (sizeof(a)/sizeof(a[0])) 4451 struct ath_txq *txq; 4452 4453 if (ac >= N(sc->sc_ac2q)) { 4454 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4455 ac, N(sc->sc_ac2q)); 4456 return 0; 4457 } 4458 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4459 if (txq != NULL) { 4460 sc->sc_ac2q[ac] = txq; 4461 return 1; 4462 } else 4463 return 0; 4464#undef N 4465} 4466 4467/* 4468 * Update WME parameters for a transmit queue. 4469 */ 4470static int 4471ath_txq_update(struct ath_softc *sc, int ac) 4472{ 4473#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4474#define ATH_TXOP_TO_US(v) (v<<5) 4475 struct ifnet *ifp = sc->sc_ifp; 4476 struct ieee80211com *ic = ifp->if_l2com; 4477 struct ath_txq *txq = sc->sc_ac2q[ac]; 4478 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4479 struct ath_hal *ah = sc->sc_ah; 4480 HAL_TXQ_INFO qi; 4481 4482 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4483#ifdef ATH_SUPPORT_TDMA 4484 if (sc->sc_tdma) { 4485 /* 4486 * AIFS is zero so there's no pre-transmit wait. The 4487 * burst time defines the slot duration and is configured 4488 * via sysctl. The QCU is setup to not do post-xmit 4489 * back off, lockout all lower-priority QCU's, and fire 4490 * off the DMA beacon alert timer which is setup based 4491 * on the slot configuration. 4492 */ 4493 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4494 | HAL_TXQ_TXERRINT_ENABLE 4495 | HAL_TXQ_TXURNINT_ENABLE 4496 | HAL_TXQ_TXEOLINT_ENABLE 4497 | HAL_TXQ_DBA_GATED 4498 | HAL_TXQ_BACKOFF_DISABLE 4499 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4500 ; 4501 qi.tqi_aifs = 0; 4502 /* XXX +dbaprep? */ 4503 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4504 qi.tqi_burstTime = qi.tqi_readyTime; 4505 } else { 4506#endif 4507 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4508 | HAL_TXQ_TXERRINT_ENABLE 4509 | HAL_TXQ_TXDESCINT_ENABLE 4510 | HAL_TXQ_TXURNINT_ENABLE 4511 ; 4512 qi.tqi_aifs = wmep->wmep_aifsn; 4513 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4514 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4515 qi.tqi_readyTime = 0; 4516 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4517#ifdef ATH_SUPPORT_TDMA 4518 } 4519#endif 4520 4521 DPRINTF(sc, ATH_DEBUG_RESET, 4522 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4523 __func__, txq->axq_qnum, qi.tqi_qflags, 4524 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4525 4526 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4527 if_printf(ifp, "unable to update hardware queue " 4528 "parameters for %s traffic!\n", 4529 ieee80211_wme_acnames[ac]); 4530 return 0; 4531 } else { 4532 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4533 return 1; 4534 } 4535#undef ATH_TXOP_TO_US 4536#undef ATH_EXPONENT_TO_VALUE 4537} 4538 4539/* 4540 * Callback from the 802.11 layer to update WME parameters. 4541 */ 4542static int 4543ath_wme_update(struct ieee80211com *ic) 4544{ 4545 struct ath_softc *sc = ic->ic_ifp->if_softc; 4546 4547 return !ath_txq_update(sc, WME_AC_BE) || 4548 !ath_txq_update(sc, WME_AC_BK) || 4549 !ath_txq_update(sc, WME_AC_VI) || 4550 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4551} 4552 4553/* 4554 * Reclaim resources for a setup queue. 4555 */ 4556static void 4557ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4558{ 4559 4560 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4561 ATH_TXQ_LOCK_DESTROY(txq); 4562 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4563} 4564 4565/* 4566 * Reclaim all tx queue resources. 4567 */ 4568static void 4569ath_tx_cleanup(struct ath_softc *sc) 4570{ 4571 int i; 4572 4573 ATH_TXBUF_LOCK_DESTROY(sc); 4574 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4575 if (ATH_TXQ_SETUP(sc, i)) 4576 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4577} 4578 4579/* 4580 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 4581 */ 4582static int 4583ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 4584{ 4585 int i; 4586 4587 for (i = 0; i < rt->rateCount; i++) 4588 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 4589 return i; 4590 return 0; /* NB: lowest rate */ 4591} 4592 4593/* 4594 * Reclaim mbuf resources. For fragmented frames we 4595 * need to claim each frag chained with m_nextpkt. 4596 */ 4597static void 4598ath_freetx(struct mbuf *m) 4599{ 4600 struct mbuf *next; 4601 4602 do { 4603 next = m->m_nextpkt; 4604 m->m_nextpkt = NULL; 4605 m_freem(m); 4606 } while ((m = next) != NULL); 4607} 4608 4609static int 4610ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4611{ 4612 struct mbuf *m; 4613 int error; 4614 4615 /* 4616 * Load the DMA map so any coalescing is done. This 4617 * also calculates the number of descriptors we need. 4618 */ 4619 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4620 bf->bf_segs, &bf->bf_nseg, 4621 BUS_DMA_NOWAIT); 4622 if (error == EFBIG) { 4623 /* XXX packet requires too many descriptors */ 4624 bf->bf_nseg = ATH_TXDESC+1; 4625 } else if (error != 0) { 4626 sc->sc_stats.ast_tx_busdma++; 4627 ath_freetx(m0); 4628 return error; 4629 } 4630 /* 4631 * Discard null packets and check for packets that 4632 * require too many TX descriptors. We try to convert 4633 * the latter to a cluster. 4634 */ 4635 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 4636 sc->sc_stats.ast_tx_linear++; 4637 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 4638 if (m == NULL) { 4639 ath_freetx(m0); 4640 sc->sc_stats.ast_tx_nombuf++; 4641 return ENOMEM; 4642 } 4643 m0 = m; 4644 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4645 bf->bf_segs, &bf->bf_nseg, 4646 BUS_DMA_NOWAIT); 4647 if (error != 0) { 4648 sc->sc_stats.ast_tx_busdma++; 4649 ath_freetx(m0); 4650 return error; 4651 } 4652 KASSERT(bf->bf_nseg <= ATH_TXDESC, 4653 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 4654 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 4655 sc->sc_stats.ast_tx_nodata++; 4656 ath_freetx(m0); 4657 return EIO; 4658 } 4659 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4660 __func__, m0, m0->m_pkthdr.len); 4661 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4662 bf->bf_m = m0; 4663 4664 return 0; 4665} 4666 4667static void 4668ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4669{ 4670 struct ath_hal *ah = sc->sc_ah; 4671 struct ath_desc *ds, *ds0; 4672 int i; 4673 4674 /* 4675 * Fillin the remainder of the descriptor info. 4676 */ 4677 ds0 = ds = bf->bf_desc; 4678 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4679 ds->ds_data = bf->bf_segs[i].ds_addr; 4680 if (i == bf->bf_nseg - 1) 4681 ds->ds_link = 0; 4682 else 4683 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4684 ath_hal_filltxdesc(ah, ds 4685 , bf->bf_segs[i].ds_len /* segment length */ 4686 , i == 0 /* first segment */ 4687 , i == bf->bf_nseg - 1 /* last segment */ 4688 , ds0 /* first descriptor */ 4689 ); 4690 DPRINTF(sc, ATH_DEBUG_XMIT, 4691 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4692 __func__, i, ds->ds_link, ds->ds_data, 4693 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4694 } 4695 /* 4696 * Insert the frame on the outbound list and pass it on 4697 * to the hardware. Multicast frames buffered for power 4698 * save stations and transmit from the CAB queue are stored 4699 * on a s/w only queue and loaded on to the CAB queue in 4700 * the SWBA handler since frames only go out on DTIM and 4701 * to avoid possible races. 4702 */ 4703 ATH_TXQ_LOCK(txq); 4704 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4705 ("busy status 0x%x", bf->bf_flags)); 4706 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4707#ifdef ATH_SUPPORT_TDMA 4708 int qbusy; 4709 4710 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4711 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4712 if (txq->axq_link == NULL) { 4713 /* 4714 * Be careful writing the address to TXDP. If 4715 * the tx q is enabled then this write will be 4716 * ignored. Normally this is not an issue but 4717 * when tdma is in use and the q is beacon gated 4718 * this race can occur. If the q is busy then 4719 * defer the work to later--either when another 4720 * packet comes along or when we prepare a beacon 4721 * frame at SWBA. 4722 */ 4723 if (!qbusy) { 4724 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4725 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 4726 DPRINTF(sc, ATH_DEBUG_XMIT, 4727 "%s: TXDP[%u] = %p (%p) depth %d\n", 4728 __func__, txq->axq_qnum, 4729 (caddr_t)bf->bf_daddr, bf->bf_desc, 4730 txq->axq_depth); 4731 } else { 4732 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4733 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 4734 "%s: Q%u busy, defer enable\n", __func__, 4735 txq->axq_qnum); 4736 } 4737 } else { 4738 *txq->axq_link = bf->bf_daddr; 4739 DPRINTF(sc, ATH_DEBUG_XMIT, 4740 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4741 txq->axq_qnum, txq->axq_link, 4742 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4743 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 4744 /* 4745 * The q was busy when we previously tried 4746 * to write the address of the first buffer 4747 * in the chain. Since it's not busy now 4748 * handle this chore. We are certain the 4749 * buffer at the front is the right one since 4750 * axq_link is NULL only when the buffer list 4751 * is/was empty. 4752 */ 4753 ath_hal_puttxbuf(ah, txq->axq_qnum, 4754 STAILQ_FIRST(&txq->axq_q)->bf_daddr); 4755 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 4756 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 4757 "%s: Q%u restarted\n", __func__, 4758 txq->axq_qnum); 4759 } 4760 } 4761#else 4762 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4763 if (txq->axq_link == NULL) { 4764 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4765 DPRINTF(sc, ATH_DEBUG_XMIT, 4766 "%s: TXDP[%u] = %p (%p) depth %d\n", 4767 __func__, txq->axq_qnum, 4768 (caddr_t)bf->bf_daddr, bf->bf_desc, 4769 txq->axq_depth); 4770 } else { 4771 *txq->axq_link = bf->bf_daddr; 4772 DPRINTF(sc, ATH_DEBUG_XMIT, 4773 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4774 txq->axq_qnum, txq->axq_link, 4775 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4776 } 4777#endif /* ATH_SUPPORT_TDMA */ 4778 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4779 ath_hal_txstart(ah, txq->axq_qnum); 4780 } else { 4781 if (txq->axq_link != NULL) { 4782 struct ath_buf *last = ATH_TXQ_LAST(txq); 4783 struct ieee80211_frame *wh; 4784 4785 /* mark previous frame */ 4786 wh = mtod(last->bf_m, struct ieee80211_frame *); 4787 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4788 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4789 BUS_DMASYNC_PREWRITE); 4790 4791 /* link descriptor */ 4792 *txq->axq_link = bf->bf_daddr; 4793 } 4794 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4795 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4796 } 4797 ATH_TXQ_UNLOCK(txq); 4798} 4799 4800static int 4801ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4802 struct mbuf *m0) 4803{ 4804 struct ieee80211vap *vap = ni->ni_vap; 4805 struct ath_vap *avp = ATH_VAP(vap); 4806 struct ath_hal *ah = sc->sc_ah; 4807 struct ifnet *ifp = sc->sc_ifp; 4808 struct ieee80211com *ic = ifp->if_l2com; 4809 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4810 int error, iswep, ismcast, isfrag, ismrr; 4811 int keyix, hdrlen, pktlen, try0; 4812 u_int8_t rix, txrate, ctsrate; 4813 u_int8_t cix = 0xff; /* NB: silence compiler */ 4814 struct ath_desc *ds; 4815 struct ath_txq *txq; 4816 struct ieee80211_frame *wh; 4817 u_int subtype, flags, ctsduration; 4818 HAL_PKT_TYPE atype; 4819 const HAL_RATE_TABLE *rt; 4820 HAL_BOOL shortPreamble; 4821 struct ath_node *an; 4822 u_int pri; 4823 4824 wh = mtod(m0, struct ieee80211_frame *); 4825 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4826 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4827 isfrag = m0->m_flags & M_FRAG; 4828 hdrlen = ieee80211_anyhdrsize(wh); 4829 /* 4830 * Packet length must not include any 4831 * pad bytes; deduct them here. 4832 */ 4833 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4834 4835 if (iswep) { 4836 const struct ieee80211_cipher *cip; 4837 struct ieee80211_key *k; 4838 4839 /* 4840 * Construct the 802.11 header+trailer for an encrypted 4841 * frame. The only reason this can fail is because of an 4842 * unknown or unsupported cipher/key type. 4843 */ 4844 k = ieee80211_crypto_encap(ni, m0); 4845 if (k == NULL) { 4846 /* 4847 * This can happen when the key is yanked after the 4848 * frame was queued. Just discard the frame; the 4849 * 802.11 layer counts failures and provides 4850 * debugging/diagnostics. 4851 */ 4852 ath_freetx(m0); 4853 return EIO; 4854 } 4855 /* 4856 * Adjust the packet + header lengths for the crypto 4857 * additions and calculate the h/w key index. When 4858 * a s/w mic is done the frame will have had any mic 4859 * added to it prior to entry so m0->m_pkthdr.len will 4860 * account for it. Otherwise we need to add it to the 4861 * packet length. 4862 */ 4863 cip = k->wk_cipher; 4864 hdrlen += cip->ic_header; 4865 pktlen += cip->ic_header + cip->ic_trailer; 4866 /* NB: frags always have any TKIP MIC done in s/w */ 4867 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4868 pktlen += cip->ic_miclen; 4869 keyix = k->wk_keyix; 4870 4871 /* packet header may have moved, reset our local pointer */ 4872 wh = mtod(m0, struct ieee80211_frame *); 4873 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4874 /* 4875 * Use station key cache slot, if assigned. 4876 */ 4877 keyix = ni->ni_ucastkey.wk_keyix; 4878 if (keyix == IEEE80211_KEYIX_NONE) 4879 keyix = HAL_TXKEYIX_INVALID; 4880 } else 4881 keyix = HAL_TXKEYIX_INVALID; 4882 4883 pktlen += IEEE80211_CRC_LEN; 4884 4885 /* 4886 * Load the DMA map so any coalescing is done. This 4887 * also calculates the number of descriptors we need. 4888 */ 4889 error = ath_tx_dmasetup(sc, bf, m0); 4890 if (error != 0) 4891 return error; 4892 bf->bf_node = ni; /* NB: held reference */ 4893 m0 = bf->bf_m; /* NB: may have changed */ 4894 wh = mtod(m0, struct ieee80211_frame *); 4895 4896 /* setup descriptors */ 4897 ds = bf->bf_desc; 4898 rt = sc->sc_currates; 4899 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4900 4901 /* 4902 * NB: the 802.11 layer marks whether or not we should 4903 * use short preamble based on the current mode and 4904 * negotiated parameters. 4905 */ 4906 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4907 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4908 shortPreamble = AH_TRUE; 4909 sc->sc_stats.ast_tx_shortpre++; 4910 } else { 4911 shortPreamble = AH_FALSE; 4912 } 4913 4914 an = ATH_NODE(ni); 4915 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4916 ismrr = 0; /* default no multi-rate retry*/ 4917 pri = M_WME_GETAC(m0); /* honor classification */ 4918 /* XXX use txparams instead of fixed values */ 4919 /* 4920 * Calculate Atheros packet type from IEEE80211 packet header, 4921 * setup for rate calculations, and select h/w transmit queue. 4922 */ 4923 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4924 case IEEE80211_FC0_TYPE_MGT: 4925 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4926 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4927 atype = HAL_PKT_TYPE_BEACON; 4928 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4929 atype = HAL_PKT_TYPE_PROBE_RESP; 4930 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4931 atype = HAL_PKT_TYPE_ATIM; 4932 else 4933 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4934 rix = an->an_mgmtrix; 4935 txrate = rt->info[rix].rateCode; 4936 if (shortPreamble) 4937 txrate |= rt->info[rix].shortPreamble; 4938 try0 = ATH_TXMGTTRY; 4939 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4940 break; 4941 case IEEE80211_FC0_TYPE_CTL: 4942 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4943 rix = an->an_mgmtrix; 4944 txrate = rt->info[rix].rateCode; 4945 if (shortPreamble) 4946 txrate |= rt->info[rix].shortPreamble; 4947 try0 = ATH_TXMGTTRY; 4948 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4949 break; 4950 case IEEE80211_FC0_TYPE_DATA: 4951 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4952 /* 4953 * Data frames: multicast frames go out at a fixed rate, 4954 * EAPOL frames use the mgmt frame rate; otherwise consult 4955 * the rate control module for the rate to use. 4956 */ 4957 if (ismcast) { 4958 rix = an->an_mcastrix; 4959 txrate = rt->info[rix].rateCode; 4960 if (shortPreamble) 4961 txrate |= rt->info[rix].shortPreamble; 4962 try0 = 1; 4963 } else if (m0->m_flags & M_EAPOL) { 4964 /* XXX? maybe always use long preamble? */ 4965 rix = an->an_mgmtrix; 4966 txrate = rt->info[rix].rateCode; 4967 if (shortPreamble) 4968 txrate |= rt->info[rix].shortPreamble; 4969 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4970 } else { 4971 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4972 &rix, &try0, &txrate); 4973 sc->sc_txrix = rix; /* for LED blinking */ 4974 sc->sc_lastdatarix = rix; /* for fast frames */ 4975 if (try0 != ATH_TXMAXTRY) 4976 ismrr = 1; 4977 } 4978 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4979 flags |= HAL_TXDESC_NOACK; 4980 break; 4981 default: 4982 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4983 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4984 /* XXX statistic */ 4985 ath_freetx(m0); 4986 return EIO; 4987 } 4988 txq = sc->sc_ac2q[pri]; 4989 4990 /* 4991 * When servicing one or more stations in power-save mode 4992 * (or) if there is some mcast data waiting on the mcast 4993 * queue (to prevent out of order delivery) multicast 4994 * frames must be buffered until after the beacon. 4995 */ 4996 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4997 txq = &avp->av_mcastq; 4998 4999 /* 5000 * Calculate miscellaneous flags. 5001 */ 5002 if (ismcast) { 5003 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 5004 } else if (pktlen > vap->iv_rtsthreshold && 5005 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 5006 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 5007 cix = rt->info[rix].controlRate; 5008 sc->sc_stats.ast_tx_rts++; 5009 } 5010 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 5011 sc->sc_stats.ast_tx_noack++; 5012#ifdef ATH_SUPPORT_TDMA 5013 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 5014 DPRINTF(sc, ATH_DEBUG_TDMA, 5015 "%s: discard frame, ACK required w/ TDMA\n", __func__); 5016 sc->sc_stats.ast_tdma_ack++; 5017 ath_freetx(m0); 5018 return EIO; 5019 } 5020#endif 5021 5022 /* 5023 * If 802.11g protection is enabled, determine whether 5024 * to use RTS/CTS or just CTS. Note that this is only 5025 * done for OFDM unicast frames. 5026 */ 5027 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 5028 rt->info[rix].phy == IEEE80211_T_OFDM && 5029 (flags & HAL_TXDESC_NOACK) == 0) { 5030 /* XXX fragments must use CCK rates w/ protection */ 5031 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 5032 flags |= HAL_TXDESC_RTSENA; 5033 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 5034 flags |= HAL_TXDESC_CTSENA; 5035 if (isfrag) { 5036 /* 5037 * For frags it would be desirable to use the 5038 * highest CCK rate for RTS/CTS. But stations 5039 * farther away may detect it at a lower CCK rate 5040 * so use the configured protection rate instead 5041 * (for now). 5042 */ 5043 cix = rt->info[sc->sc_protrix].controlRate; 5044 } else 5045 cix = rt->info[sc->sc_protrix].controlRate; 5046 sc->sc_stats.ast_tx_protect++; 5047 } 5048 5049 /* 5050 * Calculate duration. This logically belongs in the 802.11 5051 * layer but it lacks sufficient information to calculate it. 5052 */ 5053 if ((flags & HAL_TXDESC_NOACK) == 0 && 5054 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 5055 u_int16_t dur; 5056 if (shortPreamble) 5057 dur = rt->info[rix].spAckDuration; 5058 else 5059 dur = rt->info[rix].lpAckDuration; 5060 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 5061 dur += dur; /* additional SIFS+ACK */ 5062 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 5063 /* 5064 * Include the size of next fragment so NAV is 5065 * updated properly. The last fragment uses only 5066 * the ACK duration 5067 */ 5068 dur += ath_hal_computetxtime(ah, rt, 5069 m0->m_nextpkt->m_pkthdr.len, 5070 rix, shortPreamble); 5071 } 5072 if (isfrag) { 5073 /* 5074 * Force hardware to use computed duration for next 5075 * fragment by disabling multi-rate retry which updates 5076 * duration based on the multi-rate duration table. 5077 */ 5078 ismrr = 0; 5079 try0 = ATH_TXMGTTRY; /* XXX? */ 5080 } 5081 *(u_int16_t *)wh->i_dur = htole16(dur); 5082 } 5083 5084 /* 5085 * Calculate RTS/CTS rate and duration if needed. 5086 */ 5087 ctsduration = 0; 5088 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 5089 /* 5090 * CTS transmit rate is derived from the transmit rate 5091 * by looking in the h/w rate table. We must also factor 5092 * in whether or not a short preamble is to be used. 5093 */ 5094 /* NB: cix is set above where RTS/CTS is enabled */ 5095 KASSERT(cix != 0xff, ("cix not setup")); 5096 ctsrate = rt->info[cix].rateCode; 5097 /* 5098 * Compute the transmit duration based on the frame 5099 * size and the size of an ACK frame. We call into the 5100 * HAL to do the computation since it depends on the 5101 * characteristics of the actual PHY being used. 5102 * 5103 * NB: CTS is assumed the same size as an ACK so we can 5104 * use the precalculated ACK durations. 5105 */ 5106 if (shortPreamble) { 5107 ctsrate |= rt->info[cix].shortPreamble; 5108 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 5109 ctsduration += rt->info[cix].spAckDuration; 5110 ctsduration += ath_hal_computetxtime(ah, 5111 rt, pktlen, rix, AH_TRUE); 5112 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 5113 ctsduration += rt->info[rix].spAckDuration; 5114 } else { 5115 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 5116 ctsduration += rt->info[cix].lpAckDuration; 5117 ctsduration += ath_hal_computetxtime(ah, 5118 rt, pktlen, rix, AH_FALSE); 5119 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 5120 ctsduration += rt->info[rix].lpAckDuration; 5121 } 5122 /* 5123 * Must disable multi-rate retry when using RTS/CTS. 5124 */ 5125 ismrr = 0; 5126 try0 = ATH_TXMGTTRY; /* XXX */ 5127 } else 5128 ctsrate = 0; 5129 5130 /* 5131 * At this point we are committed to sending the frame 5132 * and we don't need to look at m_nextpkt; clear it in 5133 * case this frame is part of frag chain. 5134 */ 5135 m0->m_nextpkt = NULL; 5136 5137 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 5138 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 5139 sc->sc_hwmap[rix].ieeerate, -1); 5140 5141 if (bpf_peers_present(ifp->if_bpf)) { 5142 u_int64_t tsf = ath_hal_gettsf64(ah); 5143 5144 sc->sc_tx_th.wt_tsf = htole64(tsf); 5145 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 5146 if (iswep) 5147 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 5148 if (isfrag) 5149 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 5150 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 5151 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 5152 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 5153 5154 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 5155 } 5156 5157 /* 5158 * Determine if a tx interrupt should be generated for 5159 * this descriptor. We take a tx interrupt to reap 5160 * descriptors when the h/w hits an EOL condition or 5161 * when the descriptor is specifically marked to generate 5162 * an interrupt. We periodically mark descriptors in this 5163 * way to insure timely replenishing of the supply needed 5164 * for sending frames. Defering interrupts reduces system 5165 * load and potentially allows more concurrent work to be 5166 * done but if done to aggressively can cause senders to 5167 * backup. 5168 * 5169 * NB: use >= to deal with sc_txintrperiod changing 5170 * dynamically through sysctl. 5171 */ 5172 if (flags & HAL_TXDESC_INTREQ) { 5173 txq->axq_intrcnt = 0; 5174 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 5175 flags |= HAL_TXDESC_INTREQ; 5176 txq->axq_intrcnt = 0; 5177 } 5178 5179 /* 5180 * Formulate first tx descriptor with tx controls. 5181 */ 5182 /* XXX check return value? */ 5183 ath_hal_setuptxdesc(ah, ds 5184 , pktlen /* packet length */ 5185 , hdrlen /* header length */ 5186 , atype /* Atheros packet type */ 5187 , ni->ni_txpower /* txpower */ 5188 , txrate, try0 /* series 0 rate/tries */ 5189 , keyix /* key cache index */ 5190 , sc->sc_txantenna /* antenna mode */ 5191 , flags /* flags */ 5192 , ctsrate /* rts/cts rate */ 5193 , ctsduration /* rts/cts duration */ 5194 ); 5195 bf->bf_txflags = flags; 5196 /* 5197 * Setup the multi-rate retry state only when we're 5198 * going to use it. This assumes ath_hal_setuptxdesc 5199 * initializes the descriptors (so we don't have to) 5200 * when the hardware supports multi-rate retry and 5201 * we don't use it. 5202 */ 5203 if (ismrr) 5204 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 5205 5206 ath_tx_handoff(sc, txq, bf); 5207 return 0; 5208} 5209 5210/* 5211 * Process completed xmit descriptors from the specified queue. 5212 */ 5213static int 5214ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 5215{ 5216 struct ath_hal *ah = sc->sc_ah; 5217 struct ifnet *ifp = sc->sc_ifp; 5218 struct ieee80211com *ic = ifp->if_l2com; 5219 struct ath_buf *bf, *last; 5220 struct ath_desc *ds, *ds0; 5221 struct ath_tx_status *ts; 5222 struct ieee80211_node *ni; 5223 struct ath_node *an; 5224 int sr, lr, pri, nacked; 5225 HAL_STATUS status; 5226 5227 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 5228 __func__, txq->axq_qnum, 5229 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 5230 txq->axq_link); 5231 nacked = 0; 5232 for (;;) { 5233 ATH_TXQ_LOCK(txq); 5234 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 5235 bf = STAILQ_FIRST(&txq->axq_q); 5236 if (bf == NULL) { 5237 ATH_TXQ_UNLOCK(txq); 5238 break; 5239 } 5240 ds0 = &bf->bf_desc[0]; 5241 ds = &bf->bf_desc[bf->bf_nseg - 1]; 5242 ts = &bf->bf_status.ds_txstat; 5243 status = ath_hal_txprocdesc(ah, ds, ts); 5244#ifdef ATH_DEBUG 5245 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 5246 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 5247 status == HAL_OK); 5248#endif 5249 if (status == HAL_EINPROGRESS) { 5250 ATH_TXQ_UNLOCK(txq); 5251 break; 5252 } 5253 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5254#ifdef ATH_SUPPORT_TDMA 5255 if (txq->axq_depth > 0) { 5256 /* 5257 * More frames follow. Mark the buffer busy 5258 * so it's not re-used while the hardware may 5259 * still re-read the link field in the descriptor. 5260 */ 5261 bf->bf_flags |= ATH_BUF_BUSY; 5262 } else 5263#else 5264 if (txq->axq_depth == 0) 5265#endif 5266 txq->axq_link = NULL; 5267 ATH_TXQ_UNLOCK(txq); 5268 5269 ni = bf->bf_node; 5270 if (ni != NULL) { 5271 an = ATH_NODE(ni); 5272 if (ts->ts_status == 0) { 5273 u_int8_t txant = ts->ts_antenna; 5274 sc->sc_stats.ast_ant_tx[txant]++; 5275 sc->sc_ant_tx[txant]++; 5276 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 5277 sc->sc_stats.ast_tx_altrate++; 5278 pri = M_WME_GETAC(bf->bf_m); 5279 if (pri >= WME_AC_VO) 5280 ic->ic_wme.wme_hipri_traffic++; 5281 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 5282 ni->ni_inact = ni->ni_inact_reload; 5283 } else { 5284 if (ts->ts_status & HAL_TXERR_XRETRY) 5285 sc->sc_stats.ast_tx_xretries++; 5286 if (ts->ts_status & HAL_TXERR_FIFO) 5287 sc->sc_stats.ast_tx_fifoerr++; 5288 if (ts->ts_status & HAL_TXERR_FILT) 5289 sc->sc_stats.ast_tx_filtered++; 5290 if (bf->bf_m->m_flags & M_FF) 5291 sc->sc_stats.ast_ff_txerr++; 5292 } 5293 sr = ts->ts_shortretry; 5294 lr = ts->ts_longretry; 5295 sc->sc_stats.ast_tx_shortretry += sr; 5296 sc->sc_stats.ast_tx_longretry += lr; 5297 /* 5298 * Hand the descriptor to the rate control algorithm. 5299 */ 5300 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 5301 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 5302 /* 5303 * If frame was ack'd update statistics, 5304 * including the last rx time used to 5305 * workaround phantom bmiss interrupts. 5306 */ 5307 if (ts->ts_status == 0) { 5308 nacked++; 5309 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 5310 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 5311 ts->ts_rssi); 5312 } 5313 ath_rate_tx_complete(sc, an, bf); 5314 } 5315 /* 5316 * Do any tx complete callback. Note this must 5317 * be done before releasing the node reference. 5318 */ 5319 if (bf->bf_m->m_flags & M_TXCB) 5320 ieee80211_process_callback(ni, bf->bf_m, 5321 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 5322 ts->ts_status : HAL_TXERR_XRETRY); 5323 /* 5324 * Reclaim reference to node. 5325 * 5326 * NB: the node may be reclaimed here if, for example 5327 * this is a DEAUTH message that was sent and the 5328 * node was timed out due to inactivity. 5329 */ 5330 ieee80211_free_node(ni); 5331 } 5332 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5333 BUS_DMASYNC_POSTWRITE); 5334 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5335 5336 m_freem(bf->bf_m); 5337 bf->bf_m = NULL; 5338 bf->bf_node = NULL; 5339 5340 ATH_TXBUF_LOCK(sc); 5341 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5342 if (last != NULL) 5343 last->bf_flags &= ~ATH_BUF_BUSY; 5344 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5345 ATH_TXBUF_UNLOCK(sc); 5346 } 5347 /* 5348 * Flush fast-frame staging queue when traffic slows. 5349 */ 5350 if (txq->axq_depth <= 1) 5351 ath_ff_stageq_flush(sc, txq, ath_ff_always); 5352 return nacked; 5353} 5354 5355static __inline int 5356txqactive(struct ath_hal *ah, int qnum) 5357{ 5358 u_int32_t txqs = 1<<qnum; 5359 ath_hal_gettxintrtxqs(ah, &txqs); 5360 return (txqs & (1<<qnum)); 5361} 5362 5363/* 5364 * Deferred processing of transmit interrupt; special-cased 5365 * for a single hardware transmit queue (e.g. 5210 and 5211). 5366 */ 5367static void 5368ath_tx_proc_q0(void *arg, int npending) 5369{ 5370 struct ath_softc *sc = arg; 5371 struct ifnet *ifp = sc->sc_ifp; 5372 5373 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5374 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5375 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5376 ath_tx_processq(sc, sc->sc_cabq); 5377 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5378 sc->sc_wd_timer = 0; 5379 5380 if (sc->sc_softled) 5381 ath_led_event(sc, sc->sc_txrix); 5382 5383 ath_start(ifp); 5384} 5385 5386/* 5387 * Deferred processing of transmit interrupt; special-cased 5388 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5389 */ 5390static void 5391ath_tx_proc_q0123(void *arg, int npending) 5392{ 5393 struct ath_softc *sc = arg; 5394 struct ifnet *ifp = sc->sc_ifp; 5395 int nacked; 5396 5397 /* 5398 * Process each active queue. 5399 */ 5400 nacked = 0; 5401 if (txqactive(sc->sc_ah, 0)) 5402 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5403 if (txqactive(sc->sc_ah, 1)) 5404 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5405 if (txqactive(sc->sc_ah, 2)) 5406 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5407 if (txqactive(sc->sc_ah, 3)) 5408 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5409 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5410 ath_tx_processq(sc, sc->sc_cabq); 5411 if (nacked) 5412 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5413 5414 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5415 sc->sc_wd_timer = 0; 5416 5417 if (sc->sc_softled) 5418 ath_led_event(sc, sc->sc_txrix); 5419 5420 ath_start(ifp); 5421} 5422 5423/* 5424 * Deferred processing of transmit interrupt. 5425 */ 5426static void 5427ath_tx_proc(void *arg, int npending) 5428{ 5429 struct ath_softc *sc = arg; 5430 struct ifnet *ifp = sc->sc_ifp; 5431 int i, nacked; 5432 5433 /* 5434 * Process each active queue. 5435 */ 5436 nacked = 0; 5437 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5438 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5439 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5440 if (nacked) 5441 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5442 5443 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5444 sc->sc_wd_timer = 0; 5445 5446 if (sc->sc_softled) 5447 ath_led_event(sc, sc->sc_txrix); 5448 5449 ath_start(ifp); 5450} 5451 5452static void 5453ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5454{ 5455#ifdef ATH_DEBUG 5456 struct ath_hal *ah = sc->sc_ah; 5457#endif 5458 struct ieee80211_node *ni; 5459 struct ath_buf *bf; 5460 u_int ix; 5461 5462 /* 5463 * NB: this assumes output has been stopped and 5464 * we do not need to block ath_tx_proc 5465 */ 5466 ATH_TXBUF_LOCK(sc); 5467 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5468 if (bf != NULL) 5469 bf->bf_flags &= ~ATH_BUF_BUSY; 5470 ATH_TXBUF_UNLOCK(sc); 5471 for (ix = 0;; ix++) { 5472 ATH_TXQ_LOCK(txq); 5473 bf = STAILQ_FIRST(&txq->axq_q); 5474 if (bf == NULL) { 5475 txq->axq_link = NULL; 5476 ATH_TXQ_UNLOCK(txq); 5477 break; 5478 } 5479 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5480 ATH_TXQ_UNLOCK(txq); 5481#ifdef ATH_DEBUG 5482 if (sc->sc_debug & ATH_DEBUG_RESET) { 5483 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5484 5485 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5486 ath_hal_txprocdesc(ah, bf->bf_desc, 5487 &bf->bf_status.ds_txstat) == HAL_OK); 5488 ieee80211_dump_pkt(ic, mtod(bf->bf_m, caddr_t), 5489 bf->bf_m->m_len, 0, -1); 5490 } 5491#endif /* ATH_DEBUG */ 5492 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5493 ni = bf->bf_node; 5494 bf->bf_node = NULL; 5495 if (ni != NULL) { 5496 /* 5497 * Do any callback and reclaim the node reference. 5498 */ 5499 if (bf->bf_m->m_flags & M_TXCB) 5500 ieee80211_process_callback(ni, bf->bf_m, -1); 5501 ieee80211_free_node(ni); 5502 } 5503 m_freem(bf->bf_m); 5504 bf->bf_m = NULL; 5505 bf->bf_flags &= ~ATH_BUF_BUSY; 5506 5507 ATH_TXBUF_LOCK(sc); 5508 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5509 ATH_TXBUF_UNLOCK(sc); 5510 } 5511} 5512 5513static void 5514ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5515{ 5516 struct ath_hal *ah = sc->sc_ah; 5517 5518 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5519 __func__, txq->axq_qnum, 5520 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5521 txq->axq_link); 5522 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5523} 5524 5525/* 5526 * Drain the transmit queues and reclaim resources. 5527 */ 5528static void 5529ath_draintxq(struct ath_softc *sc) 5530{ 5531 struct ath_hal *ah = sc->sc_ah; 5532 struct ifnet *ifp = sc->sc_ifp; 5533 int i; 5534 5535 /* XXX return value */ 5536 if (!sc->sc_invalid) { 5537 /* don't touch the hardware if marked invalid */ 5538 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5539 __func__, sc->sc_bhalq, 5540 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5541 NULL); 5542 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5543 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5544 if (ATH_TXQ_SETUP(sc, i)) 5545 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5546 } 5547 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5548 if (ATH_TXQ_SETUP(sc, i)) 5549 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5550#ifdef ATH_DEBUG 5551 if (sc->sc_debug & ATH_DEBUG_RESET) { 5552 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5553 if (bf != NULL && bf->bf_m != NULL) { 5554 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5555 ath_hal_txprocdesc(ah, bf->bf_desc, 5556 &bf->bf_status.ds_txstat) == HAL_OK); 5557 ieee80211_dump_pkt(ifp->if_l2com, mtod(bf->bf_m, caddr_t), 5558 bf->bf_m->m_len, 0, -1); 5559 } 5560 } 5561#endif /* ATH_DEBUG */ 5562 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5563 sc->sc_wd_timer = 0; 5564} 5565 5566/* 5567 * Disable the receive h/w in preparation for a reset. 5568 */ 5569static void 5570ath_stoprecv(struct ath_softc *sc) 5571{ 5572#define PA2DESC(_sc, _pa) \ 5573 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5574 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5575 struct ath_hal *ah = sc->sc_ah; 5576 5577 ath_hal_stoppcurecv(ah); /* disable PCU */ 5578 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5579 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5580 DELAY(3000); /* 3ms is long enough for 1 frame */ 5581#ifdef ATH_DEBUG 5582 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5583 struct ath_buf *bf; 5584 u_int ix; 5585 5586 printf("%s: rx queue %p, link %p\n", __func__, 5587 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5588 ix = 0; 5589 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5590 struct ath_desc *ds = bf->bf_desc; 5591 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5592 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5593 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5594 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5595 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5596 ix++; 5597 } 5598 } 5599#endif 5600 if (sc->sc_rxpending != NULL) { 5601 m_freem(sc->sc_rxpending); 5602 sc->sc_rxpending = NULL; 5603 } 5604 sc->sc_rxlink = NULL; /* just in case */ 5605#undef PA2DESC 5606} 5607 5608/* 5609 * Enable the receive h/w following a reset. 5610 */ 5611static int 5612ath_startrecv(struct ath_softc *sc) 5613{ 5614 struct ath_hal *ah = sc->sc_ah; 5615 struct ath_buf *bf; 5616 5617 sc->sc_rxlink = NULL; 5618 sc->sc_rxpending = NULL; 5619 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5620 int error = ath_rxbuf_init(sc, bf); 5621 if (error != 0) { 5622 DPRINTF(sc, ATH_DEBUG_RECV, 5623 "%s: ath_rxbuf_init failed %d\n", 5624 __func__, error); 5625 return error; 5626 } 5627 } 5628 5629 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5630 ath_hal_putrxbuf(ah, bf->bf_daddr); 5631 ath_hal_rxena(ah); /* enable recv descriptors */ 5632 ath_mode_init(sc); /* set filters, etc. */ 5633 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5634 return 0; 5635} 5636 5637/* 5638 * Update internal state after a channel change. 5639 */ 5640static void 5641ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5642{ 5643 enum ieee80211_phymode mode; 5644 5645 /* 5646 * Change channels and update the h/w rate map 5647 * if we're switching; e.g. 11a to 11b/g. 5648 */ 5649 mode = ieee80211_chan2mode(chan); 5650 if (mode != sc->sc_curmode) 5651 ath_setcurmode(sc, mode); 5652 sc->sc_curchan = chan; 5653 5654 sc->sc_rx_th.wr_chan_flags = htole32(chan->ic_flags); 5655 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags; 5656 sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 5657 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq; 5658 sc->sc_rx_th.wr_chan_ieee = chan->ic_ieee; 5659 sc->sc_tx_th.wt_chan_ieee = sc->sc_rx_th.wr_chan_ieee; 5660 sc->sc_rx_th.wr_chan_maxpow = chan->ic_maxregpower; 5661 sc->sc_tx_th.wt_chan_maxpow = sc->sc_rx_th.wr_chan_maxpow; 5662} 5663 5664/* 5665 * Set/change channels. If the channel is really being changed, 5666 * it's done by reseting the chip. To accomplish this we must 5667 * first cleanup any pending DMA, then restart stuff after a la 5668 * ath_init. 5669 */ 5670static int 5671ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5672{ 5673 struct ifnet *ifp = sc->sc_ifp; 5674 struct ieee80211com *ic = ifp->if_l2com; 5675 struct ath_hal *ah = sc->sc_ah; 5676 5677 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5678 __func__, ieee80211_chan2ieee(ic, chan), 5679 chan->ic_freq, chan->ic_flags); 5680 if (chan != sc->sc_curchan) { 5681 HAL_STATUS status; 5682 /* 5683 * To switch channels clear any pending DMA operations; 5684 * wait long enough for the RX fifo to drain, reset the 5685 * hardware at the new frequency, and then re-enable 5686 * the relevant bits of the h/w. 5687 */ 5688 ath_hal_intrset(ah, 0); /* disable interrupts */ 5689 ath_draintxq(sc); /* clear pending tx frames */ 5690 ath_stoprecv(sc); /* turn off frame recv */ 5691 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5692 if_printf(ifp, "%s: unable to reset " 5693 "channel %u (%u Mhz, flags 0x%x), hal status %u\n", 5694 __func__, ieee80211_chan2ieee(ic, chan), 5695 chan->ic_freq, chan->ic_flags, status); 5696 return EIO; 5697 } 5698 sc->sc_diversity = ath_hal_getdiversity(ah); 5699 5700 /* 5701 * Re-enable rx framework. 5702 */ 5703 if (ath_startrecv(sc) != 0) { 5704 if_printf(ifp, "%s: unable to restart recv logic\n", 5705 __func__); 5706 return EIO; 5707 } 5708 5709 /* 5710 * Change channels and update the h/w rate map 5711 * if we're switching; e.g. 11a to 11b/g. 5712 */ 5713 ath_chan_change(sc, chan); 5714 5715 /* 5716 * Re-enable interrupts. 5717 */ 5718 ath_hal_intrset(ah, sc->sc_imask); 5719 } 5720 return 0; 5721} 5722 5723/* 5724 * Periodically recalibrate the PHY to account 5725 * for temperature/environment changes. 5726 */ 5727static void 5728ath_calibrate(void *arg) 5729{ 5730 struct ath_softc *sc = arg; 5731 struct ath_hal *ah = sc->sc_ah; 5732 struct ifnet *ifp = sc->sc_ifp; 5733 struct ieee80211com *ic = ifp->if_l2com; 5734 HAL_BOOL longCal, isCalDone; 5735 int nextcal; 5736 5737 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5738 goto restart; 5739 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5740 if (longCal) { 5741 sc->sc_stats.ast_per_cal++; 5742 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5743 /* 5744 * Rfgain is out of bounds, reset the chip 5745 * to load new gain values. 5746 */ 5747 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5748 "%s: rfgain change\n", __func__); 5749 sc->sc_stats.ast_per_rfgain++; 5750 ath_reset(ifp); 5751 } 5752 /* 5753 * If this long cal is after an idle period, then 5754 * reset the data collection state so we start fresh. 5755 */ 5756 if (sc->sc_resetcal) { 5757 (void) ath_hal_calreset(ah, sc->sc_curchan); 5758 sc->sc_lastcalreset = ticks; 5759 sc->sc_resetcal = 0; 5760 } 5761 } 5762 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5763 if (longCal) { 5764 /* 5765 * Calibrate noise floor data again in case of change. 5766 */ 5767 ath_hal_process_noisefloor(ah); 5768 } 5769 } else { 5770 DPRINTF(sc, ATH_DEBUG_ANY, 5771 "%s: calibration of channel %u failed\n", 5772 __func__, sc->sc_curchan->ic_freq); 5773 sc->sc_stats.ast_per_calfail++; 5774 } 5775 if (!isCalDone) { 5776restart: 5777 /* 5778 * Use a shorter interval to potentially collect multiple 5779 * data samples required to complete calibration. Once 5780 * we're told the work is done we drop back to a longer 5781 * interval between requests. We're more aggressive doing 5782 * work when operating as an AP to improve operation right 5783 * after startup. 5784 */ 5785 nextcal = (1000*ath_shortcalinterval)/hz; 5786 if (sc->sc_opmode != HAL_M_HOSTAP) 5787 nextcal *= 10; 5788 } else { 5789 nextcal = ath_longcalinterval*hz; 5790 sc->sc_lastlongcal = ticks; 5791 if (sc->sc_lastcalreset == 0) 5792 sc->sc_lastcalreset = sc->sc_lastlongcal; 5793 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5794 sc->sc_resetcal = 1; /* setup reset next trip */ 5795 } 5796 5797 if (nextcal != 0) { 5798 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5799 __func__, nextcal, isCalDone ? "" : "!"); 5800 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5801 } else { 5802 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5803 __func__); 5804 /* NB: don't rearm timer */ 5805 } 5806} 5807 5808static void 5809ath_scan_start(struct ieee80211com *ic) 5810{ 5811 struct ifnet *ifp = ic->ic_ifp; 5812 struct ath_softc *sc = ifp->if_softc; 5813 struct ath_hal *ah = sc->sc_ah; 5814 u_int32_t rfilt; 5815 5816 /* XXX calibration timer? */ 5817 5818 sc->sc_scanning = 1; 5819 sc->sc_syncbeacon = 0; 5820 rfilt = ath_calcrxfilter(sc); 5821 ath_hal_setrxfilter(ah, rfilt); 5822 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5823 5824 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5825 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5826} 5827 5828static void 5829ath_scan_end(struct ieee80211com *ic) 5830{ 5831 struct ifnet *ifp = ic->ic_ifp; 5832 struct ath_softc *sc = ifp->if_softc; 5833 struct ath_hal *ah = sc->sc_ah; 5834 u_int32_t rfilt; 5835 5836 sc->sc_scanning = 0; 5837 rfilt = ath_calcrxfilter(sc); 5838 ath_hal_setrxfilter(ah, rfilt); 5839 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5840 5841 ath_hal_process_noisefloor(ah); 5842 5843 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5844 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5845 sc->sc_curaid); 5846} 5847 5848static void 5849ath_set_channel(struct ieee80211com *ic) 5850{ 5851 struct ifnet *ifp = ic->ic_ifp; 5852 struct ath_softc *sc = ifp->if_softc; 5853 5854 (void) ath_chan_set(sc, ic->ic_curchan); 5855 /* 5856 * If we are returning to our bss channel then mark state 5857 * so the next recv'd beacon's tsf will be used to sync the 5858 * beacon timers. Note that since we only hear beacons in 5859 * sta/ibss mode this has no effect in other operating modes. 5860 */ 5861 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5862 sc->sc_syncbeacon = 1; 5863} 5864 5865/* 5866 * Walk the vap list and check if there any vap's in RUN state. 5867 */ 5868static int 5869ath_isanyrunningvaps(struct ieee80211vap *this) 5870{ 5871 struct ieee80211com *ic = this->iv_ic; 5872 struct ieee80211vap *vap; 5873 5874 IEEE80211_LOCK_ASSERT(ic); 5875 5876 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5877 if (vap != this && vap->iv_state == IEEE80211_S_RUN) 5878 return 1; 5879 } 5880 return 0; 5881} 5882 5883static int 5884ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5885{ 5886 struct ieee80211com *ic = vap->iv_ic; 5887 struct ath_softc *sc = ic->ic_ifp->if_softc; 5888 struct ath_vap *avp = ATH_VAP(vap); 5889 struct ath_hal *ah = sc->sc_ah; 5890 struct ieee80211_node *ni = NULL; 5891 int i, error, stamode; 5892 u_int32_t rfilt; 5893 static const HAL_LED_STATE leds[] = { 5894 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5895 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5896 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5897 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5898 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5899 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5900 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5901 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5902 }; 5903 5904 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5905 ieee80211_state_name[vap->iv_state], 5906 ieee80211_state_name[nstate]); 5907 5908 callout_drain(&sc->sc_cal_ch); 5909 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5910 5911 if (nstate == IEEE80211_S_SCAN) { 5912 /* 5913 * Scanning: turn off beacon miss and don't beacon. 5914 * Mark beacon state so when we reach RUN state we'll 5915 * [re]setup beacons. Unblock the task q thread so 5916 * deferred interrupt processing is done. 5917 */ 5918 ath_hal_intrset(ah, 5919 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5920 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5921 sc->sc_beacons = 0; 5922 taskqueue_unblock(sc->sc_tq); 5923 } 5924 5925 ni = vap->iv_bss; 5926 rfilt = ath_calcrxfilter(sc); 5927 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5928 vap->iv_opmode == IEEE80211_M_AHDEMO || 5929 vap->iv_opmode == IEEE80211_M_IBSS); 5930 if (stamode && nstate == IEEE80211_S_RUN) { 5931 sc->sc_curaid = ni->ni_associd; 5932 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5933 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5934 } 5935 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5936 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5937 ath_hal_setrxfilter(ah, rfilt); 5938 5939 /* XXX is this to restore keycache on resume? */ 5940 if (vap->iv_opmode != IEEE80211_M_STA && 5941 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5942 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5943 if (ath_hal_keyisvalid(ah, i)) 5944 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5945 } 5946 5947 /* 5948 * Invoke the parent method to do net80211 work. 5949 */ 5950 error = avp->av_newstate(vap, nstate, arg); 5951 if (error != 0) 5952 goto bad; 5953 5954 if (nstate == IEEE80211_S_RUN) { 5955 /* NB: collect bss node again, it may have changed */ 5956 ni = vap->iv_bss; 5957 5958 DPRINTF(sc, ATH_DEBUG_STATE, 5959 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5960 "capinfo 0x%04x chan %d\n", __func__, 5961 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5962 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5963 5964 switch (vap->iv_opmode) { 5965#ifdef ATH_SUPPORT_TDMA 5966 case IEEE80211_M_AHDEMO: 5967 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5968 break; 5969 /* fall thru... */ 5970#endif 5971 case IEEE80211_M_HOSTAP: 5972 case IEEE80211_M_IBSS: 5973 /* 5974 * Allocate and setup the beacon frame. 5975 * 5976 * Stop any previous beacon DMA. This may be 5977 * necessary, for example, when an ibss merge 5978 * causes reconfiguration; there will be a state 5979 * transition from RUN->RUN that means we may 5980 * be called with beacon transmission active. 5981 */ 5982 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5983 5984 error = ath_beacon_alloc(sc, ni); 5985 if (error != 0) 5986 goto bad; 5987 /* 5988 * If joining an adhoc network defer beacon timer 5989 * configuration to the next beacon frame so we 5990 * have a current TSF to use. Otherwise we're 5991 * starting an ibss/bss so there's no need to delay; 5992 * if this is the first vap moving to RUN state, then 5993 * beacon state needs to be [re]configured. 5994 */ 5995 if (vap->iv_opmode == IEEE80211_M_IBSS && 5996 ni->ni_tstamp.tsf != 0) { 5997 sc->sc_syncbeacon = 1; 5998 } else if (!sc->sc_beacons) { 5999#ifdef ATH_SUPPORT_TDMA 6000 if (vap->iv_caps & IEEE80211_C_TDMA) 6001 ath_tdma_config(sc, vap); 6002 else 6003#endif 6004 ath_beacon_config(sc, vap); 6005 sc->sc_beacons = 1; 6006 } 6007 break; 6008 case IEEE80211_M_STA: 6009 /* 6010 * Defer beacon timer configuration to the next 6011 * beacon frame so we have a current TSF to use 6012 * (any TSF collected when scanning is likely old). 6013 */ 6014 sc->sc_syncbeacon = 1; 6015 break; 6016 case IEEE80211_M_MONITOR: 6017 /* 6018 * Monitor mode vaps have only INIT->RUN and RUN->RUN 6019 * transitions so we must re-enable interrupts here to 6020 * handle the case of a single monitor mode vap. 6021 */ 6022 ath_hal_intrset(ah, sc->sc_imask); 6023 break; 6024 case IEEE80211_M_WDS: 6025 break; 6026 default: 6027 break; 6028 } 6029 /* 6030 * Let the hal process statistics collected during a 6031 * scan so it can provide calibrated noise floor data. 6032 */ 6033 ath_hal_process_noisefloor(ah); 6034 /* 6035 * Reset rssi stats; maybe not the best place... 6036 */ 6037 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 6038 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 6039 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 6040 /* 6041 * Finally, start any timers and the task q thread 6042 * (in case we didn't go through SCAN state). 6043 */ 6044 if (ath_longcalinterval != 0) { 6045 /* start periodic recalibration timer */ 6046 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6047 } else { 6048 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6049 "%s: calibration disabled\n", __func__); 6050 } 6051 taskqueue_unblock(sc->sc_tq); 6052 } else if (nstate == IEEE80211_S_INIT) { 6053 /* 6054 * If there are no vaps left in RUN state then 6055 * shutdown host/driver operation: 6056 * o disable interrupts 6057 * o disable the task queue thread 6058 * o mark beacon processing as stopped 6059 */ 6060 if (!ath_isanyrunningvaps(vap)) { 6061 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 6062 /* disable interrupts */ 6063 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 6064 taskqueue_block(sc->sc_tq); 6065 sc->sc_beacons = 0; 6066 } 6067#ifdef ATH_SUPPORT_TDMA 6068 ath_hal_setcca(ah, AH_TRUE); 6069#endif 6070 } 6071bad: 6072 return error; 6073} 6074 6075/* 6076 * Allocate a key cache slot to the station so we can 6077 * setup a mapping from key index to node. The key cache 6078 * slot is needed for managing antenna state and for 6079 * compression when stations do not use crypto. We do 6080 * it uniliaterally here; if crypto is employed this slot 6081 * will be reassigned. 6082 */ 6083static void 6084ath_setup_stationkey(struct ieee80211_node *ni) 6085{ 6086 struct ieee80211vap *vap = ni->ni_vap; 6087 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6088 ieee80211_keyix keyix, rxkeyix; 6089 6090 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 6091 /* 6092 * Key cache is full; we'll fall back to doing 6093 * the more expensive lookup in software. Note 6094 * this also means no h/w compression. 6095 */ 6096 /* XXX msg+statistic */ 6097 } else { 6098 /* XXX locking? */ 6099 ni->ni_ucastkey.wk_keyix = keyix; 6100 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 6101 /* NB: must mark device key to get called back on delete */ 6102 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 6103 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 6104 /* NB: this will create a pass-thru key entry */ 6105 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 6106 } 6107} 6108 6109/* 6110 * Setup driver-specific state for a newly associated node. 6111 * Note that we're called also on a re-associate, the isnew 6112 * param tells us if this is the first time or not. 6113 */ 6114static void 6115ath_newassoc(struct ieee80211_node *ni, int isnew) 6116{ 6117 struct ath_node *an = ATH_NODE(ni); 6118 struct ieee80211vap *vap = ni->ni_vap; 6119 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6120 const struct ieee80211_txparam *tp = ni->ni_txparms; 6121 6122 an->an_mcastrix = ath_tx_findrix(sc->sc_currates, tp->mcastrate); 6123 an->an_mgmtrix = ath_tx_findrix(sc->sc_currates, tp->mgmtrate); 6124 6125 ath_rate_newassoc(sc, an, isnew); 6126 if (isnew && 6127 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 6128 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 6129 ath_setup_stationkey(ni); 6130} 6131 6132static int 6133ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 6134 int nchans, struct ieee80211_channel chans[]) 6135{ 6136 struct ath_softc *sc = ic->ic_ifp->if_softc; 6137 struct ath_hal *ah = sc->sc_ah; 6138 HAL_STATUS status; 6139 6140 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6141 "%s: rd %u cc %u location %c%s\n", 6142 __func__, reg->regdomain, reg->country, reg->location, 6143 reg->ecm ? " ecm" : ""); 6144 6145 status = ath_hal_set_channels(ah, chans, nchans, 6146 reg->country, reg->regdomain); 6147 if (status != HAL_OK) { 6148 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 6149 __func__, status); 6150 return EINVAL; /* XXX */ 6151 } 6152 return 0; 6153} 6154 6155static void 6156ath_getradiocaps(struct ieee80211com *ic, 6157 int maxchans, int *nchans, struct ieee80211_channel chans[]) 6158{ 6159 struct ath_softc *sc = ic->ic_ifp->if_softc; 6160 struct ath_hal *ah = sc->sc_ah; 6161 6162 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 6163 __func__, SKU_DEBUG, CTRY_DEFAULT); 6164 6165 /* XXX check return */ 6166 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 6167 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 6168 6169} 6170 6171static int 6172ath_getchannels(struct ath_softc *sc) 6173{ 6174 struct ifnet *ifp = sc->sc_ifp; 6175 struct ieee80211com *ic = ifp->if_l2com; 6176 struct ath_hal *ah = sc->sc_ah; 6177 HAL_STATUS status; 6178 6179 /* 6180 * Collect channel set based on EEPROM contents. 6181 */ 6182 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 6183 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 6184 if (status != HAL_OK) { 6185 if_printf(ifp, "%s: unable to collect channel list from hal, " 6186 "status %d\n", __func__, status); 6187 return EINVAL; 6188 } 6189 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 6190 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 6191 /* XXX map Atheros sku's to net80211 SKU's */ 6192 /* XXX net80211 types too small */ 6193 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 6194 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 6195 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 6196 ic->ic_regdomain.isocc[1] = ' '; 6197 6198 ic->ic_regdomain.ecm = 1; 6199 ic->ic_regdomain.location = 'I'; 6200 6201 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6202 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 6203 __func__, sc->sc_eerd, sc->sc_eecc, 6204 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 6205 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 6206 return 0; 6207} 6208 6209static void 6210ath_led_done(void *arg) 6211{ 6212 struct ath_softc *sc = arg; 6213 6214 sc->sc_blinking = 0; 6215} 6216 6217/* 6218 * Turn the LED off: flip the pin and then set a timer so no 6219 * update will happen for the specified duration. 6220 */ 6221static void 6222ath_led_off(void *arg) 6223{ 6224 struct ath_softc *sc = arg; 6225 6226 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 6227 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 6228} 6229 6230/* 6231 * Blink the LED according to the specified on/off times. 6232 */ 6233static void 6234ath_led_blink(struct ath_softc *sc, int on, int off) 6235{ 6236 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 6237 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 6238 sc->sc_blinking = 1; 6239 sc->sc_ledoff = off; 6240 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 6241} 6242 6243static void 6244ath_led_event(struct ath_softc *sc, int rix) 6245{ 6246 sc->sc_ledevent = ticks; /* time of last event */ 6247 if (sc->sc_blinking) /* don't interrupt active blink */ 6248 return; 6249 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 6250} 6251 6252static int 6253ath_rate_setup(struct ath_softc *sc, u_int mode) 6254{ 6255 struct ath_hal *ah = sc->sc_ah; 6256 const HAL_RATE_TABLE *rt; 6257 6258 switch (mode) { 6259 case IEEE80211_MODE_11A: 6260 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6261 break; 6262 case IEEE80211_MODE_HALF: 6263 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6264 break; 6265 case IEEE80211_MODE_QUARTER: 6266 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6267 break; 6268 case IEEE80211_MODE_11B: 6269 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6270 break; 6271 case IEEE80211_MODE_11G: 6272 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6273 break; 6274 case IEEE80211_MODE_TURBO_A: 6275 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6276#if HAL_ABI_VERSION < 0x07013100 6277 if (rt == NULL) /* XXX bandaid for old hal's */ 6278 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6279#endif 6280 break; 6281 case IEEE80211_MODE_TURBO_G: 6282 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6283 break; 6284 case IEEE80211_MODE_STURBO_A: 6285 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6286 break; 6287 case IEEE80211_MODE_11NA: 6288 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6289 break; 6290 case IEEE80211_MODE_11NG: 6291 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6292 break; 6293 default: 6294 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6295 __func__, mode); 6296 return 0; 6297 } 6298 sc->sc_rates[mode] = rt; 6299 return (rt != NULL); 6300} 6301 6302static void 6303ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6304{ 6305#define N(a) (sizeof(a)/sizeof(a[0])) 6306 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6307 static const struct { 6308 u_int rate; /* tx/rx 802.11 rate */ 6309 u_int16_t timeOn; /* LED on time (ms) */ 6310 u_int16_t timeOff; /* LED off time (ms) */ 6311 } blinkrates[] = { 6312 { 108, 40, 10 }, 6313 { 96, 44, 11 }, 6314 { 72, 50, 13 }, 6315 { 48, 57, 14 }, 6316 { 36, 67, 16 }, 6317 { 24, 80, 20 }, 6318 { 22, 100, 25 }, 6319 { 18, 133, 34 }, 6320 { 12, 160, 40 }, 6321 { 10, 200, 50 }, 6322 { 6, 240, 58 }, 6323 { 4, 267, 66 }, 6324 { 2, 400, 100 }, 6325 { 0, 500, 130 }, 6326 /* XXX half/quarter rates */ 6327 }; 6328 const HAL_RATE_TABLE *rt; 6329 int i, j; 6330 6331 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6332 rt = sc->sc_rates[mode]; 6333 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6334 for (i = 0; i < rt->rateCount; i++) { 6335 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6336 if (rt->info[i].phy != IEEE80211_T_HT) 6337 sc->sc_rixmap[ieeerate] = i; 6338 else 6339 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6340 } 6341 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6342 for (i = 0; i < N(sc->sc_hwmap); i++) { 6343 if (i >= rt->rateCount) { 6344 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6345 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6346 continue; 6347 } 6348 sc->sc_hwmap[i].ieeerate = 6349 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6350 if (rt->info[i].phy == IEEE80211_T_HT) 6351 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6352 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6353 if (rt->info[i].shortPreamble || 6354 rt->info[i].phy == IEEE80211_T_OFDM) 6355 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6356 /* NB: receive frames include FCS */ 6357 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 6358 IEEE80211_RADIOTAP_F_FCS; 6359 /* setup blink rate table to avoid per-packet lookup */ 6360 for (j = 0; j < N(blinkrates)-1; j++) 6361 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6362 break; 6363 /* NB: this uses the last entry if the rate isn't found */ 6364 /* XXX beware of overlow */ 6365 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6366 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6367 } 6368 sc->sc_currates = rt; 6369 sc->sc_curmode = mode; 6370 /* 6371 * All protection frames are transmited at 2Mb/s for 6372 * 11g, otherwise at 1Mb/s. 6373 */ 6374 if (mode == IEEE80211_MODE_11G) 6375 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 6376 else 6377 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 6378 /* NB: caller is responsible for reseting rate control state */ 6379#undef N 6380} 6381 6382#ifdef ATH_DEBUG 6383static void 6384ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6385 u_int ix, int done) 6386{ 6387 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6388 struct ath_hal *ah = sc->sc_ah; 6389 const struct ath_desc *ds; 6390 int i; 6391 6392 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6393 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6394 " %08x %08x %08x %08x\n", 6395 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6396 ds->ds_link, ds->ds_data, 6397 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6398 ds->ds_ctl0, ds->ds_ctl1, 6399 ds->ds_hw[0], ds->ds_hw[1]); 6400 if (ah->ah_magic == 0x20065416) { 6401 printf(" %08x %08x %08x %08x %08x %08x %08x\n", 6402 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6403 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6404 ds->ds_hw[8]); 6405 } 6406 } 6407} 6408 6409static void 6410ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6411 u_int qnum, u_int ix, int done) 6412{ 6413 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6414 struct ath_hal *ah = sc->sc_ah; 6415 const struct ath_desc *ds; 6416 int i; 6417 6418 printf("Q%u[%3u]", qnum, ix); 6419 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6420 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6421 " %08x %08x %08x %08x %08x %08x\n", 6422 ds, (const struct ath_desc *)bf->bf_daddr + i, 6423 ds->ds_link, ds->ds_data, bf->bf_txflags, 6424 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6425 ds->ds_ctl0, ds->ds_ctl1, 6426 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6427 if (ah->ah_magic == 0x20065416) { 6428 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6429 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6430 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6431 ds->ds_hw[10],ds->ds_hw[11]); 6432 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6433 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6434 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6435 ds->ds_hw[18], ds->ds_hw[19]); 6436 } 6437 } 6438} 6439#endif /* ATH_DEBUG */ 6440 6441static void 6442ath_watchdog(void *arg) 6443{ 6444 struct ath_softc *sc = arg; 6445 6446 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6447 struct ifnet *ifp = sc->sc_ifp; 6448 uint32_t hangs; 6449 6450 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6451 hangs != 0) { 6452 if_printf(ifp, "%s hang detected (0x%x)\n", 6453 hangs & 0xff ? "bb" : "mac", hangs); 6454 } else 6455 if_printf(ifp, "device timeout\n"); 6456 ath_reset(ifp); 6457 ifp->if_oerrors++; 6458 sc->sc_stats.ast_watchdog++; 6459 } 6460 callout_schedule(&sc->sc_wd_ch, hz); 6461} 6462 6463#ifdef ATH_DIAGAPI 6464/* 6465 * Diagnostic interface to the HAL. This is used by various 6466 * tools to do things like retrieve register contents for 6467 * debugging. The mechanism is intentionally opaque so that 6468 * it can change frequently w/o concern for compatiblity. 6469 */ 6470static int 6471ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6472{ 6473 struct ath_hal *ah = sc->sc_ah; 6474 u_int id = ad->ad_id & ATH_DIAG_ID; 6475 void *indata = NULL; 6476 void *outdata = NULL; 6477 u_int32_t insize = ad->ad_in_size; 6478 u_int32_t outsize = ad->ad_out_size; 6479 int error = 0; 6480 6481 if (ad->ad_id & ATH_DIAG_IN) { 6482 /* 6483 * Copy in data. 6484 */ 6485 indata = malloc(insize, M_TEMP, M_NOWAIT); 6486 if (indata == NULL) { 6487 error = ENOMEM; 6488 goto bad; 6489 } 6490 error = copyin(ad->ad_in_data, indata, insize); 6491 if (error) 6492 goto bad; 6493 } 6494 if (ad->ad_id & ATH_DIAG_DYN) { 6495 /* 6496 * Allocate a buffer for the results (otherwise the HAL 6497 * returns a pointer to a buffer where we can read the 6498 * results). Note that we depend on the HAL leaving this 6499 * pointer for us to use below in reclaiming the buffer; 6500 * may want to be more defensive. 6501 */ 6502 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 6503 if (outdata == NULL) { 6504 error = ENOMEM; 6505 goto bad; 6506 } 6507 } 6508 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6509 if (outsize < ad->ad_out_size) 6510 ad->ad_out_size = outsize; 6511 if (outdata != NULL) 6512 error = copyout(outdata, ad->ad_out_data, 6513 ad->ad_out_size); 6514 } else { 6515 error = EINVAL; 6516 } 6517bad: 6518 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6519 free(indata, M_TEMP); 6520 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6521 free(outdata, M_TEMP); 6522 return error; 6523} 6524#endif /* ATH_DIAGAPI */ 6525 6526static int 6527ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 6528{ 6529#define IS_RUNNING(ifp) \ 6530 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 6531 struct ath_softc *sc = ifp->if_softc; 6532 struct ieee80211com *ic = ifp->if_l2com; 6533 struct ifreq *ifr = (struct ifreq *)data; 6534 const HAL_RATE_TABLE *rt; 6535 int error = 0; 6536 6537 switch (cmd) { 6538 case SIOCSIFFLAGS: 6539 ATH_LOCK(sc); 6540 if (IS_RUNNING(ifp)) { 6541 /* 6542 * To avoid rescanning another access point, 6543 * do not call ath_init() here. Instead, 6544 * only reflect promisc mode settings. 6545 */ 6546 ath_mode_init(sc); 6547 } else if (ifp->if_flags & IFF_UP) { 6548 /* 6549 * Beware of being called during attach/detach 6550 * to reset promiscuous mode. In that case we 6551 * will still be marked UP but not RUNNING. 6552 * However trying to re-init the interface 6553 * is the wrong thing to do as we've already 6554 * torn down much of our state. There's 6555 * probably a better way to deal with this. 6556 */ 6557 if (!sc->sc_invalid) 6558 ath_init(sc); /* XXX lose error */ 6559 } else { 6560 ath_stop_locked(ifp); 6561#ifdef notyet 6562 /* XXX must wakeup in places like ath_vap_delete */ 6563 if (!sc->sc_invalid) 6564 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6565#endif 6566 } 6567 ATH_UNLOCK(sc); 6568 break; 6569 case SIOCGIFMEDIA: 6570 case SIOCSIFMEDIA: 6571 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6572 break; 6573 case SIOCGATHSTATS: 6574 /* NB: embed these numbers to get a consistent view */ 6575 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6576 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6577 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6578 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6579#ifdef ATH_SUPPORT_TDMA 6580 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6581 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6582#endif 6583 rt = sc->sc_currates; 6584 /* XXX HT rates */ 6585 sc->sc_stats.ast_tx_rate = 6586 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6587 return copyout(&sc->sc_stats, 6588 ifr->ifr_data, sizeof (sc->sc_stats)); 6589 case SIOCZATHSTATS: 6590 error = priv_check(curthread, PRIV_DRIVER); 6591 if (error == 0) 6592 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6593 break; 6594#ifdef ATH_DIAGAPI 6595 case SIOCGATHDIAG: 6596 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6597 break; 6598#endif 6599 case SIOCGIFADDR: 6600 error = ether_ioctl(ifp, cmd, data); 6601 break; 6602 default: 6603 error = EINVAL; 6604 break; 6605 } 6606 return error; 6607#undef IS_RUNNING 6608} 6609 6610static int 6611ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6612{ 6613 struct ath_softc *sc = arg1; 6614 u_int slottime = ath_hal_getslottime(sc->sc_ah); 6615 int error; 6616 6617 error = sysctl_handle_int(oidp, &slottime, 0, req); 6618 if (error || !req->newptr) 6619 return error; 6620 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 6621} 6622 6623static int 6624ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6625{ 6626 struct ath_softc *sc = arg1; 6627 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6628 int error; 6629 6630 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6631 if (error || !req->newptr) 6632 return error; 6633 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 6634} 6635 6636static int 6637ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6638{ 6639 struct ath_softc *sc = arg1; 6640 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6641 int error; 6642 6643 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6644 if (error || !req->newptr) 6645 return error; 6646 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 6647} 6648 6649static int 6650ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6651{ 6652 struct ath_softc *sc = arg1; 6653 int softled = sc->sc_softled; 6654 int error; 6655 6656 error = sysctl_handle_int(oidp, &softled, 0, req); 6657 if (error || !req->newptr) 6658 return error; 6659 softled = (softled != 0); 6660 if (softled != sc->sc_softled) { 6661 if (softled) { 6662 /* NB: handle any sc_ledpin change */ 6663 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6664 HAL_GPIO_MUX_MAC_NETWORK_LED); 6665 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6666 !sc->sc_ledon); 6667 } 6668 sc->sc_softled = softled; 6669 } 6670 return 0; 6671} 6672 6673static int 6674ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6675{ 6676 struct ath_softc *sc = arg1; 6677 int ledpin = sc->sc_ledpin; 6678 int error; 6679 6680 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6681 if (error || !req->newptr) 6682 return error; 6683 if (ledpin != sc->sc_ledpin) { 6684 sc->sc_ledpin = ledpin; 6685 if (sc->sc_softled) { 6686 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6687 HAL_GPIO_MUX_MAC_NETWORK_LED); 6688 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6689 !sc->sc_ledon); 6690 } 6691 } 6692 return 0; 6693} 6694 6695static int 6696ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6697{ 6698 struct ath_softc *sc = arg1; 6699 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6700 int error; 6701 6702 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6703 if (!error && req->newptr) { 6704 /* XXX assumes 2 antenna ports */ 6705 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 6706 return EINVAL; 6707 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6708 /* 6709 * NB: with the switch locked this isn't meaningful, 6710 * but set it anyway so things like radiotap get 6711 * consistent info in their data. 6712 */ 6713 sc->sc_txantenna = txantenna; 6714 } 6715 return error; 6716} 6717 6718static int 6719ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6720{ 6721 struct ath_softc *sc = arg1; 6722 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 6723 int error; 6724 6725 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6726 if (!error && req->newptr) 6727 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6728 return error; 6729} 6730 6731static int 6732ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6733{ 6734 struct ath_softc *sc = arg1; 6735 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 6736 int error; 6737 6738 error = sysctl_handle_int(oidp, &diversity, 0, req); 6739 if (error || !req->newptr) 6740 return error; 6741 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6742 return EINVAL; 6743 sc->sc_diversity = diversity; 6744 return 0; 6745} 6746 6747static int 6748ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6749{ 6750 struct ath_softc *sc = arg1; 6751 u_int32_t diag; 6752 int error; 6753 6754 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 6755 return EINVAL; 6756 error = sysctl_handle_int(oidp, &diag, 0, req); 6757 if (error || !req->newptr) 6758 return error; 6759 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 6760} 6761 6762static int 6763ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6764{ 6765 struct ath_softc *sc = arg1; 6766 struct ifnet *ifp = sc->sc_ifp; 6767 u_int32_t scale; 6768 int error; 6769 6770 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 6771 error = sysctl_handle_int(oidp, &scale, 0, req); 6772 if (error || !req->newptr) 6773 return error; 6774 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 6775 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6776} 6777 6778static int 6779ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6780{ 6781 struct ath_softc *sc = arg1; 6782 u_int tpc = ath_hal_gettpc(sc->sc_ah); 6783 int error; 6784 6785 error = sysctl_handle_int(oidp, &tpc, 0, req); 6786 if (error || !req->newptr) 6787 return error; 6788 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 6789} 6790 6791static int 6792ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6793{ 6794 struct ath_softc *sc = arg1; 6795 struct ifnet *ifp = sc->sc_ifp; 6796 struct ath_hal *ah = sc->sc_ah; 6797 u_int rfkill = ath_hal_getrfkill(ah); 6798 int error; 6799 6800 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6801 if (error || !req->newptr) 6802 return error; 6803 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 6804 return 0; 6805 if (!ath_hal_setrfkill(ah, rfkill)) 6806 return EINVAL; 6807 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6808} 6809 6810static int 6811ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6812{ 6813 struct ath_softc *sc = arg1; 6814 u_int rfsilent; 6815 int error; 6816 6817 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6818 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6819 if (error || !req->newptr) 6820 return error; 6821 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 6822 return EINVAL; 6823 sc->sc_rfsilentpin = rfsilent & 0x1c; 6824 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6825 return 0; 6826} 6827 6828static int 6829ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6830{ 6831 struct ath_softc *sc = arg1; 6832 u_int32_t tpack; 6833 int error; 6834 6835 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 6836 error = sysctl_handle_int(oidp, &tpack, 0, req); 6837 if (error || !req->newptr) 6838 return error; 6839 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 6840} 6841 6842static int 6843ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6844{ 6845 struct ath_softc *sc = arg1; 6846 u_int32_t tpcts; 6847 int error; 6848 6849 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 6850 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6851 if (error || !req->newptr) 6852 return error; 6853 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 6854} 6855 6856static int 6857ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6858{ 6859 struct ath_softc *sc = arg1; 6860 int intmit, error; 6861 6862 intmit = ath_hal_getintmit(sc->sc_ah); 6863 error = sysctl_handle_int(oidp, &intmit, 0, req); 6864 if (error || !req->newptr) 6865 return error; 6866 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0; 6867} 6868 6869#ifdef ATH_SUPPORT_TDMA 6870static int 6871ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) 6872{ 6873 struct ath_softc *sc = arg1; 6874 int setcca, error; 6875 6876 setcca = sc->sc_setcca; 6877 error = sysctl_handle_int(oidp, &setcca, 0, req); 6878 if (error || !req->newptr) 6879 return error; 6880 sc->sc_setcca = (setcca != 0); 6881 return 0; 6882} 6883#endif /* ATH_SUPPORT_TDMA */ 6884 6885static void 6886ath_sysctlattach(struct ath_softc *sc) 6887{ 6888 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6889 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6890 struct ath_hal *ah = sc->sc_ah; 6891 6892 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6893 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6894 "EEPROM country code"); 6895 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6896 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6897 "EEPROM regdomain code"); 6898#ifdef ATH_DEBUG 6899 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6900 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6901 "control debugging printfs"); 6902#endif 6903 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6904 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6905 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6906 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6907 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6908 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6909 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6910 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6911 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6912 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6913 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6914 ath_sysctl_softled, "I", "enable/disable software LED support"); 6915 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6916 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6917 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6918 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6919 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6920 "setting to turn LED on"); 6921 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6922 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6923 "idle time for inactivity LED (ticks)"); 6924 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6925 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6926 ath_sysctl_txantenna, "I", "antenna switch"); 6927 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6928 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6929 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6930 if (ath_hal_hasdiversity(ah)) 6931 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6932 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6933 ath_sysctl_diversity, "I", "antenna diversity"); 6934 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6935 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6936 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6937 "tx descriptor batching"); 6938 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6939 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6940 ath_sysctl_diag, "I", "h/w diagnostic control"); 6941 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6942 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6943 ath_sysctl_tpscale, "I", "tx power scaling"); 6944 if (ath_hal_hastpc(ah)) { 6945 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6946 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6947 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6948 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6949 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6950 ath_sysctl_tpack, "I", "tx power for ack frames"); 6951 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6952 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6953 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6954 } 6955 if (ath_hal_hasfastframes(sc->sc_ah)) { 6956 sc->sc_fftxqmin = ATH_FF_TXQMIN; 6957 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6958 "fftxqmin", CTLFLAG_RW, &sc->sc_fftxqmin, 0, 6959 "min frames before fast-frame staging"); 6960 sc->sc_fftxqmax = ATH_FF_TXQMAX; 6961 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6962 "fftxqmax", CTLFLAG_RW, &sc->sc_fftxqmax, 0, 6963 "max queued frames before tail drop"); 6964 } 6965 if (ath_hal_hasrfsilent(ah)) { 6966 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6967 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6968 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6969 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6970 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6971 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6972 } 6973 if (ath_hal_hasintmit(ah)) { 6974 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6975 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6976 ath_sysctl_intmit, "I", "interference mitigation"); 6977 } 6978 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6979 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6980 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6981 "mask of error frames to pass when monitoring"); 6982#ifdef ATH_SUPPORT_TDMA 6983 if (ath_hal_macversion(ah) > 0x78) { 6984 sc->sc_tdmadbaprep = 2; 6985 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6986 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, 6987 "TDMA DBA preparation time"); 6988 sc->sc_tdmaswbaprep = 10; 6989 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6990 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, 6991 "TDMA SWBA preparation time"); 6992 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6993 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, 6994 "TDMA slot guard time"); 6995 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6996 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, 6997 "TDMA calculated super frame"); 6998 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6999 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 7000 ath_sysctl_setcca, "I", "enable CCA control"); 7001 } 7002#endif 7003} 7004 7005static void 7006ath_bpfattach(struct ath_softc *sc) 7007{ 7008 struct ifnet *ifp = sc->sc_ifp; 7009 7010 bpfattach(ifp, DLT_IEEE802_11_RADIO, 7011 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th)); 7012 /* 7013 * Initialize constant fields. 7014 * XXX make header lengths a multiple of 32-bits so subsequent 7015 * headers are properly aligned; this is a kludge to keep 7016 * certain applications happy. 7017 * 7018 * NB: the channel is setup each time we transition to the 7019 * RUN state to avoid filling it in for each frame. 7020 */ 7021 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 7022 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 7023 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 7024 7025 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 7026 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 7027 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 7028} 7029 7030static int 7031ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 7032 struct ath_buf *bf, struct mbuf *m0, 7033 const struct ieee80211_bpf_params *params) 7034{ 7035 struct ifnet *ifp = sc->sc_ifp; 7036 struct ieee80211com *ic = ifp->if_l2com; 7037 struct ath_hal *ah = sc->sc_ah; 7038 int error, ismcast, ismrr; 7039 int keyix, hdrlen, pktlen, try0, txantenna; 7040 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 7041 struct ieee80211_frame *wh; 7042 u_int flags, ctsduration; 7043 HAL_PKT_TYPE atype; 7044 const HAL_RATE_TABLE *rt; 7045 struct ath_desc *ds; 7046 u_int pri; 7047 7048 wh = mtod(m0, struct ieee80211_frame *); 7049 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 7050 hdrlen = ieee80211_anyhdrsize(wh); 7051 /* 7052 * Packet length must not include any 7053 * pad bytes; deduct them here. 7054 */ 7055 /* XXX honor IEEE80211_BPF_DATAPAD */ 7056 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 7057 7058 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 7059 const struct ieee80211_cipher *cip; 7060 struct ieee80211_key *k; 7061 7062 /* 7063 * Construct the 802.11 header+trailer for an encrypted 7064 * frame. The only reason this can fail is because of an 7065 * unknown or unsupported cipher/key type. 7066 */ 7067 k = ieee80211_crypto_encap(ni, m0); 7068 if (k == NULL) { 7069 /* 7070 * This can happen when the key is yanked after the 7071 * frame was queued. Just discard the frame; the 7072 * 802.11 layer counts failures and provides 7073 * debugging/diagnostics. 7074 */ 7075 ath_freetx(m0); 7076 return EIO; 7077 } 7078 /* 7079 * Adjust the packet + header lengths for the crypto 7080 * additions and calculate the h/w key index. When 7081 * a s/w mic is done the frame will have had any mic 7082 * added to it prior to entry so m0->m_pkthdr.len will 7083 * account for it. Otherwise we need to add it to the 7084 * packet length. 7085 */ 7086 cip = k->wk_cipher; 7087 hdrlen += cip->ic_header; 7088 pktlen += cip->ic_header + cip->ic_trailer; 7089 /* NB: frags always have any TKIP MIC done in s/w */ 7090 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 7091 pktlen += cip->ic_miclen; 7092 keyix = k->wk_keyix; 7093 7094 /* packet header may have moved, reset our local pointer */ 7095 wh = mtod(m0, struct ieee80211_frame *); 7096 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 7097 /* 7098 * Use station key cache slot, if assigned. 7099 */ 7100 keyix = ni->ni_ucastkey.wk_keyix; 7101 if (keyix == IEEE80211_KEYIX_NONE) 7102 keyix = HAL_TXKEYIX_INVALID; 7103 } else 7104 keyix = HAL_TXKEYIX_INVALID; 7105 7106 error = ath_tx_dmasetup(sc, bf, m0); 7107 if (error != 0) 7108 return error; 7109 m0 = bf->bf_m; /* NB: may have changed */ 7110 wh = mtod(m0, struct ieee80211_frame *); 7111 bf->bf_node = ni; /* NB: held reference */ 7112 7113 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 7114 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 7115 if (params->ibp_flags & IEEE80211_BPF_RTS) 7116 flags |= HAL_TXDESC_RTSENA; 7117 else if (params->ibp_flags & IEEE80211_BPF_CTS) 7118 flags |= HAL_TXDESC_CTSENA; 7119 /* XXX leave ismcast to injector? */ 7120 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 7121 flags |= HAL_TXDESC_NOACK; 7122 7123 rt = sc->sc_currates; 7124 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 7125 rix = ath_tx_findrix(rt, params->ibp_rate0); 7126 txrate = rt->info[rix].rateCode; 7127 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 7128 txrate |= rt->info[rix].shortPreamble; 7129 sc->sc_txrix = rix; 7130 try0 = params->ibp_try0; 7131 ismrr = (params->ibp_try1 != 0); 7132 txantenna = params->ibp_pri >> 2; 7133 if (txantenna == 0) /* XXX? */ 7134 txantenna = sc->sc_txantenna; 7135 ctsduration = 0; 7136 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 7137 cix = ath_tx_findrix(rt, params->ibp_ctsrate); 7138 ctsrate = rt->info[cix].rateCode; 7139 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 7140 ctsrate |= rt->info[cix].shortPreamble; 7141 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 7142 ctsduration += rt->info[cix].spAckDuration; 7143 ctsduration += ath_hal_computetxtime(ah, 7144 rt, pktlen, rix, AH_TRUE); 7145 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 7146 ctsduration += rt->info[rix].spAckDuration; 7147 } else { 7148 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 7149 ctsduration += rt->info[cix].lpAckDuration; 7150 ctsduration += ath_hal_computetxtime(ah, 7151 rt, pktlen, rix, AH_FALSE); 7152 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 7153 ctsduration += rt->info[rix].lpAckDuration; 7154 } 7155 ismrr = 0; /* XXX */ 7156 } else 7157 ctsrate = 0; 7158 pri = params->ibp_pri & 3; 7159 /* 7160 * NB: we mark all packets as type PSPOLL so the h/w won't 7161 * set the sequence number, duration, etc. 7162 */ 7163 atype = HAL_PKT_TYPE_PSPOLL; 7164 7165 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 7166 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 7167 sc->sc_hwmap[rix].ieeerate, -1); 7168 7169 if (bpf_peers_present(ifp->if_bpf)) { 7170 u_int64_t tsf = ath_hal_gettsf64(ah); 7171 7172 sc->sc_tx_th.wt_tsf = htole64(tsf); 7173 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 7174 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 7175 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 7176 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 7177 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 7178 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 7179 7180 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 7181 } 7182 7183 /* 7184 * Formulate first tx descriptor with tx controls. 7185 */ 7186 ds = bf->bf_desc; 7187 /* XXX check return value? */ 7188 ath_hal_setuptxdesc(ah, ds 7189 , pktlen /* packet length */ 7190 , hdrlen /* header length */ 7191 , atype /* Atheros packet type */ 7192 , params->ibp_power /* txpower */ 7193 , txrate, try0 /* series 0 rate/tries */ 7194 , keyix /* key cache index */ 7195 , txantenna /* antenna mode */ 7196 , flags /* flags */ 7197 , ctsrate /* rts/cts rate */ 7198 , ctsduration /* rts/cts duration */ 7199 ); 7200 bf->bf_txflags = flags; 7201 7202 if (ismrr) { 7203 rix = ath_tx_findrix(rt, params->ibp_rate1); 7204 rate1 = rt->info[rix].rateCode; 7205 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 7206 rate1 |= rt->info[rix].shortPreamble; 7207 if (params->ibp_try2) { 7208 rix = ath_tx_findrix(rt, params->ibp_rate2); 7209 rate2 = rt->info[rix].rateCode; 7210 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 7211 rate2 |= rt->info[rix].shortPreamble; 7212 } else 7213 rate2 = 0; 7214 if (params->ibp_try3) { 7215 rix = ath_tx_findrix(rt, params->ibp_rate3); 7216 rate3 = rt->info[rix].rateCode; 7217 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 7218 rate3 |= rt->info[rix].shortPreamble; 7219 } else 7220 rate3 = 0; 7221 ath_hal_setupxtxdesc(ah, ds 7222 , rate1, params->ibp_try1 /* series 1 */ 7223 , rate2, params->ibp_try2 /* series 2 */ 7224 , rate3, params->ibp_try3 /* series 3 */ 7225 ); 7226 } 7227 7228 /* NB: no buffered multicast in power save support */ 7229 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 7230 return 0; 7231} 7232 7233static int 7234ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 7235 const struct ieee80211_bpf_params *params) 7236{ 7237 struct ieee80211com *ic = ni->ni_ic; 7238 struct ifnet *ifp = ic->ic_ifp; 7239 struct ath_softc *sc = ifp->if_softc; 7240 struct ath_buf *bf; 7241 7242 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 7243 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 7244 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 7245 "!running" : "invalid"); 7246 sc->sc_stats.ast_tx_raw_fail++; 7247 ieee80211_free_node(ni); 7248 m_freem(m); 7249 return ENETDOWN; 7250 } 7251 /* 7252 * Grab a TX buffer and associated resources. 7253 */ 7254 bf = ath_getbuf(sc); 7255 if (bf == NULL) { 7256 /* NB: ath_getbuf handles stat+msg */ 7257 ieee80211_free_node(ni); 7258 m_freem(m); 7259 return ENOBUFS; 7260 } 7261 7262 ifp->if_opackets++; 7263 sc->sc_stats.ast_tx_raw++; 7264 7265 if (params == NULL) { 7266 /* 7267 * Legacy path; interpret frame contents to decide 7268 * precisely how to send the frame. 7269 */ 7270 if (ath_tx_start(sc, ni, bf, m)) 7271 goto bad; 7272 } else { 7273 /* 7274 * Caller supplied explicit parameters to use in 7275 * sending the frame. 7276 */ 7277 if (ath_tx_raw_start(sc, ni, bf, m, params)) 7278 goto bad; 7279 } 7280 sc->sc_wd_timer = 5; 7281 7282 return 0; 7283bad: 7284 ifp->if_oerrors++; 7285 ATH_TXBUF_LOCK(sc); 7286 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 7287 ATH_TXBUF_UNLOCK(sc); 7288 ieee80211_free_node(ni); 7289 return EIO; /* XXX */ 7290} 7291 7292/* 7293 * Announce various information on device/driver attach. 7294 */ 7295static void 7296ath_announce(struct ath_softc *sc) 7297{ 7298 struct ifnet *ifp = sc->sc_ifp; 7299 struct ath_hal *ah = sc->sc_ah; 7300 7301 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 7302 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 7303 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 7304 if (bootverbose) { 7305 int i; 7306 for (i = 0; i <= WME_AC_VO; i++) { 7307 struct ath_txq *txq = sc->sc_ac2q[i]; 7308 if_printf(ifp, "Use hw queue %u for %s traffic\n", 7309 txq->axq_qnum, ieee80211_wme_acnames[i]); 7310 } 7311 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 7312 sc->sc_cabq->axq_qnum); 7313 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 7314 } 7315 if (ath_rxbuf != ATH_RXBUF) 7316 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 7317 if (ath_txbuf != ATH_TXBUF) 7318 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 7319} 7320 7321#ifdef ATH_SUPPORT_TDMA 7322static __inline uint32_t 7323ath_hal_getnexttbtt(struct ath_hal *ah) 7324{ 7325#define AR_TIMER0 0x8028 7326 return OS_REG_READ(ah, AR_TIMER0); 7327} 7328 7329static __inline void 7330ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 7331{ 7332 /* XXX handle wrap/overflow */ 7333 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 7334} 7335 7336static void 7337ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 7338{ 7339 struct ath_hal *ah = sc->sc_ah; 7340 HAL_BEACON_TIMERS bt; 7341 7342 bt.bt_intval = bintval | HAL_BEACON_ENA; 7343 bt.bt_nexttbtt = nexttbtt; 7344 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 7345 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 7346 bt.bt_nextatim = nexttbtt+1; 7347 ath_hal_beaconsettimers(ah, &bt); 7348} 7349 7350/* 7351 * Calculate the beacon interval. This is periodic in the 7352 * superframe for the bss. We assume each station is configured 7353 * identically wrt transmit rate so the guard time we calculate 7354 * above will be the same on all stations. Note we need to 7355 * factor in the xmit time because the hardware will schedule 7356 * a frame for transmit if the start of the frame is within 7357 * the burst time. When we get hardware that properly kills 7358 * frames in the PCU we can reduce/eliminate the guard time. 7359 * 7360 * Roundup to 1024 is so we have 1 TU buffer in the guard time 7361 * to deal with the granularity of the nexttbtt timer. 11n MAC's 7362 * with 1us timer granularity should allow us to reduce/eliminate 7363 * this. 7364 */ 7365static void 7366ath_tdma_bintvalsetup(struct ath_softc *sc, 7367 const struct ieee80211_tdma_state *tdma) 7368{ 7369 /* copy from vap state (XXX check all vaps have same value?) */ 7370 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 7371 sc->sc_tdmabintcnt = tdma->tdma_bintval; 7372 7373 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 7374 tdma->tdma_slotcnt, 1024); 7375 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 7376 if (sc->sc_tdmabintval & 1) 7377 sc->sc_tdmabintval++; 7378 7379 if (tdma->tdma_slot == 0) { 7380 /* 7381 * Only slot 0 beacons; other slots respond. 7382 */ 7383 sc->sc_imask |= HAL_INT_SWBA; 7384 sc->sc_tdmaswba = 0; /* beacon immediately */ 7385 } else { 7386 /* XXX all vaps must be slot 0 or slot !0 */ 7387 sc->sc_imask &= ~HAL_INT_SWBA; 7388 } 7389} 7390 7391/* 7392 * Max 802.11 overhead. This assumes no 4-address frames and 7393 * the encapsulation done by ieee80211_encap (llc). We also 7394 * include potential crypto overhead. 7395 */ 7396#define IEEE80211_MAXOVERHEAD \ 7397 (sizeof(struct ieee80211_qosframe) \ 7398 + sizeof(struct llc) \ 7399 + IEEE80211_ADDR_LEN \ 7400 + IEEE80211_WEP_IVLEN \ 7401 + IEEE80211_WEP_KIDLEN \ 7402 + IEEE80211_WEP_CRCLEN \ 7403 + IEEE80211_WEP_MICLEN \ 7404 + IEEE80211_CRC_LEN) 7405 7406/* 7407 * Setup initially for tdma operation. Start the beacon 7408 * timers and enable SWBA if we are slot 0. Otherwise 7409 * we wait for slot 0 to arrive so we can sync up before 7410 * starting to transmit. 7411 */ 7412static void 7413ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 7414{ 7415 struct ath_hal *ah = sc->sc_ah; 7416 struct ifnet *ifp = sc->sc_ifp; 7417 struct ieee80211com *ic = ifp->if_l2com; 7418 const struct ieee80211_txparam *tp; 7419 const struct ieee80211_tdma_state *tdma = NULL; 7420 int rix; 7421 7422 if (vap == NULL) { 7423 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 7424 if (vap == NULL) { 7425 if_printf(ifp, "%s: no vaps?\n", __func__); 7426 return; 7427 } 7428 } 7429 tp = vap->iv_bss->ni_txparms; 7430 /* 7431 * Calculate the guard time for each slot. This is the 7432 * time to send a maximal-size frame according to the 7433 * fixed/lowest transmit rate. Note that the interface 7434 * mtu does not include the 802.11 overhead so we must 7435 * tack that on (ath_hal_computetxtime includes the 7436 * preamble and plcp in it's calculation). 7437 */ 7438 tdma = vap->iv_tdma; 7439 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 7440 rix = ath_tx_findrix(sc->sc_currates, tp->ucastrate); 7441 else 7442 rix = ath_tx_findrix(sc->sc_currates, tp->mcastrate); 7443 /* XXX short preamble assumed */ 7444 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 7445 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 7446 7447 ath_hal_intrset(ah, 0); 7448 7449 ath_beaconq_config(sc); /* setup h/w beacon q */ 7450 if (sc->sc_setcca) 7451 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 7452 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 7453 ath_tdma_settimers(sc, sc->sc_tdmabintval, 7454 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 7455 sc->sc_syncbeacon = 0; 7456 7457 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 7458 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 7459 7460 ath_hal_intrset(ah, sc->sc_imask); 7461 7462 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 7463 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 7464 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 7465 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 7466 sc->sc_tdmadbaprep); 7467} 7468 7469/* 7470 * Update tdma operation. Called from the 802.11 layer 7471 * when a beacon is received from the TDMA station operating 7472 * in the slot immediately preceding us in the bss. Use 7473 * the rx timestamp for the beacon frame to update our 7474 * beacon timers so we follow their schedule. Note that 7475 * by using the rx timestamp we implicitly include the 7476 * propagation delay in our schedule. 7477 */ 7478static void 7479ath_tdma_update(struct ieee80211_node *ni, 7480 const struct ieee80211_tdma_param *tdma) 7481{ 7482#define TSF_TO_TU(_h,_l) \ 7483 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 7484#define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 7485 struct ieee80211vap *vap = ni->ni_vap; 7486 struct ieee80211com *ic = ni->ni_ic; 7487 struct ath_softc *sc = ic->ic_ifp->if_softc; 7488 struct ath_hal *ah = sc->sc_ah; 7489 const HAL_RATE_TABLE *rt = sc->sc_currates; 7490 u_int64_t tsf, rstamp, nextslot; 7491 u_int32_t txtime, nextslottu, timer0; 7492 int32_t tudelta, tsfdelta; 7493 const struct ath_rx_status *rs; 7494 int rix; 7495 7496 sc->sc_stats.ast_tdma_update++; 7497 7498 /* 7499 * Check for and adopt configuration changes. 7500 */ 7501 if (isset(ATH_VAP(vap)->av_boff.bo_flags, IEEE80211_BEACON_TDMA)) { 7502 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 7503 7504 ath_tdma_bintvalsetup(sc, ts); 7505 7506 DPRINTF(sc, ATH_DEBUG_TDMA, 7507 "%s: adopt slot %u slotcnt %u slotlen %u us " 7508 "bintval %u TU\n", __func__, 7509 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 7510 sc->sc_tdmabintval); 7511 7512 ath_beaconq_config(sc); 7513 /* XXX right? */ 7514 ath_hal_intrset(ah, sc->sc_imask); 7515 /* NB: beacon timers programmed below */ 7516 } 7517 7518 /* extend rx timestamp to 64 bits */ 7519 tsf = ath_hal_gettsf64(ah); 7520 rstamp = ath_extend_tsf(ni->ni_rstamp, tsf); 7521 /* 7522 * The rx timestamp is set by the hardware on completing 7523 * reception (at the point where the rx descriptor is DMA'd 7524 * to the host). To find the start of our next slot we 7525 * must adjust this time by the time required to send 7526 * the packet just received. 7527 */ 7528 rs = sc->sc_tdmars; 7529 rix = rt->rateCodeToIndex[rs->rs_rate]; 7530 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 7531 rt->info[rix].shortPreamble); 7532 /* NB: << 9 is to cvt to TU and /2 */ 7533 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 7534 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 7535 7536 /* 7537 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 7538 * to usecs and calculate the difference between what the 7539 * other station thinks and what we have programmed. This 7540 * lets us figure how to adjust our timers to match. The 7541 * adjustments are done by pulling the TSF forward and possibly 7542 * rewriting the beacon timers. 7543 */ 7544 timer0 = ath_hal_getnexttbtt(ah); 7545 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 7546 7547 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7548 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 7549 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 7550 7551 if (tsfdelta < 0) { 7552 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7553 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 7554 tsfdelta = -tsfdelta % 1024; 7555 nextslottu++; 7556 } else if (tsfdelta > 0) { 7557 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 7558 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7559 tsfdelta = 1024 - (tsfdelta % 1024); 7560 nextslottu++; 7561 } else { 7562 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7563 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7564 } 7565 tudelta = nextslottu - timer0; 7566 7567 /* 7568 * Copy sender's timetstamp into tdma ie so they can 7569 * calculate roundtrip time. We submit a beacon frame 7570 * below after any timer adjustment. The frame goes out 7571 * at the next TBTT so the sender can calculate the 7572 * roundtrip by inspecting the tdma ie in our beacon frame. 7573 * 7574 * NB: This tstamp is subtlely preserved when 7575 * IEEE80211_BEACON_TDMA is marked (e.g. when the 7576 * slot position changes) because ieee80211_add_tdma 7577 * skips over the data. 7578 */ 7579 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 7580 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 7581 &ni->ni_tstamp.data, 8); 7582#if 0 7583 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7584 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 7585 (unsigned long long) tsf, (unsigned long long) nextslot, 7586 (int)(nextslot - tsf), tsfdelta, 7587 nextslottu, timer0, tudelta); 7588#endif 7589 /* 7590 * Adjust the beacon timers only when pulling them forward 7591 * or when going back by less than the beacon interval. 7592 * Negative jumps larger than the beacon interval seem to 7593 * cause the timers to stop and generally cause instability. 7594 * This basically filters out jumps due to missed beacons. 7595 */ 7596 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 7597 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 7598 sc->sc_stats.ast_tdma_timers++; 7599 } 7600 if (tsfdelta > 0) { 7601 ath_hal_adjusttsf(ah, tsfdelta); 7602 sc->sc_stats.ast_tdma_tsf++; 7603 } 7604 ath_tdma_beacon_send(sc, vap); /* prepare response */ 7605#undef TU_TO_TSF 7606#undef TSF_TO_TU 7607} 7608 7609/* 7610 * Transmit a beacon frame at SWBA. Dynamic updates 7611 * to the frame contents are done as needed. 7612 */ 7613static void 7614ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 7615{ 7616 struct ath_hal *ah = sc->sc_ah; 7617 struct ath_buf *bf; 7618 int otherant; 7619 7620 /* 7621 * Check if the previous beacon has gone out. If 7622 * not don't try to post another, skip this period 7623 * and wait for the next. Missed beacons indicate 7624 * a problem and should not occur. If we miss too 7625 * many consecutive beacons reset the device. 7626 */ 7627 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 7628 sc->sc_bmisscount++; 7629 DPRINTF(sc, ATH_DEBUG_BEACON, 7630 "%s: missed %u consecutive beacons\n", 7631 __func__, sc->sc_bmisscount); 7632 if (sc->sc_bmisscount >= ath_bstuck_threshold) 7633 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 7634 return; 7635 } 7636 if (sc->sc_bmisscount != 0) { 7637 DPRINTF(sc, ATH_DEBUG_BEACON, 7638 "%s: resume beacon xmit after %u misses\n", 7639 __func__, sc->sc_bmisscount); 7640 sc->sc_bmisscount = 0; 7641 } 7642 7643 /* 7644 * Check recent per-antenna transmit statistics and flip 7645 * the default antenna if noticeably more frames went out 7646 * on the non-default antenna. 7647 * XXX assumes 2 anntenae 7648 */ 7649 if (!sc->sc_diversity) { 7650 otherant = sc->sc_defant & 1 ? 2 : 1; 7651 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 7652 ath_setdefantenna(sc, otherant); 7653 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 7654 } 7655 7656 bf = ath_beacon_generate(sc, vap); 7657 if (bf != NULL) { 7658 /* 7659 * Stop any current dma and put the new frame on the queue. 7660 * This should never fail since we check above that no frames 7661 * are still pending on the queue. 7662 */ 7663 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 7664 DPRINTF(sc, ATH_DEBUG_ANY, 7665 "%s: beacon queue %u did not stop?\n", 7666 __func__, sc->sc_bhalq); 7667 /* NB: the HAL still stops DMA, so proceed */ 7668 } 7669 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 7670 ath_hal_txstart(ah, sc->sc_bhalq); 7671 7672 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 7673 7674 /* 7675 * Record local TSF for our last send for use 7676 * in arbitrating slot collisions. 7677 */ 7678 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 7679 } 7680} 7681#endif /* ATH_SUPPORT_TDMA */ 7682