if_ath.c revision 185479
1/*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 185479 2008-11-30 18:27:10Z sam $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sysctl.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/kernel.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/errno.h> 54#include <sys/callout.h> 55#include <sys/bus.h> 56#include <sys/endian.h> 57#include <sys/kthread.h> 58#include <sys/taskqueue.h> 59 60#include <machine/bus.h> 61 62#include <net/if.h> 63#include <net/if_dl.h> 64#include <net/if_media.h> 65#include <net/if_types.h> 66#include <net/if_arp.h> 67#include <net/ethernet.h> 68#include <net/if_llc.h> 69 70#include <net80211/ieee80211_var.h> 71 72#include <net/bpf.h> 73 74#ifdef INET 75#include <netinet/in.h> 76#include <netinet/if_ether.h> 77#endif 78 79#include <dev/ath/if_athvar.h> 80#include <contrib/dev/ath/ah_desc.h> 81#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 82 83#ifdef ATH_TX99_DIAG 84#include <dev/ath/ath_tx99/ath_tx99.h> 85#endif 86 87/* 88 * We require a HAL w/ the changes for split tx/rx MIC. 89 */ 90CTASSERT(HAL_ABI_VERSION > 0x06052200); 91 92/* 93 * ATH_BCBUF determines the number of vap's that can transmit 94 * beacons and also (currently) the number of vap's that can 95 * have unique mac addresses/bssid. When staggering beacons 96 * 4 is probably a good max as otherwise the beacons become 97 * very closely spaced and there is limited time for cab q traffic 98 * to go out. You can burst beacons instead but that is not good 99 * for stations in power save and at some point you really want 100 * another radio (and channel). 101 * 102 * The limit on the number of mac addresses is tied to our use of 103 * the U/L bit and tracking addresses in a byte; it would be 104 * worthwhile to allow more for applications like proxy sta. 105 */ 106CTASSERT(ATH_BCBUF <= 8); 107 108/* unaligned little endian access */ 109#define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112#define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117#define CTRY_XR9 5001 /* Ubiquiti XR9 */ 118#define CTRY_GZ901 5002 /* ZComax GZ-901 */ 119 120static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 121 const char name[IFNAMSIZ], int unit, int opmode, 122 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 123 const uint8_t mac[IEEE80211_ADDR_LEN]); 124static void ath_vap_delete(struct ieee80211vap *); 125static void ath_init(void *); 126static void ath_stop_locked(struct ifnet *); 127static void ath_stop(struct ifnet *); 128static void ath_start(struct ifnet *); 129static int ath_reset(struct ifnet *); 130static int ath_reset_vap(struct ieee80211vap *, u_long); 131static int ath_media_change(struct ifnet *); 132static void ath_watchdog(struct ifnet *); 133static int ath_ioctl(struct ifnet *, u_long, caddr_t); 134static void ath_fatal_proc(void *, int); 135static void ath_bmiss_vap(struct ieee80211vap *); 136static void ath_bmiss_proc(void *, int); 137static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 138 struct ieee80211_node *); 139static int ath_key_alloc(struct ieee80211vap *, 140 struct ieee80211_key *, 141 ieee80211_keyix *, ieee80211_keyix *); 142static int ath_key_delete(struct ieee80211vap *, 143 const struct ieee80211_key *); 144static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 145 const u_int8_t mac[IEEE80211_ADDR_LEN]); 146static void ath_key_update_begin(struct ieee80211vap *); 147static void ath_key_update_end(struct ieee80211vap *); 148static void ath_update_mcast(struct ifnet *); 149static void ath_update_promisc(struct ifnet *); 150static void ath_mode_init(struct ath_softc *); 151static void ath_setslottime(struct ath_softc *); 152static void ath_updateslot(struct ifnet *); 153static int ath_beaconq_setup(struct ath_hal *); 154static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 155static void ath_beacon_update(struct ieee80211vap *, int item); 156static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 157static void ath_beacon_proc(void *, int); 158static struct ath_buf *ath_beacon_generate(struct ath_softc *, 159 struct ieee80211vap *); 160static void ath_bstuck_proc(void *, int); 161static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 162static void ath_beacon_free(struct ath_softc *); 163static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 164static void ath_descdma_cleanup(struct ath_softc *sc, 165 struct ath_descdma *, ath_bufhead *); 166static int ath_desc_alloc(struct ath_softc *); 167static void ath_desc_free(struct ath_softc *); 168static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 169 const uint8_t [IEEE80211_ADDR_LEN]); 170static void ath_node_free(struct ieee80211_node *); 171static void ath_node_getsignal(const struct ieee80211_node *, 172 int8_t *, int8_t *); 173static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 174static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 175 int subtype, int rssi, int noise, u_int32_t rstamp); 176static void ath_setdefantenna(struct ath_softc *, u_int); 177static void ath_rx_proc(void *, int); 178static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 179static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 180static int ath_tx_setup(struct ath_softc *, int, int); 181static int ath_wme_update(struct ieee80211com *); 182static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 183static void ath_tx_cleanup(struct ath_softc *); 184static void ath_freetx(struct mbuf *); 185static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 186 struct ath_buf *, struct mbuf *); 187static void ath_tx_proc_q0(void *, int); 188static void ath_tx_proc_q0123(void *, int); 189static void ath_tx_proc(void *, int); 190static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 191static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 192static void ath_draintxq(struct ath_softc *); 193static void ath_stoprecv(struct ath_softc *); 194static int ath_startrecv(struct ath_softc *); 195static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 196static void ath_scan_start(struct ieee80211com *); 197static void ath_scan_end(struct ieee80211com *); 198static void ath_set_channel(struct ieee80211com *); 199static void ath_calibrate(void *); 200static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 201static void ath_setup_stationkey(struct ieee80211_node *); 202static void ath_newassoc(struct ieee80211_node *, int); 203static int ath_setregdomain(struct ieee80211com *, 204 struct ieee80211_regdomain *, int, 205 struct ieee80211_channel []); 206static void ath_getradiocaps(struct ieee80211com *, int *, 207 struct ieee80211_channel []); 208static int ath_getchannels(struct ath_softc *); 209static void ath_led_event(struct ath_softc *, int); 210 211static int ath_rate_setup(struct ath_softc *, u_int mode); 212static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 213 214static void ath_sysctlattach(struct ath_softc *); 215static int ath_raw_xmit(struct ieee80211_node *, 216 struct mbuf *, const struct ieee80211_bpf_params *); 217static void ath_bpfattach(struct ath_softc *); 218static void ath_announce(struct ath_softc *); 219 220SYSCTL_DECL(_hw_ath); 221 222/* XXX validate sysctl values */ 223static int ath_calinterval = 30; /* calibrate every 30 secs */ 224SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 225 0, "chip calibration interval (secs)"); 226 227static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 228SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 229 0, "rx buffers allocated"); 230TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 231static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 232SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 233 0, "tx buffers allocated"); 234TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 235 236#ifdef ATH_DEBUG 237enum { 238 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 239 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 240 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 241 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 242 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 243 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 244 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 245 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 246 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 247 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 248 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 249 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 250 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 251 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 252 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 253 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 254 ATH_DEBUG_NODE = 0x00080000, /* node management */ 255 ATH_DEBUG_LED = 0x00100000, /* led management */ 256 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 257 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 258 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 259 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 260 ATH_DEBUG_ANY = 0xffffffff 261}; 262static int ath_debug = 0; 263SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 264 0, "control debugging printfs"); 265TUNABLE_INT("hw.ath.debug", &ath_debug); 266 267#define IFF_DUMPPKTS(sc, m) \ 268 ((sc->sc_debug & (m)) || \ 269 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 270#define DPRINTF(sc, m, fmt, ...) do { \ 271 if (sc->sc_debug & (m)) \ 272 printf(fmt, __VA_ARGS__); \ 273} while (0) 274#define KEYPRINTF(sc, ix, hk, mac) do { \ 275 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 276 ath_keyprint(sc, __func__, ix, hk, mac); \ 277} while (0) 278static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 279 u_int ix, int); 280static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 281 u_int qnum, u_int ix, int done); 282#else 283#define IFF_DUMPPKTS(sc, m) \ 284 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 285#define DPRINTF(sc, m, fmt, ...) do { \ 286 (void) sc; \ 287} while (0) 288#define KEYPRINTF(sc, k, ix, mac) do { \ 289 (void) sc; \ 290} while (0) 291#endif 292 293MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 294 295int 296ath_attach(u_int16_t devid, struct ath_softc *sc) 297{ 298 struct ifnet *ifp; 299 struct ieee80211com *ic; 300 struct ath_hal *ah = NULL; 301 HAL_STATUS status; 302 int error = 0, i; 303 u_int wmodes; 304 305 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 306 307 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 308 if (ifp == NULL) { 309 device_printf(sc->sc_dev, "can not if_alloc()\n"); 310 error = ENOSPC; 311 goto bad; 312 } 313 ic = ifp->if_l2com; 314 315 /* set these up early for if_printf use */ 316 if_initname(ifp, device_get_name(sc->sc_dev), 317 device_get_unit(sc->sc_dev)); 318 319 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 320 if (ah == NULL) { 321 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 322 status); 323 error = ENXIO; 324 goto bad; 325 } 326 if (ah->ah_abi != HAL_ABI_VERSION) { 327 if_printf(ifp, "HAL ABI mismatch detected " 328 "(HAL:0x%x != driver:0x%x)\n", 329 ah->ah_abi, HAL_ABI_VERSION); 330 error = ENXIO; 331 goto bad; 332 } 333 sc->sc_ah = ah; 334 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 335#ifdef ATH_DEBUG 336 sc->sc_debug = ath_debug; 337#endif 338 339 /* 340 * Check if the MAC has multi-rate retry support. 341 * We do this by trying to setup a fake extended 342 * descriptor. MAC's that don't have support will 343 * return false w/o doing anything. MAC's that do 344 * support it will return true w/o doing anything. 345 */ 346 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 347 348 /* 349 * Check if the device has hardware counters for PHY 350 * errors. If so we need to enable the MIB interrupt 351 * so we can act on stat triggers. 352 */ 353 if (ath_hal_hwphycounters(ah)) 354 sc->sc_needmib = 1; 355 356 /* 357 * Get the hardware key cache size. 358 */ 359 sc->sc_keymax = ath_hal_keycachesize(ah); 360 if (sc->sc_keymax > ATH_KEYMAX) { 361 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 362 ATH_KEYMAX, sc->sc_keymax); 363 sc->sc_keymax = ATH_KEYMAX; 364 } 365 /* 366 * Reset the key cache since some parts do not 367 * reset the contents on initial power up. 368 */ 369 for (i = 0; i < sc->sc_keymax; i++) 370 ath_hal_keyreset(ah, i); 371 372 /* 373 * Collect the default channel list. 374 */ 375 error = ath_getchannels(sc); 376 if (error != 0) 377 goto bad; 378 379 /* 380 * Setup rate tables for all potential media types. 381 */ 382 ath_rate_setup(sc, IEEE80211_MODE_11A); 383 ath_rate_setup(sc, IEEE80211_MODE_11B); 384 ath_rate_setup(sc, IEEE80211_MODE_11G); 385 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 386 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 387 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 388 ath_rate_setup(sc, IEEE80211_MODE_11NA); 389 ath_rate_setup(sc, IEEE80211_MODE_11NG); 390 ath_rate_setup(sc, IEEE80211_MODE_HALF); 391 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 392 393 /* NB: setup here so ath_rate_update is happy */ 394 ath_setcurmode(sc, IEEE80211_MODE_11A); 395 396 /* 397 * Allocate tx+rx descriptors and populate the lists. 398 */ 399 error = ath_desc_alloc(sc); 400 if (error != 0) { 401 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 402 goto bad; 403 } 404 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 405 406 ATH_TXBUF_LOCK_INIT(sc); 407 408 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 409 taskqueue_thread_enqueue, &sc->sc_tq); 410 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 411 "%s taskq", ifp->if_xname); 412 413 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 414 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 415 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 416 417 /* 418 * Allocate hardware transmit queues: one queue for 419 * beacon frames and one data queue for each QoS 420 * priority. Note that the hal handles reseting 421 * these queues at the needed time. 422 * 423 * XXX PS-Poll 424 */ 425 sc->sc_bhalq = ath_beaconq_setup(ah); 426 if (sc->sc_bhalq == (u_int) -1) { 427 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 428 error = EIO; 429 goto bad2; 430 } 431 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 432 if (sc->sc_cabq == NULL) { 433 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 434 error = EIO; 435 goto bad2; 436 } 437 /* NB: insure BK queue is the lowest priority h/w queue */ 438 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 439 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 440 ieee80211_wme_acnames[WME_AC_BK]); 441 error = EIO; 442 goto bad2; 443 } 444 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 445 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 446 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 447 /* 448 * Not enough hardware tx queues to properly do WME; 449 * just punt and assign them all to the same h/w queue. 450 * We could do a better job of this if, for example, 451 * we allocate queues when we switch from station to 452 * AP mode. 453 */ 454 if (sc->sc_ac2q[WME_AC_VI] != NULL) 455 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 456 if (sc->sc_ac2q[WME_AC_BE] != NULL) 457 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 458 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 459 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 460 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 461 } 462 463 /* 464 * Special case certain configurations. Note the 465 * CAB queue is handled by these specially so don't 466 * include them when checking the txq setup mask. 467 */ 468 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 469 case 0x01: 470 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 471 break; 472 case 0x0f: 473 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 474 break; 475 default: 476 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 477 break; 478 } 479 480 /* 481 * Setup rate control. Some rate control modules 482 * call back to change the anntena state so expose 483 * the necessary entry points. 484 * XXX maybe belongs in struct ath_ratectrl? 485 */ 486 sc->sc_setdefantenna = ath_setdefantenna; 487 sc->sc_rc = ath_rate_attach(sc); 488 if (sc->sc_rc == NULL) { 489 error = EIO; 490 goto bad2; 491 } 492 493 sc->sc_blinking = 0; 494 sc->sc_ledstate = 1; 495 sc->sc_ledon = 0; /* low true */ 496 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 497 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 498 /* 499 * Auto-enable soft led processing for IBM cards and for 500 * 5211 minipci cards. Users can also manually enable/disable 501 * support with a sysctl. 502 */ 503 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 504 if (sc->sc_softled) { 505 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 506 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 507 } 508 509 ifp->if_softc = sc; 510 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 511 ifp->if_start = ath_start; 512 ifp->if_watchdog = ath_watchdog; 513 ifp->if_ioctl = ath_ioctl; 514 ifp->if_init = ath_init; 515 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 516 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 517 IFQ_SET_READY(&ifp->if_snd); 518 519 ic->ic_ifp = ifp; 520 /* XXX not right but it's not used anywhere important */ 521 ic->ic_phytype = IEEE80211_T_OFDM; 522 ic->ic_opmode = IEEE80211_M_STA; 523 ic->ic_caps = 524 IEEE80211_C_STA /* station mode */ 525 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 526 | IEEE80211_C_HOSTAP /* hostap mode */ 527 | IEEE80211_C_MONITOR /* monitor mode */ 528 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 529 | IEEE80211_C_WDS /* 4-address traffic works */ 530 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 531 | IEEE80211_C_SHSLOT /* short slot time supported */ 532 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 533 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 534 | IEEE80211_C_TXFRAG /* handle tx frags */ 535 ; 536 /* 537 * Query the hal to figure out h/w crypto support. 538 */ 539 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 540 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 541 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 542 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 543 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 544 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 545 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 546 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 547 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 548 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 549 /* 550 * Check if h/w does the MIC and/or whether the 551 * separate key cache entries are required to 552 * handle both tx+rx MIC keys. 553 */ 554 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 555 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 556 /* 557 * If the h/w supports storing tx+rx MIC keys 558 * in one cache slot automatically enable use. 559 */ 560 if (ath_hal_hastkipsplit(ah) || 561 !ath_hal_settkipsplit(ah, AH_FALSE)) 562 sc->sc_splitmic = 1; 563 /* 564 * If the h/w can do TKIP MIC together with WME then 565 * we use it; otherwise we force the MIC to be done 566 * in software by the net80211 layer. 567 */ 568 if (ath_hal_haswmetkipmic(ah)) 569 sc->sc_wmetkipmic = 1; 570 } 571 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 572 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 573 /* 574 * Mark key cache slots associated with global keys 575 * as in use. If we knew TKIP was not to be used we 576 * could leave the +32, +64, and +32+64 slots free. 577 */ 578 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 579 setbit(sc->sc_keymap, i); 580 setbit(sc->sc_keymap, i+64); 581 if (sc->sc_splitmic) { 582 setbit(sc->sc_keymap, i+32); 583 setbit(sc->sc_keymap, i+32+64); 584 } 585 } 586 /* 587 * TPC support can be done either with a global cap or 588 * per-packet support. The latter is not available on 589 * all parts. We're a bit pedantic here as all parts 590 * support a global cap. 591 */ 592 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 593 ic->ic_caps |= IEEE80211_C_TXPMGT; 594 595 /* 596 * Mark WME capability only if we have sufficient 597 * hardware queues to do proper priority scheduling. 598 */ 599 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 600 ic->ic_caps |= IEEE80211_C_WME; 601 /* 602 * Check for misc other capabilities. 603 */ 604 if (ath_hal_hasbursting(ah)) 605 ic->ic_caps |= IEEE80211_C_BURST; 606 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 607 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 608 if (ath_hal_hasfastframes(ah)) 609 ic->ic_caps |= IEEE80211_C_FF; 610 wmodes = ath_hal_getwirelessmodes(ah, ic->ic_regdomain.country); 611 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 612 ic->ic_caps |= IEEE80211_C_TURBOP; 613 614 /* 615 * Indicate we need the 802.11 header padded to a 616 * 32-bit boundary for 4-address and QoS frames. 617 */ 618 ic->ic_flags |= IEEE80211_F_DATAPAD; 619 620 /* 621 * Query the hal about antenna support. 622 */ 623 sc->sc_defant = ath_hal_getdefantenna(ah); 624 625 /* 626 * Not all chips have the VEOL support we want to 627 * use with IBSS beacons; check here for it. 628 */ 629 sc->sc_hasveol = ath_hal_hasveol(ah); 630 631 /* get mac address from hardware */ 632 ath_hal_getmac(ah, ic->ic_myaddr); 633 if (sc->sc_hasbmask) 634 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 635 636 /* NB: used to size node table key mapping array */ 637 ic->ic_max_keyix = sc->sc_keymax; 638 /* call MI attach routine. */ 639 ieee80211_ifattach(ic); 640 ic->ic_setregdomain = ath_setregdomain; 641 ic->ic_getradiocaps = ath_getradiocaps; 642 sc->sc_opmode = HAL_M_STA; 643 644 /* override default methods */ 645 ic->ic_newassoc = ath_newassoc; 646 ic->ic_updateslot = ath_updateslot; 647 ic->ic_wme.wme_update = ath_wme_update; 648 ic->ic_vap_create = ath_vap_create; 649 ic->ic_vap_delete = ath_vap_delete; 650 ic->ic_raw_xmit = ath_raw_xmit; 651 ic->ic_update_mcast = ath_update_mcast; 652 ic->ic_update_promisc = ath_update_promisc; 653 ic->ic_node_alloc = ath_node_alloc; 654 sc->sc_node_free = ic->ic_node_free; 655 ic->ic_node_free = ath_node_free; 656 ic->ic_node_getsignal = ath_node_getsignal; 657 ic->ic_scan_start = ath_scan_start; 658 ic->ic_scan_end = ath_scan_end; 659 ic->ic_set_channel = ath_set_channel; 660 661 ath_bpfattach(sc); 662 /* 663 * Setup dynamic sysctl's now that country code and 664 * regdomain are available from the hal. 665 */ 666 ath_sysctlattach(sc); 667 668 if (bootverbose) 669 ieee80211_announce(ic); 670 ath_announce(sc); 671 return 0; 672bad2: 673 ath_tx_cleanup(sc); 674 ath_desc_free(sc); 675bad: 676 if (ah) 677 ath_hal_detach(ah); 678 if (ifp != NULL) 679 if_free(ifp); 680 sc->sc_invalid = 1; 681 return error; 682} 683 684int 685ath_detach(struct ath_softc *sc) 686{ 687 struct ifnet *ifp = sc->sc_ifp; 688 689 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 690 __func__, ifp->if_flags); 691 692 /* 693 * NB: the order of these is important: 694 * o stop the chip so no more interrupts will fire 695 * o call the 802.11 layer before detaching the hal to 696 * insure callbacks into the driver to delete global 697 * key cache entries can be handled 698 * o free the taskqueue which drains any pending tasks 699 * o reclaim the bpf tap now that we know nothing will use 700 * it (e.g. rx processing from the task q thread) 701 * o reclaim the tx queue data structures after calling 702 * the 802.11 layer as we'll get called back to reclaim 703 * node state and potentially want to use them 704 * o to cleanup the tx queues the hal is called, so detach 705 * it last 706 * Other than that, it's straightforward... 707 */ 708 ath_stop(ifp); 709 ieee80211_ifdetach(ifp->if_l2com); 710 taskqueue_free(sc->sc_tq); 711 bpfdetach(ifp); 712#ifdef ATH_TX99_DIAG 713 if (sc->sc_tx99 != NULL) 714 sc->sc_tx99->detach(sc->sc_tx99); 715#endif 716 ath_rate_detach(sc->sc_rc); 717 ath_desc_free(sc); 718 ath_tx_cleanup(sc); 719 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 720 if_free(ifp); 721 722 return 0; 723} 724 725/* 726 * MAC address handling for multiple BSS on the same radio. 727 * The first vap uses the MAC address from the EEPROM. For 728 * subsequent vap's we set the U/L bit (bit 1) in the MAC 729 * address and use the next six bits as an index. 730 */ 731static void 732assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 733{ 734 int i; 735 736 if (clone && sc->sc_hasbmask) { 737 /* NB: we only do this if h/w supports multiple bssid */ 738 for (i = 0; i < 8; i++) 739 if ((sc->sc_bssidmask & (1<<i)) == 0) 740 break; 741 if (i != 0) 742 mac[0] |= (i << 2)|0x2; 743 } else 744 i = 0; 745 sc->sc_bssidmask |= 1<<i; 746 sc->sc_hwbssidmask[0] &= ~mac[0]; 747 if (i == 0) 748 sc->sc_nbssid0++; 749} 750 751static void 752reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 753{ 754 int i = mac[0] >> 2; 755 uint8_t mask; 756 757 if (i != 0 || --sc->sc_nbssid0 == 0) { 758 sc->sc_bssidmask &= ~(1<<i); 759 /* recalculate bssid mask from remaining addresses */ 760 mask = 0xff; 761 for (i = 1; i < 8; i++) 762 if (sc->sc_bssidmask & (1<<i)) 763 mask &= ~((i<<2)|0x2); 764 sc->sc_hwbssidmask[0] |= mask; 765 } 766} 767 768/* 769 * Assign a beacon xmit slot. We try to space out 770 * assignments so when beacons are staggered the 771 * traffic coming out of the cab q has maximal time 772 * to go out before the next beacon is scheduled. 773 */ 774static int 775assign_bslot(struct ath_softc *sc) 776{ 777 u_int slot, free; 778 779 free = 0; 780 for (slot = 0; slot < ATH_BCBUF; slot++) 781 if (sc->sc_bslot[slot] == NULL) { 782 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 783 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 784 return slot; 785 free = slot; 786 /* NB: keep looking for a double slot */ 787 } 788 return free; 789} 790 791static struct ieee80211vap * 792ath_vap_create(struct ieee80211com *ic, 793 const char name[IFNAMSIZ], int unit, int opmode, int flags, 794 const uint8_t bssid[IEEE80211_ADDR_LEN], 795 const uint8_t mac0[IEEE80211_ADDR_LEN]) 796{ 797 struct ath_softc *sc = ic->ic_ifp->if_softc; 798 struct ath_vap *avp; 799 struct ieee80211vap *vap; 800 uint8_t mac[IEEE80211_ADDR_LEN]; 801 int ic_opmode, needbeacon, error; 802 803 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 804 M_80211_VAP, M_WAITOK | M_ZERO); 805 needbeacon = 0; 806 IEEE80211_ADDR_COPY(mac, mac0); 807 808 ATH_LOCK(sc); 809 switch (opmode) { 810 case IEEE80211_M_STA: 811 if (sc->sc_nstavaps != 0) { /* XXX only 1 sta for now */ 812 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 813 goto bad; 814 } 815 if (sc->sc_nvaps) { 816 /* 817 * When there are multiple vaps we must fall 818 * back to s/w beacon miss handling. 819 */ 820 flags |= IEEE80211_CLONE_NOBEACONS; 821 } 822 if (flags & IEEE80211_CLONE_NOBEACONS) { 823 sc->sc_swbmiss = 1; 824 ic_opmode = IEEE80211_M_HOSTAP; 825 } else 826 ic_opmode = opmode; 827 break; 828 case IEEE80211_M_IBSS: 829 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 830 device_printf(sc->sc_dev, 831 "only 1 ibss vap supported\n"); 832 goto bad; 833 } 834 ic_opmode = opmode; 835 needbeacon = 1; 836 break; 837 case IEEE80211_M_AHDEMO: 838 /* fall thru... */ 839 case IEEE80211_M_MONITOR: 840 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 841 /* XXX not right for monitor mode */ 842 ic_opmode = ic->ic_opmode; 843 } else 844 ic_opmode = opmode; 845 break; 846 case IEEE80211_M_HOSTAP: 847 needbeacon = 1; 848 /* fall thru... */ 849 case IEEE80211_M_WDS: 850 if (sc->sc_nvaps && ic->ic_opmode == IEEE80211_M_STA) { 851 device_printf(sc->sc_dev, 852 "wds not supported in sta mode\n"); 853 goto bad; 854 } 855 if (opmode == IEEE80211_M_WDS) { 856 /* 857 * Silently remove any request for a unique 858 * bssid; WDS vap's always share the local 859 * mac address. 860 */ 861 flags &= ~IEEE80211_CLONE_BSSID; 862 } 863 ic_opmode = IEEE80211_M_HOSTAP; 864 break; 865 default: 866 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 867 goto bad; 868 } 869 /* 870 * Check that a beacon buffer is available; the code below assumes it. 871 */ 872 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 873 device_printf(sc->sc_dev, "no beacon buffer available\n"); 874 goto bad; 875 } 876 877 /* STA, AHDEMO? */ 878 if (opmode == IEEE80211_M_HOSTAP) { 879 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 880 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 881 } 882 883 vap = &avp->av_vap; 884 /* XXX can't hold mutex across if_alloc */ 885 ATH_UNLOCK(sc); 886 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 887 bssid, mac); 888 ATH_LOCK(sc); 889 if (error != 0) { 890 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 891 __func__, error); 892 goto bad2; 893 } 894 895 /* h/w crypto support */ 896 vap->iv_key_alloc = ath_key_alloc; 897 vap->iv_key_delete = ath_key_delete; 898 vap->iv_key_set = ath_key_set; 899 vap->iv_key_update_begin = ath_key_update_begin; 900 vap->iv_key_update_end = ath_key_update_end; 901 902 /* override various methods */ 903 avp->av_recv_mgmt = vap->iv_recv_mgmt; 904 vap->iv_recv_mgmt = ath_recv_mgmt; 905 vap->iv_reset = ath_reset_vap; 906 vap->iv_update_beacon = ath_beacon_update; 907 avp->av_newstate = vap->iv_newstate; 908 vap->iv_newstate = ath_newstate; 909 avp->av_bmiss = vap->iv_bmiss; 910 vap->iv_bmiss = ath_bmiss_vap; 911 912 avp->av_bslot = -1; 913 if (needbeacon) { 914 /* 915 * Allocate beacon state and setup the q for buffered 916 * multicast frames. We know a beacon buffer is 917 * available because we checked above. 918 */ 919 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 920 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 921 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 922 /* 923 * Assign the vap to a beacon xmit slot. As above 924 * this cannot fail to find a free one. 925 */ 926 avp->av_bslot = assign_bslot(sc); 927 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 928 ("beacon slot %u not empty", avp->av_bslot)); 929 sc->sc_bslot[avp->av_bslot] = vap; 930 sc->sc_nbcnvaps++; 931 } 932 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 933 /* 934 * Multple vaps are to transmit beacons and we 935 * have h/w support for TSF adjusting; enable 936 * use of staggered beacons. 937 */ 938 sc->sc_stagbeacons = 1; 939 } 940 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 941 } 942 943 ic->ic_opmode = ic_opmode; 944 if (opmode != IEEE80211_M_WDS) { 945 sc->sc_nvaps++; 946 if (opmode == IEEE80211_M_STA) 947 sc->sc_nstavaps++; 948 } 949 switch (ic_opmode) { 950 case IEEE80211_M_IBSS: 951 sc->sc_opmode = HAL_M_IBSS; 952 break; 953 case IEEE80211_M_STA: 954 sc->sc_opmode = HAL_M_STA; 955 break; 956 case IEEE80211_M_AHDEMO: 957 case IEEE80211_M_HOSTAP: 958 sc->sc_opmode = HAL_M_HOSTAP; 959 break; 960 case IEEE80211_M_MONITOR: 961 sc->sc_opmode = HAL_M_MONITOR; 962 break; 963 default: 964 /* XXX should not happen */ 965 break; 966 } 967 if (sc->sc_hastsfadd) { 968 /* 969 * Configure whether or not TSF adjust should be done. 970 */ 971 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 972 } 973 ATH_UNLOCK(sc); 974 975 /* complete setup */ 976 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 977 return vap; 978bad2: 979 reclaim_address(sc, mac); 980 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 981bad: 982 free(avp, M_80211_VAP); 983 ATH_UNLOCK(sc); 984 return NULL; 985} 986 987static void 988ath_vap_delete(struct ieee80211vap *vap) 989{ 990 struct ieee80211com *ic = vap->iv_ic; 991 struct ifnet *ifp = ic->ic_ifp; 992 struct ath_softc *sc = ifp->if_softc; 993 struct ath_hal *ah = sc->sc_ah; 994 struct ath_vap *avp = ATH_VAP(vap); 995 996 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 997 /* 998 * Quiesce the hardware while we remove the vap. In 999 * particular we need to reclaim all references to 1000 * the vap state by any frames pending on the tx queues. 1001 */ 1002 ath_hal_intrset(ah, 0); /* disable interrupts */ 1003 ath_draintxq(sc); /* stop xmit side */ 1004 ath_stoprecv(sc); /* stop recv side */ 1005 } 1006 1007 ieee80211_vap_detach(vap); 1008 ATH_LOCK(sc); 1009 /* 1010 * Reclaim beacon state. Note this must be done before 1011 * the vap instance is reclaimed as we may have a reference 1012 * to it in the buffer for the beacon frame. 1013 */ 1014 if (avp->av_bcbuf != NULL) { 1015 if (avp->av_bslot != -1) { 1016 sc->sc_bslot[avp->av_bslot] = NULL; 1017 sc->sc_nbcnvaps--; 1018 } 1019 ath_beacon_return(sc, avp->av_bcbuf); 1020 avp->av_bcbuf = NULL; 1021 if (sc->sc_nbcnvaps == 0) { 1022 sc->sc_stagbeacons = 0; 1023 if (sc->sc_hastsfadd) 1024 ath_hal_settsfadjust(sc->sc_ah, 0); 1025 } 1026 /* 1027 * Reclaim any pending mcast frames for the vap. 1028 */ 1029 ath_tx_draintxq(sc, &avp->av_mcastq); 1030 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1031 } 1032 /* 1033 * Update bookkeeping. 1034 */ 1035 if (vap->iv_opmode == IEEE80211_M_STA) { 1036 sc->sc_nstavaps--; 1037 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1038 sc->sc_swbmiss = 0; 1039 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 1040 reclaim_address(sc, vap->iv_myaddr); 1041 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1042 } 1043 if (vap->iv_opmode != IEEE80211_M_WDS) 1044 sc->sc_nvaps--; 1045 ATH_UNLOCK(sc); 1046 free(avp, M_80211_VAP); 1047 1048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1049 /* 1050 * Restart rx+tx machines if still running (RUNNING will 1051 * be reset if we just destroyed the last vap). 1052 */ 1053 if (ath_startrecv(sc) != 0) 1054 if_printf(ifp, "%s: unable to restart recv logic\n", 1055 __func__); 1056 if (sc->sc_beacons) 1057 ath_beacon_config(sc, NULL); 1058 ath_hal_intrset(ah, sc->sc_imask); 1059 } 1060} 1061 1062void 1063ath_suspend(struct ath_softc *sc) 1064{ 1065 struct ifnet *ifp = sc->sc_ifp; 1066 struct ieee80211com *ic = ifp->if_l2com; 1067 1068 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1069 __func__, ifp->if_flags); 1070 1071 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1072 if (ic->ic_opmode == IEEE80211_M_STA) 1073 ath_stop(ifp); 1074 else 1075 ieee80211_suspend_all(ic); 1076 /* 1077 * NB: don't worry about putting the chip in low power 1078 * mode; pci will power off our socket on suspend and 1079 * cardbus detaches the device. 1080 */ 1081} 1082 1083/* 1084 * Reset the key cache since some parts do not reset the 1085 * contents on resume. First we clear all entries, then 1086 * re-load keys that the 802.11 layer assumes are setup 1087 * in h/w. 1088 */ 1089static void 1090ath_reset_keycache(struct ath_softc *sc) 1091{ 1092 struct ifnet *ifp = sc->sc_ifp; 1093 struct ieee80211com *ic = ifp->if_l2com; 1094 struct ath_hal *ah = sc->sc_ah; 1095 int i; 1096 1097 for (i = 0; i < sc->sc_keymax; i++) 1098 ath_hal_keyreset(ah, i); 1099 ieee80211_crypto_reload_keys(ic); 1100} 1101 1102void 1103ath_resume(struct ath_softc *sc) 1104{ 1105 struct ifnet *ifp = sc->sc_ifp; 1106 struct ieee80211com *ic = ifp->if_l2com; 1107 struct ath_hal *ah = sc->sc_ah; 1108 HAL_STATUS status; 1109 1110 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1111 __func__, ifp->if_flags); 1112 1113 /* 1114 * Must reset the chip before we reload the 1115 * keycache as we were powered down on suspend. 1116 */ 1117 ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status); 1118 ath_reset_keycache(sc); 1119 if (sc->sc_resume_up) { 1120 if (ic->ic_opmode == IEEE80211_M_STA) { 1121 ath_init(sc); 1122 ieee80211_beacon_miss(ic); 1123 } else 1124 ieee80211_resume_all(ic); 1125 } 1126 if (sc->sc_softled) { 1127 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 1128 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1129 } 1130} 1131 1132void 1133ath_shutdown(struct ath_softc *sc) 1134{ 1135 struct ifnet *ifp = sc->sc_ifp; 1136 1137 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1138 __func__, ifp->if_flags); 1139 1140 ath_stop(ifp); 1141 /* NB: no point powering down chip as we're about to reboot */ 1142} 1143 1144/* 1145 * Interrupt handler. Most of the actual processing is deferred. 1146 */ 1147void 1148ath_intr(void *arg) 1149{ 1150 struct ath_softc *sc = arg; 1151 struct ifnet *ifp = sc->sc_ifp; 1152 struct ath_hal *ah = sc->sc_ah; 1153 HAL_INT status; 1154 1155 if (sc->sc_invalid) { 1156 /* 1157 * The hardware is not ready/present, don't touch anything. 1158 * Note this can happen early on if the IRQ is shared. 1159 */ 1160 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1161 return; 1162 } 1163 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1164 return; 1165 if ((ifp->if_flags & IFF_UP) == 0 || 1166 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1167 HAL_INT status; 1168 1169 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1170 __func__, ifp->if_flags); 1171 ath_hal_getisr(ah, &status); /* clear ISR */ 1172 ath_hal_intrset(ah, 0); /* disable further intr's */ 1173 return; 1174 } 1175 /* 1176 * Figure out the reason(s) for the interrupt. Note 1177 * that the hal returns a pseudo-ISR that may include 1178 * bits we haven't explicitly enabled so we mask the 1179 * value to insure we only process bits we requested. 1180 */ 1181 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1182 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1183 status &= sc->sc_imask; /* discard unasked for bits */ 1184 if (status & HAL_INT_FATAL) { 1185 sc->sc_stats.ast_hardware++; 1186 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1187 ath_fatal_proc(sc, 0); 1188 } else { 1189 if (status & HAL_INT_SWBA) { 1190 /* 1191 * Software beacon alert--time to send a beacon. 1192 * Handle beacon transmission directly; deferring 1193 * this is too slow to meet timing constraints 1194 * under load. 1195 */ 1196 ath_beacon_proc(sc, 0); 1197 } 1198 if (status & HAL_INT_RXEOL) { 1199 /* 1200 * NB: the hardware should re-read the link when 1201 * RXE bit is written, but it doesn't work at 1202 * least on older hardware revs. 1203 */ 1204 sc->sc_stats.ast_rxeol++; 1205 sc->sc_rxlink = NULL; 1206 } 1207 if (status & HAL_INT_TXURN) { 1208 sc->sc_stats.ast_txurn++; 1209 /* bump tx trigger level */ 1210 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1211 } 1212 if (status & HAL_INT_RX) 1213 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1214 if (status & HAL_INT_TX) 1215 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1216 if (status & HAL_INT_BMISS) { 1217 sc->sc_stats.ast_bmiss++; 1218 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1219 } 1220 if (status & HAL_INT_MIB) { 1221 sc->sc_stats.ast_mib++; 1222 /* 1223 * Disable interrupts until we service the MIB 1224 * interrupt; otherwise it will continue to fire. 1225 */ 1226 ath_hal_intrset(ah, 0); 1227 /* 1228 * Let the hal handle the event. We assume it will 1229 * clear whatever condition caused the interrupt. 1230 */ 1231 ath_hal_mibevent(ah, &sc->sc_halstats); 1232 ath_hal_intrset(ah, sc->sc_imask); 1233 } 1234 if (status & HAL_INT_RXORN) { 1235 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1236 sc->sc_stats.ast_rxorn++; 1237 } 1238 } 1239} 1240 1241static void 1242ath_fatal_proc(void *arg, int pending) 1243{ 1244 struct ath_softc *sc = arg; 1245 struct ifnet *ifp = sc->sc_ifp; 1246 u_int32_t *state; 1247 u_int32_t len; 1248 void *sp; 1249 1250 if_printf(ifp, "hardware error; resetting\n"); 1251 /* 1252 * Fatal errors are unrecoverable. Typically these 1253 * are caused by DMA errors. Collect h/w state from 1254 * the hal so we can diagnose what's going on. 1255 */ 1256 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1257 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1258 state = sp; 1259 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1260 state[0], state[1] , state[2], state[3], 1261 state[4], state[5]); 1262 } 1263 ath_reset(ifp); 1264} 1265 1266static void 1267ath_bmiss_vap(struct ieee80211vap *vap) 1268{ 1269 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 1270 u_int64_t lastrx = sc->sc_lastrx; 1271 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1272 u_int bmisstimeout = 1273 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1274 1275 DPRINTF(sc, ATH_DEBUG_BEACON, 1276 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1277 __func__, (unsigned long long) tsf, 1278 (unsigned long long)(tsf - lastrx), 1279 (unsigned long long) lastrx, bmisstimeout); 1280 /* 1281 * Workaround phantom bmiss interrupts by sanity-checking 1282 * the time of our last rx'd frame. If it is within the 1283 * beacon miss interval then ignore the interrupt. If it's 1284 * truly a bmiss we'll get another interrupt soon and that'll 1285 * be dispatched up for processing. 1286 */ 1287 if (tsf - lastrx > bmisstimeout) 1288 ATH_VAP(vap)->av_bmiss(vap); 1289 else 1290 sc->sc_stats.ast_bmiss_phantom++; 1291} 1292 1293static void 1294ath_bmiss_proc(void *arg, int pending) 1295{ 1296 struct ath_softc *sc = arg; 1297 struct ifnet *ifp = sc->sc_ifp; 1298 1299 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1300 ieee80211_beacon_miss(ifp->if_l2com); 1301} 1302 1303/* 1304 * Convert net80211 channel to a HAL channel with the flags 1305 * constrained to reflect the current operating mode and 1306 * the frequency possibly mapped for GSM channels. 1307 */ 1308static void 1309ath_mapchan(const struct ieee80211com *ic, 1310 HAL_CHANNEL *hc, const struct ieee80211_channel *chan) 1311{ 1312#define N(a) (sizeof(a) / sizeof(a[0])) 1313 static const u_int modeflags[IEEE80211_MODE_MAX] = { 1314 0, /* IEEE80211_MODE_AUTO */ 1315 CHANNEL_A, /* IEEE80211_MODE_11A */ 1316 CHANNEL_B, /* IEEE80211_MODE_11B */ 1317 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 1318 0, /* IEEE80211_MODE_FH */ 1319 CHANNEL_108A, /* IEEE80211_MODE_TURBO_A */ 1320 CHANNEL_108G, /* IEEE80211_MODE_TURBO_G */ 1321 CHANNEL_ST, /* IEEE80211_MODE_STURBO_A */ 1322 CHANNEL_A, /* IEEE80211_MODE_11NA */ 1323 CHANNEL_PUREG, /* IEEE80211_MODE_11NG */ 1324 }; 1325 enum ieee80211_phymode mode = ieee80211_chan2mode(chan); 1326 1327 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 1328 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 1329 hc->channelFlags = modeflags[mode]; 1330 if (IEEE80211_IS_CHAN_HALF(chan)) 1331 hc->channelFlags |= CHANNEL_HALF; 1332 if (IEEE80211_IS_CHAN_QUARTER(chan)) 1333 hc->channelFlags |= CHANNEL_QUARTER; 1334 if (IEEE80211_IS_CHAN_HT20(chan)) 1335 hc->channelFlags |= CHANNEL_HT20; 1336 if (IEEE80211_IS_CHAN_HT40D(chan)) 1337 hc->channelFlags |= CHANNEL_HT40MINUS; 1338 if (IEEE80211_IS_CHAN_HT40U(chan)) 1339 hc->channelFlags |= CHANNEL_HT40PLUS; 1340 1341 if (IEEE80211_IS_CHAN_GSM(chan)) { 1342 if (ic->ic_regdomain.country == CTRY_XR9) 1343 hc->channel = 1520 + chan->ic_freq; 1344 else if (ic->ic_regdomain.country == CTRY_GZ901) 1345 hc->channel = 1544 + chan->ic_freq; 1346 else 1347 hc->channel = 3344 - chan->ic_freq; 1348 } else 1349 hc->channel = chan->ic_freq; 1350#undef N 1351} 1352 1353/* 1354 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1355 * calcs together with WME. If necessary disable the crypto 1356 * hardware and mark the 802.11 state so keys will be setup 1357 * with the MIC work done in software. 1358 */ 1359static void 1360ath_settkipmic(struct ath_softc *sc) 1361{ 1362 struct ifnet *ifp = sc->sc_ifp; 1363 struct ieee80211com *ic = ifp->if_l2com; 1364 1365 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1366 if (ic->ic_flags & IEEE80211_F_WME) { 1367 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1368 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1369 } else { 1370 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1371 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1372 } 1373 } 1374} 1375 1376static void 1377ath_init(void *arg) 1378{ 1379 struct ath_softc *sc = (struct ath_softc *) arg; 1380 struct ifnet *ifp = sc->sc_ifp; 1381 struct ieee80211com *ic = ifp->if_l2com; 1382 struct ath_hal *ah = sc->sc_ah; 1383 HAL_STATUS status; 1384 1385 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1386 __func__, ifp->if_flags); 1387 1388 ATH_LOCK(sc); 1389 /* 1390 * Stop anything previously setup. This is safe 1391 * whether this is the first time through or not. 1392 */ 1393 ath_stop_locked(ifp); 1394 1395 /* 1396 * The basic interface to setting the hardware in a good 1397 * state is ``reset''. On return the hardware is known to 1398 * be powered up and with interrupts disabled. This must 1399 * be followed by initialization of the appropriate bits 1400 * and then setup of the interrupt mask. 1401 */ 1402 ath_mapchan(ic, &sc->sc_curchan, ic->ic_curchan); 1403 ath_settkipmic(sc); 1404 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1405 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1406 status); 1407 ATH_UNLOCK(sc); 1408 return; 1409 } 1410 ath_chan_change(sc, ic->ic_curchan); 1411 1412 /* 1413 * Likewise this is set during reset so update 1414 * state cached in the driver. 1415 */ 1416 sc->sc_diversity = ath_hal_getdiversity(ah); 1417 sc->sc_calinterval = 1; 1418 sc->sc_caltries = 0; 1419 1420 /* 1421 * Setup the hardware after reset: the key cache 1422 * is filled as needed and the receive engine is 1423 * set going. Frame transmit is handled entirely 1424 * in the frame output path; there's nothing to do 1425 * here except setup the interrupt mask. 1426 */ 1427 if (ath_startrecv(sc) != 0) { 1428 if_printf(ifp, "unable to start recv logic\n"); 1429 ATH_UNLOCK(sc); 1430 return; 1431 } 1432 1433 /* 1434 * Enable interrupts. 1435 */ 1436 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1437 | HAL_INT_RXEOL | HAL_INT_RXORN 1438 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1439 /* 1440 * Enable MIB interrupts when there are hardware phy counters. 1441 * Note we only do this (at the moment) for station mode. 1442 */ 1443 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1444 sc->sc_imask |= HAL_INT_MIB; 1445 1446 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1447 ath_hal_intrset(ah, sc->sc_imask); 1448 1449 ATH_UNLOCK(sc); 1450 1451#ifdef ATH_TX99_DIAG 1452 if (sc->sc_tx99 != NULL) 1453 sc->sc_tx99->start(sc->sc_tx99); 1454 else 1455#endif 1456 ieee80211_start_all(ic); /* start all vap's */ 1457} 1458 1459static void 1460ath_stop_locked(struct ifnet *ifp) 1461{ 1462 struct ath_softc *sc = ifp->if_softc; 1463 struct ath_hal *ah = sc->sc_ah; 1464 1465 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1466 __func__, sc->sc_invalid, ifp->if_flags); 1467 1468 ATH_LOCK_ASSERT(sc); 1469 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1470 /* 1471 * Shutdown the hardware and driver: 1472 * reset 802.11 state machine 1473 * turn off timers 1474 * disable interrupts 1475 * turn off the radio 1476 * clear transmit machinery 1477 * clear receive machinery 1478 * drain and release tx queues 1479 * reclaim beacon resources 1480 * power down hardware 1481 * 1482 * Note that some of this work is not possible if the 1483 * hardware is gone (invalid). 1484 */ 1485#ifdef ATH_TX99_DIAG 1486 if (sc->sc_tx99 != NULL) 1487 sc->sc_tx99->stop(sc->sc_tx99); 1488#endif 1489 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1490 ifp->if_timer = 0; 1491 if (!sc->sc_invalid) { 1492 if (sc->sc_softled) { 1493 callout_stop(&sc->sc_ledtimer); 1494 ath_hal_gpioset(ah, sc->sc_ledpin, 1495 !sc->sc_ledon); 1496 sc->sc_blinking = 0; 1497 } 1498 ath_hal_intrset(ah, 0); 1499 } 1500 ath_draintxq(sc); 1501 if (!sc->sc_invalid) { 1502 ath_stoprecv(sc); 1503 ath_hal_phydisable(ah); 1504 } else 1505 sc->sc_rxlink = NULL; 1506 ath_beacon_free(sc); /* XXX not needed */ 1507 } 1508} 1509 1510static void 1511ath_stop(struct ifnet *ifp) 1512{ 1513 struct ath_softc *sc = ifp->if_softc; 1514 1515 ATH_LOCK(sc); 1516 ath_stop_locked(ifp); 1517 ATH_UNLOCK(sc); 1518} 1519 1520/* 1521 * Reset the hardware w/o losing operational state. This is 1522 * basically a more efficient way of doing ath_stop, ath_init, 1523 * followed by state transitions to the current 802.11 1524 * operational state. Used to recover from various errors and 1525 * to reset or reload hardware state. 1526 */ 1527static int 1528ath_reset(struct ifnet *ifp) 1529{ 1530 struct ath_softc *sc = ifp->if_softc; 1531 struct ieee80211com *ic = ifp->if_l2com; 1532 struct ath_hal *ah = sc->sc_ah; 1533 HAL_STATUS status; 1534 1535 /* 1536 * Convert to a HAL channel description with the flags 1537 * constrained to reflect the current operating mode. 1538 */ 1539 ath_mapchan(ic, &sc->sc_curchan, ic->ic_curchan); 1540 1541 ath_hal_intrset(ah, 0); /* disable interrupts */ 1542 ath_draintxq(sc); /* stop xmit side */ 1543 ath_stoprecv(sc); /* stop recv side */ 1544 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1545 /* NB: indicate channel change so we do a full reset */ 1546 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1547 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1548 __func__, status); 1549 sc->sc_diversity = ath_hal_getdiversity(ah); 1550 sc->sc_calinterval = 1; 1551 sc->sc_caltries = 0; 1552 if (ath_startrecv(sc) != 0) /* restart recv */ 1553 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1554 /* 1555 * We may be doing a reset in response to an ioctl 1556 * that changes the channel so update any state that 1557 * might change as a result. 1558 */ 1559 ath_chan_change(sc, ic->ic_curchan); 1560 if (sc->sc_beacons) 1561 ath_beacon_config(sc, NULL); /* restart beacons */ 1562 ath_hal_intrset(ah, sc->sc_imask); 1563 1564 ath_start(ifp); /* restart xmit */ 1565 return 0; 1566} 1567 1568static int 1569ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1570{ 1571 struct ieee80211com *ic = vap->iv_ic; 1572 struct ifnet *ifp = ic->ic_ifp; 1573 struct ath_softc *sc = ifp->if_softc; 1574 struct ath_hal *ah = sc->sc_ah; 1575 1576 switch (cmd) { 1577 case IEEE80211_IOC_TXPOWER: 1578 /* 1579 * If per-packet TPC is enabled, then we have nothing 1580 * to do; otherwise we need to force the global limit. 1581 * All this can happen directly; no need to reset. 1582 */ 1583 if (!ath_hal_gettpc(ah)) 1584 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1585 return 0; 1586 } 1587 return ath_reset(ifp); 1588} 1589 1590static int 1591ath_ff_always(struct ath_txq *txq, struct ath_buf *bf) 1592{ 1593 return 0; 1594} 1595 1596#if 0 1597static int 1598ath_ff_ageflushtestdone(struct ath_txq *txq, struct ath_buf *bf) 1599{ 1600 return (txq->axq_curage - bf->bf_age) < ATH_FF_STAGEMAX; 1601} 1602#endif 1603 1604/* 1605 * Flush FF staging queue. 1606 */ 1607static void 1608ath_ff_stageq_flush(struct ath_softc *sc, struct ath_txq *txq, 1609 int (*ath_ff_flushdonetest)(struct ath_txq *txq, struct ath_buf *bf)) 1610{ 1611 struct ath_buf *bf; 1612 struct ieee80211_node *ni; 1613 int pktlen, pri; 1614 1615 for (;;) { 1616 ATH_TXQ_LOCK(txq); 1617 /* 1618 * Go from the back (oldest) to front so we can 1619 * stop early based on the age of the entry. 1620 */ 1621 bf = TAILQ_LAST(&txq->axq_stageq, axq_headtype); 1622 if (bf == NULL || ath_ff_flushdonetest(txq, bf)) { 1623 ATH_TXQ_UNLOCK(txq); 1624 break; 1625 } 1626 1627 ni = bf->bf_node; 1628 pri = M_WME_GETAC(bf->bf_m); 1629 KASSERT(ATH_NODE(ni)->an_ff_buf[pri], 1630 ("no bf on staging queue %p", bf)); 1631 ATH_NODE(ni)->an_ff_buf[pri] = NULL; 1632 TAILQ_REMOVE(&txq->axq_stageq, bf, bf_stagelist); 1633 1634 ATH_TXQ_UNLOCK(txq); 1635 1636 DPRINTF(sc, ATH_DEBUG_FF, "%s: flush frame, age %u\n", 1637 __func__, bf->bf_age); 1638 1639 sc->sc_stats.ast_ff_flush++; 1640 1641 /* encap and xmit */ 1642 bf->bf_m = ieee80211_encap(ni, bf->bf_m); 1643 if (bf->bf_m == NULL) { 1644 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1645 "%s: discard, encapsulation failure\n", 1646 __func__); 1647 sc->sc_stats.ast_tx_encap++; 1648 goto bad; 1649 } 1650 pktlen = bf->bf_m->m_pkthdr.len; /* NB: don't reference below */ 1651 if (ath_tx_start(sc, ni, bf, bf->bf_m) == 0) { 1652#if 0 /*XXX*/ 1653 ifp->if_opackets++; 1654#endif 1655 continue; 1656 } 1657 bad: 1658 if (ni != NULL) 1659 ieee80211_free_node(ni); 1660 bf->bf_node = NULL; 1661 if (bf->bf_m != NULL) { 1662 m_freem(bf->bf_m); 1663 bf->bf_m = NULL; 1664 } 1665 1666 ATH_TXBUF_LOCK(sc); 1667 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1668 ATH_TXBUF_UNLOCK(sc); 1669 } 1670} 1671 1672static __inline u_int32_t 1673ath_ff_approx_txtime(struct ath_softc *sc, struct ath_node *an, struct mbuf *m) 1674{ 1675 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1676 u_int32_t framelen; 1677 struct ath_buf *bf; 1678 1679 /* 1680 * Approximate the frame length to be transmitted. A swag to add 1681 * the following maximal values to the skb payload: 1682 * - 32: 802.11 encap + CRC 1683 * - 24: encryption overhead (if wep bit) 1684 * - 4 + 6: fast-frame header and padding 1685 * - 16: 2 LLC FF tunnel headers 1686 * - 14: 1 802.3 FF tunnel header (skb already accounts for 2nd) 1687 */ 1688 framelen = m->m_pkthdr.len + 32 + 4 + 6 + 16 + 14; 1689 if (ic->ic_flags & IEEE80211_F_PRIVACY) 1690 framelen += 24; 1691 bf = an->an_ff_buf[M_WME_GETAC(m)]; 1692 if (bf != NULL) 1693 framelen += bf->bf_m->m_pkthdr.len; 1694 return ath_hal_computetxtime(sc->sc_ah, sc->sc_currates, framelen, 1695 sc->sc_lastdatarix, AH_FALSE); 1696} 1697 1698/* 1699 * Determine if a data frame may be aggregated via ff tunnelling. 1700 * Note the caller is responsible for checking if the destination 1701 * supports fast frames. 1702 * 1703 * NB: allowing EAPOL frames to be aggregated with other unicast traffic. 1704 * Do 802.1x EAPOL frames proceed in the clear? Then they couldn't 1705 * be aggregated with other types of frames when encryption is on? 1706 * 1707 * NB: assumes lock on an_ff_buf effectively held by txq lock mechanism. 1708 */ 1709static __inline int 1710ath_ff_can_aggregate(struct ath_softc *sc, 1711 struct ath_node *an, struct mbuf *m, int *flushq) 1712{ 1713 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1714 struct ath_txq *txq; 1715 u_int32_t txoplimit; 1716 u_int pri; 1717 1718 *flushq = 0; 1719 1720 /* 1721 * If there is no frame to combine with and the txq has 1722 * fewer frames than the minimum required; then do not 1723 * attempt to aggregate this frame. 1724 */ 1725 pri = M_WME_GETAC(m); 1726 txq = sc->sc_ac2q[pri]; 1727 if (an->an_ff_buf[pri] == NULL && txq->axq_depth < sc->sc_fftxqmin) 1728 return 0; 1729 /* 1730 * When not in station mode never aggregate a multicast 1731 * frame; this insures, for example, that a combined frame 1732 * does not require multiple encryption keys when using 1733 * 802.1x/WPA. 1734 */ 1735 if (ic->ic_opmode != IEEE80211_M_STA && 1736 ETHER_IS_MULTICAST(mtod(m, struct ether_header *)->ether_dhost)) 1737 return 0; 1738 /* 1739 * Consult the max bursting interval to insure a combined 1740 * frame fits within the TxOp window. 1741 */ 1742 txoplimit = IEEE80211_TXOP_TO_US( 1743 ic->ic_wme.wme_chanParams.cap_wmeParams[pri].wmep_txopLimit); 1744 if (txoplimit != 0 && ath_ff_approx_txtime(sc, an, m) > txoplimit) { 1745 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1746 "%s: FF TxOp violation\n", __func__); 1747 if (an->an_ff_buf[pri] != NULL) 1748 *flushq = 1; 1749 return 0; 1750 } 1751 return 1; /* try to aggregate */ 1752} 1753 1754/* 1755 * Check if the supplied frame can be partnered with an existing 1756 * or pending frame. Return a reference to any frame that should be 1757 * sent on return; otherwise return NULL. 1758 */ 1759static struct mbuf * 1760ath_ff_check(struct ath_softc *sc, struct ath_txq *txq, 1761 struct ath_buf *bf, struct mbuf *m, struct ieee80211_node *ni) 1762{ 1763 struct ath_node *an = ATH_NODE(ni); 1764 struct ath_buf *bfstaged; 1765 int ff_flush, pri; 1766 1767 /* 1768 * Check if the supplied frame can be aggregated. 1769 * 1770 * NB: we use the txq lock to protect references to 1771 * an->an_ff_txbuf in ath_ff_can_aggregate(). 1772 */ 1773 ATH_TXQ_LOCK(txq); 1774 pri = M_WME_GETAC(m); 1775 if (ath_ff_can_aggregate(sc, an, m, &ff_flush)) { 1776 struct ath_buf *bfstaged = an->an_ff_buf[pri]; 1777 if (bfstaged != NULL) { 1778 /* 1779 * A frame is available for partnering; remove 1780 * it, chain it to this one, and encapsulate. 1781 */ 1782 an->an_ff_buf[pri] = NULL; 1783 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1784 ATH_TXQ_UNLOCK(txq); 1785 1786 /* 1787 * Chain mbufs and add FF magic. 1788 */ 1789 DPRINTF(sc, ATH_DEBUG_FF, 1790 "[%s] aggregate fast-frame, age %u\n", 1791 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1792 m->m_nextpkt = NULL; 1793 bfstaged->bf_m->m_nextpkt = m; 1794 m = bfstaged->bf_m; 1795 bfstaged->bf_m = NULL; 1796 m->m_flags |= M_FF; 1797 /* 1798 * Release the node reference held while 1799 * the packet sat on an_ff_buf[] 1800 */ 1801 bfstaged->bf_node = NULL; 1802 ieee80211_free_node(ni); 1803 1804 /* 1805 * Return bfstaged to the free list. 1806 */ 1807 ATH_TXBUF_LOCK(sc); 1808 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1809 ATH_TXBUF_UNLOCK(sc); 1810 1811 return m; /* ready to go */ 1812 } else { 1813 /* 1814 * No frame available, queue this frame to wait 1815 * for a partner. Note that we hold the buffer 1816 * and a reference to the node; we need the 1817 * buffer in particular so we're certain we 1818 * can flush the frame at a later time. 1819 */ 1820 DPRINTF(sc, ATH_DEBUG_FF, 1821 "[%s] stage fast-frame, age %u\n", 1822 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1823 1824 bf->bf_m = m; 1825 bf->bf_node = ni; /* NB: held reference */ 1826 bf->bf_age = txq->axq_curage; 1827 an->an_ff_buf[pri] = bf; 1828 TAILQ_INSERT_HEAD(&txq->axq_stageq, bf, bf_stagelist); 1829 ATH_TXQ_UNLOCK(txq); 1830 1831 return NULL; /* consumed */ 1832 } 1833 } 1834 /* 1835 * Frame could not be aggregated, it needs to be returned 1836 * to the caller for immediate transmission. In addition 1837 * we check if we should first flush a frame from the 1838 * staging queue before sending this one. 1839 * 1840 * NB: ath_ff_can_aggregate only marks ff_flush if a frame 1841 * is present to flush. 1842 */ 1843 if (ff_flush) { 1844 int pktlen; 1845 1846 bfstaged = an->an_ff_buf[pri]; 1847 an->an_ff_buf[pri] = NULL; 1848 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1849 ATH_TXQ_UNLOCK(txq); 1850 1851 DPRINTF(sc, ATH_DEBUG_FF, "[%s] flush staged frame\n", 1852 ether_sprintf(an->an_node.ni_macaddr)); 1853 1854 /* encap and xmit */ 1855 bfstaged->bf_m = ieee80211_encap(ni, bfstaged->bf_m); 1856 if (bfstaged->bf_m == NULL) { 1857 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1858 "%s: discard, encap failure\n", __func__); 1859 sc->sc_stats.ast_tx_encap++; 1860 goto ff_flushbad; 1861 } 1862 pktlen = bfstaged->bf_m->m_pkthdr.len; 1863 if (ath_tx_start(sc, ni, bfstaged, bfstaged->bf_m)) { 1864 DPRINTF(sc, ATH_DEBUG_XMIT, 1865 "%s: discard, xmit failure\n", __func__); 1866 ff_flushbad: 1867 /* 1868 * Unable to transmit frame that was on the staging 1869 * queue. Reclaim the node reference and other 1870 * resources. 1871 */ 1872 if (ni != NULL) 1873 ieee80211_free_node(ni); 1874 bfstaged->bf_node = NULL; 1875 if (bfstaged->bf_m != NULL) { 1876 m_freem(bfstaged->bf_m); 1877 bfstaged->bf_m = NULL; 1878 } 1879 1880 ATH_TXBUF_LOCK(sc); 1881 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1882 ATH_TXBUF_UNLOCK(sc); 1883 } else { 1884#if 0 1885 ifp->if_opackets++; 1886#endif 1887 } 1888 } else { 1889 if (an->an_ff_buf[pri] != NULL) { 1890 /* 1891 * XXX: out-of-order condition only occurs for AP 1892 * mode and multicast. There may be no valid way 1893 * to get this condition. 1894 */ 1895 DPRINTF(sc, ATH_DEBUG_FF, "[%s] out-of-order frame\n", 1896 ether_sprintf(an->an_node.ni_macaddr)); 1897 /* XXX stat */ 1898 } 1899 ATH_TXQ_UNLOCK(txq); 1900 } 1901 return m; 1902} 1903 1904/* 1905 * Cleanup driver resources when we run out of buffers 1906 * while processing fragments; return the tx buffers 1907 * allocated and drop node references. 1908 */ 1909static void 1910ath_txfrag_cleanup(struct ath_softc *sc, 1911 ath_bufhead *frags, struct ieee80211_node *ni) 1912{ 1913 struct ath_buf *bf, *next; 1914 1915 ATH_TXBUF_LOCK_ASSERT(sc); 1916 1917 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 1918 /* NB: bf assumed clean */ 1919 STAILQ_REMOVE_HEAD(frags, bf_list); 1920 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1921 ieee80211_node_decref(ni); 1922 } 1923} 1924 1925/* 1926 * Setup xmit of a fragmented frame. Allocate a buffer 1927 * for each frag and bump the node reference count to 1928 * reflect the held reference to be setup by ath_tx_start. 1929 */ 1930static int 1931ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1932 struct mbuf *m0, struct ieee80211_node *ni) 1933{ 1934 struct mbuf *m; 1935 struct ath_buf *bf; 1936 1937 ATH_TXBUF_LOCK(sc); 1938 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1939 bf = STAILQ_FIRST(&sc->sc_txbuf); 1940 if (bf == NULL) { /* out of buffers, cleanup */ 1941 ath_txfrag_cleanup(sc, frags, ni); 1942 break; 1943 } 1944 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1945 ieee80211_node_incref(ni); 1946 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1947 } 1948 ATH_TXBUF_UNLOCK(sc); 1949 1950 return !STAILQ_EMPTY(frags); 1951} 1952 1953static void 1954ath_start(struct ifnet *ifp) 1955{ 1956 struct ath_softc *sc = ifp->if_softc; 1957 struct ieee80211com *ic = ifp->if_l2com; 1958 struct ieee80211_node *ni; 1959 struct ath_buf *bf; 1960 struct mbuf *m, *next; 1961 struct ath_txq *txq; 1962 ath_bufhead frags; 1963 int pri; 1964 1965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1966 return; 1967 for (;;) { 1968 /* 1969 * Grab a TX buffer and associated resources. 1970 */ 1971 ATH_TXBUF_LOCK(sc); 1972 bf = STAILQ_FIRST(&sc->sc_txbuf); 1973 if (bf != NULL) 1974 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1975 ATH_TXBUF_UNLOCK(sc); 1976 if (bf == NULL) { 1977 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1978 __func__); 1979 sc->sc_stats.ast_tx_qstop++; 1980 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1981 break; 1982 } 1983 1984 IFQ_DEQUEUE(&ifp->if_snd, m); 1985 if (m == NULL) { 1986 ATH_TXBUF_LOCK(sc); 1987 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1988 ATH_TXBUF_UNLOCK(sc); 1989 break; 1990 } 1991 STAILQ_INIT(&frags); 1992 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1993 pri = M_WME_GETAC(m); 1994 txq = sc->sc_ac2q[pri]; 1995 if (IEEE80211_ATH_CAP(ni->ni_vap, ni, IEEE80211_NODE_FF)) { 1996 /* 1997 * Check queue length; if too deep drop this 1998 * frame (tail drop considered good). 1999 */ 2000 if (txq->axq_depth >= sc->sc_fftxqmax) { 2001 DPRINTF(sc, ATH_DEBUG_FF, 2002 "[%s] tail drop on q %u depth %u\n", 2003 ether_sprintf(ni->ni_macaddr), 2004 txq->axq_qnum, txq->axq_depth); 2005 sc->sc_stats.ast_tx_qfull++; 2006 m_freem(m); 2007 goto reclaim; 2008 } 2009 m = ath_ff_check(sc, txq, bf, m, ni); 2010 if (m == NULL) { 2011 /* NB: ni ref & bf held on stageq */ 2012 continue; 2013 } 2014 } 2015 ifp->if_opackets++; 2016 /* 2017 * Encapsulate the packet in prep for transmission. 2018 */ 2019 m = ieee80211_encap(ni, m); 2020 if (m == NULL) { 2021 DPRINTF(sc, ATH_DEBUG_XMIT, 2022 "%s: encapsulation failure\n", __func__); 2023 sc->sc_stats.ast_tx_encap++; 2024 goto bad; 2025 } 2026 /* 2027 * Check for fragmentation. If this frame 2028 * has been broken up verify we have enough 2029 * buffers to send all the fragments so all 2030 * go out or none... 2031 */ 2032 if ((m->m_flags & M_FRAG) && 2033 !ath_txfrag_setup(sc, &frags, m, ni)) { 2034 DPRINTF(sc, ATH_DEBUG_XMIT, 2035 "%s: out of txfrag buffers\n", __func__); 2036 ic->ic_stats.is_tx_nobuf++; /* XXX */ 2037 ath_freetx(m); 2038 goto bad; 2039 } 2040 nextfrag: 2041 /* 2042 * Pass the frame to the h/w for transmission. 2043 * Fragmented frames have each frag chained together 2044 * with m_nextpkt. We know there are sufficient ath_buf's 2045 * to send all the frags because of work done by 2046 * ath_txfrag_setup. We leave m_nextpkt set while 2047 * calling ath_tx_start so it can use it to extend the 2048 * the tx duration to cover the subsequent frag and 2049 * so it can reclaim all the mbufs in case of an error; 2050 * ath_tx_start clears m_nextpkt once it commits to 2051 * handing the frame to the hardware. 2052 */ 2053 next = m->m_nextpkt; 2054 if (ath_tx_start(sc, ni, bf, m)) { 2055 bad: 2056 ifp->if_oerrors++; 2057 reclaim: 2058 bf->bf_m = NULL; 2059 bf->bf_node = NULL; 2060 ATH_TXBUF_LOCK(sc); 2061 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2062 ath_txfrag_cleanup(sc, &frags, ni); 2063 ATH_TXBUF_UNLOCK(sc); 2064 if (ni != NULL) 2065 ieee80211_free_node(ni); 2066 continue; 2067 } 2068 if (next != NULL) { 2069 /* 2070 * Beware of state changing between frags. 2071 * XXX check sta power-save state? 2072 */ 2073 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2074 DPRINTF(sc, ATH_DEBUG_XMIT, 2075 "%s: flush fragmented packet, state %s\n", 2076 __func__, 2077 ieee80211_state_name[ni->ni_vap->iv_state]); 2078 ath_freetx(next); 2079 goto reclaim; 2080 } 2081 m = next; 2082 bf = STAILQ_FIRST(&frags); 2083 KASSERT(bf != NULL, ("no buf for txfrag")); 2084 STAILQ_REMOVE_HEAD(&frags, bf_list); 2085 goto nextfrag; 2086 } 2087 2088 ifp->if_timer = 5; 2089#if 0 2090 /* 2091 * Flush stale frames from the fast-frame staging queue. 2092 */ 2093 if (ic->ic_opmode != IEEE80211_M_STA) 2094 ath_ff_stageq_flush(sc, txq, ath_ff_ageflushtestdone); 2095#endif 2096 } 2097} 2098 2099static int 2100ath_media_change(struct ifnet *ifp) 2101{ 2102 int error = ieee80211_media_change(ifp); 2103 /* NB: only the fixed rate can change and that doesn't need a reset */ 2104 return (error == ENETRESET ? 0 : error); 2105} 2106 2107#ifdef ATH_DEBUG 2108static void 2109ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 2110 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2111{ 2112 static const char *ciphers[] = { 2113 "WEP", 2114 "AES-OCB", 2115 "AES-CCM", 2116 "CKIP", 2117 "TKIP", 2118 "CLR", 2119 }; 2120 int i, n; 2121 2122 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 2123 for (i = 0, n = hk->kv_len; i < n; i++) 2124 printf("%02x", hk->kv_val[i]); 2125 printf(" mac %s", ether_sprintf(mac)); 2126 if (hk->kv_type == HAL_CIPHER_TKIP) { 2127 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 2128 for (i = 0; i < sizeof(hk->kv_mic); i++) 2129 printf("%02x", hk->kv_mic[i]); 2130 if (!sc->sc_splitmic) { 2131 printf(" txmic "); 2132 for (i = 0; i < sizeof(hk->kv_txmic); i++) 2133 printf("%02x", hk->kv_txmic[i]); 2134 } 2135 } 2136 printf("\n"); 2137} 2138#endif 2139 2140/* 2141 * Set a TKIP key into the hardware. This handles the 2142 * potential distribution of key state to multiple key 2143 * cache slots for TKIP. 2144 */ 2145static int 2146ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 2147 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2148{ 2149#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 2150 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 2151 struct ath_hal *ah = sc->sc_ah; 2152 2153 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 2154 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 2155 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 2156 if (sc->sc_splitmic) { 2157 /* 2158 * TX key goes at first index, RX key at the rx index. 2159 * The hal handles the MIC keys at index+64. 2160 */ 2161 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 2162 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 2163 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 2164 return 0; 2165 2166 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2167 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 2168 /* XXX delete tx key on failure? */ 2169 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 2170 } else { 2171 /* 2172 * Room for both TX+RX MIC keys in one key cache 2173 * slot, just set key at the first index; the hal 2174 * will handle the rest. 2175 */ 2176 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2177 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2178 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2179 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2180 } 2181 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 2182 if (sc->sc_splitmic) { 2183 /* 2184 * NB: must pass MIC key in expected location when 2185 * the keycache only holds one MIC key per entry. 2186 */ 2187 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 2188 } else 2189 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2190 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2191 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2192 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 2193 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2194 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2195 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2196 } 2197 return 0; 2198#undef IEEE80211_KEY_XR 2199} 2200 2201/* 2202 * Set a net80211 key into the hardware. This handles the 2203 * potential distribution of key state to multiple key 2204 * cache slots for TKIP with hardware MIC support. 2205 */ 2206static int 2207ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2208 struct ieee80211_node *bss) 2209{ 2210#define N(a) (sizeof(a)/sizeof(a[0])) 2211 static const u_int8_t ciphermap[] = { 2212 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2213 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2214 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2215 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2216 (u_int8_t) -1, /* 4 is not allocated */ 2217 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2218 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2219 }; 2220 struct ath_hal *ah = sc->sc_ah; 2221 const struct ieee80211_cipher *cip = k->wk_cipher; 2222 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2223 const u_int8_t *mac; 2224 HAL_KEYVAL hk; 2225 2226 memset(&hk, 0, sizeof(hk)); 2227 /* 2228 * Software crypto uses a "clear key" so non-crypto 2229 * state kept in the key cache are maintained and 2230 * so that rx frames have an entry to match. 2231 */ 2232 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2233 KASSERT(cip->ic_cipher < N(ciphermap), 2234 ("invalid cipher type %u", cip->ic_cipher)); 2235 hk.kv_type = ciphermap[cip->ic_cipher]; 2236 hk.kv_len = k->wk_keylen; 2237 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2238 } else 2239 hk.kv_type = HAL_CIPHER_CLR; 2240 2241 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2242 /* 2243 * Group keys on hardware that supports multicast frame 2244 * key search use a mac that is the sender's address with 2245 * the high bit set instead of the app-specified address. 2246 */ 2247 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2248 gmac[0] |= 0x80; 2249 mac = gmac; 2250 } else 2251 mac = k->wk_macaddr; 2252 2253 if (hk.kv_type == HAL_CIPHER_TKIP && 2254 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2255 return ath_keyset_tkip(sc, k, &hk, mac); 2256 } else { 2257 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2258 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2259 } 2260#undef N 2261} 2262 2263/* 2264 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2265 * each key, one for decrypt/encrypt and the other for the MIC. 2266 */ 2267static u_int16_t 2268key_alloc_2pair(struct ath_softc *sc, 2269 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2270{ 2271#define N(a) (sizeof(a)/sizeof(a[0])) 2272 u_int i, keyix; 2273 2274 KASSERT(sc->sc_splitmic, ("key cache !split")); 2275 /* XXX could optimize */ 2276 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2277 u_int8_t b = sc->sc_keymap[i]; 2278 if (b != 0xff) { 2279 /* 2280 * One or more slots in this byte are free. 2281 */ 2282 keyix = i*NBBY; 2283 while (b & 1) { 2284 again: 2285 keyix++; 2286 b >>= 1; 2287 } 2288 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2289 if (isset(sc->sc_keymap, keyix+32) || 2290 isset(sc->sc_keymap, keyix+64) || 2291 isset(sc->sc_keymap, keyix+32+64)) { 2292 /* full pair unavailable */ 2293 /* XXX statistic */ 2294 if (keyix == (i+1)*NBBY) { 2295 /* no slots were appropriate, advance */ 2296 continue; 2297 } 2298 goto again; 2299 } 2300 setbit(sc->sc_keymap, keyix); 2301 setbit(sc->sc_keymap, keyix+64); 2302 setbit(sc->sc_keymap, keyix+32); 2303 setbit(sc->sc_keymap, keyix+32+64); 2304 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2305 "%s: key pair %u,%u %u,%u\n", 2306 __func__, keyix, keyix+64, 2307 keyix+32, keyix+32+64); 2308 *txkeyix = keyix; 2309 *rxkeyix = keyix+32; 2310 return 1; 2311 } 2312 } 2313 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2314 return 0; 2315#undef N 2316} 2317 2318/* 2319 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2320 * each key, one for decrypt/encrypt and the other for the MIC. 2321 */ 2322static u_int16_t 2323key_alloc_pair(struct ath_softc *sc, 2324 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2325{ 2326#define N(a) (sizeof(a)/sizeof(a[0])) 2327 u_int i, keyix; 2328 2329 KASSERT(!sc->sc_splitmic, ("key cache split")); 2330 /* XXX could optimize */ 2331 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2332 u_int8_t b = sc->sc_keymap[i]; 2333 if (b != 0xff) { 2334 /* 2335 * One or more slots in this byte are free. 2336 */ 2337 keyix = i*NBBY; 2338 while (b & 1) { 2339 again: 2340 keyix++; 2341 b >>= 1; 2342 } 2343 if (isset(sc->sc_keymap, keyix+64)) { 2344 /* full pair unavailable */ 2345 /* XXX statistic */ 2346 if (keyix == (i+1)*NBBY) { 2347 /* no slots were appropriate, advance */ 2348 continue; 2349 } 2350 goto again; 2351 } 2352 setbit(sc->sc_keymap, keyix); 2353 setbit(sc->sc_keymap, keyix+64); 2354 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2355 "%s: key pair %u,%u\n", 2356 __func__, keyix, keyix+64); 2357 *txkeyix = *rxkeyix = keyix; 2358 return 1; 2359 } 2360 } 2361 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2362 return 0; 2363#undef N 2364} 2365 2366/* 2367 * Allocate a single key cache slot. 2368 */ 2369static int 2370key_alloc_single(struct ath_softc *sc, 2371 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2372{ 2373#define N(a) (sizeof(a)/sizeof(a[0])) 2374 u_int i, keyix; 2375 2376 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2377 for (i = 0; i < N(sc->sc_keymap); i++) { 2378 u_int8_t b = sc->sc_keymap[i]; 2379 if (b != 0xff) { 2380 /* 2381 * One or more slots are free. 2382 */ 2383 keyix = i*NBBY; 2384 while (b & 1) 2385 keyix++, b >>= 1; 2386 setbit(sc->sc_keymap, keyix); 2387 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2388 __func__, keyix); 2389 *txkeyix = *rxkeyix = keyix; 2390 return 1; 2391 } 2392 } 2393 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2394 return 0; 2395#undef N 2396} 2397 2398/* 2399 * Allocate one or more key cache slots for a uniacst key. The 2400 * key itself is needed only to identify the cipher. For hardware 2401 * TKIP with split cipher+MIC keys we allocate two key cache slot 2402 * pairs so that we can setup separate TX and RX MIC keys. Note 2403 * that the MIC key for a TKIP key at slot i is assumed by the 2404 * hardware to be at slot i+64. This limits TKIP keys to the first 2405 * 64 entries. 2406 */ 2407static int 2408ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2409 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2410{ 2411 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2412 2413 /* 2414 * Group key allocation must be handled specially for 2415 * parts that do not support multicast key cache search 2416 * functionality. For those parts the key id must match 2417 * the h/w key index so lookups find the right key. On 2418 * parts w/ the key search facility we install the sender's 2419 * mac address (with the high bit set) and let the hardware 2420 * find the key w/o using the key id. This is preferred as 2421 * it permits us to support multiple users for adhoc and/or 2422 * multi-station operation. 2423 */ 2424 if (k->wk_keyix != IEEE80211_KEYIX_NONE || /* global key */ 2425 ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey)) { 2426 if (!(&vap->iv_nw_keys[0] <= k && 2427 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2428 /* should not happen */ 2429 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2430 "%s: bogus group key\n", __func__); 2431 return 0; 2432 } 2433 /* 2434 * XXX we pre-allocate the global keys so 2435 * have no way to check if they've already been allocated. 2436 */ 2437 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2438 return 1; 2439 } 2440 2441 /* 2442 * We allocate two pair for TKIP when using the h/w to do 2443 * the MIC. For everything else, including software crypto, 2444 * we allocate a single entry. Note that s/w crypto requires 2445 * a pass-through slot on the 5211 and 5212. The 5210 does 2446 * not support pass-through cache entries and we map all 2447 * those requests to slot 0. 2448 */ 2449 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2450 return key_alloc_single(sc, keyix, rxkeyix); 2451 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2452 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2453 if (sc->sc_splitmic) 2454 return key_alloc_2pair(sc, keyix, rxkeyix); 2455 else 2456 return key_alloc_pair(sc, keyix, rxkeyix); 2457 } else { 2458 return key_alloc_single(sc, keyix, rxkeyix); 2459 } 2460} 2461 2462/* 2463 * Delete an entry in the key cache allocated by ath_key_alloc. 2464 */ 2465static int 2466ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2467{ 2468 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2469 struct ath_hal *ah = sc->sc_ah; 2470 const struct ieee80211_cipher *cip = k->wk_cipher; 2471 u_int keyix = k->wk_keyix; 2472 2473 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2474 2475 ath_hal_keyreset(ah, keyix); 2476 /* 2477 * Handle split tx/rx keying required for TKIP with h/w MIC. 2478 */ 2479 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2480 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2481 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2482 if (keyix >= IEEE80211_WEP_NKID) { 2483 /* 2484 * Don't touch keymap entries for global keys so 2485 * they are never considered for dynamic allocation. 2486 */ 2487 clrbit(sc->sc_keymap, keyix); 2488 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2489 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2490 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2491 if (sc->sc_splitmic) { 2492 /* +32 for RX key, +32+64 for RX key MIC */ 2493 clrbit(sc->sc_keymap, keyix+32); 2494 clrbit(sc->sc_keymap, keyix+32+64); 2495 } 2496 } 2497 } 2498 return 1; 2499} 2500 2501/* 2502 * Set the key cache contents for the specified key. Key cache 2503 * slot(s) must already have been allocated by ath_key_alloc. 2504 */ 2505static int 2506ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2507 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2508{ 2509 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2510 2511 return ath_keyset(sc, k, vap->iv_bss); 2512} 2513 2514/* 2515 * Block/unblock tx+rx processing while a key change is done. 2516 * We assume the caller serializes key management operations 2517 * so we only need to worry about synchronization with other 2518 * uses that originate in the driver. 2519 */ 2520static void 2521ath_key_update_begin(struct ieee80211vap *vap) 2522{ 2523 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2524 struct ath_softc *sc = ifp->if_softc; 2525 2526 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2527 taskqueue_block(sc->sc_tq); 2528 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2529} 2530 2531static void 2532ath_key_update_end(struct ieee80211vap *vap) 2533{ 2534 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2535 struct ath_softc *sc = ifp->if_softc; 2536 2537 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2538 IF_UNLOCK(&ifp->if_snd); 2539 taskqueue_unblock(sc->sc_tq); 2540} 2541 2542/* 2543 * Calculate the receive filter according to the 2544 * operating mode and state: 2545 * 2546 * o always accept unicast, broadcast, and multicast traffic 2547 * o accept PHY error frames when hardware doesn't have MIB support 2548 * to count and we need them for ANI (sta mode only until recently) 2549 * and we are not scanning (ANI is disabled) 2550 * NB: older hal's add rx filter bits out of sight and we need to 2551 * blindly preserve them 2552 * o probe request frames are accepted only when operating in 2553 * hostap, adhoc, or monitor modes 2554 * o enable promiscuous mode 2555 * - when in monitor mode 2556 * - if interface marked PROMISC (assumes bridge setting is filtered) 2557 * o accept beacons: 2558 * - when operating in station mode for collecting rssi data when 2559 * the station is otherwise quiet, or 2560 * - when operating in adhoc mode so the 802.11 layer creates 2561 * node table entries for peers, 2562 * - when scanning 2563 * - when doing s/w beacon miss (e.g. for ap+sta) 2564 * - when operating in ap mode in 11g to detect overlapping bss that 2565 * require protection 2566 * o accept control frames: 2567 * - when in monitor mode 2568 * XXX BAR frames for 11n 2569 * XXX HT protection for 11n 2570 */ 2571static u_int32_t 2572ath_calcrxfilter(struct ath_softc *sc) 2573{ 2574 struct ifnet *ifp = sc->sc_ifp; 2575 struct ieee80211com *ic = ifp->if_l2com; 2576 u_int32_t rfilt; 2577 2578 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2579#if HAL_ABI_VERSION < 0x08011600 2580 rfilt |= (ath_hal_getrxfilter(sc->sc_ah) & 2581 (HAL_RX_FILTER_PHYRADAR | HAL_RX_FILTER_PHYERR)); 2582#elif HAL_ABI_VERSION < 0x08060100 2583 if (ic->ic_opmode == IEEE80211_M_STA && 2584 !sc->sc_needmib && !sc->sc_scanning) 2585 rfilt |= HAL_RX_FILTER_PHYERR; 2586#else 2587 if (!sc->sc_needmib && !sc->sc_scanning) 2588 rfilt |= HAL_RX_FILTER_PHYERR; 2589#endif 2590 if (ic->ic_opmode != IEEE80211_M_STA) 2591 rfilt |= HAL_RX_FILTER_PROBEREQ; 2592 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2593 rfilt |= HAL_RX_FILTER_PROM; 2594 if (ic->ic_opmode == IEEE80211_M_STA || 2595 ic->ic_opmode == IEEE80211_M_IBSS || 2596 sc->sc_swbmiss || sc->sc_scanning) 2597 rfilt |= HAL_RX_FILTER_BEACON; 2598 /* 2599 * NB: We don't recalculate the rx filter when 2600 * ic_protmode changes; otherwise we could do 2601 * this only when ic_protmode != NONE. 2602 */ 2603 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2604 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2605 rfilt |= HAL_RX_FILTER_BEACON; 2606 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2607 rfilt |= HAL_RX_FILTER_CONTROL; 2608 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2609 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2610 return rfilt; 2611} 2612 2613static void 2614ath_update_promisc(struct ifnet *ifp) 2615{ 2616 struct ath_softc *sc = ifp->if_softc; 2617 u_int32_t rfilt; 2618 2619 /* configure rx filter */ 2620 rfilt = ath_calcrxfilter(sc); 2621 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2622 2623 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2624} 2625 2626static void 2627ath_update_mcast(struct ifnet *ifp) 2628{ 2629 struct ath_softc *sc = ifp->if_softc; 2630 u_int32_t mfilt[2]; 2631 2632 /* calculate and install multicast filter */ 2633 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2634 struct ifmultiaddr *ifma; 2635 /* 2636 * Merge multicast addresses to form the hardware filter. 2637 */ 2638 mfilt[0] = mfilt[1] = 0; 2639 IF_ADDR_LOCK(ifp); /* XXX need some fiddling to remove? */ 2640 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2641 caddr_t dl; 2642 u_int32_t val; 2643 u_int8_t pos; 2644 2645 /* calculate XOR of eight 6bit values */ 2646 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2647 val = LE_READ_4(dl + 0); 2648 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2649 val = LE_READ_4(dl + 3); 2650 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2651 pos &= 0x3f; 2652 mfilt[pos / 32] |= (1 << (pos % 32)); 2653 } 2654 IF_ADDR_UNLOCK(ifp); 2655 } else 2656 mfilt[0] = mfilt[1] = ~0; 2657 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2658 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2659 __func__, mfilt[0], mfilt[1]); 2660} 2661 2662static void 2663ath_mode_init(struct ath_softc *sc) 2664{ 2665 struct ifnet *ifp = sc->sc_ifp; 2666 struct ieee80211com *ic = ifp->if_l2com; 2667 struct ath_hal *ah = sc->sc_ah; 2668 u_int32_t rfilt; 2669 2670 /* configure rx filter */ 2671 rfilt = ath_calcrxfilter(sc); 2672 ath_hal_setrxfilter(ah, rfilt); 2673 2674 /* configure operational mode */ 2675 ath_hal_setopmode(ah); 2676 2677 /* 2678 * Handle any link-level address change. Note that we only 2679 * need to force ic_myaddr; any other addresses are handled 2680 * as a byproduct of the ifnet code marking the interface 2681 * down then up. 2682 * 2683 * XXX should get from lladdr instead of arpcom but that's more work 2684 */ 2685 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2686 ath_hal_setmac(ah, ic->ic_myaddr); 2687 2688 /* calculate and install multicast filter */ 2689 ath_update_mcast(ifp); 2690} 2691 2692/* 2693 * Set the slot time based on the current setting. 2694 */ 2695static void 2696ath_setslottime(struct ath_softc *sc) 2697{ 2698 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2699 struct ath_hal *ah = sc->sc_ah; 2700 u_int usec; 2701 2702 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2703 usec = 13; 2704 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2705 usec = 21; 2706 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2707 /* honor short/long slot time only in 11g */ 2708 /* XXX shouldn't honor on pure g or turbo g channel */ 2709 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2710 usec = HAL_SLOT_TIME_9; 2711 else 2712 usec = HAL_SLOT_TIME_20; 2713 } else 2714 usec = HAL_SLOT_TIME_9; 2715 2716 DPRINTF(sc, ATH_DEBUG_RESET, 2717 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2718 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2719 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2720 2721 ath_hal_setslottime(ah, usec); 2722 sc->sc_updateslot = OK; 2723} 2724 2725/* 2726 * Callback from the 802.11 layer to update the 2727 * slot time based on the current setting. 2728 */ 2729static void 2730ath_updateslot(struct ifnet *ifp) 2731{ 2732 struct ath_softc *sc = ifp->if_softc; 2733 struct ieee80211com *ic = ifp->if_l2com; 2734 2735 /* 2736 * When not coordinating the BSS, change the hardware 2737 * immediately. For other operation we defer the change 2738 * until beacon updates have propagated to the stations. 2739 */ 2740 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2741 sc->sc_updateslot = UPDATE; 2742 else 2743 ath_setslottime(sc); 2744} 2745 2746/* 2747 * Setup a h/w transmit queue for beacons. 2748 */ 2749static int 2750ath_beaconq_setup(struct ath_hal *ah) 2751{ 2752 HAL_TXQ_INFO qi; 2753 2754 memset(&qi, 0, sizeof(qi)); 2755 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2756 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2757 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2758 /* NB: for dynamic turbo, don't enable any other interrupts */ 2759 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2760 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2761} 2762 2763/* 2764 * Setup the transmit queue parameters for the beacon queue. 2765 */ 2766static int 2767ath_beaconq_config(struct ath_softc *sc) 2768{ 2769#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2770 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2771 struct ath_hal *ah = sc->sc_ah; 2772 HAL_TXQ_INFO qi; 2773 2774 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2775 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2776 /* 2777 * Always burst out beacon and CAB traffic. 2778 */ 2779 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2780 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2781 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2782 } else { 2783 struct wmeParams *wmep = 2784 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2785 /* 2786 * Adhoc mode; important thing is to use 2x cwmin. 2787 */ 2788 qi.tqi_aifs = wmep->wmep_aifsn; 2789 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2790 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2791 } 2792 2793 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2794 device_printf(sc->sc_dev, "unable to update parameters for " 2795 "beacon hardware queue!\n"); 2796 return 0; 2797 } else { 2798 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2799 return 1; 2800 } 2801#undef ATH_EXPONENT_TO_VALUE 2802} 2803 2804/* 2805 * Allocate and setup an initial beacon frame. 2806 */ 2807static int 2808ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2809{ 2810 struct ieee80211vap *vap = ni->ni_vap; 2811 struct ath_vap *avp = ATH_VAP(vap); 2812 struct ath_buf *bf; 2813 struct mbuf *m; 2814 int error; 2815 2816 bf = avp->av_bcbuf; 2817 if (bf->bf_m != NULL) { 2818 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2819 m_freem(bf->bf_m); 2820 bf->bf_m = NULL; 2821 } 2822 if (bf->bf_node != NULL) { 2823 ieee80211_free_node(bf->bf_node); 2824 bf->bf_node = NULL; 2825 } 2826 2827 /* 2828 * NB: the beacon data buffer must be 32-bit aligned; 2829 * we assume the mbuf routines will return us something 2830 * with this alignment (perhaps should assert). 2831 */ 2832 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2833 if (m == NULL) { 2834 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2835 sc->sc_stats.ast_be_nombuf++; 2836 return ENOMEM; 2837 } 2838 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2839 bf->bf_segs, &bf->bf_nseg, 2840 BUS_DMA_NOWAIT); 2841 if (error != 0) { 2842 device_printf(sc->sc_dev, 2843 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2844 __func__, error); 2845 m_freem(m); 2846 return error; 2847 } 2848 2849 /* 2850 * Calculate a TSF adjustment factor required for staggered 2851 * beacons. Note that we assume the format of the beacon 2852 * frame leaves the tstamp field immediately following the 2853 * header. 2854 */ 2855 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2856 uint64_t tsfadjust; 2857 struct ieee80211_frame *wh; 2858 2859 /* 2860 * The beacon interval is in TU's; the TSF is in usecs. 2861 * We figure out how many TU's to add to align the timestamp 2862 * then convert to TSF units and handle byte swapping before 2863 * inserting it in the frame. The hardware will then add this 2864 * each time a beacon frame is sent. Note that we align vap's 2865 * 1..N and leave vap 0 untouched. This means vap 0 has a 2866 * timestamp in one beacon interval while the others get a 2867 * timstamp aligned to the next interval. 2868 */ 2869 tsfadjust = ni->ni_intval * 2870 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2871 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2872 2873 DPRINTF(sc, ATH_DEBUG_BEACON, 2874 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2875 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2876 avp->av_bslot, ni->ni_intval, 2877 (long long unsigned) le64toh(tsfadjust)); 2878 2879 wh = mtod(m, struct ieee80211_frame *); 2880 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2881 } 2882 bf->bf_m = m; 2883 bf->bf_node = ieee80211_ref_node(ni); 2884 2885 return 0; 2886} 2887 2888/* 2889 * Setup the beacon frame for transmit. 2890 */ 2891static void 2892ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2893{ 2894#define USE_SHPREAMBLE(_ic) \ 2895 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2896 == IEEE80211_F_SHPREAMBLE) 2897 struct ieee80211_node *ni = bf->bf_node; 2898 struct ieee80211com *ic = ni->ni_ic; 2899 struct mbuf *m = bf->bf_m; 2900 struct ath_hal *ah = sc->sc_ah; 2901 struct ath_desc *ds; 2902 int flags, antenna; 2903 const HAL_RATE_TABLE *rt; 2904 u_int8_t rix, rate; 2905 2906 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2907 __func__, m, m->m_len); 2908 2909 /* setup descriptors */ 2910 ds = bf->bf_desc; 2911 2912 flags = HAL_TXDESC_NOACK; 2913 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2914 ds->ds_link = bf->bf_daddr; /* self-linked */ 2915 flags |= HAL_TXDESC_VEOL; 2916 /* 2917 * Let hardware handle antenna switching. 2918 */ 2919 antenna = sc->sc_txantenna; 2920 } else { 2921 ds->ds_link = 0; 2922 /* 2923 * Switch antenna every 4 beacons. 2924 * XXX assumes two antenna 2925 */ 2926 if (sc->sc_txantenna != 0) 2927 antenna = sc->sc_txantenna; 2928 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2929 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2930 else 2931 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2932 } 2933 2934 KASSERT(bf->bf_nseg == 1, 2935 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2936 ds->ds_data = bf->bf_segs[0].ds_addr; 2937 /* 2938 * Calculate rate code. 2939 * XXX everything at min xmit rate 2940 */ 2941 rix = 0; 2942 rt = sc->sc_currates; 2943 rate = rt->info[rix].rateCode; 2944 if (USE_SHPREAMBLE(ic)) 2945 rate |= rt->info[rix].shortPreamble; 2946 ath_hal_setuptxdesc(ah, ds 2947 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2948 , sizeof(struct ieee80211_frame)/* header length */ 2949 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2950 , ni->ni_txpower /* txpower XXX */ 2951 , rate, 1 /* series 0 rate/tries */ 2952 , HAL_TXKEYIX_INVALID /* no encryption */ 2953 , antenna /* antenna mode */ 2954 , flags /* no ack, veol for beacons */ 2955 , 0 /* rts/cts rate */ 2956 , 0 /* rts/cts duration */ 2957 ); 2958 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2959 ath_hal_filltxdesc(ah, ds 2960 , roundup(m->m_len, 4) /* buffer length */ 2961 , AH_TRUE /* first segment */ 2962 , AH_TRUE /* last segment */ 2963 , ds /* first descriptor */ 2964 ); 2965#if 0 2966 ath_desc_swap(ds); 2967#endif 2968#undef USE_SHPREAMBLE 2969} 2970 2971static void 2972ath_beacon_update(struct ieee80211vap *vap, int item) 2973{ 2974 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2975 2976 setbit(bo->bo_flags, item); 2977} 2978 2979/* 2980 * Append the contents of src to dst; both queues 2981 * are assumed to be locked. 2982 */ 2983static void 2984ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2985{ 2986 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2987 dst->axq_link = src->axq_link; 2988 src->axq_link = NULL; 2989 dst->axq_depth += src->axq_depth; 2990 src->axq_depth = 0; 2991} 2992 2993/* 2994 * Transmit a beacon frame at SWBA. Dynamic updates to the 2995 * frame contents are done as needed and the slot time is 2996 * also adjusted based on current state. 2997 */ 2998static void 2999ath_beacon_proc(void *arg, int pending) 3000{ 3001 struct ath_softc *sc = arg; 3002 struct ath_hal *ah = sc->sc_ah; 3003 struct ieee80211vap *vap; 3004 struct ath_buf *bf; 3005 int slot, otherant; 3006 uint32_t bfaddr; 3007 3008 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 3009 __func__, pending); 3010 /* 3011 * Check if the previous beacon has gone out. If 3012 * not don't try to post another, skip this period 3013 * and wait for the next. Missed beacons indicate 3014 * a problem and should not occur. If we miss too 3015 * many consecutive beacons reset the device. 3016 */ 3017 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 3018 sc->sc_bmisscount++; 3019 DPRINTF(sc, ATH_DEBUG_BEACON, 3020 "%s: missed %u consecutive beacons\n", 3021 __func__, sc->sc_bmisscount); 3022 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 3023 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 3024 return; 3025 } 3026 if (sc->sc_bmisscount != 0) { 3027 DPRINTF(sc, ATH_DEBUG_BEACON, 3028 "%s: resume beacon xmit after %u misses\n", 3029 __func__, sc->sc_bmisscount); 3030 sc->sc_bmisscount = 0; 3031 } 3032 3033 if (sc->sc_stagbeacons) { /* staggered beacons */ 3034 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3035 uint32_t tsftu; 3036 3037 tsftu = ath_hal_gettsf32(ah) >> 10; 3038 /* XXX lintval */ 3039 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 3040 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 3041 bfaddr = 0; 3042 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 3043 bf = ath_beacon_generate(sc, vap); 3044 if (bf != NULL) 3045 bfaddr = bf->bf_daddr; 3046 } 3047 } else { /* burst'd beacons */ 3048 uint32_t *bflink = &bfaddr; 3049 3050 for (slot = 0; slot < ATH_BCBUF; slot++) { 3051 vap = sc->sc_bslot[slot]; 3052 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 3053 bf = ath_beacon_generate(sc, vap); 3054 if (bf != NULL) { 3055 *bflink = bf->bf_daddr; 3056 bflink = &bf->bf_desc->ds_link; 3057 } 3058 } 3059 } 3060 *bflink = 0; /* terminate list */ 3061 } 3062 3063 /* 3064 * Handle slot time change when a non-ERP station joins/leaves 3065 * an 11g network. The 802.11 layer notifies us via callback, 3066 * we mark updateslot, then wait one beacon before effecting 3067 * the change. This gives associated stations at least one 3068 * beacon interval to note the state change. 3069 */ 3070 /* XXX locking */ 3071 if (sc->sc_updateslot == UPDATE) { 3072 sc->sc_updateslot = COMMIT; /* commit next beacon */ 3073 sc->sc_slotupdate = slot; 3074 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 3075 ath_setslottime(sc); /* commit change to h/w */ 3076 3077 /* 3078 * Check recent per-antenna transmit statistics and flip 3079 * the default antenna if noticeably more frames went out 3080 * on the non-default antenna. 3081 * XXX assumes 2 anntenae 3082 */ 3083 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 3084 otherant = sc->sc_defant & 1 ? 2 : 1; 3085 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 3086 ath_setdefantenna(sc, otherant); 3087 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 3088 } 3089 3090 if (bfaddr != 0) { 3091 /* 3092 * Stop any current dma and put the new frame on the queue. 3093 * This should never fail since we check above that no frames 3094 * are still pending on the queue. 3095 */ 3096 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 3097 DPRINTF(sc, ATH_DEBUG_ANY, 3098 "%s: beacon queue %u did not stop?\n", 3099 __func__, sc->sc_bhalq); 3100 } 3101 /* NB: cabq traffic should already be queued and primed */ 3102 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 3103 ath_hal_txstart(ah, sc->sc_bhalq); 3104 3105 sc->sc_stats.ast_be_xmit++; 3106 } 3107} 3108 3109static struct ath_buf * 3110ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 3111{ 3112 struct ath_vap *avp = ATH_VAP(vap); 3113 struct ath_txq *cabq = sc->sc_cabq; 3114 struct ath_buf *bf; 3115 struct mbuf *m; 3116 int nmcastq, error; 3117 3118 KASSERT(vap->iv_state == IEEE80211_S_RUN, 3119 ("not running, state %d", vap->iv_state)); 3120 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3121 3122 /* 3123 * Update dynamic beacon contents. If this returns 3124 * non-zero then we need to remap the memory because 3125 * the beacon frame changed size (probably because 3126 * of the TIM bitmap). 3127 */ 3128 bf = avp->av_bcbuf; 3129 m = bf->bf_m; 3130 nmcastq = avp->av_mcastq.axq_depth; 3131 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 3132 /* XXX too conservative? */ 3133 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3134 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3135 bf->bf_segs, &bf->bf_nseg, 3136 BUS_DMA_NOWAIT); 3137 if (error != 0) { 3138 if_printf(vap->iv_ifp, 3139 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3140 __func__, error); 3141 return NULL; 3142 } 3143 } 3144 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 3145 DPRINTF(sc, ATH_DEBUG_BEACON, 3146 "%s: cabq did not drain, mcastq %u cabq %u\n", 3147 __func__, nmcastq, cabq->axq_depth); 3148 sc->sc_stats.ast_cabq_busy++; 3149 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 3150 /* 3151 * CABQ traffic from a previous vap is still pending. 3152 * We must drain the q before this beacon frame goes 3153 * out as otherwise this vap's stations will get cab 3154 * frames from a different vap. 3155 * XXX could be slow causing us to miss DBA 3156 */ 3157 ath_tx_draintxq(sc, cabq); 3158 } 3159 } 3160 ath_beacon_setup(sc, bf); 3161 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3162 3163 /* 3164 * Enable the CAB queue before the beacon queue to 3165 * insure cab frames are triggered by this beacon. 3166 */ 3167 if (avp->av_boff.bo_tim[4] & 1) { 3168 struct ath_hal *ah = sc->sc_ah; 3169 3170 /* NB: only at DTIM */ 3171 ATH_TXQ_LOCK(cabq); 3172 ATH_TXQ_LOCK(&avp->av_mcastq); 3173 if (nmcastq) { 3174 struct ath_buf *bfm; 3175 3176 /* 3177 * Move frames from the s/w mcast q to the h/w cab q. 3178 * XXX MORE_DATA bit 3179 */ 3180 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 3181 if (cabq->axq_link != NULL) { 3182 *cabq->axq_link = bfm->bf_daddr; 3183 } else 3184 ath_hal_puttxbuf(ah, cabq->axq_qnum, 3185 bfm->bf_daddr); 3186 ath_txqmove(cabq, &avp->av_mcastq); 3187 3188 sc->sc_stats.ast_cabq_xmit += nmcastq; 3189 } 3190 /* NB: gated by beacon so safe to start here */ 3191 ath_hal_txstart(ah, cabq->axq_qnum); 3192 ATH_TXQ_UNLOCK(cabq); 3193 ATH_TXQ_UNLOCK(&avp->av_mcastq); 3194 } 3195 return bf; 3196} 3197 3198static void 3199ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3200{ 3201 struct ath_vap *avp = ATH_VAP(vap); 3202 struct ath_hal *ah = sc->sc_ah; 3203 struct ath_buf *bf; 3204 struct mbuf *m; 3205 int error; 3206 3207 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3208 3209 /* 3210 * Update dynamic beacon contents. If this returns 3211 * non-zero then we need to remap the memory because 3212 * the beacon frame changed size (probably because 3213 * of the TIM bitmap). 3214 */ 3215 bf = avp->av_bcbuf; 3216 m = bf->bf_m; 3217 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3218 /* XXX too conservative? */ 3219 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3220 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3221 bf->bf_segs, &bf->bf_nseg, 3222 BUS_DMA_NOWAIT); 3223 if (error != 0) { 3224 if_printf(vap->iv_ifp, 3225 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3226 __func__, error); 3227 return; 3228 } 3229 } 3230 ath_beacon_setup(sc, bf); 3231 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3232 3233 /* NB: caller is known to have already stopped tx dma */ 3234 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3235 ath_hal_txstart(ah, sc->sc_bhalq); 3236} 3237 3238/* 3239 * Reset the hardware after detecting beacons have stopped. 3240 */ 3241static void 3242ath_bstuck_proc(void *arg, int pending) 3243{ 3244 struct ath_softc *sc = arg; 3245 struct ifnet *ifp = sc->sc_ifp; 3246 3247 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3248 sc->sc_bmisscount); 3249 ath_reset(ifp); 3250} 3251 3252/* 3253 * Reclaim beacon resources and return buffer to the pool. 3254 */ 3255static void 3256ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3257{ 3258 3259 if (bf->bf_m != NULL) { 3260 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3261 m_freem(bf->bf_m); 3262 bf->bf_m = NULL; 3263 } 3264 if (bf->bf_node != NULL) { 3265 ieee80211_free_node(bf->bf_node); 3266 bf->bf_node = NULL; 3267 } 3268 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3269} 3270 3271/* 3272 * Reclaim beacon resources. 3273 */ 3274static void 3275ath_beacon_free(struct ath_softc *sc) 3276{ 3277 struct ath_buf *bf; 3278 3279 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3280 if (bf->bf_m != NULL) { 3281 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3282 m_freem(bf->bf_m); 3283 bf->bf_m = NULL; 3284 } 3285 if (bf->bf_node != NULL) { 3286 ieee80211_free_node(bf->bf_node); 3287 bf->bf_node = NULL; 3288 } 3289 } 3290} 3291 3292/* 3293 * Configure the beacon and sleep timers. 3294 * 3295 * When operating as an AP this resets the TSF and sets 3296 * up the hardware to notify us when we need to issue beacons. 3297 * 3298 * When operating in station mode this sets up the beacon 3299 * timers according to the timestamp of the last received 3300 * beacon and the current TSF, configures PCF and DTIM 3301 * handling, programs the sleep registers so the hardware 3302 * will wakeup in time to receive beacons, and configures 3303 * the beacon miss handling so we'll receive a BMISS 3304 * interrupt when we stop seeing beacons from the AP 3305 * we've associated with. 3306 */ 3307static void 3308ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3309{ 3310#define TSF_TO_TU(_h,_l) \ 3311 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3312#define FUDGE 2 3313 struct ath_hal *ah = sc->sc_ah; 3314 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3315 struct ieee80211_node *ni; 3316 u_int32_t nexttbtt, intval, tsftu; 3317 u_int64_t tsf; 3318 3319 if (vap == NULL) 3320 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3321 ni = vap->iv_bss; 3322 3323 /* extract tstamp from last beacon and convert to TU */ 3324 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3325 LE_READ_4(ni->ni_tstamp.data)); 3326 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3327 /* 3328 * For multi-bss ap support beacons are either staggered 3329 * evenly over N slots or burst together. For the former 3330 * arrange for the SWBA to be delivered for each slot. 3331 * Slots that are not occupied will generate nothing. 3332 */ 3333 /* NB: the beacon interval is kept internally in TU's */ 3334 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3335 if (sc->sc_stagbeacons) 3336 intval /= ATH_BCBUF; 3337 } else { 3338 /* NB: the beacon interval is kept internally in TU's */ 3339 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3340 } 3341 if (nexttbtt == 0) /* e.g. for ap mode */ 3342 nexttbtt = intval; 3343 else if (intval) /* NB: can be 0 for monitor mode */ 3344 nexttbtt = roundup(nexttbtt, intval); 3345 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3346 __func__, nexttbtt, intval, ni->ni_intval); 3347 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3348 HAL_BEACON_STATE bs; 3349 int dtimperiod, dtimcount; 3350 int cfpperiod, cfpcount; 3351 3352 /* 3353 * Setup dtim and cfp parameters according to 3354 * last beacon we received (which may be none). 3355 */ 3356 dtimperiod = ni->ni_dtim_period; 3357 if (dtimperiod <= 0) /* NB: 0 if not known */ 3358 dtimperiod = 1; 3359 dtimcount = ni->ni_dtim_count; 3360 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3361 dtimcount = 0; /* XXX? */ 3362 cfpperiod = 1; /* NB: no PCF support yet */ 3363 cfpcount = 0; 3364 /* 3365 * Pull nexttbtt forward to reflect the current 3366 * TSF and calculate dtim+cfp state for the result. 3367 */ 3368 tsf = ath_hal_gettsf64(ah); 3369 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3370 do { 3371 nexttbtt += intval; 3372 if (--dtimcount < 0) { 3373 dtimcount = dtimperiod - 1; 3374 if (--cfpcount < 0) 3375 cfpcount = cfpperiod - 1; 3376 } 3377 } while (nexttbtt < tsftu); 3378 memset(&bs, 0, sizeof(bs)); 3379 bs.bs_intval = intval; 3380 bs.bs_nexttbtt = nexttbtt; 3381 bs.bs_dtimperiod = dtimperiod*intval; 3382 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3383 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3384 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3385 bs.bs_cfpmaxduration = 0; 3386#if 0 3387 /* 3388 * The 802.11 layer records the offset to the DTIM 3389 * bitmap while receiving beacons; use it here to 3390 * enable h/w detection of our AID being marked in 3391 * the bitmap vector (to indicate frames for us are 3392 * pending at the AP). 3393 * XXX do DTIM handling in s/w to WAR old h/w bugs 3394 * XXX enable based on h/w rev for newer chips 3395 */ 3396 bs.bs_timoffset = ni->ni_timoff; 3397#endif 3398 /* 3399 * Calculate the number of consecutive beacons to miss 3400 * before taking a BMISS interrupt. 3401 * Note that we clamp the result to at most 10 beacons. 3402 */ 3403 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3404 if (bs.bs_bmissthreshold > 10) 3405 bs.bs_bmissthreshold = 10; 3406 else if (bs.bs_bmissthreshold <= 0) 3407 bs.bs_bmissthreshold = 1; 3408 3409 /* 3410 * Calculate sleep duration. The configuration is 3411 * given in ms. We insure a multiple of the beacon 3412 * period is used. Also, if the sleep duration is 3413 * greater than the DTIM period then it makes senses 3414 * to make it a multiple of that. 3415 * 3416 * XXX fixed at 100ms 3417 */ 3418 bs.bs_sleepduration = 3419 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3420 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3421 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3422 3423 DPRINTF(sc, ATH_DEBUG_BEACON, 3424 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3425 , __func__ 3426 , tsf, tsftu 3427 , bs.bs_intval 3428 , bs.bs_nexttbtt 3429 , bs.bs_dtimperiod 3430 , bs.bs_nextdtim 3431 , bs.bs_bmissthreshold 3432 , bs.bs_sleepduration 3433 , bs.bs_cfpperiod 3434 , bs.bs_cfpmaxduration 3435 , bs.bs_cfpnext 3436 , bs.bs_timoffset 3437 ); 3438 ath_hal_intrset(ah, 0); 3439 ath_hal_beacontimers(ah, &bs); 3440 sc->sc_imask |= HAL_INT_BMISS; 3441 ath_hal_intrset(ah, sc->sc_imask); 3442 } else { 3443 ath_hal_intrset(ah, 0); 3444 if (nexttbtt == intval) 3445 intval |= HAL_BEACON_RESET_TSF; 3446 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3447 /* 3448 * In IBSS mode enable the beacon timers but only 3449 * enable SWBA interrupts if we need to manually 3450 * prepare beacon frames. Otherwise we use a 3451 * self-linked tx descriptor and let the hardware 3452 * deal with things. 3453 */ 3454 intval |= HAL_BEACON_ENA; 3455 if (!sc->sc_hasveol) 3456 sc->sc_imask |= HAL_INT_SWBA; 3457 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3458 /* 3459 * Pull nexttbtt forward to reflect 3460 * the current TSF. 3461 */ 3462 tsf = ath_hal_gettsf64(ah); 3463 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3464 do { 3465 nexttbtt += intval; 3466 } while (nexttbtt < tsftu); 3467 } 3468 ath_beaconq_config(sc); 3469 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3470 /* 3471 * In AP mode we enable the beacon timers and 3472 * SWBA interrupts to prepare beacon frames. 3473 */ 3474 intval |= HAL_BEACON_ENA; 3475 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3476 ath_beaconq_config(sc); 3477 } 3478 ath_hal_beaconinit(ah, nexttbtt, intval); 3479 sc->sc_bmisscount = 0; 3480 ath_hal_intrset(ah, sc->sc_imask); 3481 /* 3482 * When using a self-linked beacon descriptor in 3483 * ibss mode load it once here. 3484 */ 3485 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3486 ath_beacon_start_adhoc(sc, vap); 3487 } 3488 sc->sc_syncbeacon = 0; 3489#undef FUDGE 3490#undef TSF_TO_TU 3491} 3492 3493static void 3494ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3495{ 3496 bus_addr_t *paddr = (bus_addr_t*) arg; 3497 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3498 *paddr = segs->ds_addr; 3499} 3500 3501static int 3502ath_descdma_setup(struct ath_softc *sc, 3503 struct ath_descdma *dd, ath_bufhead *head, 3504 const char *name, int nbuf, int ndesc) 3505{ 3506#define DS2PHYS(_dd, _ds) \ 3507 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3508 struct ifnet *ifp = sc->sc_ifp; 3509 struct ath_desc *ds; 3510 struct ath_buf *bf; 3511 int i, bsize, error; 3512 3513 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3514 __func__, name, nbuf, ndesc); 3515 3516 dd->dd_name = name; 3517 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3518 3519 /* 3520 * Setup DMA descriptor area. 3521 */ 3522 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3523 PAGE_SIZE, 0, /* alignment, bounds */ 3524 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3525 BUS_SPACE_MAXADDR, /* highaddr */ 3526 NULL, NULL, /* filter, filterarg */ 3527 dd->dd_desc_len, /* maxsize */ 3528 1, /* nsegments */ 3529 dd->dd_desc_len, /* maxsegsize */ 3530 BUS_DMA_ALLOCNOW, /* flags */ 3531 NULL, /* lockfunc */ 3532 NULL, /* lockarg */ 3533 &dd->dd_dmat); 3534 if (error != 0) { 3535 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3536 return error; 3537 } 3538 3539 /* allocate descriptors */ 3540 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3541 if (error != 0) { 3542 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3543 "error %u\n", dd->dd_name, error); 3544 goto fail0; 3545 } 3546 3547 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3548 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3549 &dd->dd_dmamap); 3550 if (error != 0) { 3551 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3552 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3553 goto fail1; 3554 } 3555 3556 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3557 dd->dd_desc, dd->dd_desc_len, 3558 ath_load_cb, &dd->dd_desc_paddr, 3559 BUS_DMA_NOWAIT); 3560 if (error != 0) { 3561 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3562 dd->dd_name, error); 3563 goto fail2; 3564 } 3565 3566 ds = dd->dd_desc; 3567 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3568 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3569 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3570 3571 /* allocate rx buffers */ 3572 bsize = sizeof(struct ath_buf) * nbuf; 3573 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3574 if (bf == NULL) { 3575 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3576 dd->dd_name, bsize); 3577 goto fail3; 3578 } 3579 dd->dd_bufptr = bf; 3580 3581 STAILQ_INIT(head); 3582 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3583 bf->bf_desc = ds; 3584 bf->bf_daddr = DS2PHYS(dd, ds); 3585 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3586 &bf->bf_dmamap); 3587 if (error != 0) { 3588 if_printf(ifp, "unable to create dmamap for %s " 3589 "buffer %u, error %u\n", dd->dd_name, i, error); 3590 ath_descdma_cleanup(sc, dd, head); 3591 return error; 3592 } 3593 STAILQ_INSERT_TAIL(head, bf, bf_list); 3594 } 3595 return 0; 3596fail3: 3597 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3598fail2: 3599 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3600fail1: 3601 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3602fail0: 3603 bus_dma_tag_destroy(dd->dd_dmat); 3604 memset(dd, 0, sizeof(*dd)); 3605 return error; 3606#undef DS2PHYS 3607} 3608 3609static void 3610ath_descdma_cleanup(struct ath_softc *sc, 3611 struct ath_descdma *dd, ath_bufhead *head) 3612{ 3613 struct ath_buf *bf; 3614 struct ieee80211_node *ni; 3615 3616 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3617 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3618 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3619 bus_dma_tag_destroy(dd->dd_dmat); 3620 3621 STAILQ_FOREACH(bf, head, bf_list) { 3622 if (bf->bf_m) { 3623 m_freem(bf->bf_m); 3624 bf->bf_m = NULL; 3625 } 3626 if (bf->bf_dmamap != NULL) { 3627 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3628 bf->bf_dmamap = NULL; 3629 } 3630 ni = bf->bf_node; 3631 bf->bf_node = NULL; 3632 if (ni != NULL) { 3633 /* 3634 * Reclaim node reference. 3635 */ 3636 ieee80211_free_node(ni); 3637 } 3638 } 3639 3640 STAILQ_INIT(head); 3641 free(dd->dd_bufptr, M_ATHDEV); 3642 memset(dd, 0, sizeof(*dd)); 3643} 3644 3645static int 3646ath_desc_alloc(struct ath_softc *sc) 3647{ 3648 int error; 3649 3650 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3651 "rx", ath_rxbuf, 1); 3652 if (error != 0) 3653 return error; 3654 3655 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3656 "tx", ath_txbuf, ATH_TXDESC); 3657 if (error != 0) { 3658 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3659 return error; 3660 } 3661 3662 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3663 "beacon", ATH_BCBUF, 1); 3664 if (error != 0) { 3665 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3666 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3667 return error; 3668 } 3669 return 0; 3670} 3671 3672static void 3673ath_desc_free(struct ath_softc *sc) 3674{ 3675 3676 if (sc->sc_bdma.dd_desc_len != 0) 3677 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3678 if (sc->sc_txdma.dd_desc_len != 0) 3679 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3680 if (sc->sc_rxdma.dd_desc_len != 0) 3681 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3682} 3683 3684static struct ieee80211_node * 3685ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3686{ 3687 struct ieee80211com *ic = vap->iv_ic; 3688 struct ath_softc *sc = ic->ic_ifp->if_softc; 3689 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3690 struct ath_node *an; 3691 3692 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3693 if (an == NULL) { 3694 /* XXX stat+msg */ 3695 return NULL; 3696 } 3697 ath_rate_node_init(sc, an); 3698 3699 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3700 return &an->an_node; 3701} 3702 3703static void 3704ath_node_free(struct ieee80211_node *ni) 3705{ 3706 struct ieee80211com *ic = ni->ni_ic; 3707 struct ath_softc *sc = ic->ic_ifp->if_softc; 3708 3709 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3710 3711 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3712 sc->sc_node_free(ni); 3713} 3714 3715static void 3716ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3717{ 3718 struct ieee80211com *ic = ni->ni_ic; 3719 struct ath_softc *sc = ic->ic_ifp->if_softc; 3720 struct ath_hal *ah = sc->sc_ah; 3721 HAL_CHANNEL hchan; 3722 3723 *rssi = ic->ic_node_getrssi(ni); 3724 if (ni->ni_chan != IEEE80211_CHAN_ANYC) { 3725 ath_mapchan(ic, &hchan, ni->ni_chan); 3726 *noise = ath_hal_getchannoise(ah, &hchan); 3727 } else 3728 *noise = -95; /* nominally correct */ 3729} 3730 3731static int 3732ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3733{ 3734 struct ath_hal *ah = sc->sc_ah; 3735 int error; 3736 struct mbuf *m; 3737 struct ath_desc *ds; 3738 3739 m = bf->bf_m; 3740 if (m == NULL) { 3741 /* 3742 * NB: by assigning a page to the rx dma buffer we 3743 * implicitly satisfy the Atheros requirement that 3744 * this buffer be cache-line-aligned and sized to be 3745 * multiple of the cache line size. Not doing this 3746 * causes weird stuff to happen (for the 5210 at least). 3747 */ 3748 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3749 if (m == NULL) { 3750 DPRINTF(sc, ATH_DEBUG_ANY, 3751 "%s: no mbuf/cluster\n", __func__); 3752 sc->sc_stats.ast_rx_nombuf++; 3753 return ENOMEM; 3754 } 3755 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3756 3757 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3758 bf->bf_dmamap, m, 3759 bf->bf_segs, &bf->bf_nseg, 3760 BUS_DMA_NOWAIT); 3761 if (error != 0) { 3762 DPRINTF(sc, ATH_DEBUG_ANY, 3763 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3764 __func__, error); 3765 sc->sc_stats.ast_rx_busdma++; 3766 m_freem(m); 3767 return error; 3768 } 3769 KASSERT(bf->bf_nseg == 1, 3770 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3771 bf->bf_m = m; 3772 } 3773 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3774 3775 /* 3776 * Setup descriptors. For receive we always terminate 3777 * the descriptor list with a self-linked entry so we'll 3778 * not get overrun under high load (as can happen with a 3779 * 5212 when ANI processing enables PHY error frames). 3780 * 3781 * To insure the last descriptor is self-linked we create 3782 * each descriptor as self-linked and add it to the end. As 3783 * each additional descriptor is added the previous self-linked 3784 * entry is ``fixed'' naturally. This should be safe even 3785 * if DMA is happening. When processing RX interrupts we 3786 * never remove/process the last, self-linked, entry on the 3787 * descriptor list. This insures the hardware always has 3788 * someplace to write a new frame. 3789 */ 3790 ds = bf->bf_desc; 3791 ds->ds_link = bf->bf_daddr; /* link to self */ 3792 ds->ds_data = bf->bf_segs[0].ds_addr; 3793 ath_hal_setuprxdesc(ah, ds 3794 , m->m_len /* buffer size */ 3795 , 0 3796 ); 3797 3798 if (sc->sc_rxlink != NULL) 3799 *sc->sc_rxlink = bf->bf_daddr; 3800 sc->sc_rxlink = &ds->ds_link; 3801 return 0; 3802} 3803 3804/* 3805 * Extend 15-bit time stamp from rx descriptor to 3806 * a full 64-bit TSF using the specified TSF. 3807 */ 3808static __inline u_int64_t 3809ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3810{ 3811 if ((tsf & 0x7fff) < rstamp) 3812 tsf -= 0x8000; 3813 return ((tsf &~ 0x7fff) | rstamp); 3814} 3815 3816/* 3817 * Intercept management frames to collect beacon rssi data 3818 * and to do ibss merges. 3819 */ 3820static void 3821ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3822 int subtype, int rssi, int noise, u_int32_t rstamp) 3823{ 3824 struct ieee80211vap *vap = ni->ni_vap; 3825 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3826 3827 /* 3828 * Call up first so subsequent work can use information 3829 * potentially stored in the node (e.g. for ibss merge). 3830 */ 3831 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, noise, rstamp); 3832 switch (subtype) { 3833 case IEEE80211_FC0_SUBTYPE_BEACON: 3834 /* update rssi statistics for use by the hal */ 3835 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3836 if (sc->sc_syncbeacon && 3837 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3838 /* 3839 * Resync beacon timers using the tsf of the beacon 3840 * frame we just received. 3841 */ 3842 ath_beacon_config(sc, vap); 3843 } 3844 /* fall thru... */ 3845 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3846 if (vap->iv_opmode == IEEE80211_M_IBSS && 3847 vap->iv_state == IEEE80211_S_RUN) { 3848 u_int64_t tsf = ath_extend_tsf(rstamp, 3849 ath_hal_gettsf64(sc->sc_ah)); 3850 /* 3851 * Handle ibss merge as needed; check the tsf on the 3852 * frame before attempting the merge. The 802.11 spec 3853 * says the station should change it's bssid to match 3854 * the oldest station with the same ssid, where oldest 3855 * is determined by the tsf. Note that hardware 3856 * reconfiguration happens through callback to 3857 * ath_newstate as the state machine will go from 3858 * RUN -> RUN when this happens. 3859 */ 3860 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3861 DPRINTF(sc, ATH_DEBUG_STATE, 3862 "ibss merge, rstamp %u tsf %ju " 3863 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3864 (uintmax_t)ni->ni_tstamp.tsf); 3865 (void) ieee80211_ibss_merge(ni); 3866 } 3867 } 3868 break; 3869 } 3870} 3871 3872/* 3873 * Set the default antenna. 3874 */ 3875static void 3876ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3877{ 3878 struct ath_hal *ah = sc->sc_ah; 3879 3880 /* XXX block beacon interrupts */ 3881 ath_hal_setdefantenna(ah, antenna); 3882 if (sc->sc_defant != antenna) 3883 sc->sc_stats.ast_ant_defswitch++; 3884 sc->sc_defant = antenna; 3885 sc->sc_rxotherant = 0; 3886} 3887 3888static int 3889ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3890 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3891{ 3892#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3893#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3894#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3895#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3896 struct ath_softc *sc = ifp->if_softc; 3897 const HAL_RATE_TABLE *rt; 3898 uint8_t rix; 3899 3900 /* 3901 * Discard anything shorter than an ack or cts. 3902 */ 3903 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 3904 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 3905 __func__, m->m_pkthdr.len); 3906 sc->sc_stats.ast_rx_tooshort++; 3907 return 0; 3908 } 3909 rt = sc->sc_currates; 3910 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3911 rix = rt->rateCodeToIndex[rs->rs_rate]; 3912 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3913 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3914#ifdef AH_SUPPORT_AR5416 3915 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3916 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3917 if ((rs->rs_flags & HAL_RX_2040) == 0) 3918 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3919 else if (sc->sc_curchan.channelFlags & CHANNEL_HT40PLUS) 3920 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3921 else 3922 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3923 if ((rs->rs_flags & HAL_RX_GI) == 0) 3924 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3925 } 3926#endif 3927 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3928 if (rs->rs_status & HAL_RXERR_CRC) 3929 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3930 /* XXX propagate other error flags from descriptor */ 3931 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf; 3932 sc->sc_rx_th.wr_antnoise = nf; 3933 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3934 3935 bpf_mtap2(ifp->if_bpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 3936 3937 return 1; 3938#undef CHAN_HT 3939#undef CHAN_HT20 3940#undef CHAN_HT40U 3941#undef CHAN_HT40D 3942} 3943 3944static void 3945ath_handle_micerror(struct ieee80211com *ic, 3946 struct ieee80211_frame *wh, int keyix) 3947{ 3948 struct ieee80211_node *ni; 3949 3950 /* XXX recheck MIC to deal w/ chips that lie */ 3951 /* XXX discard MIC errors on !data frames */ 3952 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3953 if (ni != NULL) { 3954 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3955 ieee80211_free_node(ni); 3956 } 3957} 3958 3959static void 3960ath_rx_proc(void *arg, int npending) 3961{ 3962#define PA2DESC(_sc, _pa) \ 3963 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3964 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3965 struct ath_softc *sc = arg; 3966 struct ath_buf *bf; 3967 struct ifnet *ifp = sc->sc_ifp; 3968 struct ieee80211com *ic = ifp->if_l2com; 3969 struct ath_hal *ah = sc->sc_ah; 3970 struct ath_desc *ds; 3971 struct ath_rx_status *rs; 3972 struct mbuf *m; 3973 struct ieee80211_node *ni; 3974 int len, type, ngood; 3975 u_int phyerr; 3976 HAL_STATUS status; 3977 int16_t nf; 3978 u_int64_t tsf; 3979 3980 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3981 ngood = 0; 3982 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3983 sc->sc_stats.ast_rx_noise = nf; 3984 tsf = ath_hal_gettsf64(ah); 3985 do { 3986 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3987 if (bf == NULL) { /* NB: shouldn't happen */ 3988 if_printf(ifp, "%s: no buffer!\n", __func__); 3989 break; 3990 } 3991 m = bf->bf_m; 3992 if (m == NULL) { /* NB: shouldn't happen */ 3993 /* 3994 * If mbuf allocation failed previously there 3995 * will be no mbuf; try again to re-populate it. 3996 */ 3997 /* XXX make debug msg */ 3998 if_printf(ifp, "%s: no mbuf!\n", __func__); 3999 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 4000 goto rx_next; 4001 } 4002 ds = bf->bf_desc; 4003 if (ds->ds_link == bf->bf_daddr) { 4004 /* NB: never process the self-linked entry at the end */ 4005 break; 4006 } 4007 /* XXX sync descriptor memory */ 4008 /* 4009 * Must provide the virtual address of the current 4010 * descriptor, the physical address, and the virtual 4011 * address of the next descriptor in the h/w chain. 4012 * This allows the HAL to look ahead to see if the 4013 * hardware is done with a descriptor by checking the 4014 * done bit in the following descriptor and the address 4015 * of the current descriptor the DMA engine is working 4016 * on. All this is necessary because of our use of 4017 * a self-linked list to avoid rx overruns. 4018 */ 4019 rs = &bf->bf_status.ds_rxstat; 4020 status = ath_hal_rxprocdesc(ah, ds, 4021 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 4022#ifdef ATH_DEBUG 4023 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 4024 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 4025#endif 4026 if (status == HAL_EINPROGRESS) 4027 break; 4028 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 4029 if (rs->rs_status != 0) { 4030 if (rs->rs_status & HAL_RXERR_CRC) 4031 sc->sc_stats.ast_rx_crcerr++; 4032 if (rs->rs_status & HAL_RXERR_FIFO) 4033 sc->sc_stats.ast_rx_fifoerr++; 4034 if (rs->rs_status & HAL_RXERR_PHY) { 4035 sc->sc_stats.ast_rx_phyerr++; 4036 phyerr = rs->rs_phyerr & 0x1f; 4037 sc->sc_stats.ast_rx_phy[phyerr]++; 4038 goto rx_error; /* NB: don't count in ierrors */ 4039 } 4040 if (rs->rs_status & HAL_RXERR_DECRYPT) { 4041 /* 4042 * Decrypt error. If the error occurred 4043 * because there was no hardware key, then 4044 * let the frame through so the upper layers 4045 * can process it. This is necessary for 5210 4046 * parts which have no way to setup a ``clear'' 4047 * key cache entry. 4048 * 4049 * XXX do key cache faulting 4050 */ 4051 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 4052 goto rx_accept; 4053 sc->sc_stats.ast_rx_badcrypt++; 4054 } 4055 if (rs->rs_status & HAL_RXERR_MIC) { 4056 sc->sc_stats.ast_rx_badmic++; 4057 /* 4058 * Do minimal work required to hand off 4059 * the 802.11 header for notifcation. 4060 */ 4061 /* XXX frag's and qos frames */ 4062 len = rs->rs_datalen; 4063 if (len >= sizeof (struct ieee80211_frame)) { 4064 bus_dmamap_sync(sc->sc_dmat, 4065 bf->bf_dmamap, 4066 BUS_DMASYNC_POSTREAD); 4067 ath_handle_micerror(ic, 4068 mtod(m, struct ieee80211_frame *), 4069 sc->sc_splitmic ? 4070 rs->rs_keyix-32 : rs->rs_keyix); 4071 } 4072 } 4073 ifp->if_ierrors++; 4074rx_error: 4075 /* 4076 * Cleanup any pending partial frame. 4077 */ 4078 if (sc->sc_rxpending != NULL) { 4079 m_freem(sc->sc_rxpending); 4080 sc->sc_rxpending = NULL; 4081 } 4082 /* 4083 * When a tap is present pass error frames 4084 * that have been requested. By default we 4085 * pass decrypt+mic errors but others may be 4086 * interesting (e.g. crc). 4087 */ 4088 if (bpf_peers_present(ifp->if_bpf) && 4089 (rs->rs_status & sc->sc_monpass)) { 4090 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4091 BUS_DMASYNC_POSTREAD); 4092 /* NB: bpf needs the mbuf length setup */ 4093 len = rs->rs_datalen; 4094 m->m_pkthdr.len = m->m_len = len; 4095 (void) ath_rx_tap(ifp, m, rs, tsf, nf); 4096 } 4097 /* XXX pass MIC errors up for s/w reclaculation */ 4098 goto rx_next; 4099 } 4100rx_accept: 4101 /* 4102 * Sync and unmap the frame. At this point we're 4103 * committed to passing the mbuf somewhere so clear 4104 * bf_m; this means a new mbuf must be allocated 4105 * when the rx descriptor is setup again to receive 4106 * another frame. 4107 */ 4108 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4109 BUS_DMASYNC_POSTREAD); 4110 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4111 bf->bf_m = NULL; 4112 4113 len = rs->rs_datalen; 4114 m->m_len = len; 4115 4116 if (rs->rs_more) { 4117 /* 4118 * Frame spans multiple descriptors; save 4119 * it for the next completed descriptor, it 4120 * will be used to construct a jumbogram. 4121 */ 4122 if (sc->sc_rxpending != NULL) { 4123 /* NB: max frame size is currently 2 clusters */ 4124 sc->sc_stats.ast_rx_toobig++; 4125 m_freem(sc->sc_rxpending); 4126 } 4127 m->m_pkthdr.rcvif = ifp; 4128 m->m_pkthdr.len = len; 4129 sc->sc_rxpending = m; 4130 goto rx_next; 4131 } else if (sc->sc_rxpending != NULL) { 4132 /* 4133 * This is the second part of a jumbogram, 4134 * chain it to the first mbuf, adjust the 4135 * frame length, and clear the rxpending state. 4136 */ 4137 sc->sc_rxpending->m_next = m; 4138 sc->sc_rxpending->m_pkthdr.len += len; 4139 m = sc->sc_rxpending; 4140 sc->sc_rxpending = NULL; 4141 } else { 4142 /* 4143 * Normal single-descriptor receive; setup 4144 * the rcvif and packet length. 4145 */ 4146 m->m_pkthdr.rcvif = ifp; 4147 m->m_pkthdr.len = len; 4148 } 4149 4150 ifp->if_ipackets++; 4151 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 4152 4153 if (bpf_peers_present(ifp->if_bpf) && 4154 !ath_rx_tap(ifp, m, rs, tsf, nf)) { 4155 m_freem(m); /* XXX reclaim */ 4156 goto rx_next; 4157 } 4158 4159 /* 4160 * From this point on we assume the frame is at least 4161 * as large as ieee80211_frame_min; verify that. 4162 */ 4163 if (len < IEEE80211_MIN_LEN) { 4164 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 4165 __func__, len); 4166 sc->sc_stats.ast_rx_tooshort++; 4167 m_freem(m); 4168 goto rx_next; 4169 } 4170 4171 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 4172 const HAL_RATE_TABLE *rt = sc->sc_currates; 4173 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 4174 4175 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 4176 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 4177 } 4178 4179 m_adj(m, -IEEE80211_CRC_LEN); 4180 4181 /* 4182 * Locate the node for sender, track state, and then 4183 * pass the (referenced) node up to the 802.11 layer 4184 * for its use. 4185 */ 4186 ni = ieee80211_find_rxnode_withkey(ic, 4187 mtod(m, const struct ieee80211_frame_min *), 4188 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4189 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4190 if (ni != NULL) { 4191 /* 4192 * Sending station is known, dispatch directly. 4193 */ 4194 type = ieee80211_input(ni, m, 4195 rs->rs_rssi, nf, rs->rs_tstamp); 4196 ieee80211_free_node(ni); 4197 /* 4198 * Arrange to update the last rx timestamp only for 4199 * frames from our ap when operating in station mode. 4200 * This assumes the rx key is always setup when 4201 * associated. 4202 */ 4203 if (ic->ic_opmode == IEEE80211_M_STA && 4204 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4205 ngood++; 4206 } else { 4207 type = ieee80211_input_all(ic, m, 4208 rs->rs_rssi, nf, rs->rs_tstamp); 4209 } 4210 /* 4211 * Track rx rssi and do any rx antenna management. 4212 */ 4213 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4214 if (sc->sc_diversity) { 4215 /* 4216 * When using fast diversity, change the default rx 4217 * antenna if diversity chooses the other antenna 3 4218 * times in a row. 4219 */ 4220 if (sc->sc_defant != rs->rs_antenna) { 4221 if (++sc->sc_rxotherant >= 3) 4222 ath_setdefantenna(sc, rs->rs_antenna); 4223 } else 4224 sc->sc_rxotherant = 0; 4225 } 4226 if (sc->sc_softled) { 4227 /* 4228 * Blink for any data frame. Otherwise do a 4229 * heartbeat-style blink when idle. The latter 4230 * is mainly for station mode where we depend on 4231 * periodic beacon frames to trigger the poll event. 4232 */ 4233 if (type == IEEE80211_FC0_TYPE_DATA) { 4234 const HAL_RATE_TABLE *rt = sc->sc_currates; 4235 ath_led_event(sc, 4236 rt->rateCodeToIndex[rs->rs_rate]); 4237 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4238 ath_led_event(sc, 0); 4239 } 4240rx_next: 4241 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4242 } while (ath_rxbuf_init(sc, bf) == 0); 4243 4244 /* rx signal state monitoring */ 4245 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 4246 if (ngood) 4247 sc->sc_lastrx = tsf; 4248 4249 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 4250 !IFQ_IS_EMPTY(&ifp->if_snd)) 4251 ath_start(ifp); 4252 4253#undef PA2DESC 4254} 4255 4256static void 4257ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4258{ 4259 txq->axq_qnum = qnum; 4260 txq->axq_depth = 0; 4261 txq->axq_intrcnt = 0; 4262 txq->axq_link = NULL; 4263 STAILQ_INIT(&txq->axq_q); 4264 ATH_TXQ_LOCK_INIT(sc, txq); 4265 TAILQ_INIT(&txq->axq_stageq); 4266 txq->axq_curage = 0; 4267} 4268 4269/* 4270 * Setup a h/w transmit queue. 4271 */ 4272static struct ath_txq * 4273ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4274{ 4275#define N(a) (sizeof(a)/sizeof(a[0])) 4276 struct ath_hal *ah = sc->sc_ah; 4277 HAL_TXQ_INFO qi; 4278 int qnum; 4279 4280 memset(&qi, 0, sizeof(qi)); 4281 qi.tqi_subtype = subtype; 4282 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4283 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4284 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4285 /* 4286 * Enable interrupts only for EOL and DESC conditions. 4287 * We mark tx descriptors to receive a DESC interrupt 4288 * when a tx queue gets deep; otherwise waiting for the 4289 * EOL to reap descriptors. Note that this is done to 4290 * reduce interrupt load and this only defers reaping 4291 * descriptors, never transmitting frames. Aside from 4292 * reducing interrupts this also permits more concurrency. 4293 * The only potential downside is if the tx queue backs 4294 * up in which case the top half of the kernel may backup 4295 * due to a lack of tx descriptors. 4296 */ 4297 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4298 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4299 if (qnum == -1) { 4300 /* 4301 * NB: don't print a message, this happens 4302 * normally on parts with too few tx queues 4303 */ 4304 return NULL; 4305 } 4306 if (qnum >= N(sc->sc_txq)) { 4307 device_printf(sc->sc_dev, 4308 "hal qnum %u out of range, max %zu!\n", 4309 qnum, N(sc->sc_txq)); 4310 ath_hal_releasetxqueue(ah, qnum); 4311 return NULL; 4312 } 4313 if (!ATH_TXQ_SETUP(sc, qnum)) { 4314 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4315 sc->sc_txqsetup |= 1<<qnum; 4316 } 4317 return &sc->sc_txq[qnum]; 4318#undef N 4319} 4320 4321/* 4322 * Setup a hardware data transmit queue for the specified 4323 * access control. The hal may not support all requested 4324 * queues in which case it will return a reference to a 4325 * previously setup queue. We record the mapping from ac's 4326 * to h/w queues for use by ath_tx_start and also track 4327 * the set of h/w queues being used to optimize work in the 4328 * transmit interrupt handler and related routines. 4329 */ 4330static int 4331ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4332{ 4333#define N(a) (sizeof(a)/sizeof(a[0])) 4334 struct ath_txq *txq; 4335 4336 if (ac >= N(sc->sc_ac2q)) { 4337 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4338 ac, N(sc->sc_ac2q)); 4339 return 0; 4340 } 4341 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4342 if (txq != NULL) { 4343 sc->sc_ac2q[ac] = txq; 4344 return 1; 4345 } else 4346 return 0; 4347#undef N 4348} 4349 4350/* 4351 * Update WME parameters for a transmit queue. 4352 */ 4353static int 4354ath_txq_update(struct ath_softc *sc, int ac) 4355{ 4356#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4357#define ATH_TXOP_TO_US(v) (v<<5) 4358 struct ifnet *ifp = sc->sc_ifp; 4359 struct ieee80211com *ic = ifp->if_l2com; 4360 struct ath_txq *txq = sc->sc_ac2q[ac]; 4361 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4362 struct ath_hal *ah = sc->sc_ah; 4363 HAL_TXQ_INFO qi; 4364 4365 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4366 qi.tqi_aifs = wmep->wmep_aifsn; 4367 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4368 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4369 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4370 4371 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4372 if_printf(ifp, "unable to update hardware queue " 4373 "parameters for %s traffic!\n", 4374 ieee80211_wme_acnames[ac]); 4375 return 0; 4376 } else { 4377 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4378 return 1; 4379 } 4380#undef ATH_TXOP_TO_US 4381#undef ATH_EXPONENT_TO_VALUE 4382} 4383 4384/* 4385 * Callback from the 802.11 layer to update WME parameters. 4386 */ 4387static int 4388ath_wme_update(struct ieee80211com *ic) 4389{ 4390 struct ath_softc *sc = ic->ic_ifp->if_softc; 4391 4392 return !ath_txq_update(sc, WME_AC_BE) || 4393 !ath_txq_update(sc, WME_AC_BK) || 4394 !ath_txq_update(sc, WME_AC_VI) || 4395 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4396} 4397 4398/* 4399 * Reclaim resources for a setup queue. 4400 */ 4401static void 4402ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4403{ 4404 4405 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4406 ATH_TXQ_LOCK_DESTROY(txq); 4407 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4408} 4409 4410/* 4411 * Reclaim all tx queue resources. 4412 */ 4413static void 4414ath_tx_cleanup(struct ath_softc *sc) 4415{ 4416 int i; 4417 4418 ATH_TXBUF_LOCK_DESTROY(sc); 4419 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4420 if (ATH_TXQ_SETUP(sc, i)) 4421 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4422} 4423 4424/* 4425 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 4426 */ 4427static int 4428ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 4429{ 4430 int i; 4431 4432 for (i = 0; i < rt->rateCount; i++) 4433 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 4434 return i; 4435 return 0; /* NB: lowest rate */ 4436} 4437 4438/* 4439 * Reclaim mbuf resources. For fragmented frames we 4440 * need to claim each frag chained with m_nextpkt. 4441 */ 4442static void 4443ath_freetx(struct mbuf *m) 4444{ 4445 struct mbuf *next; 4446 4447 do { 4448 next = m->m_nextpkt; 4449 m->m_nextpkt = NULL; 4450 m_freem(m); 4451 } while ((m = next) != NULL); 4452} 4453 4454static int 4455ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4456{ 4457 struct mbuf *m; 4458 int error; 4459 4460 /* 4461 * Load the DMA map so any coalescing is done. This 4462 * also calculates the number of descriptors we need. 4463 */ 4464 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4465 bf->bf_segs, &bf->bf_nseg, 4466 BUS_DMA_NOWAIT); 4467 if (error == EFBIG) { 4468 /* XXX packet requires too many descriptors */ 4469 bf->bf_nseg = ATH_TXDESC+1; 4470 } else if (error != 0) { 4471 sc->sc_stats.ast_tx_busdma++; 4472 ath_freetx(m0); 4473 return error; 4474 } 4475 /* 4476 * Discard null packets and check for packets that 4477 * require too many TX descriptors. We try to convert 4478 * the latter to a cluster. 4479 */ 4480 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 4481 sc->sc_stats.ast_tx_linear++; 4482 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 4483 if (m == NULL) { 4484 ath_freetx(m0); 4485 sc->sc_stats.ast_tx_nombuf++; 4486 return ENOMEM; 4487 } 4488 m0 = m; 4489 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4490 bf->bf_segs, &bf->bf_nseg, 4491 BUS_DMA_NOWAIT); 4492 if (error != 0) { 4493 sc->sc_stats.ast_tx_busdma++; 4494 ath_freetx(m0); 4495 return error; 4496 } 4497 KASSERT(bf->bf_nseg <= ATH_TXDESC, 4498 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 4499 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 4500 sc->sc_stats.ast_tx_nodata++; 4501 ath_freetx(m0); 4502 return EIO; 4503 } 4504 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4505 __func__, m0, m0->m_pkthdr.len); 4506 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4507 bf->bf_m = m0; 4508 4509 return 0; 4510} 4511 4512static void 4513ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4514{ 4515 struct ath_hal *ah = sc->sc_ah; 4516 struct ath_desc *ds, *ds0; 4517 int i; 4518 4519 /* 4520 * Fillin the remainder of the descriptor info. 4521 */ 4522 ds0 = ds = bf->bf_desc; 4523 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4524 ds->ds_data = bf->bf_segs[i].ds_addr; 4525 if (i == bf->bf_nseg - 1) 4526 ds->ds_link = 0; 4527 else 4528 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4529 ath_hal_filltxdesc(ah, ds 4530 , bf->bf_segs[i].ds_len /* segment length */ 4531 , i == 0 /* first segment */ 4532 , i == bf->bf_nseg - 1 /* last segment */ 4533 , ds0 /* first descriptor */ 4534 ); 4535 DPRINTF(sc, ATH_DEBUG_XMIT, 4536 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4537 __func__, i, ds->ds_link, ds->ds_data, 4538 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4539 } 4540 /* 4541 * Insert the frame on the outbound list and pass it on 4542 * to the hardware. Multicast frames buffered for power 4543 * save stations and transmit from the CAB queue are stored 4544 * on a s/w only queue and loaded on to the CAB queue in 4545 * the SWBA handler since frames only go out on DTIM and 4546 * to avoid possible races. 4547 */ 4548 ATH_TXQ_LOCK(txq); 4549 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4550 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4551 if (txq->axq_link == NULL) { 4552 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4553 DPRINTF(sc, ATH_DEBUG_XMIT, 4554 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 4555 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 4556 txq->axq_depth); 4557 } else { 4558 *txq->axq_link = bf->bf_daddr; 4559 DPRINTF(sc, ATH_DEBUG_XMIT, 4560 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4561 txq->axq_qnum, txq->axq_link, 4562 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4563 } 4564 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4565 ath_hal_txstart(ah, txq->axq_qnum); 4566 } else { 4567 if (txq->axq_link != NULL) { 4568 struct ath_buf *last = ATH_TXQ_LAST(txq); 4569 struct ieee80211_frame *wh; 4570 4571 /* mark previous frame */ 4572 wh = mtod(last->bf_m, struct ieee80211_frame *); 4573 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4574 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4575 BUS_DMASYNC_PREWRITE); 4576 4577 /* link descriptor */ 4578 *txq->axq_link = bf->bf_daddr; 4579 } 4580 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4581 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4582 } 4583 ATH_TXQ_UNLOCK(txq); 4584} 4585 4586static int 4587ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4588 struct mbuf *m0) 4589{ 4590 struct ieee80211vap *vap = ni->ni_vap; 4591 struct ath_vap *avp = ATH_VAP(vap); 4592 struct ath_hal *ah = sc->sc_ah; 4593 struct ifnet *ifp = sc->sc_ifp; 4594 struct ieee80211com *ic = ifp->if_l2com; 4595 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4596 int error, iswep, ismcast, isfrag, ismrr; 4597 int keyix, hdrlen, pktlen, try0; 4598 u_int8_t rix, txrate, ctsrate; 4599 u_int8_t cix = 0xff; /* NB: silence compiler */ 4600 struct ath_desc *ds; 4601 struct ath_txq *txq; 4602 struct ieee80211_frame *wh; 4603 u_int subtype, flags, ctsduration; 4604 HAL_PKT_TYPE atype; 4605 const HAL_RATE_TABLE *rt; 4606 HAL_BOOL shortPreamble; 4607 struct ath_node *an; 4608 u_int pri; 4609 4610 wh = mtod(m0, struct ieee80211_frame *); 4611 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4612 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4613 isfrag = m0->m_flags & M_FRAG; 4614 hdrlen = ieee80211_anyhdrsize(wh); 4615 /* 4616 * Packet length must not include any 4617 * pad bytes; deduct them here. 4618 */ 4619 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4620 4621 if (iswep) { 4622 const struct ieee80211_cipher *cip; 4623 struct ieee80211_key *k; 4624 4625 /* 4626 * Construct the 802.11 header+trailer for an encrypted 4627 * frame. The only reason this can fail is because of an 4628 * unknown or unsupported cipher/key type. 4629 */ 4630 k = ieee80211_crypto_encap(ni, m0); 4631 if (k == NULL) { 4632 /* 4633 * This can happen when the key is yanked after the 4634 * frame was queued. Just discard the frame; the 4635 * 802.11 layer counts failures and provides 4636 * debugging/diagnostics. 4637 */ 4638 ath_freetx(m0); 4639 return EIO; 4640 } 4641 /* 4642 * Adjust the packet + header lengths for the crypto 4643 * additions and calculate the h/w key index. When 4644 * a s/w mic is done the frame will have had any mic 4645 * added to it prior to entry so m0->m_pkthdr.len will 4646 * account for it. Otherwise we need to add it to the 4647 * packet length. 4648 */ 4649 cip = k->wk_cipher; 4650 hdrlen += cip->ic_header; 4651 pktlen += cip->ic_header + cip->ic_trailer; 4652 /* NB: frags always have any TKIP MIC done in s/w */ 4653 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4654 pktlen += cip->ic_miclen; 4655 keyix = k->wk_keyix; 4656 4657 /* packet header may have moved, reset our local pointer */ 4658 wh = mtod(m0, struct ieee80211_frame *); 4659 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4660 /* 4661 * Use station key cache slot, if assigned. 4662 */ 4663 keyix = ni->ni_ucastkey.wk_keyix; 4664 if (keyix == IEEE80211_KEYIX_NONE) 4665 keyix = HAL_TXKEYIX_INVALID; 4666 } else 4667 keyix = HAL_TXKEYIX_INVALID; 4668 4669 pktlen += IEEE80211_CRC_LEN; 4670 4671 /* 4672 * Load the DMA map so any coalescing is done. This 4673 * also calculates the number of descriptors we need. 4674 */ 4675 error = ath_tx_dmasetup(sc, bf, m0); 4676 if (error != 0) 4677 return error; 4678 bf->bf_node = ni; /* NB: held reference */ 4679 m0 = bf->bf_m; /* NB: may have changed */ 4680 wh = mtod(m0, struct ieee80211_frame *); 4681 4682 /* setup descriptors */ 4683 ds = bf->bf_desc; 4684 rt = sc->sc_currates; 4685 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4686 4687 /* 4688 * NB: the 802.11 layer marks whether or not we should 4689 * use short preamble based on the current mode and 4690 * negotiated parameters. 4691 */ 4692 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4693 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4694 shortPreamble = AH_TRUE; 4695 sc->sc_stats.ast_tx_shortpre++; 4696 } else { 4697 shortPreamble = AH_FALSE; 4698 } 4699 4700 an = ATH_NODE(ni); 4701 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4702 ismrr = 0; /* default no multi-rate retry*/ 4703 pri = M_WME_GETAC(m0); /* honor classification */ 4704 /* XXX use txparams instead of fixed values */ 4705 /* 4706 * Calculate Atheros packet type from IEEE80211 packet header, 4707 * setup for rate calculations, and select h/w transmit queue. 4708 */ 4709 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4710 case IEEE80211_FC0_TYPE_MGT: 4711 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4712 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4713 atype = HAL_PKT_TYPE_BEACON; 4714 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4715 atype = HAL_PKT_TYPE_PROBE_RESP; 4716 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4717 atype = HAL_PKT_TYPE_ATIM; 4718 else 4719 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4720 rix = an->an_mgmtrix; 4721 txrate = rt->info[rix].rateCode; 4722 if (shortPreamble) 4723 txrate |= rt->info[rix].shortPreamble; 4724 try0 = ATH_TXMGTTRY; 4725 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4726 break; 4727 case IEEE80211_FC0_TYPE_CTL: 4728 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4729 rix = an->an_mgmtrix; 4730 txrate = rt->info[rix].rateCode; 4731 if (shortPreamble) 4732 txrate |= rt->info[rix].shortPreamble; 4733 try0 = ATH_TXMGTTRY; 4734 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4735 break; 4736 case IEEE80211_FC0_TYPE_DATA: 4737 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4738 /* 4739 * Data frames: multicast frames go out at a fixed rate, 4740 * EAPOL frames use the mgmt frame rate; otherwise consult 4741 * the rate control module for the rate to use. 4742 */ 4743 if (ismcast) { 4744 rix = an->an_mcastrix; 4745 txrate = rt->info[rix].rateCode; 4746 if (shortPreamble) 4747 txrate |= rt->info[rix].shortPreamble; 4748 try0 = 1; 4749 } else if (m0->m_flags & M_EAPOL) { 4750 /* XXX? maybe always use long preamble? */ 4751 rix = an->an_mgmtrix; 4752 txrate = rt->info[rix].rateCode; 4753 if (shortPreamble) 4754 txrate |= rt->info[rix].shortPreamble; 4755 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4756 } else { 4757 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4758 &rix, &try0, &txrate); 4759 sc->sc_txrix = rix; /* for LED blinking */ 4760 sc->sc_lastdatarix = rix; /* for fast frames */ 4761 if (try0 != ATH_TXMAXTRY) 4762 ismrr = 1; 4763 } 4764 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4765 flags |= HAL_TXDESC_NOACK; 4766 break; 4767 default: 4768 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4769 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4770 /* XXX statistic */ 4771 ath_freetx(m0); 4772 return EIO; 4773 } 4774 txq = sc->sc_ac2q[pri]; 4775 4776 /* 4777 * When servicing one or more stations in power-save mode 4778 * (or) if there is some mcast data waiting on the mcast 4779 * queue (to prevent out of order delivery) multicast 4780 * frames must be buffered until after the beacon. 4781 */ 4782 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4783 txq = &avp->av_mcastq; 4784 4785 /* 4786 * Calculate miscellaneous flags. 4787 */ 4788 if (ismcast) { 4789 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4790 } else if (pktlen > vap->iv_rtsthreshold && 4791 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4792 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4793 cix = rt->info[rix].controlRate; 4794 sc->sc_stats.ast_tx_rts++; 4795 } 4796 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4797 sc->sc_stats.ast_tx_noack++; 4798 4799 /* 4800 * If 802.11g protection is enabled, determine whether 4801 * to use RTS/CTS or just CTS. Note that this is only 4802 * done for OFDM unicast frames. 4803 */ 4804 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4805 rt->info[rix].phy == IEEE80211_T_OFDM && 4806 (flags & HAL_TXDESC_NOACK) == 0) { 4807 /* XXX fragments must use CCK rates w/ protection */ 4808 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4809 flags |= HAL_TXDESC_RTSENA; 4810 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4811 flags |= HAL_TXDESC_CTSENA; 4812 if (isfrag) { 4813 /* 4814 * For frags it would be desirable to use the 4815 * highest CCK rate for RTS/CTS. But stations 4816 * farther away may detect it at a lower CCK rate 4817 * so use the configured protection rate instead 4818 * (for now). 4819 */ 4820 cix = rt->info[sc->sc_protrix].controlRate; 4821 } else 4822 cix = rt->info[sc->sc_protrix].controlRate; 4823 sc->sc_stats.ast_tx_protect++; 4824 } 4825 4826 /* 4827 * Calculate duration. This logically belongs in the 802.11 4828 * layer but it lacks sufficient information to calculate it. 4829 */ 4830 if ((flags & HAL_TXDESC_NOACK) == 0 && 4831 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4832 u_int16_t dur; 4833 if (shortPreamble) 4834 dur = rt->info[rix].spAckDuration; 4835 else 4836 dur = rt->info[rix].lpAckDuration; 4837 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4838 dur += dur; /* additional SIFS+ACK */ 4839 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4840 /* 4841 * Include the size of next fragment so NAV is 4842 * updated properly. The last fragment uses only 4843 * the ACK duration 4844 */ 4845 dur += ath_hal_computetxtime(ah, rt, 4846 m0->m_nextpkt->m_pkthdr.len, 4847 rix, shortPreamble); 4848 } 4849 if (isfrag) { 4850 /* 4851 * Force hardware to use computed duration for next 4852 * fragment by disabling multi-rate retry which updates 4853 * duration based on the multi-rate duration table. 4854 */ 4855 ismrr = 0; 4856 try0 = ATH_TXMGTTRY; /* XXX? */ 4857 } 4858 *(u_int16_t *)wh->i_dur = htole16(dur); 4859 } 4860 4861 /* 4862 * Calculate RTS/CTS rate and duration if needed. 4863 */ 4864 ctsduration = 0; 4865 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4866 /* 4867 * CTS transmit rate is derived from the transmit rate 4868 * by looking in the h/w rate table. We must also factor 4869 * in whether or not a short preamble is to be used. 4870 */ 4871 /* NB: cix is set above where RTS/CTS is enabled */ 4872 KASSERT(cix != 0xff, ("cix not setup")); 4873 ctsrate = rt->info[cix].rateCode; 4874 /* 4875 * Compute the transmit duration based on the frame 4876 * size and the size of an ACK frame. We call into the 4877 * HAL to do the computation since it depends on the 4878 * characteristics of the actual PHY being used. 4879 * 4880 * NB: CTS is assumed the same size as an ACK so we can 4881 * use the precalculated ACK durations. 4882 */ 4883 if (shortPreamble) { 4884 ctsrate |= rt->info[cix].shortPreamble; 4885 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4886 ctsduration += rt->info[cix].spAckDuration; 4887 ctsduration += ath_hal_computetxtime(ah, 4888 rt, pktlen, rix, AH_TRUE); 4889 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4890 ctsduration += rt->info[rix].spAckDuration; 4891 } else { 4892 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4893 ctsduration += rt->info[cix].lpAckDuration; 4894 ctsduration += ath_hal_computetxtime(ah, 4895 rt, pktlen, rix, AH_FALSE); 4896 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4897 ctsduration += rt->info[rix].lpAckDuration; 4898 } 4899 /* 4900 * Must disable multi-rate retry when using RTS/CTS. 4901 */ 4902 ismrr = 0; 4903 try0 = ATH_TXMGTTRY; /* XXX */ 4904 } else 4905 ctsrate = 0; 4906 4907 /* 4908 * At this point we are committed to sending the frame 4909 * and we don't need to look at m_nextpkt; clear it in 4910 * case this frame is part of frag chain. 4911 */ 4912 m0->m_nextpkt = NULL; 4913 4914 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4915 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 4916 sc->sc_hwmap[rix].ieeerate, -1); 4917 4918 if (bpf_peers_present(ifp->if_bpf)) { 4919 u_int64_t tsf = ath_hal_gettsf64(ah); 4920 4921 sc->sc_tx_th.wt_tsf = htole64(tsf); 4922 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 4923 if (iswep) 4924 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4925 if (isfrag) 4926 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4927 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 4928 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4929 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4930 4931 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 4932 } 4933 4934 /* 4935 * Determine if a tx interrupt should be generated for 4936 * this descriptor. We take a tx interrupt to reap 4937 * descriptors when the h/w hits an EOL condition or 4938 * when the descriptor is specifically marked to generate 4939 * an interrupt. We periodically mark descriptors in this 4940 * way to insure timely replenishing of the supply needed 4941 * for sending frames. Defering interrupts reduces system 4942 * load and potentially allows more concurrent work to be 4943 * done but if done to aggressively can cause senders to 4944 * backup. 4945 * 4946 * NB: use >= to deal with sc_txintrperiod changing 4947 * dynamically through sysctl. 4948 */ 4949 if (flags & HAL_TXDESC_INTREQ) { 4950 txq->axq_intrcnt = 0; 4951 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4952 flags |= HAL_TXDESC_INTREQ; 4953 txq->axq_intrcnt = 0; 4954 } 4955 4956 /* 4957 * Formulate first tx descriptor with tx controls. 4958 */ 4959 /* XXX check return value? */ 4960 ath_hal_setuptxdesc(ah, ds 4961 , pktlen /* packet length */ 4962 , hdrlen /* header length */ 4963 , atype /* Atheros packet type */ 4964 , ni->ni_txpower /* txpower */ 4965 , txrate, try0 /* series 0 rate/tries */ 4966 , keyix /* key cache index */ 4967 , sc->sc_txantenna /* antenna mode */ 4968 , flags /* flags */ 4969 , ctsrate /* rts/cts rate */ 4970 , ctsduration /* rts/cts duration */ 4971 ); 4972 bf->bf_txflags = flags; 4973 /* 4974 * Setup the multi-rate retry state only when we're 4975 * going to use it. This assumes ath_hal_setuptxdesc 4976 * initializes the descriptors (so we don't have to) 4977 * when the hardware supports multi-rate retry and 4978 * we don't use it. 4979 */ 4980 if (ismrr) 4981 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4982 4983 ath_tx_handoff(sc, txq, bf); 4984 return 0; 4985} 4986 4987/* 4988 * Process completed xmit descriptors from the specified queue. 4989 */ 4990static int 4991ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4992{ 4993 struct ath_hal *ah = sc->sc_ah; 4994 struct ifnet *ifp = sc->sc_ifp; 4995 struct ieee80211com *ic = ifp->if_l2com; 4996 struct ath_buf *bf; 4997 struct ath_desc *ds, *ds0; 4998 struct ath_tx_status *ts; 4999 struct ieee80211_node *ni; 5000 struct ath_node *an; 5001 int sr, lr, pri, nacked; 5002 HAL_STATUS status; 5003 5004 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 5005 __func__, txq->axq_qnum, 5006 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 5007 txq->axq_link); 5008 nacked = 0; 5009 for (;;) { 5010 ATH_TXQ_LOCK(txq); 5011 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 5012 bf = STAILQ_FIRST(&txq->axq_q); 5013 if (bf == NULL) { 5014 ATH_TXQ_UNLOCK(txq); 5015 break; 5016 } 5017 ds0 = &bf->bf_desc[0]; 5018 ds = &bf->bf_desc[bf->bf_nseg - 1]; 5019 ts = &bf->bf_status.ds_txstat; 5020 status = ath_hal_txprocdesc(ah, ds, ts); 5021#ifdef ATH_DEBUG 5022 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 5023 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 5024 status == HAL_OK); 5025#endif 5026 if (status == HAL_EINPROGRESS) { 5027 ATH_TXQ_UNLOCK(txq); 5028 break; 5029 } 5030 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5031 if (txq->axq_depth == 0) 5032 txq->axq_link = NULL; 5033 ATH_TXQ_UNLOCK(txq); 5034 5035 ni = bf->bf_node; 5036 if (ni != NULL) { 5037 an = ATH_NODE(ni); 5038 if (ts->ts_status == 0) { 5039 u_int8_t txant = ts->ts_antenna; 5040 sc->sc_stats.ast_ant_tx[txant]++; 5041 sc->sc_ant_tx[txant]++; 5042 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 5043 sc->sc_stats.ast_tx_altrate++; 5044 pri = M_WME_GETAC(bf->bf_m); 5045 if (pri >= WME_AC_VO) 5046 ic->ic_wme.wme_hipri_traffic++; 5047 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 5048 ni->ni_inact = ni->ni_inact_reload; 5049 } else { 5050 if (ts->ts_status & HAL_TXERR_XRETRY) 5051 sc->sc_stats.ast_tx_xretries++; 5052 if (ts->ts_status & HAL_TXERR_FIFO) 5053 sc->sc_stats.ast_tx_fifoerr++; 5054 if (ts->ts_status & HAL_TXERR_FILT) 5055 sc->sc_stats.ast_tx_filtered++; 5056 if (bf->bf_m->m_flags & M_FF) 5057 sc->sc_stats.ast_ff_txerr++; 5058 } 5059 sr = ts->ts_shortretry; 5060 lr = ts->ts_longretry; 5061 sc->sc_stats.ast_tx_shortretry += sr; 5062 sc->sc_stats.ast_tx_longretry += lr; 5063 /* 5064 * Hand the descriptor to the rate control algorithm. 5065 */ 5066 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 5067 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 5068 /* 5069 * If frame was ack'd update statistics, 5070 * including the last rx time used to 5071 * workaround phantom bmiss interrupts. 5072 */ 5073 if (ts->ts_status == 0) { 5074 nacked++; 5075 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 5076 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 5077 ts->ts_rssi); 5078 } 5079 ath_rate_tx_complete(sc, an, bf); 5080 } 5081 /* 5082 * Do any tx complete callback. Note this must 5083 * be done before releasing the node reference. 5084 */ 5085 if (bf->bf_m->m_flags & M_TXCB) 5086 ieee80211_process_callback(ni, bf->bf_m, 5087 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 5088 ts->ts_status : HAL_TXERR_XRETRY); 5089 /* 5090 * Reclaim reference to node. 5091 * 5092 * NB: the node may be reclaimed here if, for example 5093 * this is a DEAUTH message that was sent and the 5094 * node was timed out due to inactivity. 5095 */ 5096 ieee80211_free_node(ni); 5097 } 5098 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5099 BUS_DMASYNC_POSTWRITE); 5100 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5101 5102 m_freem(bf->bf_m); 5103 bf->bf_m = NULL; 5104 bf->bf_node = NULL; 5105 5106 ATH_TXBUF_LOCK(sc); 5107 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5108 ATH_TXBUF_UNLOCK(sc); 5109 } 5110 /* 5111 * Flush fast-frame staging queue when traffic slows. 5112 */ 5113 if (txq->axq_depth <= 1) 5114 ath_ff_stageq_flush(sc, txq, ath_ff_always); 5115 return nacked; 5116} 5117 5118static __inline int 5119txqactive(struct ath_hal *ah, int qnum) 5120{ 5121 u_int32_t txqs = 1<<qnum; 5122 ath_hal_gettxintrtxqs(ah, &txqs); 5123 return (txqs & (1<<qnum)); 5124} 5125 5126/* 5127 * Deferred processing of transmit interrupt; special-cased 5128 * for a single hardware transmit queue (e.g. 5210 and 5211). 5129 */ 5130static void 5131ath_tx_proc_q0(void *arg, int npending) 5132{ 5133 struct ath_softc *sc = arg; 5134 struct ifnet *ifp = sc->sc_ifp; 5135 5136 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5137 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5138 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5139 ath_tx_processq(sc, sc->sc_cabq); 5140 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5141 ifp->if_timer = 0; 5142 5143 if (sc->sc_softled) 5144 ath_led_event(sc, sc->sc_txrix); 5145 5146 ath_start(ifp); 5147} 5148 5149/* 5150 * Deferred processing of transmit interrupt; special-cased 5151 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5152 */ 5153static void 5154ath_tx_proc_q0123(void *arg, int npending) 5155{ 5156 struct ath_softc *sc = arg; 5157 struct ifnet *ifp = sc->sc_ifp; 5158 int nacked; 5159 5160 /* 5161 * Process each active queue. 5162 */ 5163 nacked = 0; 5164 if (txqactive(sc->sc_ah, 0)) 5165 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5166 if (txqactive(sc->sc_ah, 1)) 5167 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5168 if (txqactive(sc->sc_ah, 2)) 5169 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5170 if (txqactive(sc->sc_ah, 3)) 5171 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5172 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5173 ath_tx_processq(sc, sc->sc_cabq); 5174 if (nacked) 5175 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5176 5177 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5178 ifp->if_timer = 0; 5179 5180 if (sc->sc_softled) 5181 ath_led_event(sc, sc->sc_txrix); 5182 5183 ath_start(ifp); 5184} 5185 5186/* 5187 * Deferred processing of transmit interrupt. 5188 */ 5189static void 5190ath_tx_proc(void *arg, int npending) 5191{ 5192 struct ath_softc *sc = arg; 5193 struct ifnet *ifp = sc->sc_ifp; 5194 int i, nacked; 5195 5196 /* 5197 * Process each active queue. 5198 */ 5199 nacked = 0; 5200 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5201 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5202 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5203 if (nacked) 5204 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5205 5206 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5207 ifp->if_timer = 0; 5208 5209 if (sc->sc_softled) 5210 ath_led_event(sc, sc->sc_txrix); 5211 5212 ath_start(ifp); 5213} 5214 5215static void 5216ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5217{ 5218#ifdef ATH_DEBUG 5219 struct ath_hal *ah = sc->sc_ah; 5220#endif 5221 struct ieee80211_node *ni; 5222 struct ath_buf *bf; 5223 u_int ix; 5224 5225 /* 5226 * NB: this assumes output has been stopped and 5227 * we do not need to block ath_tx_proc 5228 */ 5229 for (ix = 0;; ix++) { 5230 ATH_TXQ_LOCK(txq); 5231 bf = STAILQ_FIRST(&txq->axq_q); 5232 if (bf == NULL) { 5233 txq->axq_link = NULL; 5234 ATH_TXQ_UNLOCK(txq); 5235 break; 5236 } 5237 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5238 ATH_TXQ_UNLOCK(txq); 5239#ifdef ATH_DEBUG 5240 if (sc->sc_debug & ATH_DEBUG_RESET) { 5241 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5242 5243 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5244 ath_hal_txprocdesc(ah, bf->bf_desc, 5245 &bf->bf_status.ds_txstat) == HAL_OK); 5246 ieee80211_dump_pkt(ic, mtod(bf->bf_m, caddr_t), 5247 bf->bf_m->m_len, 0, -1); 5248 } 5249#endif /* ATH_DEBUG */ 5250 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5251 ni = bf->bf_node; 5252 bf->bf_node = NULL; 5253 if (ni != NULL) { 5254 /* 5255 * Do any callback and reclaim the node reference. 5256 */ 5257 if (bf->bf_m->m_flags & M_TXCB) 5258 ieee80211_process_callback(ni, bf->bf_m, -1); 5259 ieee80211_free_node(ni); 5260 } 5261 m_freem(bf->bf_m); 5262 bf->bf_m = NULL; 5263 5264 ATH_TXBUF_LOCK(sc); 5265 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5266 ATH_TXBUF_UNLOCK(sc); 5267 } 5268} 5269 5270static void 5271ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5272{ 5273 struct ath_hal *ah = sc->sc_ah; 5274 5275 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5276 __func__, txq->axq_qnum, 5277 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5278 txq->axq_link); 5279 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5280} 5281 5282/* 5283 * Drain the transmit queues and reclaim resources. 5284 */ 5285static void 5286ath_draintxq(struct ath_softc *sc) 5287{ 5288 struct ath_hal *ah = sc->sc_ah; 5289 struct ifnet *ifp = sc->sc_ifp; 5290 int i; 5291 5292 /* XXX return value */ 5293 if (!sc->sc_invalid) { 5294 /* don't touch the hardware if marked invalid */ 5295 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5296 __func__, sc->sc_bhalq, 5297 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5298 NULL); 5299 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5300 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5301 if (ATH_TXQ_SETUP(sc, i)) 5302 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5303 } 5304 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5305 if (ATH_TXQ_SETUP(sc, i)) 5306 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5307#ifdef ATH_DEBUG 5308 if (sc->sc_debug & ATH_DEBUG_RESET) { 5309 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5310 if (bf != NULL && bf->bf_m != NULL) { 5311 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5312 ath_hal_txprocdesc(ah, bf->bf_desc, 5313 &bf->bf_status.ds_txstat) == HAL_OK); 5314 ieee80211_dump_pkt(ifp->if_l2com, mtod(bf->bf_m, caddr_t), 5315 bf->bf_m->m_len, 0, -1); 5316 } 5317 } 5318#endif /* ATH_DEBUG */ 5319 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5320 ifp->if_timer = 0; 5321} 5322 5323/* 5324 * Disable the receive h/w in preparation for a reset. 5325 */ 5326static void 5327ath_stoprecv(struct ath_softc *sc) 5328{ 5329#define PA2DESC(_sc, _pa) \ 5330 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5331 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5332 struct ath_hal *ah = sc->sc_ah; 5333 5334 ath_hal_stoppcurecv(ah); /* disable PCU */ 5335 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5336 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5337 DELAY(3000); /* 3ms is long enough for 1 frame */ 5338#ifdef ATH_DEBUG 5339 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5340 struct ath_buf *bf; 5341 u_int ix; 5342 5343 printf("%s: rx queue %p, link %p\n", __func__, 5344 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5345 ix = 0; 5346 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5347 struct ath_desc *ds = bf->bf_desc; 5348 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5349 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5350 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5351 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5352 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5353 ix++; 5354 } 5355 } 5356#endif 5357 if (sc->sc_rxpending != NULL) { 5358 m_freem(sc->sc_rxpending); 5359 sc->sc_rxpending = NULL; 5360 } 5361 sc->sc_rxlink = NULL; /* just in case */ 5362#undef PA2DESC 5363} 5364 5365/* 5366 * Enable the receive h/w following a reset. 5367 */ 5368static int 5369ath_startrecv(struct ath_softc *sc) 5370{ 5371 struct ath_hal *ah = sc->sc_ah; 5372 struct ath_buf *bf; 5373 5374 sc->sc_rxlink = NULL; 5375 sc->sc_rxpending = NULL; 5376 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5377 int error = ath_rxbuf_init(sc, bf); 5378 if (error != 0) { 5379 DPRINTF(sc, ATH_DEBUG_RECV, 5380 "%s: ath_rxbuf_init failed %d\n", 5381 __func__, error); 5382 return error; 5383 } 5384 } 5385 5386 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5387 ath_hal_putrxbuf(ah, bf->bf_daddr); 5388 ath_hal_rxena(ah); /* enable recv descriptors */ 5389 ath_mode_init(sc); /* set filters, etc. */ 5390 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5391 return 0; 5392} 5393 5394/* 5395 * Update internal state after a channel change. 5396 */ 5397static void 5398ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5399{ 5400 enum ieee80211_phymode mode; 5401 5402 /* 5403 * Change channels and update the h/w rate map 5404 * if we're switching; e.g. 11a to 11b/g. 5405 */ 5406 if (IEEE80211_IS_CHAN_HALF(chan)) 5407 mode = IEEE80211_MODE_HALF; 5408 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 5409 mode = IEEE80211_MODE_QUARTER; 5410 else 5411 mode = ieee80211_chan2mode(chan); 5412 if (mode != sc->sc_curmode) 5413 ath_setcurmode(sc, mode); 5414 5415 sc->sc_rx_th.wr_chan_flags = htole32(chan->ic_flags); 5416 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags; 5417 sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 5418 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq; 5419 sc->sc_rx_th.wr_chan_ieee = chan->ic_ieee; 5420 sc->sc_tx_th.wt_chan_ieee = sc->sc_rx_th.wr_chan_ieee; 5421 sc->sc_rx_th.wr_chan_maxpow = chan->ic_maxregpower; 5422 sc->sc_tx_th.wt_chan_maxpow = sc->sc_rx_th.wr_chan_maxpow; 5423} 5424 5425/* 5426 * Set/change channels. If the channel is really being changed, 5427 * it's done by reseting the chip. To accomplish this we must 5428 * first cleanup any pending DMA, then restart stuff after a la 5429 * ath_init. 5430 */ 5431static int 5432ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5433{ 5434 struct ifnet *ifp = sc->sc_ifp; 5435 struct ieee80211com *ic = ifp->if_l2com; 5436 struct ath_hal *ah = sc->sc_ah; 5437 HAL_CHANNEL hchan; 5438 5439 /* 5440 * Convert to a HAL channel description with 5441 * the flags constrained to reflect the current 5442 * operating mode. 5443 */ 5444 ath_mapchan(ic, &hchan, chan); 5445 5446 DPRINTF(sc, ATH_DEBUG_RESET, 5447 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 5448 __func__, 5449 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 5450 sc->sc_curchan.channelFlags), 5451 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 5452 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 5453 hchan.channel, hchan.channelFlags); 5454 if (hchan.channel != sc->sc_curchan.channel || 5455 hchan.channelFlags != sc->sc_curchan.channelFlags) { 5456 HAL_STATUS status; 5457 5458 /* 5459 * To switch channels clear any pending DMA operations; 5460 * wait long enough for the RX fifo to drain, reset the 5461 * hardware at the new frequency, and then re-enable 5462 * the relevant bits of the h/w. 5463 */ 5464 ath_hal_intrset(ah, 0); /* disable interrupts */ 5465 ath_draintxq(sc); /* clear pending tx frames */ 5466 ath_stoprecv(sc); /* turn off frame recv */ 5467 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) { 5468 if_printf(ifp, "%s: unable to reset " 5469 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x), " 5470 "hal status %u\n", __func__, 5471 ieee80211_chan2ieee(ic, chan), chan->ic_freq, 5472 chan->ic_flags, hchan.channelFlags, status); 5473 return EIO; 5474 } 5475 sc->sc_curchan = hchan; 5476 sc->sc_diversity = ath_hal_getdiversity(ah); 5477 sc->sc_calinterval = 1; 5478 sc->sc_caltries = 0; 5479 5480 /* 5481 * Re-enable rx framework. 5482 */ 5483 if (ath_startrecv(sc) != 0) { 5484 if_printf(ifp, "%s: unable to restart recv logic\n", 5485 __func__); 5486 return EIO; 5487 } 5488 5489 /* 5490 * Change channels and update the h/w rate map 5491 * if we're switching; e.g. 11a to 11b/g. 5492 */ 5493 ath_chan_change(sc, chan); 5494 5495 /* 5496 * Re-enable interrupts. 5497 */ 5498 ath_hal_intrset(ah, sc->sc_imask); 5499 } 5500 return 0; 5501} 5502 5503/* 5504 * Periodically recalibrate the PHY to account 5505 * for temperature/environment changes. 5506 */ 5507static void 5508ath_calibrate(void *arg) 5509{ 5510 struct ath_softc *sc = arg; 5511 struct ath_hal *ah = sc->sc_ah; 5512 HAL_BOOL iqCalDone; 5513 5514 sc->sc_stats.ast_per_cal++; 5515 5516 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5517 /* 5518 * Rfgain is out of bounds, reset the chip 5519 * to load new gain values. 5520 */ 5521 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5522 "%s: rfgain change\n", __func__); 5523 sc->sc_stats.ast_per_rfgain++; 5524 ath_reset(sc->sc_ifp); 5525 } 5526 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 5527 DPRINTF(sc, ATH_DEBUG_ANY, 5528 "%s: calibration of channel %u failed\n", 5529 __func__, sc->sc_curchan.channel); 5530 sc->sc_stats.ast_per_calfail++; 5531 } 5532 /* 5533 * Calibrate noise floor data again in case of change. 5534 */ 5535 ath_hal_process_noisefloor(ah); 5536 /* 5537 * Poll more frequently when the IQ calibration is in 5538 * progress to speedup loading the final settings. 5539 * We temper this aggressive polling with an exponential 5540 * back off after 4 tries up to ath_calinterval. 5541 */ 5542 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 5543 sc->sc_caltries = 0; 5544 sc->sc_calinterval = ath_calinterval; 5545 } else if (sc->sc_caltries > 4) { 5546 sc->sc_caltries = 0; 5547 sc->sc_calinterval <<= 1; 5548 if (sc->sc_calinterval > ath_calinterval) 5549 sc->sc_calinterval = ath_calinterval; 5550 } 5551 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 5552 ("bad calibration interval %u", sc->sc_calinterval)); 5553 5554 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5555 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 5556 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 5557 sc->sc_caltries++; 5558 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5559 ath_calibrate, sc); 5560} 5561 5562static void 5563ath_scan_start(struct ieee80211com *ic) 5564{ 5565 struct ifnet *ifp = ic->ic_ifp; 5566 struct ath_softc *sc = ifp->if_softc; 5567 struct ath_hal *ah = sc->sc_ah; 5568 u_int32_t rfilt; 5569 5570 /* XXX calibration timer? */ 5571 5572 sc->sc_scanning = 1; 5573 sc->sc_syncbeacon = 0; 5574 rfilt = ath_calcrxfilter(sc); 5575 ath_hal_setrxfilter(ah, rfilt); 5576 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5577 5578 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5579 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5580} 5581 5582static void 5583ath_scan_end(struct ieee80211com *ic) 5584{ 5585 struct ifnet *ifp = ic->ic_ifp; 5586 struct ath_softc *sc = ifp->if_softc; 5587 struct ath_hal *ah = sc->sc_ah; 5588 u_int32_t rfilt; 5589 5590 sc->sc_scanning = 0; 5591 rfilt = ath_calcrxfilter(sc); 5592 ath_hal_setrxfilter(ah, rfilt); 5593 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5594 5595 ath_hal_process_noisefloor(ah); 5596 5597 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5598 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5599 sc->sc_curaid); 5600} 5601 5602static void 5603ath_set_channel(struct ieee80211com *ic) 5604{ 5605 struct ifnet *ifp = ic->ic_ifp; 5606 struct ath_softc *sc = ifp->if_softc; 5607 5608 (void) ath_chan_set(sc, ic->ic_curchan); 5609 /* 5610 * If we are returning to our bss channel then mark state 5611 * so the next recv'd beacon's tsf will be used to sync the 5612 * beacon timers. Note that since we only hear beacons in 5613 * sta/ibss mode this has no effect in other operating modes. 5614 */ 5615 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5616 sc->sc_syncbeacon = 1; 5617} 5618 5619/* 5620 * Walk the vap list and check if there any vap's in RUN state. 5621 */ 5622static int 5623ath_isanyrunningvaps(struct ieee80211vap *this) 5624{ 5625 struct ieee80211com *ic = this->iv_ic; 5626 struct ieee80211vap *vap; 5627 5628 IEEE80211_LOCK_ASSERT(ic); 5629 5630 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5631 if (vap != this && vap->iv_state == IEEE80211_S_RUN) 5632 return 1; 5633 } 5634 return 0; 5635} 5636 5637static int 5638ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5639{ 5640 struct ieee80211com *ic = vap->iv_ic; 5641 struct ath_softc *sc = ic->ic_ifp->if_softc; 5642 struct ath_vap *avp = ATH_VAP(vap); 5643 struct ath_hal *ah = sc->sc_ah; 5644 struct ieee80211_node *ni = NULL; 5645 int i, error, stamode; 5646 u_int32_t rfilt; 5647 static const HAL_LED_STATE leds[] = { 5648 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5649 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5650 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5651 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5652 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5653 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5654 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5655 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5656 }; 5657 5658 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5659 ieee80211_state_name[vap->iv_state], 5660 ieee80211_state_name[nstate]); 5661 5662 callout_stop(&sc->sc_cal_ch); 5663 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5664 5665 if (nstate == IEEE80211_S_SCAN) { 5666 /* 5667 * Scanning: turn off beacon miss and don't beacon. 5668 * Mark beacon state so when we reach RUN state we'll 5669 * [re]setup beacons. Unblock the task q thread so 5670 * deferred interrupt processing is done. 5671 */ 5672 ath_hal_intrset(ah, 5673 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5674 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5675 sc->sc_beacons = 0; 5676 taskqueue_unblock(sc->sc_tq); 5677 } 5678 5679 ni = vap->iv_bss; 5680 rfilt = ath_calcrxfilter(sc); 5681 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5682 vap->iv_opmode == IEEE80211_M_AHDEMO || 5683 vap->iv_opmode == IEEE80211_M_IBSS); 5684 if (stamode && nstate == IEEE80211_S_RUN) { 5685 sc->sc_curaid = ni->ni_associd; 5686 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5687 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5688 } 5689 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5690 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5691 ath_hal_setrxfilter(ah, rfilt); 5692 5693 /* XXX is this to restore keycache on resume? */ 5694 if (vap->iv_opmode != IEEE80211_M_STA && 5695 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5696 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5697 if (ath_hal_keyisvalid(ah, i)) 5698 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5699 } 5700 5701 /* 5702 * Invoke the parent method to do net80211 work. 5703 */ 5704 error = avp->av_newstate(vap, nstate, arg); 5705 if (error != 0) 5706 goto bad; 5707 5708 if (nstate == IEEE80211_S_RUN) { 5709 /* NB: collect bss node again, it may have changed */ 5710 ni = vap->iv_bss; 5711 5712 DPRINTF(sc, ATH_DEBUG_STATE, 5713 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5714 "capinfo 0x%04x chan %d\n", __func__, 5715 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5716 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5717 5718 switch (vap->iv_opmode) { 5719 case IEEE80211_M_HOSTAP: 5720 case IEEE80211_M_IBSS: 5721 /* 5722 * Allocate and setup the beacon frame. 5723 * 5724 * Stop any previous beacon DMA. This may be 5725 * necessary, for example, when an ibss merge 5726 * causes reconfiguration; there will be a state 5727 * transition from RUN->RUN that means we may 5728 * be called with beacon transmission active. 5729 */ 5730 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5731 5732 error = ath_beacon_alloc(sc, ni); 5733 if (error != 0) 5734 goto bad; 5735 /* 5736 * If joining an adhoc network defer beacon timer 5737 * configuration to the next beacon frame so we 5738 * have a current TSF to use. Otherwise we're 5739 * starting an ibss/bss so there's no need to delay; 5740 * if this is the first vap moving to RUN state, then 5741 * beacon state needs to be [re]configured. 5742 */ 5743 if (vap->iv_opmode == IEEE80211_M_IBSS && 5744 ni->ni_tstamp.tsf != 0) { 5745 sc->sc_syncbeacon = 1; 5746 } else if (!sc->sc_beacons) { 5747 ath_beacon_config(sc, vap); 5748 sc->sc_beacons = 1; 5749 } 5750 break; 5751 case IEEE80211_M_STA: 5752 /* 5753 * Defer beacon timer configuration to the next 5754 * beacon frame so we have a current TSF to use 5755 * (any TSF collected when scanning is likely old). 5756 */ 5757 sc->sc_syncbeacon = 1; 5758 break; 5759 case IEEE80211_M_MONITOR: 5760 /* 5761 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5762 * transitions so we must re-enable interrupts here to 5763 * handle the case of a single monitor mode vap. 5764 */ 5765 ath_hal_intrset(ah, sc->sc_imask); 5766 break; 5767 case IEEE80211_M_WDS: 5768 break; 5769 default: 5770 break; 5771 } 5772 /* 5773 * Let the hal process statistics collected during a 5774 * scan so it can provide calibrated noise floor data. 5775 */ 5776 ath_hal_process_noisefloor(ah); 5777 /* 5778 * Reset rssi stats; maybe not the best place... 5779 */ 5780 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5781 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5782 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5783 /* 5784 * Finally, start any timers and the task q thread 5785 * (in case we didn't go through SCAN state). 5786 */ 5787 if (sc->sc_calinterval != 0) { 5788 /* start periodic recalibration timer */ 5789 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5790 ath_calibrate, sc); 5791 } 5792 taskqueue_unblock(sc->sc_tq); 5793 } else if (nstate == IEEE80211_S_INIT) { 5794 /* 5795 * If there are no vaps left in RUN state then 5796 * shutdown host/driver operation: 5797 * o disable interrupts 5798 * o disable the task queue thread 5799 * o mark beacon processing as stopped 5800 */ 5801 if (!ath_isanyrunningvaps(vap)) { 5802 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5803 /* disable interrupts */ 5804 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5805 taskqueue_block(sc->sc_tq); 5806 sc->sc_beacons = 0; 5807 } 5808 } 5809bad: 5810 return error; 5811} 5812 5813/* 5814 * Allocate a key cache slot to the station so we can 5815 * setup a mapping from key index to node. The key cache 5816 * slot is needed for managing antenna state and for 5817 * compression when stations do not use crypto. We do 5818 * it uniliaterally here; if crypto is employed this slot 5819 * will be reassigned. 5820 */ 5821static void 5822ath_setup_stationkey(struct ieee80211_node *ni) 5823{ 5824 struct ieee80211vap *vap = ni->ni_vap; 5825 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5826 ieee80211_keyix keyix, rxkeyix; 5827 5828 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5829 /* 5830 * Key cache is full; we'll fall back to doing 5831 * the more expensive lookup in software. Note 5832 * this also means no h/w compression. 5833 */ 5834 /* XXX msg+statistic */ 5835 } else { 5836 /* XXX locking? */ 5837 ni->ni_ucastkey.wk_keyix = keyix; 5838 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5839 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5840 /* NB: this will create a pass-thru key entry */ 5841 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5842 } 5843} 5844 5845/* 5846 * Setup driver-specific state for a newly associated node. 5847 * Note that we're called also on a re-associate, the isnew 5848 * param tells us if this is the first time or not. 5849 */ 5850static void 5851ath_newassoc(struct ieee80211_node *ni, int isnew) 5852{ 5853 struct ath_node *an = ATH_NODE(ni); 5854 struct ieee80211vap *vap = ni->ni_vap; 5855 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5856 const struct ieee80211_txparam *tp = ni->ni_txparms; 5857 5858 an->an_mcastrix = ath_tx_findrix(sc->sc_currates, tp->mcastrate); 5859 an->an_mgmtrix = ath_tx_findrix(sc->sc_currates, tp->mgmtrate); 5860 5861 ath_rate_newassoc(sc, an, isnew); 5862 if (isnew && 5863 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5864 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5865 ath_setup_stationkey(ni); 5866} 5867 5868static int 5869getchannels(struct ath_softc *sc, int *nchans, struct ieee80211_channel chans[], 5870 int cc, int ecm, int outdoor) 5871{ 5872 struct ath_hal *ah = sc->sc_ah; 5873 HAL_CHANNEL *halchans; 5874 int i, nhalchans, error; 5875 5876 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: cc %u outdoor %u ecm %u\n", 5877 __func__, cc, outdoor, ecm); 5878 5879 halchans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 5880 M_TEMP, M_NOWAIT | M_ZERO); 5881 if (halchans == NULL) { 5882 device_printf(sc->sc_dev, 5883 "%s: unable to allocate channel table\n", __func__); 5884 return ENOMEM; 5885 } 5886 error = 0; 5887 if (!ath_hal_init_channels(ah, halchans, IEEE80211_CHAN_MAX, &nhalchans, 5888 NULL, 0, NULL, cc, HAL_MODE_ALL, outdoor, ecm)) { 5889 u_int32_t rd; 5890 (void) ath_hal_getregdomain(ah, &rd); 5891 device_printf(sc->sc_dev, "ath_hal_init_channels failed, " 5892 "rd %d cc %u outdoor %u ecm %u\n", rd, cc, outdoor, ecm); 5893 error = EINVAL; 5894 goto done; 5895 } 5896 if (nchans == NULL) /* no table requested */ 5897 goto done; 5898 5899 /* 5900 * Convert HAL channels to ieee80211 ones. 5901 */ 5902 for (i = 0; i < nhalchans; i++) { 5903 HAL_CHANNEL *c = &halchans[i]; 5904 struct ieee80211_channel *ichan = &chans[i]; 5905 5906 ichan->ic_ieee = ath_hal_mhz2ieee(ah, c->channel, 5907 c->channelFlags); 5908 if (bootverbose) 5909 device_printf(sc->sc_dev, "hal channel %u/%x -> %u " 5910 "maxpow %d minpow %d maxreg %d\n", 5911 c->channel, c->channelFlags, ichan->ic_ieee, 5912 c->maxTxPower, c->minTxPower, c->maxRegTxPower); 5913 ichan->ic_freq = c->channel; 5914 5915 if ((c->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) { 5916 /* 5917 * Except for AR5211, HAL's PUREG means mixed 5918 * DSSS and OFDM. 5919 */ 5920 ichan->ic_flags = c->channelFlags &~ CHANNEL_PUREG; 5921 ichan->ic_flags |= IEEE80211_CHAN_G; 5922 } else { 5923 ichan->ic_flags = c->channelFlags; 5924 } 5925 5926 if (ath_hal_isgsmsku(ah)) { 5927 /* 5928 * Remap to true frequencies: Ubiquiti XR9 cards use a 5929 * frequency mapping different from their SR9 cards. 5930 * We define special country codes to deal with this. 5931 */ 5932 if (cc == CTRY_XR9) 5933 ichan->ic_freq = ichan->ic_freq - 1520; 5934 else if (cc == CTRY_GZ901) 5935 ichan->ic_freq = ichan->ic_freq - 1544; 5936 else 5937 ichan->ic_freq = 3344 - ichan->ic_freq; 5938 ichan->ic_flags |= IEEE80211_CHAN_GSM; 5939 ichan->ic_ieee = ieee80211_mhz2ieee(ichan->ic_freq, 5940 ichan->ic_flags); 5941 } 5942 ichan->ic_maxregpower = c->maxRegTxPower; /* dBm */ 5943 /* XXX: old hal's don't provide maxTxPower for some parts */ 5944 ichan->ic_maxpower = (c->maxTxPower != 0) ? 5945 c->maxTxPower : 2*c->maxRegTxPower; /* 1/2 dBm */ 5946 ichan->ic_minpower = c->minTxPower; /* 1/2 dBm */ 5947 } 5948 *nchans = nhalchans; 5949done: 5950 free(halchans, M_TEMP); 5951 return error; 5952} 5953 5954/* XXX hard to include ieee80211_regdomain.h right now */ 5955#define SKU_DEBUG 0x1ff 5956 5957static void 5958ath_maprd(const struct ieee80211_regdomain *rd, 5959 u_int32_t *ath_rd, u_int32_t *ath_cc) 5960{ 5961 /* map SKU's to Atheros sku's */ 5962 switch (rd->regdomain) { 5963 case SKU_DEBUG: 5964 if (rd->country == 0) { 5965 *ath_rd = 0; 5966 *ath_cc = CTRY_DEBUG; 5967 return; 5968 } 5969 break; 5970 } 5971 *ath_rd = rd->regdomain; 5972 *ath_cc = rd->country; 5973} 5974 5975static int 5976ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 5977 int nchans, struct ieee80211_channel chans[]) 5978{ 5979 struct ath_softc *sc = ic->ic_ifp->if_softc; 5980 struct ath_hal *ah = sc->sc_ah; 5981 u_int32_t ord, regdomain, cc; 5982 int error; 5983 5984 (void) ath_hal_getregdomain(ah, &ord); 5985 ath_maprd(rd, ®domain, &cc); 5986 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5987 "%s: rd %u cc %u location %c ecm %u (mapped rd %u cc %u)\n", 5988 __func__, rd->regdomain, rd->country, rd->location, rd->ecm, 5989 regdomain, cc); 5990 ath_hal_setregdomain(ah, regdomain); 5991 5992 error = getchannels(sc, &nchans, chans, cc, 5993 rd->ecm ? AH_TRUE : AH_FALSE, 5994 rd->location != 'I' ? AH_TRUE : AH_FALSE); 5995 if (error != 0) { 5996 /* 5997 * Restore previous state. 5998 */ 5999 ath_hal_setregdomain(ah, ord); 6000 (void) getchannels(sc, NULL, NULL, ic->ic_regdomain.country, 6001 ic->ic_regdomain.ecm ? AH_TRUE : AH_FALSE, 6002 ic->ic_regdomain.location != 'I' ? AH_TRUE : AH_FALSE); 6003 return error; 6004 } 6005 return 0; 6006} 6007 6008static void 6009ath_getradiocaps(struct ieee80211com *ic, 6010 int *nchans, struct ieee80211_channel chans[]) 6011{ 6012 struct ath_softc *sc = ic->ic_ifp->if_softc; 6013 struct ath_hal *ah = sc->sc_ah; 6014 u_int32_t ord; 6015 6016 (void) ath_hal_getregdomain(ah, &ord); 6017 6018 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d, ord %u\n", 6019 __func__, 0, CTRY_DEBUG, ord); 6020 6021 ath_hal_setregdomain(ah, 0); 6022 /* XXX not quite right but close enough for now */ 6023 getchannels(sc, nchans, chans, CTRY_DEBUG, AH_TRUE, AH_FALSE); 6024 6025 /* NB: restore previous state */ 6026 ath_hal_setregdomain(ah, ord); 6027 (void) getchannels(sc, NULL, NULL, ic->ic_regdomain.country, 6028 ic->ic_regdomain.ecm ? AH_TRUE : AH_FALSE, 6029 ic->ic_regdomain.location != 'I' ? AH_TRUE : AH_FALSE); 6030} 6031 6032static void 6033ath_mapsku(u_int32_t ath_rd, u_int32_t ath_cc, struct ieee80211_regdomain *rd) 6034{ 6035 rd->isocc[0] = ' '; /* XXX don't know */ 6036 rd->isocc[1] = ' '; 6037 6038 /* map Atheros sku's to SKU's */ 6039 switch (ath_rd) { 6040 case 0: 6041 if (ath_cc == CTRY_DEBUG) { 6042 rd->regdomain = SKU_DEBUG; 6043 rd->country = 0; 6044 return; 6045 } 6046 break; 6047 } 6048 /* XXX net80211 types too small */ 6049 rd->regdomain = (uint16_t) ath_rd; 6050 rd->country = (uint16_t) ath_cc; 6051} 6052 6053static int 6054ath_getchannels(struct ath_softc *sc) 6055{ 6056 struct ifnet *ifp = sc->sc_ifp; 6057 struct ieee80211com *ic = ifp->if_l2com; 6058 struct ath_hal *ah = sc->sc_ah; 6059 int error; 6060 6061 /* 6062 * Convert HAL channels to ieee80211 ones. 6063 */ 6064 error = getchannels(sc, &ic->ic_nchans, ic->ic_channels, 6065 CTRY_DEFAULT, AH_TRUE, AH_FALSE); 6066 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 6067 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 6068 if (error) { 6069 if_printf(ifp, "%s: unable to collect channel list from hal, " 6070 "error %d\n", __func__, error); 6071 if (error == EINVAL) { 6072 if_printf(ifp, "%s: regdomain likely %u country code %u\n", 6073 __func__, sc->sc_eerd, sc->sc_eecc); 6074 } 6075 return error; 6076 } 6077 ic->ic_regdomain.ecm = 1; 6078 ic->ic_regdomain.location = 'I'; 6079 ath_mapsku(sc->sc_eerd, sc->sc_eecc, &ic->ic_regdomain); 6080 6081 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6082 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c ecm %u\n", 6083 __func__, sc->sc_eerd, sc->sc_eecc, 6084 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 6085 ic->ic_regdomain.location, ic->ic_regdomain.ecm); 6086 return 0; 6087} 6088 6089static void 6090ath_led_done(void *arg) 6091{ 6092 struct ath_softc *sc = arg; 6093 6094 sc->sc_blinking = 0; 6095} 6096 6097/* 6098 * Turn the LED off: flip the pin and then set a timer so no 6099 * update will happen for the specified duration. 6100 */ 6101static void 6102ath_led_off(void *arg) 6103{ 6104 struct ath_softc *sc = arg; 6105 6106 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 6107 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 6108} 6109 6110/* 6111 * Blink the LED according to the specified on/off times. 6112 */ 6113static void 6114ath_led_blink(struct ath_softc *sc, int on, int off) 6115{ 6116 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 6117 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 6118 sc->sc_blinking = 1; 6119 sc->sc_ledoff = off; 6120 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 6121} 6122 6123static void 6124ath_led_event(struct ath_softc *sc, int rix) 6125{ 6126 sc->sc_ledevent = ticks; /* time of last event */ 6127 if (sc->sc_blinking) /* don't interrupt active blink */ 6128 return; 6129 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 6130} 6131 6132static int 6133ath_rate_setup(struct ath_softc *sc, u_int mode) 6134{ 6135 struct ath_hal *ah = sc->sc_ah; 6136 const HAL_RATE_TABLE *rt; 6137 6138 switch (mode) { 6139 case IEEE80211_MODE_11A: 6140 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6141 break; 6142 case IEEE80211_MODE_HALF: 6143 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6144 break; 6145 case IEEE80211_MODE_QUARTER: 6146 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6147 break; 6148 case IEEE80211_MODE_11B: 6149 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6150 break; 6151 case IEEE80211_MODE_11G: 6152 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6153 break; 6154 case IEEE80211_MODE_TURBO_A: 6155 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6156#if HAL_ABI_VERSION < 0x07013100 6157 if (rt == NULL) /* XXX bandaid for old hal's */ 6158 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6159#endif 6160 break; 6161 case IEEE80211_MODE_TURBO_G: 6162 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6163 break; 6164 case IEEE80211_MODE_STURBO_A: 6165 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6166 break; 6167 case IEEE80211_MODE_11NA: 6168 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6169 break; 6170 case IEEE80211_MODE_11NG: 6171 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6172 break; 6173 default: 6174 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6175 __func__, mode); 6176 return 0; 6177 } 6178 sc->sc_rates[mode] = rt; 6179 return (rt != NULL); 6180} 6181 6182static void 6183ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6184{ 6185#define N(a) (sizeof(a)/sizeof(a[0])) 6186 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6187 static const struct { 6188 u_int rate; /* tx/rx 802.11 rate */ 6189 u_int16_t timeOn; /* LED on time (ms) */ 6190 u_int16_t timeOff; /* LED off time (ms) */ 6191 } blinkrates[] = { 6192 { 108, 40, 10 }, 6193 { 96, 44, 11 }, 6194 { 72, 50, 13 }, 6195 { 48, 57, 14 }, 6196 { 36, 67, 16 }, 6197 { 24, 80, 20 }, 6198 { 22, 100, 25 }, 6199 { 18, 133, 34 }, 6200 { 12, 160, 40 }, 6201 { 10, 200, 50 }, 6202 { 6, 240, 58 }, 6203 { 4, 267, 66 }, 6204 { 2, 400, 100 }, 6205 { 0, 500, 130 }, 6206 /* XXX half/quarter rates */ 6207 }; 6208 const HAL_RATE_TABLE *rt; 6209 int i, j; 6210 6211 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6212 rt = sc->sc_rates[mode]; 6213 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6214 for (i = 0; i < rt->rateCount; i++) { 6215 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6216 if (rt->info[i].phy != IEEE80211_T_HT) 6217 sc->sc_rixmap[ieeerate] = i; 6218 else 6219 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6220 } 6221 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6222 for (i = 0; i < N(sc->sc_hwmap); i++) { 6223 if (i >= rt->rateCount) { 6224 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6225 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6226 continue; 6227 } 6228 sc->sc_hwmap[i].ieeerate = 6229 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6230 if (rt->info[i].phy == IEEE80211_T_HT) 6231 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6232 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6233 if (rt->info[i].shortPreamble || 6234 rt->info[i].phy == IEEE80211_T_OFDM) 6235 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6236 /* NB: receive frames include FCS */ 6237 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 6238 IEEE80211_RADIOTAP_F_FCS; 6239 /* setup blink rate table to avoid per-packet lookup */ 6240 for (j = 0; j < N(blinkrates)-1; j++) 6241 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6242 break; 6243 /* NB: this uses the last entry if the rate isn't found */ 6244 /* XXX beware of overlow */ 6245 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6246 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6247 } 6248 sc->sc_currates = rt; 6249 sc->sc_curmode = mode; 6250 /* 6251 * All protection frames are transmited at 2Mb/s for 6252 * 11g, otherwise at 1Mb/s. 6253 */ 6254 if (mode == IEEE80211_MODE_11G) 6255 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 6256 else 6257 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 6258 /* NB: caller is responsible for reseting rate control state */ 6259#undef N 6260} 6261 6262#ifdef ATH_DEBUG 6263static void 6264ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6265 u_int ix, int done) 6266{ 6267 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6268 struct ath_hal *ah = sc->sc_ah; 6269 const struct ath_desc *ds; 6270 int i; 6271 6272 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6273 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6274 " %08x %08x %08x %08x\n", 6275 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6276 ds->ds_link, ds->ds_data, 6277 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6278 ds->ds_ctl0, ds->ds_ctl1, 6279 ds->ds_hw[0], ds->ds_hw[1]); 6280 if (ah->ah_magic == 0x20065416) { 6281 printf(" %08x %08x %08x %08x %08x %08x %08x\n", 6282 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6283 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6284 ds->ds_hw[8]); 6285 } 6286 } 6287} 6288 6289static void 6290ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6291 u_int qnum, u_int ix, int done) 6292{ 6293 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6294 struct ath_hal *ah = sc->sc_ah; 6295 const struct ath_desc *ds; 6296 int i; 6297 6298 printf("Q%u[%3u]", qnum, ix); 6299 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6300 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6301 " %08x %08x %08x %08x %08x %08x\n", 6302 ds, (const struct ath_desc *)bf->bf_daddr + i, 6303 ds->ds_link, ds->ds_data, bf->bf_txflags, 6304 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6305 ds->ds_ctl0, ds->ds_ctl1, 6306 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6307 if (ah->ah_magic == 0x20065416) { 6308 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6309 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6310 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6311 ds->ds_hw[10],ds->ds_hw[11]); 6312 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6313 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6314 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6315 ds->ds_hw[18], ds->ds_hw[19]); 6316 } 6317 } 6318} 6319#endif /* ATH_DEBUG */ 6320 6321static void 6322ath_watchdog(struct ifnet *ifp) 6323{ 6324 struct ath_softc *sc = ifp->if_softc; 6325 6326 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && !sc->sc_invalid) { 6327 if_printf(ifp, "device timeout\n"); 6328 ath_reset(ifp); 6329 ifp->if_oerrors++; 6330 sc->sc_stats.ast_watchdog++; 6331 } 6332} 6333 6334#ifdef ATH_DIAGAPI 6335/* 6336 * Diagnostic interface to the HAL. This is used by various 6337 * tools to do things like retrieve register contents for 6338 * debugging. The mechanism is intentionally opaque so that 6339 * it can change frequently w/o concern for compatiblity. 6340 */ 6341static int 6342ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6343{ 6344 struct ath_hal *ah = sc->sc_ah; 6345 u_int id = ad->ad_id & ATH_DIAG_ID; 6346 void *indata = NULL; 6347 void *outdata = NULL; 6348 u_int32_t insize = ad->ad_in_size; 6349 u_int32_t outsize = ad->ad_out_size; 6350 int error = 0; 6351 6352 if (ad->ad_id & ATH_DIAG_IN) { 6353 /* 6354 * Copy in data. 6355 */ 6356 indata = malloc(insize, M_TEMP, M_NOWAIT); 6357 if (indata == NULL) { 6358 error = ENOMEM; 6359 goto bad; 6360 } 6361 error = copyin(ad->ad_in_data, indata, insize); 6362 if (error) 6363 goto bad; 6364 } 6365 if (ad->ad_id & ATH_DIAG_DYN) { 6366 /* 6367 * Allocate a buffer for the results (otherwise the HAL 6368 * returns a pointer to a buffer where we can read the 6369 * results). Note that we depend on the HAL leaving this 6370 * pointer for us to use below in reclaiming the buffer; 6371 * may want to be more defensive. 6372 */ 6373 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 6374 if (outdata == NULL) { 6375 error = ENOMEM; 6376 goto bad; 6377 } 6378 } 6379 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6380 if (outsize < ad->ad_out_size) 6381 ad->ad_out_size = outsize; 6382 if (outdata != NULL) 6383 error = copyout(outdata, ad->ad_out_data, 6384 ad->ad_out_size); 6385 } else { 6386 error = EINVAL; 6387 } 6388bad: 6389 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6390 free(indata, M_TEMP); 6391 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6392 free(outdata, M_TEMP); 6393 return error; 6394} 6395#endif /* ATH_DIAGAPI */ 6396 6397static int 6398ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 6399{ 6400#define IS_RUNNING(ifp) \ 6401 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 6402 struct ath_softc *sc = ifp->if_softc; 6403 struct ieee80211com *ic = ifp->if_l2com; 6404 struct ifreq *ifr = (struct ifreq *)data; 6405 const HAL_RATE_TABLE *rt; 6406 int error = 0; 6407 6408 switch (cmd) { 6409 case SIOCSIFFLAGS: 6410 ATH_LOCK(sc); 6411 if (IS_RUNNING(ifp)) { 6412 /* 6413 * To avoid rescanning another access point, 6414 * do not call ath_init() here. Instead, 6415 * only reflect promisc mode settings. 6416 */ 6417 ath_mode_init(sc); 6418 } else if (ifp->if_flags & IFF_UP) { 6419 /* 6420 * Beware of being called during attach/detach 6421 * to reset promiscuous mode. In that case we 6422 * will still be marked UP but not RUNNING. 6423 * However trying to re-init the interface 6424 * is the wrong thing to do as we've already 6425 * torn down much of our state. There's 6426 * probably a better way to deal with this. 6427 */ 6428 if (!sc->sc_invalid) 6429 ath_init(sc); /* XXX lose error */ 6430 } else { 6431 ath_stop_locked(ifp); 6432#ifdef notyet 6433 /* XXX must wakeup in places like ath_vap_delete */ 6434 if (!sc->sc_invalid) 6435 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6436#endif 6437 } 6438 ATH_UNLOCK(sc); 6439 break; 6440 case SIOCGIFMEDIA: 6441 case SIOCSIFMEDIA: 6442 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6443 break; 6444 case SIOCGATHSTATS: 6445 /* NB: embed these numbers to get a consistent view */ 6446 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6447 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6448 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6449 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6450 rt = sc->sc_currates; 6451 /* XXX HT rates */ 6452 sc->sc_stats.ast_tx_rate = 6453 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6454 return copyout(&sc->sc_stats, 6455 ifr->ifr_data, sizeof (sc->sc_stats)); 6456#ifdef ATH_DIAGAPI 6457 case SIOCGATHDIAG: 6458 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6459 break; 6460#endif 6461 case SIOCGIFADDR: 6462 error = ether_ioctl(ifp, cmd, data); 6463 break; 6464 default: 6465 error = EINVAL; 6466 break; 6467 } 6468 return error; 6469#undef IS_RUNNING 6470} 6471 6472static int 6473ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6474{ 6475 struct ath_softc *sc = arg1; 6476 u_int slottime = ath_hal_getslottime(sc->sc_ah); 6477 int error; 6478 6479 error = sysctl_handle_int(oidp, &slottime, 0, req); 6480 if (error || !req->newptr) 6481 return error; 6482 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 6483} 6484 6485static int 6486ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6487{ 6488 struct ath_softc *sc = arg1; 6489 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6490 int error; 6491 6492 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6493 if (error || !req->newptr) 6494 return error; 6495 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 6496} 6497 6498static int 6499ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6500{ 6501 struct ath_softc *sc = arg1; 6502 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6503 int error; 6504 6505 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6506 if (error || !req->newptr) 6507 return error; 6508 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 6509} 6510 6511static int 6512ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6513{ 6514 struct ath_softc *sc = arg1; 6515 int softled = sc->sc_softled; 6516 int error; 6517 6518 error = sysctl_handle_int(oidp, &softled, 0, req); 6519 if (error || !req->newptr) 6520 return error; 6521 softled = (softled != 0); 6522 if (softled != sc->sc_softled) { 6523 if (softled) { 6524 /* NB: handle any sc_ledpin change */ 6525 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 6526 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6527 !sc->sc_ledon); 6528 } 6529 sc->sc_softled = softled; 6530 } 6531 return 0; 6532} 6533 6534static int 6535ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6536{ 6537 struct ath_softc *sc = arg1; 6538 int ledpin = sc->sc_ledpin; 6539 int error; 6540 6541 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6542 if (error || !req->newptr) 6543 return error; 6544 if (ledpin != sc->sc_ledpin) { 6545 sc->sc_ledpin = ledpin; 6546 if (sc->sc_softled) { 6547 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 6548 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6549 !sc->sc_ledon); 6550 } 6551 } 6552 return 0; 6553} 6554 6555static int 6556ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6557{ 6558 struct ath_softc *sc = arg1; 6559 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6560 int error; 6561 6562 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6563 if (!error && req->newptr) { 6564 /* XXX assumes 2 antenna ports */ 6565 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 6566 return EINVAL; 6567 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6568 /* 6569 * NB: with the switch locked this isn't meaningful, 6570 * but set it anyway so things like radiotap get 6571 * consistent info in their data. 6572 */ 6573 sc->sc_txantenna = txantenna; 6574 } 6575 return error; 6576} 6577 6578static int 6579ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6580{ 6581 struct ath_softc *sc = arg1; 6582 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 6583 int error; 6584 6585 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6586 if (!error && req->newptr) 6587 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6588 return error; 6589} 6590 6591static int 6592ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6593{ 6594 struct ath_softc *sc = arg1; 6595 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 6596 int error; 6597 6598 error = sysctl_handle_int(oidp, &diversity, 0, req); 6599 if (error || !req->newptr) 6600 return error; 6601 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6602 return EINVAL; 6603 sc->sc_diversity = diversity; 6604 return 0; 6605} 6606 6607static int 6608ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6609{ 6610 struct ath_softc *sc = arg1; 6611 u_int32_t diag; 6612 int error; 6613 6614 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 6615 return EINVAL; 6616 error = sysctl_handle_int(oidp, &diag, 0, req); 6617 if (error || !req->newptr) 6618 return error; 6619 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 6620} 6621 6622static int 6623ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6624{ 6625 struct ath_softc *sc = arg1; 6626 struct ifnet *ifp = sc->sc_ifp; 6627 u_int32_t scale; 6628 int error; 6629 6630 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 6631 error = sysctl_handle_int(oidp, &scale, 0, req); 6632 if (error || !req->newptr) 6633 return error; 6634 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 6635 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6636} 6637 6638static int 6639ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6640{ 6641 struct ath_softc *sc = arg1; 6642 u_int tpc = ath_hal_gettpc(sc->sc_ah); 6643 int error; 6644 6645 error = sysctl_handle_int(oidp, &tpc, 0, req); 6646 if (error || !req->newptr) 6647 return error; 6648 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 6649} 6650 6651static int 6652ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6653{ 6654 struct ath_softc *sc = arg1; 6655 struct ifnet *ifp = sc->sc_ifp; 6656 struct ath_hal *ah = sc->sc_ah; 6657 u_int rfkill = ath_hal_getrfkill(ah); 6658 int error; 6659 6660 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6661 if (error || !req->newptr) 6662 return error; 6663 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 6664 return 0; 6665 if (!ath_hal_setrfkill(ah, rfkill)) 6666 return EINVAL; 6667 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6668} 6669 6670static int 6671ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6672{ 6673 struct ath_softc *sc = arg1; 6674 u_int rfsilent; 6675 int error; 6676 6677 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6678 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6679 if (error || !req->newptr) 6680 return error; 6681 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 6682 return EINVAL; 6683 sc->sc_rfsilentpin = rfsilent & 0x1c; 6684 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6685 return 0; 6686} 6687 6688static int 6689ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6690{ 6691 struct ath_softc *sc = arg1; 6692 u_int32_t tpack; 6693 int error; 6694 6695 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 6696 error = sysctl_handle_int(oidp, &tpack, 0, req); 6697 if (error || !req->newptr) 6698 return error; 6699 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 6700} 6701 6702static int 6703ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6704{ 6705 struct ath_softc *sc = arg1; 6706 u_int32_t tpcts; 6707 int error; 6708 6709 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 6710 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6711 if (error || !req->newptr) 6712 return error; 6713 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 6714} 6715 6716static int 6717ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6718{ 6719 struct ath_softc *sc = arg1; 6720 int intmit, error; 6721 6722 intmit = ath_hal_getintmit(sc->sc_ah); 6723 error = sysctl_handle_int(oidp, &intmit, 0, req); 6724 if (error || !req->newptr) 6725 return error; 6726 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0; 6727} 6728 6729static void 6730ath_sysctlattach(struct ath_softc *sc) 6731{ 6732 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6733 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6734 struct ath_hal *ah = sc->sc_ah; 6735 6736 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6737 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6738 "EEPROM country code"); 6739 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6740 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6741 "EEPROM regdomain code"); 6742#ifdef ATH_DEBUG 6743 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6744 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6745 "control debugging printfs"); 6746#endif 6747 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6748 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6749 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6750 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6751 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6752 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6753 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6754 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6755 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6756 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6757 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6758 ath_sysctl_softled, "I", "enable/disable software LED support"); 6759 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6760 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6761 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6762 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6763 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6764 "setting to turn LED on"); 6765 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6766 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6767 "idle time for inactivity LED (ticks)"); 6768 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6769 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6770 ath_sysctl_txantenna, "I", "antenna switch"); 6771 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6772 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6773 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6774 if (ath_hal_hasdiversity(ah)) 6775 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6776 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6777 ath_sysctl_diversity, "I", "antenna diversity"); 6778 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6779 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6780 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6781 "tx descriptor batching"); 6782 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6783 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6784 ath_sysctl_diag, "I", "h/w diagnostic control"); 6785 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6786 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6787 ath_sysctl_tpscale, "I", "tx power scaling"); 6788 if (ath_hal_hastpc(ah)) { 6789 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6790 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6791 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6792 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6793 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6794 ath_sysctl_tpack, "I", "tx power for ack frames"); 6795 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6796 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6797 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6798 } 6799 if (ath_hal_hasfastframes(sc->sc_ah)) { 6800 sc->sc_fftxqmin = ATH_FF_TXQMIN; 6801 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6802 "fftxqmin", CTLFLAG_RW, &sc->sc_fftxqmin, 0, 6803 "min frames before fast-frame staging"); 6804 sc->sc_fftxqmax = ATH_FF_TXQMAX; 6805 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6806 "fftxqmax", CTLFLAG_RW, &sc->sc_fftxqmax, 0, 6807 "max queued frames before tail drop"); 6808 } 6809 if (ath_hal_hasrfsilent(ah)) { 6810 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6811 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6812 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6813 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6814 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6815 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6816 } 6817 if (ath_hal_hasintmit(ah)) { 6818 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6819 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6820 ath_sysctl_intmit, "I", "interference mitigation"); 6821 } 6822 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6823 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6824 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6825 "mask of error frames to pass when monitoring"); 6826} 6827 6828static void 6829ath_bpfattach(struct ath_softc *sc) 6830{ 6831 struct ifnet *ifp = sc->sc_ifp; 6832 6833 bpfattach(ifp, DLT_IEEE802_11_RADIO, 6834 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th)); 6835 /* 6836 * Initialize constant fields. 6837 * XXX make header lengths a multiple of 32-bits so subsequent 6838 * headers are properly aligned; this is a kludge to keep 6839 * certain applications happy. 6840 * 6841 * NB: the channel is setup each time we transition to the 6842 * RUN state to avoid filling it in for each frame. 6843 */ 6844 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 6845 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 6846 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 6847 6848 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 6849 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 6850 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 6851} 6852 6853static int 6854ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6855 struct ath_buf *bf, struct mbuf *m0, 6856 const struct ieee80211_bpf_params *params) 6857{ 6858 struct ifnet *ifp = sc->sc_ifp; 6859 struct ieee80211com *ic = ifp->if_l2com; 6860 struct ath_hal *ah = sc->sc_ah; 6861 int error, ismcast, ismrr; 6862 int hdrlen, pktlen, try0, txantenna; 6863 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6864 struct ieee80211_frame *wh; 6865 u_int flags, ctsduration; 6866 HAL_PKT_TYPE atype; 6867 const HAL_RATE_TABLE *rt; 6868 struct ath_desc *ds; 6869 u_int pri; 6870 6871 wh = mtod(m0, struct ieee80211_frame *); 6872 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6873 hdrlen = ieee80211_anyhdrsize(wh); 6874 /* 6875 * Packet length must not include any 6876 * pad bytes; deduct them here. 6877 */ 6878 /* XXX honor IEEE80211_BPF_DATAPAD */ 6879 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6880 6881 error = ath_tx_dmasetup(sc, bf, m0); 6882 if (error != 0) 6883 return error; 6884 m0 = bf->bf_m; /* NB: may have changed */ 6885 wh = mtod(m0, struct ieee80211_frame *); 6886 bf->bf_node = ni; /* NB: held reference */ 6887 6888 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6889 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6890 if (params->ibp_flags & IEEE80211_BPF_RTS) 6891 flags |= HAL_TXDESC_RTSENA; 6892 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6893 flags |= HAL_TXDESC_CTSENA; 6894 /* XXX leave ismcast to injector? */ 6895 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6896 flags |= HAL_TXDESC_NOACK; 6897 6898 rt = sc->sc_currates; 6899 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6900 rix = ath_tx_findrix(rt, params->ibp_rate0); 6901 txrate = rt->info[rix].rateCode; 6902 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6903 txrate |= rt->info[rix].shortPreamble; 6904 sc->sc_txrix = rix; 6905 try0 = params->ibp_try0; 6906 ismrr = (params->ibp_try1 != 0); 6907 txantenna = params->ibp_pri >> 2; 6908 if (txantenna == 0) /* XXX? */ 6909 txantenna = sc->sc_txantenna; 6910 ctsduration = 0; 6911 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6912 cix = ath_tx_findrix(rt, params->ibp_ctsrate); 6913 ctsrate = rt->info[cix].rateCode; 6914 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6915 ctsrate |= rt->info[cix].shortPreamble; 6916 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6917 ctsduration += rt->info[cix].spAckDuration; 6918 ctsduration += ath_hal_computetxtime(ah, 6919 rt, pktlen, rix, AH_TRUE); 6920 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6921 ctsduration += rt->info[rix].spAckDuration; 6922 } else { 6923 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6924 ctsduration += rt->info[cix].lpAckDuration; 6925 ctsduration += ath_hal_computetxtime(ah, 6926 rt, pktlen, rix, AH_FALSE); 6927 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6928 ctsduration += rt->info[rix].lpAckDuration; 6929 } 6930 ismrr = 0; /* XXX */ 6931 } else 6932 ctsrate = 0; 6933 pri = params->ibp_pri & 3; 6934 /* 6935 * NB: we mark all packets as type PSPOLL so the h/w won't 6936 * set the sequence number, duration, etc. 6937 */ 6938 atype = HAL_PKT_TYPE_PSPOLL; 6939 6940 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6941 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6942 sc->sc_hwmap[rix].ieeerate, -1); 6943 6944 if (bpf_peers_present(ifp->if_bpf)) { 6945 u_int64_t tsf = ath_hal_gettsf64(ah); 6946 6947 sc->sc_tx_th.wt_tsf = htole64(tsf); 6948 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 6949 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6950 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6951 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 6952 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6953 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6954 6955 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 6956 } 6957 6958 /* 6959 * Formulate first tx descriptor with tx controls. 6960 */ 6961 ds = bf->bf_desc; 6962 /* XXX check return value? */ 6963 ath_hal_setuptxdesc(ah, ds 6964 , pktlen /* packet length */ 6965 , hdrlen /* header length */ 6966 , atype /* Atheros packet type */ 6967 , params->ibp_power /* txpower */ 6968 , txrate, try0 /* series 0 rate/tries */ 6969 , HAL_TXKEYIX_INVALID /* key cache index */ 6970 , txantenna /* antenna mode */ 6971 , flags /* flags */ 6972 , ctsrate /* rts/cts rate */ 6973 , ctsduration /* rts/cts duration */ 6974 ); 6975 bf->bf_txflags = flags; 6976 6977 if (ismrr) { 6978 rix = ath_tx_findrix(rt, params->ibp_rate1); 6979 rate1 = rt->info[rix].rateCode; 6980 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6981 rate1 |= rt->info[rix].shortPreamble; 6982 if (params->ibp_try2) { 6983 rix = ath_tx_findrix(rt, params->ibp_rate2); 6984 rate2 = rt->info[rix].rateCode; 6985 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6986 rate2 |= rt->info[rix].shortPreamble; 6987 } else 6988 rate2 = 0; 6989 if (params->ibp_try3) { 6990 rix = ath_tx_findrix(rt, params->ibp_rate3); 6991 rate3 = rt->info[rix].rateCode; 6992 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6993 rate3 |= rt->info[rix].shortPreamble; 6994 } else 6995 rate3 = 0; 6996 ath_hal_setupxtxdesc(ah, ds 6997 , rate1, params->ibp_try1 /* series 1 */ 6998 , rate2, params->ibp_try2 /* series 2 */ 6999 , rate3, params->ibp_try3 /* series 3 */ 7000 ); 7001 } 7002 7003 /* NB: no buffered multicast in power save support */ 7004 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 7005 return 0; 7006} 7007 7008static int 7009ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 7010 const struct ieee80211_bpf_params *params) 7011{ 7012 struct ieee80211com *ic = ni->ni_ic; 7013 struct ifnet *ifp = ic->ic_ifp; 7014 struct ath_softc *sc = ifp->if_softc; 7015 struct ath_buf *bf; 7016 7017 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 7018 ieee80211_free_node(ni); 7019 m_freem(m); 7020 return ENETDOWN; 7021 } 7022 /* 7023 * Grab a TX buffer and associated resources. 7024 */ 7025 ATH_TXBUF_LOCK(sc); 7026 bf = STAILQ_FIRST(&sc->sc_txbuf); 7027 if (bf != NULL) 7028 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 7029 ATH_TXBUF_UNLOCK(sc); 7030 if (bf == NULL) { 7031 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 7032 __func__); 7033 sc->sc_stats.ast_tx_qstop++; 7034 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7035 ieee80211_free_node(ni); 7036 m_freem(m); 7037 return ENOBUFS; 7038 } 7039 7040 ifp->if_opackets++; 7041 sc->sc_stats.ast_tx_raw++; 7042 7043 if (params == NULL) { 7044 /* 7045 * Legacy path; interpret frame contents to decide 7046 * precisely how to send the frame. 7047 */ 7048 if (ath_tx_start(sc, ni, bf, m)) 7049 goto bad; 7050 } else { 7051 /* 7052 * Caller supplied explicit parameters to use in 7053 * sending the frame. 7054 */ 7055 if (ath_tx_raw_start(sc, ni, bf, m, params)) 7056 goto bad; 7057 } 7058 ifp->if_timer = 5; 7059 7060 return 0; 7061bad: 7062 ifp->if_oerrors++; 7063 ATH_TXBUF_LOCK(sc); 7064 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 7065 ATH_TXBUF_UNLOCK(sc); 7066 ieee80211_free_node(ni); 7067 return EIO; /* XXX */ 7068} 7069 7070/* 7071 * Announce various information on device/driver attach. 7072 */ 7073static void 7074ath_announce(struct ath_softc *sc) 7075{ 7076#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 7077 struct ifnet *ifp = sc->sc_ifp; 7078 struct ath_hal *ah = sc->sc_ah; 7079 u_int modes, cc; 7080 7081 if_printf(ifp, "mac %d.%d phy %d.%d", 7082 ah->ah_macVersion, ah->ah_macRev, 7083 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 7084 /* 7085 * Print radio revision(s). We check the wireless modes 7086 * to avoid falsely printing revs for inoperable parts. 7087 * Dual-band radio revs are returned in the 5Ghz rev number. 7088 */ 7089 ath_hal_getcountrycode(ah, &cc); 7090 modes = ath_hal_getwirelessmodes(ah, cc); 7091 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 7092 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 7093 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 7094 ah->ah_analog5GhzRev >> 4, 7095 ah->ah_analog5GhzRev & 0xf, 7096 ah->ah_analog2GhzRev >> 4, 7097 ah->ah_analog2GhzRev & 0xf); 7098 else 7099 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 7100 ah->ah_analog5GhzRev & 0xf); 7101 } else 7102 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 7103 ah->ah_analog5GhzRev & 0xf); 7104 printf("\n"); 7105 if (bootverbose) { 7106 int i; 7107 for (i = 0; i <= WME_AC_VO; i++) { 7108 struct ath_txq *txq = sc->sc_ac2q[i]; 7109 if_printf(ifp, "Use hw queue %u for %s traffic\n", 7110 txq->axq_qnum, ieee80211_wme_acnames[i]); 7111 } 7112 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 7113 sc->sc_cabq->axq_qnum); 7114 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 7115 } 7116 if (ath_rxbuf != ATH_RXBUF) 7117 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 7118 if (ath_txbuf != ATH_TXBUF) 7119 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 7120#undef HAL_MODE_DUALBAND 7121} 7122