if_ath.c revision 170375
1/*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 170375 2007-06-06 15:49:16Z sam $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sysctl.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/kernel.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/errno.h> 54#include <sys/callout.h> 55#include <sys/bus.h> 56#include <sys/endian.h> 57#include <sys/kthread.h> 58#include <sys/taskqueue.h> 59 60#include <machine/bus.h> 61 62#include <net/if.h> 63#include <net/if_dl.h> 64#include <net/if_media.h> 65#include <net/if_types.h> 66#include <net/if_arp.h> 67#include <net/ethernet.h> 68#include <net/if_llc.h> 69 70#include <net80211/ieee80211_var.h> 71 72#include <net/bpf.h> 73 74#ifdef INET 75#include <netinet/in.h> 76#include <netinet/if_ether.h> 77#endif 78 79#include <dev/ath/if_athvar.h> 80#include <contrib/dev/ath/ah_desc.h> 81#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 82 83#ifdef ATH_TX99_DIAG 84#include <dev/ath/ath_tx99/ath_tx99.h> 85#endif 86 87/* unaligned little endian access */ 88#define LE_READ_2(p) \ 89 ((u_int16_t) \ 90 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 91#define LE_READ_4(p) \ 92 ((u_int32_t) \ 93 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 94 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 95 96enum { 97 ATH_LED_TX, 98 ATH_LED_RX, 99 ATH_LED_POLL, 100}; 101 102static void ath_init(void *); 103static void ath_stop_locked(struct ifnet *); 104static void ath_stop(struct ifnet *); 105static void ath_start(struct ifnet *); 106static int ath_reset(struct ifnet *); 107static int ath_media_change(struct ifnet *); 108static void ath_watchdog(struct ifnet *); 109static int ath_ioctl(struct ifnet *, u_long, caddr_t); 110static void ath_fatal_proc(void *, int); 111static void ath_rxorn_proc(void *, int); 112static void ath_bmiss_proc(void *, int); 113static int ath_key_alloc(struct ieee80211com *, 114 const struct ieee80211_key *, 115 ieee80211_keyix *, ieee80211_keyix *); 116static int ath_key_delete(struct ieee80211com *, 117 const struct ieee80211_key *); 118static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 119 const u_int8_t mac[IEEE80211_ADDR_LEN]); 120static void ath_key_update_begin(struct ieee80211com *); 121static void ath_key_update_end(struct ieee80211com *); 122static void ath_mode_init(struct ath_softc *); 123static void ath_setslottime(struct ath_softc *); 124static void ath_updateslot(struct ifnet *); 125static int ath_beaconq_setup(struct ath_hal *); 126static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 127static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 128static void ath_beacon_proc(void *, int); 129static void ath_bstuck_proc(void *, int); 130static void ath_beacon_free(struct ath_softc *); 131static void ath_beacon_config(struct ath_softc *); 132static void ath_descdma_cleanup(struct ath_softc *sc, 133 struct ath_descdma *, ath_bufhead *); 134static int ath_desc_alloc(struct ath_softc *); 135static void ath_desc_free(struct ath_softc *); 136static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 137static void ath_node_free(struct ieee80211_node *); 138static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 139static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 140static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 141 struct ieee80211_node *ni, 142 int subtype, int rssi, u_int32_t rstamp); 143static void ath_setdefantenna(struct ath_softc *, u_int); 144static void ath_rx_proc(void *, int); 145static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 146static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 147static int ath_tx_setup(struct ath_softc *, int, int); 148static int ath_wme_update(struct ieee80211com *); 149static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 150static void ath_tx_cleanup(struct ath_softc *); 151static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 152 struct ath_buf *, struct mbuf *); 153static void ath_tx_proc_q0(void *, int); 154static void ath_tx_proc_q0123(void *, int); 155static void ath_tx_proc(void *, int); 156static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 157static void ath_draintxq(struct ath_softc *); 158static void ath_stoprecv(struct ath_softc *); 159static int ath_startrecv(struct ath_softc *); 160static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 161static void ath_next_scan(void *); 162static void ath_calibrate(void *); 163static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 164static void ath_setup_stationkey(struct ieee80211_node *); 165static void ath_newassoc(struct ieee80211_node *, int); 166static int ath_getchannels(struct ath_softc *, 167 HAL_REG_DOMAIN, HAL_CTRY_CODE, HAL_BOOL, HAL_BOOL); 168static void ath_led_event(struct ath_softc *, int); 169static void ath_update_txpow(struct ath_softc *); 170 171static int ath_rate_setup(struct ath_softc *, u_int mode); 172static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 173 174static void ath_sysctlattach(struct ath_softc *); 175static int ath_raw_xmit(struct ieee80211_node *, 176 struct mbuf *, const struct ieee80211_bpf_params *); 177static void ath_bpfattach(struct ath_softc *); 178static void ath_announce(struct ath_softc *); 179 180SYSCTL_DECL(_hw_ath); 181 182/* XXX validate sysctl values */ 183static int ath_dwelltime = 200; /* 5 channels/second */ 184SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 185 0, "channel dwell time (ms) for AP/station scanning"); 186static int ath_calinterval = 30; /* calibrate every 30 secs */ 187SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 188 0, "chip calibration interval (secs)"); 189static int ath_outdoor = AH_TRUE; /* outdoor operation */ 190SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RW, &ath_outdoor, 191 0, "outdoor operation"); 192TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 193static int ath_xchanmode = AH_TRUE; /* extended channel use */ 194SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RW, &ath_xchanmode, 195 0, "extended channel mode"); 196TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 197static int ath_countrycode = CTRY_DEFAULT; /* country code */ 198SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RW, &ath_countrycode, 199 0, "country code"); 200TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 201static int ath_regdomain = 0; /* regulatory domain */ 202SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 203 0, "regulatory domain"); 204 205static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 206SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 207 0, "rx buffers allocated"); 208TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 209static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 210SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 211 0, "tx buffers allocated"); 212TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 213 214#ifdef ATH_DEBUG 215static int ath_debug = 0; 216SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 217 0, "control debugging printfs"); 218TUNABLE_INT("hw.ath.debug", &ath_debug); 219enum { 220 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 221 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 222 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 223 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 224 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 225 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 226 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 227 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 228 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 229 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 230 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 231 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 232 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 233 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 234 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 235 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 236 ATH_DEBUG_NODE = 0x00080000, /* node management */ 237 ATH_DEBUG_LED = 0x00100000, /* led management */ 238 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 239 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 240 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 241 ATH_DEBUG_ANY = 0xffffffff 242}; 243#define IFF_DUMPPKTS(sc, m) \ 244 ((sc->sc_debug & (m)) || \ 245 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 246#define DPRINTF(sc, m, fmt, ...) do { \ 247 if (sc->sc_debug & (m)) \ 248 printf(fmt, __VA_ARGS__); \ 249} while (0) 250#define KEYPRINTF(sc, ix, hk, mac) do { \ 251 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 252 ath_keyprint(sc, __func__, ix, hk, mac); \ 253} while (0) 254static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int); 255static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done); 256#else 257#define IFF_DUMPPKTS(sc, m) \ 258 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 259#define DPRINTF(sc, m, fmt, ...) do { \ 260 (void) sc; \ 261} while (0) 262#define KEYPRINTF(sc, k, ix, mac) do { \ 263 (void) sc; \ 264} while (0) 265#endif 266 267MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 268 269int 270ath_attach(u_int16_t devid, struct ath_softc *sc) 271{ 272 struct ifnet *ifp; 273 struct ieee80211com *ic = &sc->sc_ic; 274 struct ath_hal *ah = NULL; 275 HAL_STATUS status; 276 int error = 0, i; 277 278 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 279 280 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 281 if (ifp == NULL) { 282 device_printf(sc->sc_dev, "can not if_alloc()\n"); 283 error = ENOSPC; 284 goto bad; 285 } 286 287 /* set these up early for if_printf use */ 288 if_initname(ifp, device_get_name(sc->sc_dev), 289 device_get_unit(sc->sc_dev)); 290 291 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 292 if (ah == NULL) { 293 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 294 status); 295 error = ENXIO; 296 goto bad; 297 } 298 if (ah->ah_abi != HAL_ABI_VERSION) { 299 if_printf(ifp, "HAL ABI mismatch detected " 300 "(HAL:0x%x != driver:0x%x)\n", 301 ah->ah_abi, HAL_ABI_VERSION); 302 error = ENXIO; 303 goto bad; 304 } 305 sc->sc_ah = ah; 306 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 307 308 /* 309 * Check if the MAC has multi-rate retry support. 310 * We do this by trying to setup a fake extended 311 * descriptor. MAC's that don't have support will 312 * return false w/o doing anything. MAC's that do 313 * support it will return true w/o doing anything. 314 */ 315 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 316 317 /* 318 * Check if the device has hardware counters for PHY 319 * errors. If so we need to enable the MIB interrupt 320 * so we can act on stat triggers. 321 */ 322 if (ath_hal_hwphycounters(ah)) 323 sc->sc_needmib = 1; 324 325 /* 326 * Get the hardware key cache size. 327 */ 328 sc->sc_keymax = ath_hal_keycachesize(ah); 329 if (sc->sc_keymax > ATH_KEYMAX) { 330 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 331 ATH_KEYMAX, sc->sc_keymax); 332 sc->sc_keymax = ATH_KEYMAX; 333 } 334 /* 335 * Reset the key cache since some parts do not 336 * reset the contents on initial power up. 337 */ 338 for (i = 0; i < sc->sc_keymax; i++) 339 ath_hal_keyreset(ah, i); 340 341 /* 342 * Collect the channel list using the default country 343 * code and including outdoor channels. The 802.11 layer 344 * is resposible for filtering this list based on settings 345 * like the phy mode. 346 */ 347 error = ath_getchannels(sc, ath_regdomain, ath_countrycode, 348 ath_xchanmode != 0, ath_outdoor != 0); 349 if (error != 0) 350 goto bad; 351 352 /* 353 * Setup rate tables for all potential media types. 354 */ 355 ath_rate_setup(sc, IEEE80211_MODE_11A); 356 ath_rate_setup(sc, IEEE80211_MODE_11B); 357 ath_rate_setup(sc, IEEE80211_MODE_11G); 358 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 360 ath_rate_setup(sc, IEEE80211_MODE_HALF); 361 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 362 363 /* NB: setup here so ath_rate_update is happy */ 364 ath_setcurmode(sc, IEEE80211_MODE_11A); 365 366 /* 367 * Allocate tx+rx descriptors and populate the lists. 368 */ 369 error = ath_desc_alloc(sc); 370 if (error != 0) { 371 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 372 goto bad; 373 } 374 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 375 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 376 callout_init(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 377 378 ATH_TXBUF_LOCK_INIT(sc); 379 380 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 381 taskqueue_thread_enqueue, &sc->sc_tq); 382 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 383 "%s taskq", ifp->if_xname); 384 385 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 386 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 387 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 388 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 389 390 /* 391 * Allocate hardware transmit queues: one queue for 392 * beacon frames and one data queue for each QoS 393 * priority. Note that the hal handles reseting 394 * these queues at the needed time. 395 * 396 * XXX PS-Poll 397 */ 398 sc->sc_bhalq = ath_beaconq_setup(ah); 399 if (sc->sc_bhalq == (u_int) -1) { 400 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 401 error = EIO; 402 goto bad2; 403 } 404 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 405 if (sc->sc_cabq == NULL) { 406 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 407 error = EIO; 408 goto bad2; 409 } 410 /* NB: s/w q, qnum used only by WITNESS */ 411 ath_txq_init(sc, &sc->sc_mcastq, HAL_NUM_TX_QUEUES+1); 412 /* NB: insure BK queue is the lowest priority h/w queue */ 413 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 414 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 415 ieee80211_wme_acnames[WME_AC_BK]); 416 error = EIO; 417 goto bad2; 418 } 419 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 420 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 421 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 422 /* 423 * Not enough hardware tx queues to properly do WME; 424 * just punt and assign them all to the same h/w queue. 425 * We could do a better job of this if, for example, 426 * we allocate queues when we switch from station to 427 * AP mode. 428 */ 429 if (sc->sc_ac2q[WME_AC_VI] != NULL) 430 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 431 if (sc->sc_ac2q[WME_AC_BE] != NULL) 432 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 433 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 434 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 435 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 436 } 437 438 /* 439 * Special case certain configurations. Note the 440 * CAB queue is handled by these specially so don't 441 * include them when checking the txq setup mask. 442 */ 443 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 444 case 0x01: 445 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 446 break; 447 case 0x0f: 448 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 449 break; 450 default: 451 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 452 break; 453 } 454 455 /* 456 * Setup rate control. Some rate control modules 457 * call back to change the anntena state so expose 458 * the necessary entry points. 459 * XXX maybe belongs in struct ath_ratectrl? 460 */ 461 sc->sc_setdefantenna = ath_setdefantenna; 462 sc->sc_rc = ath_rate_attach(sc); 463 if (sc->sc_rc == NULL) { 464 error = EIO; 465 goto bad2; 466 } 467 468 sc->sc_blinking = 0; 469 sc->sc_ledstate = 1; 470 sc->sc_ledon = 0; /* low true */ 471 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 472 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 473 /* 474 * Auto-enable soft led processing for IBM cards and for 475 * 5211 minipci cards. Users can also manually enable/disable 476 * support with a sysctl. 477 */ 478 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 479 if (sc->sc_softled) { 480 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 481 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 482 } 483 484 ifp->if_softc = sc; 485 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 486 ifp->if_start = ath_start; 487 ifp->if_watchdog = ath_watchdog; 488 ifp->if_ioctl = ath_ioctl; 489 ifp->if_init = ath_init; 490 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 491 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 492 IFQ_SET_READY(&ifp->if_snd); 493 494 ic->ic_ifp = ifp; 495 ic->ic_reset = ath_reset; 496 ic->ic_newassoc = ath_newassoc; 497 ic->ic_updateslot = ath_updateslot; 498 ic->ic_wme.wme_update = ath_wme_update; 499 /* XXX not right but it's not used anywhere important */ 500 ic->ic_phytype = IEEE80211_T_OFDM; 501 ic->ic_opmode = IEEE80211_M_STA; 502 ic->ic_caps = 503 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 504 | IEEE80211_C_HOSTAP /* hostap mode */ 505 | IEEE80211_C_MONITOR /* monitor mode */ 506 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 507 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 508 | IEEE80211_C_SHSLOT /* short slot time supported */ 509 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 510 ; 511 /* 512 * Query the hal to figure out h/w crypto support. 513 */ 514 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 515 ic->ic_caps |= IEEE80211_C_WEP; 516 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 517 ic->ic_caps |= IEEE80211_C_AES; 518 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 519 ic->ic_caps |= IEEE80211_C_AES_CCM; 520 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 521 ic->ic_caps |= IEEE80211_C_CKIP; 522 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 523 ic->ic_caps |= IEEE80211_C_TKIP; 524 /* 525 * Check if h/w does the MIC and/or whether the 526 * separate key cache entries are required to 527 * handle both tx+rx MIC keys. 528 */ 529 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 530 ic->ic_caps |= IEEE80211_C_TKIPMIC; 531 /* 532 * If the h/w supports storing tx+rx MIC keys 533 * in one cache slot automatically enable use. 534 */ 535 if (ath_hal_hastkipsplit(ah) || 536 !ath_hal_settkipsplit(ah, AH_FALSE)) 537 sc->sc_splitmic = 1; 538 } 539 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 540 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 541 /* 542 * Mark key cache slots associated with global keys 543 * as in use. If we knew TKIP was not to be used we 544 * could leave the +32, +64, and +32+64 slots free. 545 */ 546 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 547 setbit(sc->sc_keymap, i); 548 setbit(sc->sc_keymap, i+64); 549 if (sc->sc_splitmic) { 550 setbit(sc->sc_keymap, i+32); 551 setbit(sc->sc_keymap, i+32+64); 552 } 553 } 554 /* 555 * TPC support can be done either with a global cap or 556 * per-packet support. The latter is not available on 557 * all parts. We're a bit pedantic here as all parts 558 * support a global cap. 559 */ 560 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 561 ic->ic_caps |= IEEE80211_C_TXPMGT; 562 563 /* 564 * Mark WME capability only if we have sufficient 565 * hardware queues to do proper priority scheduling. 566 */ 567 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 568 ic->ic_caps |= IEEE80211_C_WME; 569 /* 570 * Check for misc other capabilities. 571 */ 572 if (ath_hal_hasbursting(ah)) 573 ic->ic_caps |= IEEE80211_C_BURST; 574 575 /* 576 * Indicate we need the 802.11 header padded to a 577 * 32-bit boundary for 4-address and QoS frames. 578 */ 579 ic->ic_flags |= IEEE80211_F_DATAPAD; 580 581 /* 582 * Query the hal about antenna support. 583 */ 584 sc->sc_defant = ath_hal_getdefantenna(ah); 585 586 /* 587 * Not all chips have the VEOL support we want to 588 * use with IBSS beacons; check here for it. 589 */ 590 sc->sc_hasveol = ath_hal_hasveol(ah); 591 592 /* get mac address from hardware */ 593 ath_hal_getmac(ah, ic->ic_myaddr); 594 595 /* call MI attach routine. */ 596 ieee80211_ifattach(ic); 597 sc->sc_opmode = ic->ic_opmode; 598 /* override default methods */ 599 ic->ic_node_alloc = ath_node_alloc; 600 sc->sc_node_free = ic->ic_node_free; 601 ic->ic_node_free = ath_node_free; 602 ic->ic_node_getrssi = ath_node_getrssi; 603 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 604 ic->ic_recv_mgmt = ath_recv_mgmt; 605 sc->sc_newstate = ic->ic_newstate; 606 ic->ic_newstate = ath_newstate; 607 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 608 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 609 ic->ic_crypto.cs_key_delete = ath_key_delete; 610 ic->ic_crypto.cs_key_set = ath_key_set; 611 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 612 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 613 ic->ic_raw_xmit = ath_raw_xmit; 614 /* complete initialization */ 615 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 616 617 ath_bpfattach(sc); 618 /* 619 * Setup dynamic sysctl's now that country code and 620 * regdomain are available from the hal. 621 */ 622 ath_sysctlattach(sc); 623 624 if (bootverbose) 625 ieee80211_announce(ic); 626 ath_announce(sc); 627 return 0; 628bad2: 629 ath_tx_cleanup(sc); 630 ath_desc_free(sc); 631bad: 632 if (ah) 633 ath_hal_detach(ah); 634 if (ifp != NULL) 635 if_free(ifp); 636 sc->sc_invalid = 1; 637 return error; 638} 639 640int 641ath_detach(struct ath_softc *sc) 642{ 643 struct ifnet *ifp = sc->sc_ifp; 644 645 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 646 __func__, ifp->if_flags); 647 648 ath_stop(ifp); 649 bpfdetach(ifp); 650 /* 651 * NB: the order of these is important: 652 * o call the 802.11 layer before detaching the hal to 653 * insure callbacks into the driver to delete global 654 * key cache entries can be handled 655 * o reclaim the tx queue data structures after calling 656 * the 802.11 layer as we'll get called back to reclaim 657 * node state and potentially want to use them 658 * o to cleanup the tx queues the hal is called, so detach 659 * it last 660 * Other than that, it's straightforward... 661 */ 662 ieee80211_ifdetach(&sc->sc_ic); 663#ifdef ATH_TX99_DIAG 664 if (sc->sc_tx99 != NULL) 665 sc->sc_tx99->detach(sc->sc_tx99); 666#endif 667 taskqueue_free(sc->sc_tq); 668 ath_rate_detach(sc->sc_rc); 669 ath_desc_free(sc); 670 ath_tx_cleanup(sc); 671 ath_hal_detach(sc->sc_ah); 672 if_free(ifp); 673 674 return 0; 675} 676 677void 678ath_suspend(struct ath_softc *sc) 679{ 680 struct ifnet *ifp = sc->sc_ifp; 681 682 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 683 __func__, ifp->if_flags); 684 685 ath_stop(ifp); 686} 687 688void 689ath_resume(struct ath_softc *sc) 690{ 691 struct ifnet *ifp = sc->sc_ifp; 692 693 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 694 __func__, ifp->if_flags); 695 696 if (ifp->if_flags & IFF_UP) { 697 ath_init(sc); 698 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 699 ath_start(ifp); 700 } 701 if (sc->sc_softled) { 702 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 703 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 704 } 705} 706 707void 708ath_shutdown(struct ath_softc *sc) 709{ 710 struct ifnet *ifp = sc->sc_ifp; 711 712 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 713 __func__, ifp->if_flags); 714 715 ath_stop(ifp); 716} 717 718/* 719 * Interrupt handler. Most of the actual processing is deferred. 720 */ 721void 722ath_intr(void *arg) 723{ 724 struct ath_softc *sc = arg; 725 struct ifnet *ifp = sc->sc_ifp; 726 struct ath_hal *ah = sc->sc_ah; 727 HAL_INT status; 728 729 if (sc->sc_invalid) { 730 /* 731 * The hardware is not ready/present, don't touch anything. 732 * Note this can happen early on if the IRQ is shared. 733 */ 734 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 735 return; 736 } 737 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 738 return; 739 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & 740 IFF_DRV_RUNNING))) { 741 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 742 __func__, ifp->if_flags); 743 ath_hal_getisr(ah, &status); /* clear ISR */ 744 ath_hal_intrset(ah, 0); /* disable further intr's */ 745 return; 746 } 747 /* 748 * Figure out the reason(s) for the interrupt. Note 749 * that the hal returns a pseudo-ISR that may include 750 * bits we haven't explicitly enabled so we mask the 751 * value to insure we only process bits we requested. 752 */ 753 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 754 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 755 status &= sc->sc_imask; /* discard unasked for bits */ 756 if (status & HAL_INT_FATAL) { 757 sc->sc_stats.ast_hardware++; 758 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 759 ath_fatal_proc(sc, 0); 760 } else if (status & HAL_INT_RXORN) { 761 sc->sc_stats.ast_rxorn++; 762 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 763 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask); 764 } else { 765 if (status & HAL_INT_SWBA) { 766 /* 767 * Software beacon alert--time to send a beacon. 768 * Handle beacon transmission directly; deferring 769 * this is too slow to meet timing constraints 770 * under load. 771 */ 772 ath_beacon_proc(sc, 0); 773 } 774 if (status & HAL_INT_RXEOL) { 775 /* 776 * NB: the hardware should re-read the link when 777 * RXE bit is written, but it doesn't work at 778 * least on older hardware revs. 779 */ 780 sc->sc_stats.ast_rxeol++; 781 sc->sc_rxlink = NULL; 782 } 783 if (status & HAL_INT_TXURN) { 784 sc->sc_stats.ast_txurn++; 785 /* bump tx trigger level */ 786 ath_hal_updatetxtriglevel(ah, AH_TRUE); 787 } 788 if (status & HAL_INT_RX) 789 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 790 if (status & HAL_INT_TX) 791 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 792 if (status & HAL_INT_BMISS) { 793 sc->sc_stats.ast_bmiss++; 794 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 795 } 796 if (status & HAL_INT_MIB) { 797 sc->sc_stats.ast_mib++; 798 /* 799 * Disable interrupts until we service the MIB 800 * interrupt; otherwise it will continue to fire. 801 */ 802 ath_hal_intrset(ah, 0); 803 /* 804 * Let the hal handle the event. We assume it will 805 * clear whatever condition caused the interrupt. 806 */ 807 ath_hal_mibevent(ah, &sc->sc_halstats); 808 ath_hal_intrset(ah, sc->sc_imask); 809 } 810 } 811} 812 813static void 814ath_fatal_proc(void *arg, int pending) 815{ 816 struct ath_softc *sc = arg; 817 struct ifnet *ifp = sc->sc_ifp; 818 u_int32_t *state; 819 u_int32_t len; 820 821 if_printf(ifp, "hardware error; resetting\n"); 822 /* 823 * Fatal errors are unrecoverable. Typically these 824 * are caused by DMA errors. Collect h/w state from 825 * the hal so we can diagnose what's going on. 826 */ 827 if (ath_hal_getfatalstate(sc->sc_ah, &state, &len)) { 828 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 829 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 830 state[0], state[1] , state[2], state[3], 831 state[4], state[5]); 832 } 833 ath_reset(ifp); 834} 835 836static void 837ath_rxorn_proc(void *arg, int pending) 838{ 839 struct ath_softc *sc = arg; 840 struct ifnet *ifp = sc->sc_ifp; 841 842 if_printf(ifp, "rx FIFO overrun; resetting\n"); 843 ath_reset(ifp); 844} 845 846static void 847ath_bmiss_proc(void *arg, int pending) 848{ 849 struct ath_softc *sc = arg; 850 struct ieee80211com *ic = &sc->sc_ic; 851 852 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 853 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 854 ("unexpect operating mode %u", ic->ic_opmode)); 855 if (ic->ic_state == IEEE80211_S_RUN) { 856 u_int64_t lastrx = sc->sc_lastrx; 857 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 858 u_int bmisstimeout = 859 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024; 860 861 DPRINTF(sc, ATH_DEBUG_BEACON, 862 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 863 __func__, (unsigned long long) tsf, 864 (unsigned long long)(tsf - lastrx), 865 (unsigned long long) lastrx, bmisstimeout); 866 /* 867 * Workaround phantom bmiss interrupts by sanity-checking 868 * the time of our last rx'd frame. If it is within the 869 * beacon miss interval then ignore the interrupt. If it's 870 * truly a bmiss we'll get another interrupt soon and that'll 871 * be dispatched up for processing. 872 */ 873 if (tsf - lastrx > bmisstimeout) { 874 NET_LOCK_GIANT(); 875 ieee80211_beacon_miss(ic); 876 NET_UNLOCK_GIANT(); 877 } else 878 sc->sc_stats.ast_bmiss_phantom++; 879 } 880} 881 882/* 883 * Convert net80211 channel to a HAL channel with the flags 884 * constrained to reflect the current operating mode and 885 * the frequency possibly mapped for GSM channels. 886 */ 887static void 888ath_mapchan(struct ieee80211com *ic, HAL_CHANNEL *hc, 889 const struct ieee80211_channel *chan) 890{ 891#define N(a) (sizeof(a) / sizeof(a[0])) 892 static const u_int modeflags[] = { 893 0, /* IEEE80211_MODE_AUTO */ 894 CHANNEL_A, /* IEEE80211_MODE_11A */ 895 CHANNEL_B, /* IEEE80211_MODE_11B */ 896 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 897 0, /* IEEE80211_MODE_FH */ 898 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 899 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 900 }; 901 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 902 903 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 904 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 905 hc->channelFlags = modeflags[mode]; 906 if (IEEE80211_IS_CHAN_HALF(chan)) 907 hc->channelFlags |= CHANNEL_HALF; 908 if (IEEE80211_IS_CHAN_QUARTER(chan)) 909 hc->channelFlags |= CHANNEL_QUARTER; 910 911 hc->channel = IEEE80211_IS_CHAN_GSM(chan) ? 912 2422 + (922 - chan->ic_freq) : chan->ic_freq; 913#undef N 914} 915 916static void 917ath_init(void *arg) 918{ 919 struct ath_softc *sc = (struct ath_softc *) arg; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct ifnet *ifp = sc->sc_ifp; 922 struct ath_hal *ah = sc->sc_ah; 923 HAL_STATUS status; 924 925 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 926 __func__, ifp->if_flags); 927 928 ATH_LOCK(sc); 929 /* 930 * Stop anything previously setup. This is safe 931 * whether this is the first time through or not. 932 */ 933 ath_stop_locked(ifp); 934 935 /* 936 * The basic interface to setting the hardware in a good 937 * state is ``reset''. On return the hardware is known to 938 * be powered up and with interrupts disabled. This must 939 * be followed by initialization of the appropriate bits 940 * and then setup of the interrupt mask. 941 */ 942 ath_mapchan(ic, &sc->sc_curchan, ic->ic_curchan); 943 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 944 if_printf(ifp, "unable to reset hardware; hal status %u\n", 945 status); 946 goto done; 947 } 948 949 /* 950 * This is needed only to setup initial state 951 * but it's best done after a reset. 952 */ 953 ath_update_txpow(sc); 954 /* 955 * Likewise this is set during reset so update 956 * state cached in the driver. 957 */ 958 sc->sc_diversity = ath_hal_getdiversity(ah); 959 sc->sc_calinterval = 1; 960 sc->sc_caltries = 0; 961 962 /* 963 * Setup the hardware after reset: the key cache 964 * is filled as needed and the receive engine is 965 * set going. Frame transmit is handled entirely 966 * in the frame output path; there's nothing to do 967 * here except setup the interrupt mask. 968 */ 969 if (ath_startrecv(sc) != 0) { 970 if_printf(ifp, "unable to start recv logic\n"); 971 goto done; 972 } 973 974 /* 975 * Enable interrupts. 976 */ 977 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 978 | HAL_INT_RXEOL | HAL_INT_RXORN 979 | HAL_INT_FATAL | HAL_INT_GLOBAL; 980 /* 981 * Enable MIB interrupts when there are hardware phy counters. 982 * Note we only do this (at the moment) for station mode. 983 */ 984 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 985 sc->sc_imask |= HAL_INT_MIB; 986 ath_hal_intrset(ah, sc->sc_imask); 987 988 ifp->if_drv_flags |= IFF_DRV_RUNNING; 989 ic->ic_state = IEEE80211_S_INIT; 990 991 /* 992 * The hardware should be ready to go now so it's safe 993 * to kick the 802.11 state machine as it's likely to 994 * immediately call back to us to send mgmt frames. 995 */ 996 ath_chan_change(sc, ic->ic_curchan); 997#ifdef ATH_TX99_DIAG 998 if (sc->sc_tx99 != NULL) 999 sc->sc_tx99->start(sc->sc_tx99); 1000 else 1001#endif 1002 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1003 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1004 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1005 } else 1006 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1007done: 1008 ATH_UNLOCK(sc); 1009} 1010 1011static void 1012ath_stop_locked(struct ifnet *ifp) 1013{ 1014 struct ath_softc *sc = ifp->if_softc; 1015 struct ieee80211com *ic = &sc->sc_ic; 1016 struct ath_hal *ah = sc->sc_ah; 1017 1018 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1019 __func__, sc->sc_invalid, ifp->if_flags); 1020 1021 ATH_LOCK_ASSERT(sc); 1022 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1023 /* 1024 * Shutdown the hardware and driver: 1025 * reset 802.11 state machine 1026 * turn off timers 1027 * disable interrupts 1028 * turn off the radio 1029 * clear transmit machinery 1030 * clear receive machinery 1031 * drain and release tx queues 1032 * reclaim beacon resources 1033 * power down hardware 1034 * 1035 * Note that some of this work is not possible if the 1036 * hardware is gone (invalid). 1037 */ 1038#ifdef ATH_TX99_DIAG 1039 if (sc->sc_tx99 != NULL) 1040 sc->sc_tx99->stop(sc->sc_tx99); 1041#endif 1042 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1043 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1044 ifp->if_timer = 0; 1045 if (!sc->sc_invalid) { 1046 if (sc->sc_softled) { 1047 callout_stop(&sc->sc_ledtimer); 1048 ath_hal_gpioset(ah, sc->sc_ledpin, 1049 !sc->sc_ledon); 1050 sc->sc_blinking = 0; 1051 } 1052 ath_hal_intrset(ah, 0); 1053 } 1054 ath_draintxq(sc); 1055 if (!sc->sc_invalid) { 1056 ath_stoprecv(sc); 1057 ath_hal_phydisable(ah); 1058 } else 1059 sc->sc_rxlink = NULL; 1060 IFQ_DRV_PURGE(&ifp->if_snd); 1061 ath_beacon_free(sc); 1062 } 1063} 1064 1065static void 1066ath_stop(struct ifnet *ifp) 1067{ 1068 struct ath_softc *sc = ifp->if_softc; 1069 1070 ATH_LOCK(sc); 1071 ath_stop_locked(ifp); 1072 if (!sc->sc_invalid) { 1073 /* 1074 * Set the chip in full sleep mode. Note that we are 1075 * careful to do this only when bringing the interface 1076 * completely to a stop. When the chip is in this state 1077 * it must be carefully woken up or references to 1078 * registers in the PCI clock domain may freeze the bus 1079 * (and system). This varies by chip and is mostly an 1080 * issue with newer parts that go to sleep more quickly. 1081 */ 1082 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1083 } 1084 ATH_UNLOCK(sc); 1085} 1086 1087/* 1088 * Reset the hardware w/o losing operational state. This is 1089 * basically a more efficient way of doing ath_stop, ath_init, 1090 * followed by state transitions to the current 802.11 1091 * operational state. Used to recover from various errors and 1092 * to reset or reload hardware state. 1093 */ 1094static int 1095ath_reset(struct ifnet *ifp) 1096{ 1097 struct ath_softc *sc = ifp->if_softc; 1098 struct ieee80211com *ic = &sc->sc_ic; 1099 struct ath_hal *ah = sc->sc_ah; 1100 HAL_STATUS status; 1101 1102 /* 1103 * Convert to a HAL channel description with the flags 1104 * constrained to reflect the current operating mode. 1105 */ 1106 ath_mapchan(ic, &sc->sc_curchan, ic->ic_curchan); 1107 1108 ath_hal_intrset(ah, 0); /* disable interrupts */ 1109 ath_draintxq(sc); /* stop xmit side */ 1110 ath_stoprecv(sc); /* stop recv side */ 1111 /* NB: indicate channel change so we do a full reset */ 1112 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1113 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1114 __func__, status); 1115 ath_update_txpow(sc); /* update tx power state */ 1116 sc->sc_diversity = ath_hal_getdiversity(ah); 1117 sc->sc_calinterval = 1; 1118 sc->sc_caltries = 0; 1119 /* 1120 * We may be doing a reset in response to an ioctl 1121 * that changes the channel so update any state that 1122 * might change as a result. 1123 */ 1124 ath_chan_change(sc, ic->ic_curchan); 1125 if (ath_startrecv(sc) != 0) /* restart recv */ 1126 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1127 if (ic->ic_state == IEEE80211_S_RUN) 1128 ath_beacon_config(sc); /* restart beacons */ 1129 ath_hal_intrset(ah, sc->sc_imask); 1130 1131 ath_start(ifp); /* restart xmit */ 1132 return 0; 1133} 1134 1135static void 1136ath_start(struct ifnet *ifp) 1137{ 1138 struct ath_softc *sc = ifp->if_softc; 1139 struct ath_hal *ah = sc->sc_ah; 1140 struct ieee80211com *ic = &sc->sc_ic; 1141 struct ieee80211_node *ni; 1142 struct ath_buf *bf; 1143 struct mbuf *m; 1144 struct ieee80211_frame *wh; 1145 struct ether_header *eh; 1146 1147 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1148 return; 1149 for (;;) { 1150 /* 1151 * Grab a TX buffer and associated resources. 1152 */ 1153 ATH_TXBUF_LOCK(sc); 1154 bf = STAILQ_FIRST(&sc->sc_txbuf); 1155 if (bf != NULL) 1156 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1157 ATH_TXBUF_UNLOCK(sc); 1158 if (bf == NULL) { 1159 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1160 __func__); 1161 sc->sc_stats.ast_tx_qstop++; 1162 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1163 break; 1164 } 1165 /* 1166 * Poll the management queue for frames; they 1167 * have priority over normal data frames. 1168 */ 1169 IF_DEQUEUE(&ic->ic_mgtq, m); 1170 if (m == NULL) { 1171 /* 1172 * No data frames go out unless we're associated. 1173 */ 1174 if (ic->ic_state != IEEE80211_S_RUN) { 1175 DPRINTF(sc, ATH_DEBUG_XMIT, 1176 "%s: discard data packet, state %s\n", 1177 __func__, 1178 ieee80211_state_name[ic->ic_state]); 1179 sc->sc_stats.ast_tx_discard++; 1180 ATH_TXBUF_LOCK(sc); 1181 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1182 ATH_TXBUF_UNLOCK(sc); 1183 break; 1184 } 1185 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1186 if (m == NULL) { 1187 ATH_TXBUF_LOCK(sc); 1188 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1189 ATH_TXBUF_UNLOCK(sc); 1190 break; 1191 } 1192 /* 1193 * Find the node for the destination so we can do 1194 * things like power save and fast frames aggregation. 1195 */ 1196 if (m->m_len < sizeof(struct ether_header) && 1197 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1198 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1199 ni = NULL; 1200 goto bad; 1201 } 1202 eh = mtod(m, struct ether_header *); 1203 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1204 if (ni == NULL) { 1205 /* NB: ieee80211_find_txnode does stat+msg */ 1206 m_freem(m); 1207 goto bad; 1208 } 1209 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1210 (m->m_flags & M_PWR_SAV) == 0) { 1211 /* 1212 * Station in power save mode; pass the frame 1213 * to the 802.11 layer and continue. We'll get 1214 * the frame back when the time is right. 1215 */ 1216 ieee80211_pwrsave(ic, ni, m); 1217 goto reclaim; 1218 } 1219 /* calculate priority so we can find the tx queue */ 1220 if (ieee80211_classify(ic, m, ni)) { 1221 DPRINTF(sc, ATH_DEBUG_XMIT, 1222 "%s: discard, classification failure\n", 1223 __func__); 1224 m_freem(m); 1225 goto bad; 1226 } 1227 ifp->if_opackets++; 1228 BPF_MTAP(ifp, m); 1229 /* 1230 * Encapsulate the packet in prep for transmission. 1231 */ 1232 m = ieee80211_encap(ic, m, ni); 1233 if (m == NULL) { 1234 DPRINTF(sc, ATH_DEBUG_XMIT, 1235 "%s: encapsulation failure\n", 1236 __func__); 1237 sc->sc_stats.ast_tx_encap++; 1238 goto bad; 1239 } 1240 } else { 1241 /* 1242 * Hack! The referenced node pointer is in the 1243 * rcvif field of the packet header. This is 1244 * placed there by ieee80211_mgmt_output because 1245 * we need to hold the reference with the frame 1246 * and there's no other way (other than packet 1247 * tags which we consider too expensive to use) 1248 * to pass it along. 1249 */ 1250 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1251 m->m_pkthdr.rcvif = NULL; 1252 1253 wh = mtod(m, struct ieee80211_frame *); 1254 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1255 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1256 /* fill time stamp */ 1257 u_int64_t tsf; 1258 u_int32_t *tstamp; 1259 1260 tsf = ath_hal_gettsf64(ah); 1261 /* XXX: adjust 100us delay to xmit */ 1262 tsf += 100; 1263 tstamp = (u_int32_t *)&wh[1]; 1264 tstamp[0] = htole32(tsf & 0xffffffff); 1265 tstamp[1] = htole32(tsf >> 32); 1266 } 1267 sc->sc_stats.ast_tx_mgmt++; 1268 } 1269 1270 if (ath_tx_start(sc, ni, bf, m)) { 1271 bad: 1272 ifp->if_oerrors++; 1273 reclaim: 1274 ATH_TXBUF_LOCK(sc); 1275 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1276 ATH_TXBUF_UNLOCK(sc); 1277 if (ni != NULL) 1278 ieee80211_free_node(ni); 1279 continue; 1280 } 1281 1282 sc->sc_tx_timer = 5; 1283 ifp->if_timer = 1; 1284 } 1285} 1286 1287static int 1288ath_media_change(struct ifnet *ifp) 1289{ 1290#define IS_UP(ifp) \ 1291 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1292 int error; 1293 1294 error = ieee80211_media_change(ifp); 1295 if (error == ENETRESET) { 1296 struct ath_softc *sc = ifp->if_softc; 1297 struct ieee80211com *ic = &sc->sc_ic; 1298 1299 if (ic->ic_opmode == IEEE80211_M_AHDEMO) { 1300 /* 1301 * Adhoc demo mode is just ibss mode w/o beacons 1302 * (mostly). The hal knows nothing about it; 1303 * tell it we're operating in ibss mode. 1304 */ 1305 sc->sc_opmode = HAL_M_IBSS; 1306 } else 1307 sc->sc_opmode = ic->ic_opmode; 1308 if (IS_UP(ifp)) 1309 ath_init(ifp->if_softc); /* XXX lose error */ 1310 error = 0; 1311 } 1312 return error; 1313#undef IS_UP 1314} 1315 1316#ifdef ATH_DEBUG 1317static void 1318ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1319 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1320{ 1321 static const char *ciphers[] = { 1322 "WEP", 1323 "AES-OCB", 1324 "AES-CCM", 1325 "CKIP", 1326 "TKIP", 1327 "CLR", 1328 }; 1329 int i, n; 1330 1331 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1332 for (i = 0, n = hk->kv_len; i < n; i++) 1333 printf("%02x", hk->kv_val[i]); 1334 printf(" mac %s", ether_sprintf(mac)); 1335 if (hk->kv_type == HAL_CIPHER_TKIP) { 1336 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1337 for (i = 0; i < sizeof(hk->kv_mic); i++) 1338 printf("%02x", hk->kv_mic[i]); 1339#if HAL_ABI_VERSION > 0x06052200 1340 if (!sc->sc_splitmic) { 1341 printf(" txmic "); 1342 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1343 printf("%02x", hk->kv_txmic[i]); 1344 } 1345#endif 1346 } 1347 printf("\n"); 1348} 1349#endif 1350 1351/* 1352 * Set a TKIP key into the hardware. This handles the 1353 * potential distribution of key state to multiple key 1354 * cache slots for TKIP. 1355 */ 1356static int 1357ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1358 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1359{ 1360#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1361 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1362 struct ath_hal *ah = sc->sc_ah; 1363 1364 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1365 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1366 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1367 if (sc->sc_splitmic) { 1368 /* 1369 * TX key goes at first index, RX key at the rx index. 1370 * The hal handles the MIC keys at index+64. 1371 */ 1372 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1373 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1374 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1375 return 0; 1376 1377 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1378 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1379 /* XXX delete tx key on failure? */ 1380 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1381 } else { 1382 /* 1383 * Room for both TX+RX MIC keys in one key cache 1384 * slot, just set key at the first index; the hal 1385 * will handle the reset. 1386 */ 1387 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1388#if HAL_ABI_VERSION > 0x06052200 1389 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1390#endif 1391 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1392 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1393 } 1394 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1395 /* 1396 * TX/RX key goes at first index. 1397 * The hal handles the MIC keys are index+64. 1398 */ 1399 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1400 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1401 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1402 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1403 } 1404 return 0; 1405#undef IEEE80211_KEY_XR 1406} 1407 1408/* 1409 * Set a net80211 key into the hardware. This handles the 1410 * potential distribution of key state to multiple key 1411 * cache slots for TKIP with hardware MIC support. 1412 */ 1413static int 1414ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1415 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1416 struct ieee80211_node *bss) 1417{ 1418#define N(a) (sizeof(a)/sizeof(a[0])) 1419 static const u_int8_t ciphermap[] = { 1420 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1421 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1422 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1423 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1424 (u_int8_t) -1, /* 4 is not allocated */ 1425 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1426 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1427 }; 1428 struct ath_hal *ah = sc->sc_ah; 1429 const struct ieee80211_cipher *cip = k->wk_cipher; 1430 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1431 const u_int8_t *mac; 1432 HAL_KEYVAL hk; 1433 1434 memset(&hk, 0, sizeof(hk)); 1435 /* 1436 * Software crypto uses a "clear key" so non-crypto 1437 * state kept in the key cache are maintained and 1438 * so that rx frames have an entry to match. 1439 */ 1440 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1441 KASSERT(cip->ic_cipher < N(ciphermap), 1442 ("invalid cipher type %u", cip->ic_cipher)); 1443 hk.kv_type = ciphermap[cip->ic_cipher]; 1444 hk.kv_len = k->wk_keylen; 1445 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1446 } else 1447 hk.kv_type = HAL_CIPHER_CLR; 1448 1449 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1450 /* 1451 * Group keys on hardware that supports multicast frame 1452 * key search use a mac that is the sender's address with 1453 * the high bit set instead of the app-specified address. 1454 */ 1455 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1456 gmac[0] |= 0x80; 1457 mac = gmac; 1458 } else 1459 mac = mac0; 1460 1461 if (hk.kv_type == HAL_CIPHER_TKIP && 1462 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1463 return ath_keyset_tkip(sc, k, &hk, mac); 1464 } else { 1465 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1466 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1467 } 1468#undef N 1469} 1470 1471/* 1472 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1473 * each key, one for decrypt/encrypt and the other for the MIC. 1474 */ 1475static u_int16_t 1476key_alloc_2pair(struct ath_softc *sc, 1477 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1478{ 1479#define N(a) (sizeof(a)/sizeof(a[0])) 1480 u_int i, keyix; 1481 1482 KASSERT(sc->sc_splitmic, ("key cache !split")); 1483 /* XXX could optimize */ 1484 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1485 u_int8_t b = sc->sc_keymap[i]; 1486 if (b != 0xff) { 1487 /* 1488 * One or more slots in this byte are free. 1489 */ 1490 keyix = i*NBBY; 1491 while (b & 1) { 1492 again: 1493 keyix++; 1494 b >>= 1; 1495 } 1496 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1497 if (isset(sc->sc_keymap, keyix+32) || 1498 isset(sc->sc_keymap, keyix+64) || 1499 isset(sc->sc_keymap, keyix+32+64)) { 1500 /* full pair unavailable */ 1501 /* XXX statistic */ 1502 if (keyix == (i+1)*NBBY) { 1503 /* no slots were appropriate, advance */ 1504 continue; 1505 } 1506 goto again; 1507 } 1508 setbit(sc->sc_keymap, keyix); 1509 setbit(sc->sc_keymap, keyix+64); 1510 setbit(sc->sc_keymap, keyix+32); 1511 setbit(sc->sc_keymap, keyix+32+64); 1512 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1513 "%s: key pair %u,%u %u,%u\n", 1514 __func__, keyix, keyix+64, 1515 keyix+32, keyix+32+64); 1516 *txkeyix = keyix; 1517 *rxkeyix = keyix+32; 1518 return 1; 1519 } 1520 } 1521 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1522 return 0; 1523#undef N 1524} 1525 1526/* 1527 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1528 * each key, one for decrypt/encrypt and the other for the MIC. 1529 */ 1530static u_int16_t 1531key_alloc_pair(struct ath_softc *sc, 1532 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1533{ 1534#define N(a) (sizeof(a)/sizeof(a[0])) 1535 u_int i, keyix; 1536 1537 KASSERT(!sc->sc_splitmic, ("key cache split")); 1538 /* XXX could optimize */ 1539 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1540 u_int8_t b = sc->sc_keymap[i]; 1541 if (b != 0xff) { 1542 /* 1543 * One or more slots in this byte are free. 1544 */ 1545 keyix = i*NBBY; 1546 while (b & 1) { 1547 again: 1548 keyix++; 1549 b >>= 1; 1550 } 1551 if (isset(sc->sc_keymap, keyix+64)) { 1552 /* full pair unavailable */ 1553 /* XXX statistic */ 1554 if (keyix == (i+1)*NBBY) { 1555 /* no slots were appropriate, advance */ 1556 continue; 1557 } 1558 goto again; 1559 } 1560 setbit(sc->sc_keymap, keyix); 1561 setbit(sc->sc_keymap, keyix+64); 1562 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1563 "%s: key pair %u,%u\n", 1564 __func__, keyix, keyix+64); 1565 *txkeyix = *rxkeyix = keyix; 1566 return 1; 1567 } 1568 } 1569 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1570 return 0; 1571#undef N 1572} 1573 1574/* 1575 * Allocate a single key cache slot. 1576 */ 1577static int 1578key_alloc_single(struct ath_softc *sc, 1579 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1580{ 1581#define N(a) (sizeof(a)/sizeof(a[0])) 1582 u_int i, keyix; 1583 1584 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1585 for (i = 0; i < N(sc->sc_keymap); i++) { 1586 u_int8_t b = sc->sc_keymap[i]; 1587 if (b != 0xff) { 1588 /* 1589 * One or more slots are free. 1590 */ 1591 keyix = i*NBBY; 1592 while (b & 1) 1593 keyix++, b >>= 1; 1594 setbit(sc->sc_keymap, keyix); 1595 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1596 __func__, keyix); 1597 *txkeyix = *rxkeyix = keyix; 1598 return 1; 1599 } 1600 } 1601 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1602 return 0; 1603#undef N 1604} 1605 1606/* 1607 * Allocate one or more key cache slots for a uniacst key. The 1608 * key itself is needed only to identify the cipher. For hardware 1609 * TKIP with split cipher+MIC keys we allocate two key cache slot 1610 * pairs so that we can setup separate TX and RX MIC keys. Note 1611 * that the MIC key for a TKIP key at slot i is assumed by the 1612 * hardware to be at slot i+64. This limits TKIP keys to the first 1613 * 64 entries. 1614 */ 1615static int 1616ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1617 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1618{ 1619 struct ath_softc *sc = ic->ic_ifp->if_softc; 1620 1621 /* 1622 * Group key allocation must be handled specially for 1623 * parts that do not support multicast key cache search 1624 * functionality. For those parts the key id must match 1625 * the h/w key index so lookups find the right key. On 1626 * parts w/ the key search facility we install the sender's 1627 * mac address (with the high bit set) and let the hardware 1628 * find the key w/o using the key id. This is preferred as 1629 * it permits us to support multiple users for adhoc and/or 1630 * multi-station operation. 1631 */ 1632 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1633 if (!(&ic->ic_nw_keys[0] <= k && 1634 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1635 /* should not happen */ 1636 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1637 "%s: bogus group key\n", __func__); 1638 return 0; 1639 } 1640 /* 1641 * XXX we pre-allocate the global keys so 1642 * have no way to check if they've already been allocated. 1643 */ 1644 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1645 return 1; 1646 } 1647 1648 /* 1649 * We allocate two pair for TKIP when using the h/w to do 1650 * the MIC. For everything else, including software crypto, 1651 * we allocate a single entry. Note that s/w crypto requires 1652 * a pass-through slot on the 5211 and 5212. The 5210 does 1653 * not support pass-through cache entries and we map all 1654 * those requests to slot 0. 1655 */ 1656 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1657 return key_alloc_single(sc, keyix, rxkeyix); 1658 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1659 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1660 if (sc->sc_splitmic) 1661 return key_alloc_2pair(sc, keyix, rxkeyix); 1662 else 1663 return key_alloc_pair(sc, keyix, rxkeyix); 1664 } else { 1665 return key_alloc_single(sc, keyix, rxkeyix); 1666 } 1667} 1668 1669/* 1670 * Delete an entry in the key cache allocated by ath_key_alloc. 1671 */ 1672static int 1673ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1674{ 1675 struct ath_softc *sc = ic->ic_ifp->if_softc; 1676 struct ath_hal *ah = sc->sc_ah; 1677 const struct ieee80211_cipher *cip = k->wk_cipher; 1678 u_int keyix = k->wk_keyix; 1679 1680 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1681 1682 ath_hal_keyreset(ah, keyix); 1683 /* 1684 * Handle split tx/rx keying required for TKIP with h/w MIC. 1685 */ 1686 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1687 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1688 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1689 if (keyix >= IEEE80211_WEP_NKID) { 1690 /* 1691 * Don't touch keymap entries for global keys so 1692 * they are never considered for dynamic allocation. 1693 */ 1694 clrbit(sc->sc_keymap, keyix); 1695 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1696 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1697 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1698 if (sc->sc_splitmic) { 1699 /* +32 for RX key, +32+64 for RX key MIC */ 1700 clrbit(sc->sc_keymap, keyix+32); 1701 clrbit(sc->sc_keymap, keyix+32+64); 1702 } 1703 } 1704 } 1705 return 1; 1706} 1707 1708/* 1709 * Set the key cache contents for the specified key. Key cache 1710 * slot(s) must already have been allocated by ath_key_alloc. 1711 */ 1712static int 1713ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1714 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1715{ 1716 struct ath_softc *sc = ic->ic_ifp->if_softc; 1717 1718 return ath_keyset(sc, k, mac, ic->ic_bss); 1719} 1720 1721/* 1722 * Block/unblock tx+rx processing while a key change is done. 1723 * We assume the caller serializes key management operations 1724 * so we only need to worry about synchronization with other 1725 * uses that originate in the driver. 1726 */ 1727static void 1728ath_key_update_begin(struct ieee80211com *ic) 1729{ 1730 struct ifnet *ifp = ic->ic_ifp; 1731 struct ath_softc *sc = ifp->if_softc; 1732 1733 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1734#if 0 1735 tasklet_disable(&sc->sc_rxtq); 1736#endif 1737 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1738} 1739 1740static void 1741ath_key_update_end(struct ieee80211com *ic) 1742{ 1743 struct ifnet *ifp = ic->ic_ifp; 1744 struct ath_softc *sc = ifp->if_softc; 1745 1746 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1747 IF_UNLOCK(&ifp->if_snd); 1748#if 0 1749 tasklet_enable(&sc->sc_rxtq); 1750#endif 1751} 1752 1753/* 1754 * Calculate the receive filter according to the 1755 * operating mode and state: 1756 * 1757 * o always accept unicast, broadcast, and multicast traffic 1758 * o maintain current state of phy error reception (the hal 1759 * may enable phy error frames for noise immunity work) 1760 * o probe request frames are accepted only when operating in 1761 * hostap, adhoc, or monitor modes 1762 * o enable promiscuous mode according to the interface state 1763 * o accept beacons: 1764 * - when operating in adhoc mode so the 802.11 layer creates 1765 * node table entries for peers, 1766 * - when operating in station mode for collecting rssi data when 1767 * the station is otherwise quiet, or 1768 * - when scanning 1769 * o accept control frames: 1770 * - when in monitor mode 1771 */ 1772static u_int32_t 1773ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1774{ 1775#define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR) 1776 struct ieee80211com *ic = &sc->sc_ic; 1777 struct ath_hal *ah = sc->sc_ah; 1778 struct ifnet *ifp = sc->sc_ifp; 1779 u_int32_t rfilt; 1780 1781 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE) 1782 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1783 if (ic->ic_opmode != IEEE80211_M_STA) 1784 rfilt |= HAL_RX_FILTER_PROBEREQ; 1785 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1786 (ifp->if_flags & IFF_PROMISC)) 1787 rfilt |= HAL_RX_FILTER_PROM; 1788 if (ic->ic_opmode == IEEE80211_M_STA || 1789 ic->ic_opmode == IEEE80211_M_IBSS || 1790 state == IEEE80211_S_SCAN) 1791 rfilt |= HAL_RX_FILTER_BEACON; 1792 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1793 rfilt |= HAL_RX_FILTER_CONTROL; 1794 return rfilt; 1795#undef RX_FILTER_PRESERVE 1796} 1797 1798static void 1799ath_mode_init(struct ath_softc *sc) 1800{ 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 struct ath_hal *ah = sc->sc_ah; 1803 struct ifnet *ifp = sc->sc_ifp; 1804 u_int32_t rfilt, mfilt[2], val; 1805 u_int8_t pos; 1806 struct ifmultiaddr *ifma; 1807 1808 /* configure rx filter */ 1809 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1810 ath_hal_setrxfilter(ah, rfilt); 1811 1812 /* configure operational mode */ 1813 ath_hal_setopmode(ah); 1814 1815 /* 1816 * Handle any link-level address change. Note that we only 1817 * need to force ic_myaddr; any other addresses are handled 1818 * as a byproduct of the ifnet code marking the interface 1819 * down then up. 1820 * 1821 * XXX should get from lladdr instead of arpcom but that's more work 1822 */ 1823 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1824 ath_hal_setmac(ah, ic->ic_myaddr); 1825 1826 /* calculate and install multicast filter */ 1827 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1828 mfilt[0] = mfilt[1] = 0; 1829 IF_ADDR_LOCK(ifp); 1830 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1831 caddr_t dl; 1832 1833 /* calculate XOR of eight 6bit values */ 1834 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1835 val = LE_READ_4(dl + 0); 1836 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1837 val = LE_READ_4(dl + 3); 1838 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1839 pos &= 0x3f; 1840 mfilt[pos / 32] |= (1 << (pos % 32)); 1841 } 1842 IF_ADDR_UNLOCK(ifp); 1843 } else { 1844 mfilt[0] = mfilt[1] = ~0; 1845 } 1846 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1847 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1848 __func__, rfilt, mfilt[0], mfilt[1]); 1849} 1850 1851/* 1852 * Set the slot time based on the current setting. 1853 */ 1854static void 1855ath_setslottime(struct ath_softc *sc) 1856{ 1857 struct ieee80211com *ic = &sc->sc_ic; 1858 struct ath_hal *ah = sc->sc_ah; 1859 u_int usec; 1860 1861 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 1862 usec = 13; 1863 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 1864 usec = 21; 1865 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 1866 /* honor short/long slot time only in 11g */ 1867 /* XXX shouldn't honor on pure g or turbo g channel */ 1868 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1869 usec = HAL_SLOT_TIME_9; 1870 else 1871 usec = HAL_SLOT_TIME_20; 1872 } else 1873 usec = HAL_SLOT_TIME_9; 1874 1875 DPRINTF(sc, ATH_DEBUG_RESET, 1876 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 1877 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 1878 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 1879 1880 ath_hal_setslottime(ah, usec); 1881 sc->sc_updateslot = OK; 1882} 1883 1884/* 1885 * Callback from the 802.11 layer to update the 1886 * slot time based on the current setting. 1887 */ 1888static void 1889ath_updateslot(struct ifnet *ifp) 1890{ 1891 struct ath_softc *sc = ifp->if_softc; 1892 struct ieee80211com *ic = &sc->sc_ic; 1893 1894 /* 1895 * When not coordinating the BSS, change the hardware 1896 * immediately. For other operation we defer the change 1897 * until beacon updates have propagated to the stations. 1898 */ 1899 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1900 sc->sc_updateslot = UPDATE; 1901 else 1902 ath_setslottime(sc); 1903} 1904 1905/* 1906 * Setup a h/w transmit queue for beacons. 1907 */ 1908static int 1909ath_beaconq_setup(struct ath_hal *ah) 1910{ 1911 HAL_TXQ_INFO qi; 1912 1913 memset(&qi, 0, sizeof(qi)); 1914 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1915 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1916 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1917 /* NB: for dynamic turbo, don't enable any other interrupts */ 1918 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1919 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1920} 1921 1922/* 1923 * Setup the transmit queue parameters for the beacon queue. 1924 */ 1925static int 1926ath_beaconq_config(struct ath_softc *sc) 1927{ 1928#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 struct ath_hal *ah = sc->sc_ah; 1931 HAL_TXQ_INFO qi; 1932 1933 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1934 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1935 /* 1936 * Always burst out beacon and CAB traffic. 1937 */ 1938 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1939 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1940 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1941 } else { 1942 struct wmeParams *wmep = 1943 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1944 /* 1945 * Adhoc mode; important thing is to use 2x cwmin. 1946 */ 1947 qi.tqi_aifs = wmep->wmep_aifsn; 1948 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1949 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1950 } 1951 1952 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1953 device_printf(sc->sc_dev, "unable to update parameters for " 1954 "beacon hardware queue!\n"); 1955 return 0; 1956 } else { 1957 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1958 return 1; 1959 } 1960#undef ATH_EXPONENT_TO_VALUE 1961} 1962 1963/* 1964 * Allocate and setup an initial beacon frame. 1965 */ 1966static int 1967ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1968{ 1969 struct ieee80211com *ic = ni->ni_ic; 1970 struct ath_buf *bf; 1971 struct mbuf *m; 1972 int error; 1973 1974 bf = STAILQ_FIRST(&sc->sc_bbuf); 1975 if (bf == NULL) { 1976 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1977 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1978 return ENOMEM; /* XXX */ 1979 } 1980 /* 1981 * NB: the beacon data buffer must be 32-bit aligned; 1982 * we assume the mbuf routines will return us something 1983 * with this alignment (perhaps should assert). 1984 */ 1985 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1986 if (m == NULL) { 1987 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1988 __func__); 1989 sc->sc_stats.ast_be_nombuf++; 1990 return ENOMEM; 1991 } 1992 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1993 bf->bf_segs, &bf->bf_nseg, 1994 BUS_DMA_NOWAIT); 1995 if (error == 0) { 1996 bf->bf_m = m; 1997 bf->bf_node = ieee80211_ref_node(ni); 1998 } else { 1999 m_freem(m); 2000 } 2001 return error; 2002} 2003 2004/* 2005 * Setup the beacon frame for transmit. 2006 */ 2007static void 2008ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2009{ 2010#define USE_SHPREAMBLE(_ic) \ 2011 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2012 == IEEE80211_F_SHPREAMBLE) 2013 struct ieee80211_node *ni = bf->bf_node; 2014 struct ieee80211com *ic = ni->ni_ic; 2015 struct mbuf *m = bf->bf_m; 2016 struct ath_hal *ah = sc->sc_ah; 2017 struct ath_desc *ds; 2018 int flags, antenna; 2019 const HAL_RATE_TABLE *rt; 2020 u_int8_t rix, rate; 2021 2022 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2023 __func__, m, m->m_len); 2024 2025 /* setup descriptors */ 2026 ds = bf->bf_desc; 2027 2028 flags = HAL_TXDESC_NOACK; 2029 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2030 ds->ds_link = bf->bf_daddr; /* self-linked */ 2031 flags |= HAL_TXDESC_VEOL; 2032 /* 2033 * Let hardware handle antenna switching. 2034 */ 2035 antenna = sc->sc_txantenna; 2036 } else { 2037 ds->ds_link = 0; 2038 /* 2039 * Switch antenna every 4 beacons. 2040 * XXX assumes two antenna 2041 */ 2042 antenna = sc->sc_txantenna != 0 ? sc->sc_txantenna 2043 : (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2044 } 2045 2046 KASSERT(bf->bf_nseg == 1, 2047 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2048 ds->ds_data = bf->bf_segs[0].ds_addr; 2049 /* 2050 * Calculate rate code. 2051 * XXX everything at min xmit rate 2052 */ 2053 rix = sc->sc_minrateix; 2054 rt = sc->sc_currates; 2055 rate = rt->info[rix].rateCode; 2056 if (USE_SHPREAMBLE(ic)) 2057 rate |= rt->info[rix].shortPreamble; 2058 ath_hal_setuptxdesc(ah, ds 2059 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2060 , sizeof(struct ieee80211_frame)/* header length */ 2061 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2062 , ni->ni_txpower /* txpower XXX */ 2063 , rate, 1 /* series 0 rate/tries */ 2064 , HAL_TXKEYIX_INVALID /* no encryption */ 2065 , antenna /* antenna mode */ 2066 , flags /* no ack, veol for beacons */ 2067 , 0 /* rts/cts rate */ 2068 , 0 /* rts/cts duration */ 2069 ); 2070 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2071 ath_hal_filltxdesc(ah, ds 2072 , roundup(m->m_len, 4) /* buffer length */ 2073 , AH_TRUE /* first segment */ 2074 , AH_TRUE /* last segment */ 2075 , ds /* first descriptor */ 2076 ); 2077#undef USE_SHPREAMBLE 2078} 2079 2080/* 2081 * Append the contents of src to dst; both queues 2082 * are assumed to be locked. 2083 */ 2084static void 2085ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2086{ 2087 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2088 dst->axq_link = src->axq_link; 2089 src->axq_link = NULL; 2090 dst->axq_depth += src->axq_depth; 2091 src->axq_depth = 0; 2092} 2093 2094/* 2095 * Transmit a beacon frame at SWBA. Dynamic updates to the 2096 * frame contents are done as needed and the slot time is 2097 * also adjusted based on current state. 2098 */ 2099static void 2100ath_beacon_proc(void *arg, int pending) 2101{ 2102 struct ath_softc *sc = arg; 2103 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2104 struct ieee80211_node *ni = bf->bf_node; 2105 struct ieee80211com *ic = ni->ni_ic; 2106 struct ath_hal *ah = sc->sc_ah; 2107 struct ath_txq *cabq = sc->sc_cabq; 2108 struct mbuf *m; 2109 int ncabq, nmcastq, error, otherant; 2110 2111 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2112 __func__, pending); 2113 2114 if (ic->ic_opmode == IEEE80211_M_STA || 2115 ic->ic_opmode == IEEE80211_M_MONITOR || 2116 bf == NULL || bf->bf_m == NULL) { 2117 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2118 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2119 return; 2120 } 2121 /* 2122 * Check if the previous beacon has gone out. If 2123 * not don't try to post another, skip this period 2124 * and wait for the next. Missed beacons indicate 2125 * a problem and should not occur. If we miss too 2126 * many consecutive beacons reset the device. 2127 */ 2128 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2129 sc->sc_bmisscount++; 2130 DPRINTF(sc, ATH_DEBUG_BEACON, 2131 "%s: missed %u consecutive beacons\n", 2132 __func__, sc->sc_bmisscount); 2133 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2134 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2135 return; 2136 } 2137 if (sc->sc_bmisscount != 0) { 2138 DPRINTF(sc, ATH_DEBUG_BEACON, 2139 "%s: resume beacon xmit after %u misses\n", 2140 __func__, sc->sc_bmisscount); 2141 sc->sc_bmisscount = 0; 2142 } 2143 2144 /* 2145 * Update dynamic beacon contents. If this returns 2146 * non-zero then we need to remap the memory because 2147 * the beacon frame changed size (probably because 2148 * of the TIM bitmap). 2149 */ 2150 m = bf->bf_m; 2151 nmcastq = sc->sc_mcastq.axq_depth; 2152 ncabq = ath_hal_numtxpending(ah, cabq->axq_qnum); 2153 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq+nmcastq)) { 2154 /* XXX too conservative? */ 2155 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2156 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2157 bf->bf_segs, &bf->bf_nseg, 2158 BUS_DMA_NOWAIT); 2159 if (error != 0) { 2160 if_printf(ic->ic_ifp, 2161 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2162 __func__, error); 2163 return; 2164 } 2165 } 2166 if (ncabq && (sc->sc_boff.bo_tim[4] & 1)) { 2167 /* 2168 * CABQ traffic from the previous DTIM is still pending. 2169 * This is ok for now but when there are multiple vap's 2170 * and we are using staggered beacons we'll want to drain 2171 * the cabq before loading frames for the different vap. 2172 */ 2173 DPRINTF(sc, ATH_DEBUG_BEACON, 2174 "%s: cabq did not drain, mcastq %u cabq %u/%u\n", 2175 __func__, nmcastq, ncabq, cabq->axq_depth); 2176 sc->sc_stats.ast_cabq_busy++; 2177 } 2178 2179 /* 2180 * Handle slot time change when a non-ERP station joins/leaves 2181 * an 11g network. The 802.11 layer notifies us via callback, 2182 * we mark updateslot, then wait one beacon before effecting 2183 * the change. This gives associated stations at least one 2184 * beacon interval to note the state change. 2185 */ 2186 /* XXX locking */ 2187 if (sc->sc_updateslot == UPDATE) 2188 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2189 else if (sc->sc_updateslot == COMMIT) 2190 ath_setslottime(sc); /* commit change to h/w */ 2191 2192 /* 2193 * Check recent per-antenna transmit statistics and flip 2194 * the default antenna if noticeably more frames went out 2195 * on the non-default antenna. 2196 * XXX assumes 2 anntenae 2197 */ 2198 otherant = sc->sc_defant & 1 ? 2 : 1; 2199 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2200 ath_setdefantenna(sc, otherant); 2201 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2202 2203 /* 2204 * Construct tx descriptor. 2205 */ 2206 ath_beacon_setup(sc, bf); 2207 2208 /* 2209 * Stop any current dma and put the new frame on the queue. 2210 * This should never fail since we check above that no frames 2211 * are still pending on the queue. 2212 */ 2213 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2214 DPRINTF(sc, ATH_DEBUG_ANY, 2215 "%s: beacon queue %u did not stop?\n", 2216 __func__, sc->sc_bhalq); 2217 } 2218 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2219 2220 /* 2221 * Enable the CAB queue before the beacon queue to 2222 * insure cab frames are triggered by this beacon. 2223 */ 2224 if (sc->sc_boff.bo_tim_len && (sc->sc_boff.bo_tim[4] & 1)) { 2225 /* NB: only at DTIM */ 2226 ATH_TXQ_LOCK(cabq); 2227 ATH_TXQ_LOCK(&sc->sc_mcastq); 2228 if (nmcastq) { 2229 struct ath_buf *bfm; 2230 2231 /* 2232 * Move frames from the s/w mcast q to the h/w cab q. 2233 */ 2234 bfm = STAILQ_FIRST(&sc->sc_mcastq.axq_q); 2235 if (cabq->axq_link != NULL) { 2236 *cabq->axq_link = bfm->bf_daddr; 2237 } else 2238 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2239 bfm->bf_daddr); 2240 ath_txqmove(cabq, &sc->sc_mcastq); 2241 2242 sc->sc_stats.ast_cabq_xmit += nmcastq; 2243 } 2244 /* NB: gated by beacon so safe to start here */ 2245 ath_hal_txstart(ah, cabq->axq_qnum); 2246 ATH_TXQ_UNLOCK(cabq); 2247 ATH_TXQ_UNLOCK(&sc->sc_mcastq); 2248 } 2249 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2250 ath_hal_txstart(ah, sc->sc_bhalq); 2251 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2252 "%s: TXDP[%u] = %p (%p)\n", __func__, 2253 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2254 2255 sc->sc_stats.ast_be_xmit++; 2256} 2257 2258/* 2259 * Reset the hardware after detecting beacons have stopped. 2260 */ 2261static void 2262ath_bstuck_proc(void *arg, int pending) 2263{ 2264 struct ath_softc *sc = arg; 2265 struct ifnet *ifp = sc->sc_ifp; 2266 2267 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2268 sc->sc_bmisscount); 2269 ath_reset(ifp); 2270} 2271 2272/* 2273 * Reclaim beacon resources. 2274 */ 2275static void 2276ath_beacon_free(struct ath_softc *sc) 2277{ 2278 struct ath_buf *bf; 2279 2280 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2281 if (bf->bf_m != NULL) { 2282 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2283 m_freem(bf->bf_m); 2284 bf->bf_m = NULL; 2285 } 2286 if (bf->bf_node != NULL) { 2287 ieee80211_free_node(bf->bf_node); 2288 bf->bf_node = NULL; 2289 } 2290 } 2291} 2292 2293/* 2294 * Configure the beacon and sleep timers. 2295 * 2296 * When operating as an AP this resets the TSF and sets 2297 * up the hardware to notify us when we need to issue beacons. 2298 * 2299 * When operating in station mode this sets up the beacon 2300 * timers according to the timestamp of the last received 2301 * beacon and the current TSF, configures PCF and DTIM 2302 * handling, programs the sleep registers so the hardware 2303 * will wakeup in time to receive beacons, and configures 2304 * the beacon miss handling so we'll receive a BMISS 2305 * interrupt when we stop seeing beacons from the AP 2306 * we've associated with. 2307 */ 2308static void 2309ath_beacon_config(struct ath_softc *sc) 2310{ 2311#define TSF_TO_TU(_h,_l) \ 2312 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2313#define FUDGE 2 2314 struct ath_hal *ah = sc->sc_ah; 2315 struct ieee80211com *ic = &sc->sc_ic; 2316 struct ieee80211_node *ni = ic->ic_bss; 2317 u_int32_t nexttbtt, intval, tsftu; 2318 u_int64_t tsf; 2319 2320 /* extract tstamp from last beacon and convert to TU */ 2321 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2322 LE_READ_4(ni->ni_tstamp.data)); 2323 /* NB: the beacon interval is kept internally in TU's */ 2324 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2325 if (nexttbtt == 0) /* e.g. for ap mode */ 2326 nexttbtt = intval; 2327 else if (intval) /* NB: can be 0 for monitor mode */ 2328 nexttbtt = roundup(nexttbtt, intval); 2329 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2330 __func__, nexttbtt, intval, ni->ni_intval); 2331 if (ic->ic_opmode == IEEE80211_M_STA) { 2332 HAL_BEACON_STATE bs; 2333 int dtimperiod, dtimcount; 2334 int cfpperiod, cfpcount; 2335 2336 /* 2337 * Setup dtim and cfp parameters according to 2338 * last beacon we received (which may be none). 2339 */ 2340 dtimperiod = ni->ni_dtim_period; 2341 if (dtimperiod <= 0) /* NB: 0 if not known */ 2342 dtimperiod = 1; 2343 dtimcount = ni->ni_dtim_count; 2344 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2345 dtimcount = 0; /* XXX? */ 2346 cfpperiod = 1; /* NB: no PCF support yet */ 2347 cfpcount = 0; 2348 /* 2349 * Pull nexttbtt forward to reflect the current 2350 * TSF and calculate dtim+cfp state for the result. 2351 */ 2352 tsf = ath_hal_gettsf64(ah); 2353 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2354 do { 2355 nexttbtt += intval; 2356 if (--dtimcount < 0) { 2357 dtimcount = dtimperiod - 1; 2358 if (--cfpcount < 0) 2359 cfpcount = cfpperiod - 1; 2360 } 2361 } while (nexttbtt < tsftu); 2362 memset(&bs, 0, sizeof(bs)); 2363 bs.bs_intval = intval; 2364 bs.bs_nexttbtt = nexttbtt; 2365 bs.bs_dtimperiod = dtimperiod*intval; 2366 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2367 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2368 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2369 bs.bs_cfpmaxduration = 0; 2370#if 0 2371 /* 2372 * The 802.11 layer records the offset to the DTIM 2373 * bitmap while receiving beacons; use it here to 2374 * enable h/w detection of our AID being marked in 2375 * the bitmap vector (to indicate frames for us are 2376 * pending at the AP). 2377 * XXX do DTIM handling in s/w to WAR old h/w bugs 2378 * XXX enable based on h/w rev for newer chips 2379 */ 2380 bs.bs_timoffset = ni->ni_timoff; 2381#endif 2382 /* 2383 * Calculate the number of consecutive beacons to miss 2384 * before taking a BMISS interrupt. The configuration 2385 * is specified in ms, so we need to convert that to 2386 * TU's and then calculate based on the beacon interval. 2387 * Note that we clamp the result to at most 10 beacons. 2388 */ 2389 bs.bs_bmissthreshold = ic->ic_bmissthreshold; 2390 if (bs.bs_bmissthreshold > 10) 2391 bs.bs_bmissthreshold = 10; 2392 else if (bs.bs_bmissthreshold <= 0) 2393 bs.bs_bmissthreshold = 1; 2394 2395 /* 2396 * Calculate sleep duration. The configuration is 2397 * given in ms. We insure a multiple of the beacon 2398 * period is used. Also, if the sleep duration is 2399 * greater than the DTIM period then it makes senses 2400 * to make it a multiple of that. 2401 * 2402 * XXX fixed at 100ms 2403 */ 2404 bs.bs_sleepduration = 2405 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2406 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2407 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2408 2409 DPRINTF(sc, ATH_DEBUG_BEACON, 2410 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2411 , __func__ 2412 , tsf, tsftu 2413 , bs.bs_intval 2414 , bs.bs_nexttbtt 2415 , bs.bs_dtimperiod 2416 , bs.bs_nextdtim 2417 , bs.bs_bmissthreshold 2418 , bs.bs_sleepduration 2419 , bs.bs_cfpperiod 2420 , bs.bs_cfpmaxduration 2421 , bs.bs_cfpnext 2422 , bs.bs_timoffset 2423 ); 2424 ath_hal_intrset(ah, 0); 2425 ath_hal_beacontimers(ah, &bs); 2426 sc->sc_imask |= HAL_INT_BMISS; 2427 ath_hal_intrset(ah, sc->sc_imask); 2428 } else { 2429 ath_hal_intrset(ah, 0); 2430 if (nexttbtt == intval) 2431 intval |= HAL_BEACON_RESET_TSF; 2432 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2433 /* 2434 * In IBSS mode enable the beacon timers but only 2435 * enable SWBA interrupts if we need to manually 2436 * prepare beacon frames. Otherwise we use a 2437 * self-linked tx descriptor and let the hardware 2438 * deal with things. 2439 */ 2440 intval |= HAL_BEACON_ENA; 2441 if (!sc->sc_hasveol) 2442 sc->sc_imask |= HAL_INT_SWBA; 2443 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2444 /* 2445 * Pull nexttbtt forward to reflect 2446 * the current TSF. 2447 */ 2448 tsf = ath_hal_gettsf64(ah); 2449 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2450 do { 2451 nexttbtt += intval; 2452 } while (nexttbtt < tsftu); 2453 } 2454 ath_beaconq_config(sc); 2455 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2456 /* 2457 * In AP mode we enable the beacon timers and 2458 * SWBA interrupts to prepare beacon frames. 2459 */ 2460 intval |= HAL_BEACON_ENA; 2461 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2462 ath_beaconq_config(sc); 2463 } 2464 ath_hal_beaconinit(ah, nexttbtt, intval); 2465 sc->sc_bmisscount = 0; 2466 ath_hal_intrset(ah, sc->sc_imask); 2467 /* 2468 * When using a self-linked beacon descriptor in 2469 * ibss mode load it once here. 2470 */ 2471 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2472 ath_beacon_proc(sc, 0); 2473 } 2474 sc->sc_syncbeacon = 0; 2475#undef FUDGE 2476#undef TSF_TO_TU 2477} 2478 2479static void 2480ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2481{ 2482 bus_addr_t *paddr = (bus_addr_t*) arg; 2483 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2484 *paddr = segs->ds_addr; 2485} 2486 2487static int 2488ath_descdma_setup(struct ath_softc *sc, 2489 struct ath_descdma *dd, ath_bufhead *head, 2490 const char *name, int nbuf, int ndesc) 2491{ 2492#define DS2PHYS(_dd, _ds) \ 2493 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2494 struct ifnet *ifp = sc->sc_ifp; 2495 struct ath_desc *ds; 2496 struct ath_buf *bf; 2497 int i, bsize, error; 2498 2499 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2500 __func__, name, nbuf, ndesc); 2501 2502 dd->dd_name = name; 2503 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2504 2505 /* 2506 * Setup DMA descriptor area. 2507 */ 2508 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 2509 PAGE_SIZE, 0, /* alignment, bounds */ 2510 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2511 BUS_SPACE_MAXADDR, /* highaddr */ 2512 NULL, NULL, /* filter, filterarg */ 2513 dd->dd_desc_len, /* maxsize */ 2514 1, /* nsegments */ 2515 dd->dd_desc_len, /* maxsegsize */ 2516 BUS_DMA_ALLOCNOW, /* flags */ 2517 NULL, /* lockfunc */ 2518 NULL, /* lockarg */ 2519 &dd->dd_dmat); 2520 if (error != 0) { 2521 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2522 return error; 2523 } 2524 2525 /* allocate descriptors */ 2526 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2527 if (error != 0) { 2528 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2529 "error %u\n", dd->dd_name, error); 2530 goto fail0; 2531 } 2532 2533 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2534 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2535 &dd->dd_dmamap); 2536 if (error != 0) { 2537 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2538 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2539 goto fail1; 2540 } 2541 2542 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2543 dd->dd_desc, dd->dd_desc_len, 2544 ath_load_cb, &dd->dd_desc_paddr, 2545 BUS_DMA_NOWAIT); 2546 if (error != 0) { 2547 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2548 dd->dd_name, error); 2549 goto fail2; 2550 } 2551 2552 ds = dd->dd_desc; 2553 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2554 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2555 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2556 2557 /* allocate rx buffers */ 2558 bsize = sizeof(struct ath_buf) * nbuf; 2559 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2560 if (bf == NULL) { 2561 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2562 dd->dd_name, bsize); 2563 goto fail3; 2564 } 2565 dd->dd_bufptr = bf; 2566 2567 STAILQ_INIT(head); 2568 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2569 bf->bf_desc = ds; 2570 bf->bf_daddr = DS2PHYS(dd, ds); 2571 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2572 &bf->bf_dmamap); 2573 if (error != 0) { 2574 if_printf(ifp, "unable to create dmamap for %s " 2575 "buffer %u, error %u\n", dd->dd_name, i, error); 2576 ath_descdma_cleanup(sc, dd, head); 2577 return error; 2578 } 2579 STAILQ_INSERT_TAIL(head, bf, bf_list); 2580 } 2581 return 0; 2582fail3: 2583 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2584fail2: 2585 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2586fail1: 2587 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2588fail0: 2589 bus_dma_tag_destroy(dd->dd_dmat); 2590 memset(dd, 0, sizeof(*dd)); 2591 return error; 2592#undef DS2PHYS 2593} 2594 2595static void 2596ath_descdma_cleanup(struct ath_softc *sc, 2597 struct ath_descdma *dd, ath_bufhead *head) 2598{ 2599 struct ath_buf *bf; 2600 struct ieee80211_node *ni; 2601 2602 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2603 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2604 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2605 bus_dma_tag_destroy(dd->dd_dmat); 2606 2607 STAILQ_FOREACH(bf, head, bf_list) { 2608 if (bf->bf_m) { 2609 m_freem(bf->bf_m); 2610 bf->bf_m = NULL; 2611 } 2612 if (bf->bf_dmamap != NULL) { 2613 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2614 bf->bf_dmamap = NULL; 2615 } 2616 ni = bf->bf_node; 2617 bf->bf_node = NULL; 2618 if (ni != NULL) { 2619 /* 2620 * Reclaim node reference. 2621 */ 2622 ieee80211_free_node(ni); 2623 } 2624 } 2625 2626 STAILQ_INIT(head); 2627 free(dd->dd_bufptr, M_ATHDEV); 2628 memset(dd, 0, sizeof(*dd)); 2629} 2630 2631static int 2632ath_desc_alloc(struct ath_softc *sc) 2633{ 2634 int error; 2635 2636 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2637 "rx", ath_rxbuf, 1); 2638 if (error != 0) 2639 return error; 2640 2641 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2642 "tx", ath_txbuf, ATH_TXDESC); 2643 if (error != 0) { 2644 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2645 return error; 2646 } 2647 2648 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2649 "beacon", 1, 1); 2650 if (error != 0) { 2651 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2652 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2653 return error; 2654 } 2655 return 0; 2656} 2657 2658static void 2659ath_desc_free(struct ath_softc *sc) 2660{ 2661 2662 if (sc->sc_bdma.dd_desc_len != 0) 2663 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2664 if (sc->sc_txdma.dd_desc_len != 0) 2665 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2666 if (sc->sc_rxdma.dd_desc_len != 0) 2667 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2668} 2669 2670static struct ieee80211_node * 2671ath_node_alloc(struct ieee80211_node_table *nt) 2672{ 2673 struct ieee80211com *ic = nt->nt_ic; 2674 struct ath_softc *sc = ic->ic_ifp->if_softc; 2675 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2676 struct ath_node *an; 2677 2678 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2679 if (an == NULL) { 2680 /* XXX stat+msg */ 2681 return NULL; 2682 } 2683 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2684 ath_rate_node_init(sc, an); 2685 2686 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2687 return &an->an_node; 2688} 2689 2690static void 2691ath_node_free(struct ieee80211_node *ni) 2692{ 2693 struct ieee80211com *ic = ni->ni_ic; 2694 struct ath_softc *sc = ic->ic_ifp->if_softc; 2695 2696 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2697 2698 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2699 sc->sc_node_free(ni); 2700} 2701 2702static u_int8_t 2703ath_node_getrssi(const struct ieee80211_node *ni) 2704{ 2705#define HAL_EP_RND(x, mul) \ 2706 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2707 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2708 int32_t rssi; 2709 2710 /* 2711 * When only one frame is received there will be no state in 2712 * avgrssi so fallback on the value recorded by the 802.11 layer. 2713 */ 2714 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2715 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2716 else 2717 rssi = ni->ni_rssi; 2718 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2719#undef HAL_EP_RND 2720} 2721 2722static int 2723ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2724{ 2725 struct ath_hal *ah = sc->sc_ah; 2726 int error; 2727 struct mbuf *m; 2728 struct ath_desc *ds; 2729 2730 m = bf->bf_m; 2731 if (m == NULL) { 2732 /* 2733 * NB: by assigning a page to the rx dma buffer we 2734 * implicitly satisfy the Atheros requirement that 2735 * this buffer be cache-line-aligned and sized to be 2736 * multiple of the cache line size. Not doing this 2737 * causes weird stuff to happen (for the 5210 at least). 2738 */ 2739 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2740 if (m == NULL) { 2741 DPRINTF(sc, ATH_DEBUG_ANY, 2742 "%s: no mbuf/cluster\n", __func__); 2743 sc->sc_stats.ast_rx_nombuf++; 2744 return ENOMEM; 2745 } 2746 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2747 2748 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 2749 bf->bf_dmamap, m, 2750 bf->bf_segs, &bf->bf_nseg, 2751 BUS_DMA_NOWAIT); 2752 if (error != 0) { 2753 DPRINTF(sc, ATH_DEBUG_ANY, 2754 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 2755 __func__, error); 2756 sc->sc_stats.ast_rx_busdma++; 2757 m_freem(m); 2758 return error; 2759 } 2760 KASSERT(bf->bf_nseg == 1, 2761 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2762 bf->bf_m = m; 2763 } 2764 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 2765 2766 /* 2767 * Setup descriptors. For receive we always terminate 2768 * the descriptor list with a self-linked entry so we'll 2769 * not get overrun under high load (as can happen with a 2770 * 5212 when ANI processing enables PHY error frames). 2771 * 2772 * To insure the last descriptor is self-linked we create 2773 * each descriptor as self-linked and add it to the end. As 2774 * each additional descriptor is added the previous self-linked 2775 * entry is ``fixed'' naturally. This should be safe even 2776 * if DMA is happening. When processing RX interrupts we 2777 * never remove/process the last, self-linked, entry on the 2778 * descriptor list. This insures the hardware always has 2779 * someplace to write a new frame. 2780 */ 2781 ds = bf->bf_desc; 2782 ds->ds_link = bf->bf_daddr; /* link to self */ 2783 ds->ds_data = bf->bf_segs[0].ds_addr; 2784 ath_hal_setuprxdesc(ah, ds 2785 , m->m_len /* buffer size */ 2786 , 0 2787 ); 2788 2789 if (sc->sc_rxlink != NULL) 2790 *sc->sc_rxlink = bf->bf_daddr; 2791 sc->sc_rxlink = &ds->ds_link; 2792 return 0; 2793} 2794 2795/* 2796 * Extend 15-bit time stamp from rx descriptor to 2797 * a full 64-bit TSF using the specified TSF. 2798 */ 2799static __inline u_int64_t 2800ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2801{ 2802 if ((tsf & 0x7fff) < rstamp) 2803 tsf -= 0x8000; 2804 return ((tsf &~ 0x7fff) | rstamp); 2805} 2806 2807/* 2808 * Intercept management frames to collect beacon rssi data 2809 * and to do ibss merges. 2810 */ 2811static void 2812ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2813 struct ieee80211_node *ni, 2814 int subtype, int rssi, u_int32_t rstamp) 2815{ 2816 struct ath_softc *sc = ic->ic_ifp->if_softc; 2817 2818 /* 2819 * Call up first so subsequent work can use information 2820 * potentially stored in the node (e.g. for ibss merge). 2821 */ 2822 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2823 switch (subtype) { 2824 case IEEE80211_FC0_SUBTYPE_BEACON: 2825 /* update rssi statistics for use by the hal */ 2826 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2827 if (sc->sc_syncbeacon && 2828 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2829 /* 2830 * Resync beacon timers using the tsf of the beacon 2831 * frame we just received. 2832 */ 2833 ath_beacon_config(sc); 2834 } 2835 /* fall thru... */ 2836 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2837 if (ic->ic_opmode == IEEE80211_M_IBSS && 2838 ic->ic_state == IEEE80211_S_RUN) { 2839 u_int64_t tsf = ath_extend_tsf(rstamp, 2840 ath_hal_gettsf64(sc->sc_ah)); 2841 /* 2842 * Handle ibss merge as needed; check the tsf on the 2843 * frame before attempting the merge. The 802.11 spec 2844 * says the station should change it's bssid to match 2845 * the oldest station with the same ssid, where oldest 2846 * is determined by the tsf. Note that hardware 2847 * reconfiguration happens through callback to 2848 * ath_newstate as the state machine will go from 2849 * RUN -> RUN when this happens. 2850 */ 2851 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2852 DPRINTF(sc, ATH_DEBUG_STATE, 2853 "ibss merge, rstamp %u tsf %ju " 2854 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2855 (uintmax_t)ni->ni_tstamp.tsf); 2856 (void) ieee80211_ibss_merge(ni); 2857 } 2858 } 2859 break; 2860 } 2861} 2862 2863/* 2864 * Set the default antenna. 2865 */ 2866static void 2867ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2868{ 2869 struct ath_hal *ah = sc->sc_ah; 2870 2871 /* XXX block beacon interrupts */ 2872 ath_hal_setdefantenna(ah, antenna); 2873 if (sc->sc_defant != antenna) 2874 sc->sc_stats.ast_ant_defswitch++; 2875 sc->sc_defant = antenna; 2876 sc->sc_rxotherant = 0; 2877} 2878 2879static int 2880ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 2881 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 2882{ 2883 u_int8_t rix; 2884 2885 KASSERT(sc->sc_drvbpf != NULL, ("no tap")); 2886 2887 /* 2888 * Discard anything shorter than an ack or cts. 2889 */ 2890 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 2891 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 2892 __func__, m->m_pkthdr.len); 2893 sc->sc_stats.ast_rx_tooshort++; 2894 return 0; 2895 } 2896 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 2897 rix = rs->rs_rate; 2898 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2899 if (rs->rs_status & HAL_RXERR_CRC) 2900 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2901 /* XXX propagate other error flags from descriptor */ 2902 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2903 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf; 2904 sc->sc_rx_th.wr_antnoise = nf; 2905 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 2906 2907 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 2908 2909 return 1; 2910} 2911 2912static void 2913ath_rx_proc(void *arg, int npending) 2914{ 2915#define PA2DESC(_sc, _pa) \ 2916 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2917 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2918 struct ath_softc *sc = arg; 2919 struct ath_buf *bf; 2920 struct ieee80211com *ic = &sc->sc_ic; 2921 struct ifnet *ifp = sc->sc_ifp; 2922 struct ath_hal *ah = sc->sc_ah; 2923 struct ath_desc *ds; 2924 struct ath_rx_status *rs; 2925 struct mbuf *m; 2926 struct ieee80211_node *ni; 2927 struct ath_node *an; 2928 int len, type, ngood; 2929 u_int phyerr; 2930 HAL_STATUS status; 2931 int16_t nf; 2932 u_int64_t tsf; 2933 2934 NET_LOCK_GIANT(); /* XXX */ 2935 2936 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2937 ngood = 0; 2938 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2939 tsf = ath_hal_gettsf64(ah); 2940 do { 2941 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2942 if (bf == NULL) { /* NB: shouldn't happen */ 2943 if_printf(ifp, "%s: no buffer!\n", __func__); 2944 break; 2945 } 2946 m = bf->bf_m; 2947 if (m == NULL) { /* NB: shouldn't happen */ 2948 /* 2949 * If mbuf allocation failed previously there 2950 * will be no mbuf; try again to re-populate it. 2951 */ 2952 /* XXX make debug msg */ 2953 if_printf(ifp, "%s: no mbuf!\n", __func__); 2954 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2955 goto rx_next; 2956 } 2957 ds = bf->bf_desc; 2958 if (ds->ds_link == bf->bf_daddr) { 2959 /* NB: never process the self-linked entry at the end */ 2960 break; 2961 } 2962 /* XXX sync descriptor memory */ 2963 /* 2964 * Must provide the virtual address of the current 2965 * descriptor, the physical address, and the virtual 2966 * address of the next descriptor in the h/w chain. 2967 * This allows the HAL to look ahead to see if the 2968 * hardware is done with a descriptor by checking the 2969 * done bit in the following descriptor and the address 2970 * of the current descriptor the DMA engine is working 2971 * on. All this is necessary because of our use of 2972 * a self-linked list to avoid rx overruns. 2973 */ 2974 rs = &bf->bf_status.ds_rxstat; 2975 status = ath_hal_rxprocdesc(ah, ds, 2976 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 2977#ifdef ATH_DEBUG 2978 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2979 ath_printrxbuf(bf, 0, status == HAL_OK); 2980#endif 2981 if (status == HAL_EINPROGRESS) 2982 break; 2983 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2984 if (rs->rs_more) { 2985 /* 2986 * Frame spans multiple descriptors; this 2987 * cannot happen yet as we don't support 2988 * jumbograms. If not in monitor mode, 2989 * discard the frame. 2990 */ 2991 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2992 sc->sc_stats.ast_rx_toobig++; 2993 goto rx_next; 2994 } 2995 /* fall thru for monitor mode handling... */ 2996 } else if (rs->rs_status != 0) { 2997 if (rs->rs_status & HAL_RXERR_CRC) 2998 sc->sc_stats.ast_rx_crcerr++; 2999 if (rs->rs_status & HAL_RXERR_FIFO) 3000 sc->sc_stats.ast_rx_fifoerr++; 3001 if (rs->rs_status & HAL_RXERR_PHY) { 3002 sc->sc_stats.ast_rx_phyerr++; 3003 phyerr = rs->rs_phyerr & 0x1f; 3004 sc->sc_stats.ast_rx_phy[phyerr]++; 3005 goto rx_next; 3006 } 3007 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3008 /* 3009 * Decrypt error. If the error occurred 3010 * because there was no hardware key, then 3011 * let the frame through so the upper layers 3012 * can process it. This is necessary for 5210 3013 * parts which have no way to setup a ``clear'' 3014 * key cache entry. 3015 * 3016 * XXX do key cache faulting 3017 */ 3018 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3019 goto rx_accept; 3020 sc->sc_stats.ast_rx_badcrypt++; 3021 } 3022 if (rs->rs_status & HAL_RXERR_MIC) { 3023 sc->sc_stats.ast_rx_badmic++; 3024 /* 3025 * Do minimal work required to hand off 3026 * the 802.11 header for notifcation. 3027 */ 3028 /* XXX frag's and qos frames */ 3029 len = rs->rs_datalen; 3030 if (len >= sizeof (struct ieee80211_frame)) { 3031 bus_dmamap_sync(sc->sc_dmat, 3032 bf->bf_dmamap, 3033 BUS_DMASYNC_POSTREAD); 3034 ieee80211_notify_michael_failure(ic, 3035 mtod(m, struct ieee80211_frame *), 3036 sc->sc_splitmic ? 3037 rs->rs_keyix-32 : rs->rs_keyix 3038 ); 3039 } 3040 } 3041 ifp->if_ierrors++; 3042 /* 3043 * When a tap is present pass error frames 3044 * that have been requested. By default we 3045 * pass decrypt+mic errors but others may be 3046 * interesting (e.g. crc). 3047 */ 3048 if (bpf_peers_present(sc->sc_drvbpf) && 3049 (rs->rs_status & sc->sc_monpass)) { 3050 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3051 BUS_DMASYNC_POSTREAD); 3052 /* NB: bpf needs the mbuf length setup */ 3053 len = rs->rs_datalen; 3054 m->m_pkthdr.len = m->m_len = len; 3055 (void) ath_rx_tap(sc, m, rs, tsf, nf); 3056 } 3057 /* XXX pass MIC errors up for s/w reclaculation */ 3058 goto rx_next; 3059 } 3060rx_accept: 3061 /* 3062 * Sync and unmap the frame. At this point we're 3063 * committed to passing the mbuf somewhere so clear 3064 * bf_m; this means a new mbuf must be allocated 3065 * when the rx descriptor is setup again to receive 3066 * another frame. 3067 */ 3068 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3069 BUS_DMASYNC_POSTREAD); 3070 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3071 bf->bf_m = NULL; 3072 3073 m->m_pkthdr.rcvif = ifp; 3074 len = rs->rs_datalen; 3075 m->m_pkthdr.len = m->m_len = len; 3076 3077 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3078 3079 if (bpf_peers_present(sc->sc_drvbpf) && 3080 !ath_rx_tap(sc, m, rs, tsf, nf)) { 3081 m_freem(m); /* XXX reclaim */ 3082 goto rx_next; 3083 } 3084 3085 /* 3086 * From this point on we assume the frame is at least 3087 * as large as ieee80211_frame_min; verify that. 3088 */ 3089 if (len < IEEE80211_MIN_LEN) { 3090 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3091 __func__, len); 3092 sc->sc_stats.ast_rx_tooshort++; 3093 m_freem(m); 3094 goto rx_next; 3095 } 3096 3097 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3098 ieee80211_dump_pkt(mtod(m, caddr_t), len, 3099 sc->sc_hwmap[rs->rs_rate].ieeerate, 3100 rs->rs_rssi); 3101 } 3102 3103 m_adj(m, -IEEE80211_CRC_LEN); 3104 3105 /* 3106 * Locate the node for sender, track state, and then 3107 * pass the (referenced) node up to the 802.11 layer 3108 * for its use. 3109 */ 3110 ni = ieee80211_find_rxnode_withkey(ic, 3111 mtod(m, const struct ieee80211_frame_min *), 3112 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 3113 IEEE80211_KEYIX_NONE : rs->rs_keyix); 3114 /* 3115 * Track rx rssi and do any rx antenna management. 3116 */ 3117 an = ATH_NODE(ni); 3118 ATH_RSSI_LPF(an->an_avgrssi, rs->rs_rssi); 3119 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 3120 /* 3121 * Send frame up for processing. 3122 */ 3123 type = ieee80211_input(ic, m, ni, rs->rs_rssi, rs->rs_tstamp); 3124 ieee80211_free_node(ni); 3125 if (sc->sc_diversity) { 3126 /* 3127 * When using fast diversity, change the default rx 3128 * antenna if diversity chooses the other antenna 3 3129 * times in a row. 3130 */ 3131 if (sc->sc_defant != rs->rs_antenna) { 3132 if (++sc->sc_rxotherant >= 3) 3133 ath_setdefantenna(sc, rs->rs_antenna); 3134 } else 3135 sc->sc_rxotherant = 0; 3136 } 3137 if (sc->sc_softled) { 3138 /* 3139 * Blink for any data frame. Otherwise do a 3140 * heartbeat-style blink when idle. The latter 3141 * is mainly for station mode where we depend on 3142 * periodic beacon frames to trigger the poll event. 3143 */ 3144 if (type == IEEE80211_FC0_TYPE_DATA) { 3145 sc->sc_rxrate = rs->rs_rate; 3146 ath_led_event(sc, ATH_LED_RX); 3147 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3148 ath_led_event(sc, ATH_LED_POLL); 3149 } 3150 /* 3151 * Arrange to update the last rx timestamp only for 3152 * frames from our ap when operating in station mode. 3153 * This assumes the rx key is always setup when associated. 3154 */ 3155 if (ic->ic_opmode == IEEE80211_M_STA && 3156 rs->rs_keyix != HAL_RXKEYIX_INVALID) 3157 ngood++; 3158rx_next: 3159 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3160 } while (ath_rxbuf_init(sc, bf) == 0); 3161 3162 /* rx signal state monitoring */ 3163 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3164 if (ngood) 3165 sc->sc_lastrx = tsf; 3166 3167 /* NB: may want to check mgtq too */ 3168 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 3169 !IFQ_IS_EMPTY(&ifp->if_snd)) 3170 ath_start(ifp); 3171 3172 NET_UNLOCK_GIANT(); /* XXX */ 3173#undef PA2DESC 3174} 3175 3176static void 3177ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3178{ 3179 txq->axq_qnum = qnum; 3180 txq->axq_depth = 0; 3181 txq->axq_intrcnt = 0; 3182 txq->axq_link = NULL; 3183 STAILQ_INIT(&txq->axq_q); 3184 ATH_TXQ_LOCK_INIT(sc, txq); 3185} 3186 3187/* 3188 * Setup a h/w transmit queue. 3189 */ 3190static struct ath_txq * 3191ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3192{ 3193#define N(a) (sizeof(a)/sizeof(a[0])) 3194 struct ath_hal *ah = sc->sc_ah; 3195 HAL_TXQ_INFO qi; 3196 int qnum; 3197 3198 memset(&qi, 0, sizeof(qi)); 3199 qi.tqi_subtype = subtype; 3200 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3201 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3202 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3203 /* 3204 * Enable interrupts only for EOL and DESC conditions. 3205 * We mark tx descriptors to receive a DESC interrupt 3206 * when a tx queue gets deep; otherwise waiting for the 3207 * EOL to reap descriptors. Note that this is done to 3208 * reduce interrupt load and this only defers reaping 3209 * descriptors, never transmitting frames. Aside from 3210 * reducing interrupts this also permits more concurrency. 3211 * The only potential downside is if the tx queue backs 3212 * up in which case the top half of the kernel may backup 3213 * due to a lack of tx descriptors. 3214 */ 3215 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3216 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3217 if (qnum == -1) { 3218 /* 3219 * NB: don't print a message, this happens 3220 * normally on parts with too few tx queues 3221 */ 3222 return NULL; 3223 } 3224 if (qnum >= N(sc->sc_txq)) { 3225 device_printf(sc->sc_dev, 3226 "hal qnum %u out of range, max %zu!\n", 3227 qnum, N(sc->sc_txq)); 3228 ath_hal_releasetxqueue(ah, qnum); 3229 return NULL; 3230 } 3231 if (!ATH_TXQ_SETUP(sc, qnum)) { 3232 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 3233 sc->sc_txqsetup |= 1<<qnum; 3234 } 3235 return &sc->sc_txq[qnum]; 3236#undef N 3237} 3238 3239/* 3240 * Setup a hardware data transmit queue for the specified 3241 * access control. The hal may not support all requested 3242 * queues in which case it will return a reference to a 3243 * previously setup queue. We record the mapping from ac's 3244 * to h/w queues for use by ath_tx_start and also track 3245 * the set of h/w queues being used to optimize work in the 3246 * transmit interrupt handler and related routines. 3247 */ 3248static int 3249ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3250{ 3251#define N(a) (sizeof(a)/sizeof(a[0])) 3252 struct ath_txq *txq; 3253 3254 if (ac >= N(sc->sc_ac2q)) { 3255 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3256 ac, N(sc->sc_ac2q)); 3257 return 0; 3258 } 3259 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3260 if (txq != NULL) { 3261 sc->sc_ac2q[ac] = txq; 3262 return 1; 3263 } else 3264 return 0; 3265#undef N 3266} 3267 3268/* 3269 * Update WME parameters for a transmit queue. 3270 */ 3271static int 3272ath_txq_update(struct ath_softc *sc, int ac) 3273{ 3274#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3275#define ATH_TXOP_TO_US(v) (v<<5) 3276 struct ieee80211com *ic = &sc->sc_ic; 3277 struct ath_txq *txq = sc->sc_ac2q[ac]; 3278 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3279 struct ath_hal *ah = sc->sc_ah; 3280 HAL_TXQ_INFO qi; 3281 3282 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3283 qi.tqi_aifs = wmep->wmep_aifsn; 3284 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3285 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3286 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3287 3288 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3289 device_printf(sc->sc_dev, "unable to update hardware queue " 3290 "parameters for %s traffic!\n", 3291 ieee80211_wme_acnames[ac]); 3292 return 0; 3293 } else { 3294 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3295 return 1; 3296 } 3297#undef ATH_TXOP_TO_US 3298#undef ATH_EXPONENT_TO_VALUE 3299} 3300 3301/* 3302 * Callback from the 802.11 layer to update WME parameters. 3303 */ 3304static int 3305ath_wme_update(struct ieee80211com *ic) 3306{ 3307 struct ath_softc *sc = ic->ic_ifp->if_softc; 3308 3309 return !ath_txq_update(sc, WME_AC_BE) || 3310 !ath_txq_update(sc, WME_AC_BK) || 3311 !ath_txq_update(sc, WME_AC_VI) || 3312 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3313} 3314 3315/* 3316 * Reclaim resources for a setup queue. 3317 */ 3318static void 3319ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3320{ 3321 3322 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3323 ATH_TXQ_LOCK_DESTROY(txq); 3324 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3325} 3326 3327/* 3328 * Reclaim all tx queue resources. 3329 */ 3330static void 3331ath_tx_cleanup(struct ath_softc *sc) 3332{ 3333 int i; 3334 3335 ATH_TXBUF_LOCK_DESTROY(sc); 3336 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3337 if (ATH_TXQ_SETUP(sc, i)) 3338 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3339 ATH_TXQ_LOCK_DESTROY(&sc->sc_mcastq); 3340} 3341 3342/* 3343 * Defragment an mbuf chain, returning at most maxfrags separate 3344 * mbufs+clusters. If this is not possible NULL is returned and 3345 * the original mbuf chain is left in it's present (potentially 3346 * modified) state. We use two techniques: collapsing consecutive 3347 * mbufs and replacing consecutive mbufs by a cluster. 3348 */ 3349static struct mbuf * 3350ath_defrag(struct mbuf *m0, int how, int maxfrags) 3351{ 3352 struct mbuf *m, *n, *n2, **prev; 3353 u_int curfrags; 3354 3355 /* 3356 * Calculate the current number of frags. 3357 */ 3358 curfrags = 0; 3359 for (m = m0; m != NULL; m = m->m_next) 3360 curfrags++; 3361 /* 3362 * First, try to collapse mbufs. Note that we always collapse 3363 * towards the front so we don't need to deal with moving the 3364 * pkthdr. This may be suboptimal if the first mbuf has much 3365 * less data than the following. 3366 */ 3367 m = m0; 3368again: 3369 for (;;) { 3370 n = m->m_next; 3371 if (n == NULL) 3372 break; 3373 if ((m->m_flags & M_RDONLY) == 0 && 3374 n->m_len < M_TRAILINGSPACE(m)) { 3375 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3376 n->m_len); 3377 m->m_len += n->m_len; 3378 m->m_next = n->m_next; 3379 m_free(n); 3380 if (--curfrags <= maxfrags) 3381 return m0; 3382 } else 3383 m = n; 3384 } 3385 KASSERT(maxfrags > 1, 3386 ("maxfrags %u, but normal collapse failed", maxfrags)); 3387 /* 3388 * Collapse consecutive mbufs to a cluster. 3389 */ 3390 prev = &m0->m_next; /* NB: not the first mbuf */ 3391 while ((n = *prev) != NULL) { 3392 if ((n2 = n->m_next) != NULL && 3393 n->m_len + n2->m_len < MCLBYTES) { 3394 m = m_getcl(how, MT_DATA, 0); 3395 if (m == NULL) 3396 goto bad; 3397 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3398 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3399 n2->m_len); 3400 m->m_len = n->m_len + n2->m_len; 3401 m->m_next = n2->m_next; 3402 *prev = m; 3403 m_free(n); 3404 m_free(n2); 3405 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3406 return m0; 3407 /* 3408 * Still not there, try the normal collapse 3409 * again before we allocate another cluster. 3410 */ 3411 goto again; 3412 } 3413 prev = &n->m_next; 3414 } 3415 /* 3416 * No place where we can collapse to a cluster; punt. 3417 * This can occur if, for example, you request 2 frags 3418 * but the packet requires that both be clusters (we 3419 * never reallocate the first mbuf to avoid moving the 3420 * packet header). 3421 */ 3422bad: 3423 return NULL; 3424} 3425 3426/* 3427 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3428 */ 3429static int 3430ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3431{ 3432 int i; 3433 3434 for (i = 0; i < rt->rateCount; i++) 3435 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3436 return i; 3437 return 0; /* NB: lowest rate */ 3438} 3439 3440static int 3441ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 3442{ 3443 struct mbuf *m; 3444 int error; 3445 3446 /* 3447 * Load the DMA map so any coalescing is done. This 3448 * also calculates the number of descriptors we need. 3449 */ 3450 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3451 bf->bf_segs, &bf->bf_nseg, 3452 BUS_DMA_NOWAIT); 3453 if (error == EFBIG) { 3454 /* XXX packet requires too many descriptors */ 3455 bf->bf_nseg = ATH_TXDESC+1; 3456 } else if (error != 0) { 3457 sc->sc_stats.ast_tx_busdma++; 3458 m_freem(m0); 3459 return error; 3460 } 3461 /* 3462 * Discard null packets and check for packets that 3463 * require too many TX descriptors. We try to convert 3464 * the latter to a cluster. 3465 */ 3466 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 3467 sc->sc_stats.ast_tx_linear++; 3468 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3469 if (m == NULL) { 3470 m_freem(m0); 3471 sc->sc_stats.ast_tx_nombuf++; 3472 return ENOMEM; 3473 } 3474 m0 = m; 3475 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3476 bf->bf_segs, &bf->bf_nseg, 3477 BUS_DMA_NOWAIT); 3478 if (error != 0) { 3479 sc->sc_stats.ast_tx_busdma++; 3480 m_freem(m0); 3481 return error; 3482 } 3483 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3484 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3485 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3486 sc->sc_stats.ast_tx_nodata++; 3487 m_freem(m0); 3488 return EIO; 3489 } 3490 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 3491 __func__, m0, m0->m_pkthdr.len); 3492 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3493 bf->bf_m = m0; 3494 3495 return 0; 3496} 3497 3498static void 3499ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 3500{ 3501 struct ath_hal *ah = sc->sc_ah; 3502 struct ath_desc *ds, *ds0; 3503 int i; 3504 3505 /* 3506 * Fillin the remainder of the descriptor info. 3507 */ 3508 ds0 = ds = bf->bf_desc; 3509 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3510 ds->ds_data = bf->bf_segs[i].ds_addr; 3511 if (i == bf->bf_nseg - 1) 3512 ds->ds_link = 0; 3513 else 3514 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3515 ath_hal_filltxdesc(ah, ds 3516 , bf->bf_segs[i].ds_len /* segment length */ 3517 , i == 0 /* first segment */ 3518 , i == bf->bf_nseg - 1 /* last segment */ 3519 , ds0 /* first descriptor */ 3520 ); 3521 DPRINTF(sc, ATH_DEBUG_XMIT, 3522 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3523 __func__, i, ds->ds_link, ds->ds_data, 3524 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3525 } 3526 /* 3527 * Insert the frame on the outbound list and pass it on 3528 * to the hardware. Multicast frames buffered for power 3529 * save stations and transmit from the CAB queue are stored 3530 * on a s/w only queue and loaded on to the CAB queue in 3531 * the SWBA handler since frames only go out on DTIM and 3532 * to avoid possible races. 3533 */ 3534 ATH_TXQ_LOCK(txq); 3535 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3536 if (txq != &sc->sc_mcastq) { 3537 if (txq->axq_link == NULL) { 3538 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3539 DPRINTF(sc, ATH_DEBUG_XMIT, 3540 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3541 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3542 txq->axq_depth); 3543 } else { 3544 *txq->axq_link = bf->bf_daddr; 3545 DPRINTF(sc, ATH_DEBUG_XMIT, 3546 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3547 txq->axq_qnum, txq->axq_link, 3548 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3549 } 3550 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3551 ath_hal_txstart(ah, txq->axq_qnum); 3552 } else { 3553 if (txq->axq_link != NULL) 3554 *txq->axq_link = bf->bf_daddr; 3555 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3556 } 3557 ATH_TXQ_UNLOCK(txq); 3558} 3559 3560static int 3561ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3562 struct mbuf *m0) 3563{ 3564 struct ieee80211com *ic = &sc->sc_ic; 3565 struct ath_hal *ah = sc->sc_ah; 3566 struct ifnet *ifp = sc->sc_ifp; 3567 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3568 int error, iswep, ismcast, ismrr; 3569 int keyix, hdrlen, pktlen, try0; 3570 u_int8_t rix, txrate, ctsrate; 3571 u_int8_t cix = 0xff; /* NB: silence compiler */ 3572 struct ath_desc *ds; 3573 struct ath_txq *txq; 3574 struct ieee80211_frame *wh; 3575 u_int subtype, flags, ctsduration; 3576 HAL_PKT_TYPE atype; 3577 const HAL_RATE_TABLE *rt; 3578 HAL_BOOL shortPreamble; 3579 struct ath_node *an; 3580 u_int pri; 3581 3582 wh = mtod(m0, struct ieee80211_frame *); 3583 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3584 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3585 hdrlen = ieee80211_anyhdrsize(wh); 3586 /* 3587 * Packet length must not include any 3588 * pad bytes; deduct them here. 3589 */ 3590 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3591 3592 if (iswep) { 3593 const struct ieee80211_cipher *cip; 3594 struct ieee80211_key *k; 3595 3596 /* 3597 * Construct the 802.11 header+trailer for an encrypted 3598 * frame. The only reason this can fail is because of an 3599 * unknown or unsupported cipher/key type. 3600 */ 3601 k = ieee80211_crypto_encap(ic, ni, m0); 3602 if (k == NULL) { 3603 /* 3604 * This can happen when the key is yanked after the 3605 * frame was queued. Just discard the frame; the 3606 * 802.11 layer counts failures and provides 3607 * debugging/diagnostics. 3608 */ 3609 m_freem(m0); 3610 return EIO; 3611 } 3612 /* 3613 * Adjust the packet + header lengths for the crypto 3614 * additions and calculate the h/w key index. When 3615 * a s/w mic is done the frame will have had any mic 3616 * added to it prior to entry so m0->m_pkthdr.len above will 3617 * account for it. Otherwise we need to add it to the 3618 * packet length. 3619 */ 3620 cip = k->wk_cipher; 3621 hdrlen += cip->ic_header; 3622 pktlen += cip->ic_header + cip->ic_trailer; 3623 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3624 pktlen += cip->ic_miclen; 3625 keyix = k->wk_keyix; 3626 3627 /* packet header may have moved, reset our local pointer */ 3628 wh = mtod(m0, struct ieee80211_frame *); 3629 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3630 /* 3631 * Use station key cache slot, if assigned. 3632 */ 3633 keyix = ni->ni_ucastkey.wk_keyix; 3634 if (keyix == IEEE80211_KEYIX_NONE) 3635 keyix = HAL_TXKEYIX_INVALID; 3636 } else 3637 keyix = HAL_TXKEYIX_INVALID; 3638 3639 pktlen += IEEE80211_CRC_LEN; 3640 3641 /* 3642 * Load the DMA map so any coalescing is done. This 3643 * also calculates the number of descriptors we need. 3644 */ 3645 error = ath_tx_dmasetup(sc, bf, m0); 3646 if (error != 0) 3647 return error; 3648 bf->bf_node = ni; /* NB: held reference */ 3649 m0 = bf->bf_m; /* NB: may have changed */ 3650 wh = mtod(m0, struct ieee80211_frame *); 3651 3652 /* setup descriptors */ 3653 ds = bf->bf_desc; 3654 rt = sc->sc_currates; 3655 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3656 3657 /* 3658 * NB: the 802.11 layer marks whether or not we should 3659 * use short preamble based on the current mode and 3660 * negotiated parameters. 3661 */ 3662 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3663 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3664 shortPreamble = AH_TRUE; 3665 sc->sc_stats.ast_tx_shortpre++; 3666 } else { 3667 shortPreamble = AH_FALSE; 3668 } 3669 3670 an = ATH_NODE(ni); 3671 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3672 ismrr = 0; /* default no multi-rate retry*/ 3673 /* 3674 * Calculate Atheros packet type from IEEE80211 packet header, 3675 * setup for rate calculations, and select h/w transmit queue. 3676 */ 3677 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3678 case IEEE80211_FC0_TYPE_MGT: 3679 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3680 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3681 atype = HAL_PKT_TYPE_BEACON; 3682 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3683 atype = HAL_PKT_TYPE_PROBE_RESP; 3684 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3685 atype = HAL_PKT_TYPE_ATIM; 3686 else 3687 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3688 rix = sc->sc_minrateix; 3689 txrate = rt->info[rix].rateCode; 3690 if (shortPreamble) 3691 txrate |= rt->info[rix].shortPreamble; 3692 try0 = ATH_TXMGTTRY; 3693 /* NB: force all management frames to highest queue */ 3694 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3695 /* NB: force all management frames to highest queue */ 3696 pri = WME_AC_VO; 3697 } else 3698 pri = WME_AC_BE; 3699 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3700 break; 3701 case IEEE80211_FC0_TYPE_CTL: 3702 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3703 rix = sc->sc_minrateix; 3704 txrate = rt->info[rix].rateCode; 3705 if (shortPreamble) 3706 txrate |= rt->info[rix].shortPreamble; 3707 try0 = ATH_TXMGTTRY; 3708 /* NB: force all ctl frames to highest queue */ 3709 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3710 /* NB: force all ctl frames to highest queue */ 3711 pri = WME_AC_VO; 3712 } else 3713 pri = WME_AC_BE; 3714 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3715 break; 3716 case IEEE80211_FC0_TYPE_DATA: 3717 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3718 /* 3719 * Data frames: multicast frames go out at a fixed rate, 3720 * otherwise consult the rate control module for the 3721 * rate to use. 3722 */ 3723 if (ismcast) { 3724 /* 3725 * Check mcast rate setting in case it's changed. 3726 * XXX move out of fastpath 3727 */ 3728 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3729 sc->sc_mcastrix = 3730 ath_tx_findrix(rt, ic->ic_mcast_rate); 3731 sc->sc_mcastrate = ic->ic_mcast_rate; 3732 } 3733 rix = sc->sc_mcastrix; 3734 txrate = rt->info[rix].rateCode; 3735 if (shortPreamble) 3736 txrate |= rt->info[rix].shortPreamble; 3737 try0 = 1; 3738 } else { 3739 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3740 &rix, &try0, &txrate); 3741 sc->sc_txrate = txrate; /* for LED blinking */ 3742 if (try0 != ATH_TXMAXTRY) 3743 ismrr = 1; 3744 } 3745 pri = M_WME_GETAC(m0); 3746 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3747 flags |= HAL_TXDESC_NOACK; 3748 break; 3749 default: 3750 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3751 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3752 /* XXX statistic */ 3753 m_freem(m0); 3754 return EIO; 3755 } 3756 txq = sc->sc_ac2q[pri]; 3757 3758 /* 3759 * When servicing one or more stations in power-save mode 3760 * (or) if there is some mcast data waiting on the mcast 3761 * queue (to prevent out of order delivery) multicast 3762 * frames must be buffered until after the beacon. 3763 */ 3764 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) { 3765 txq = &sc->sc_mcastq; 3766 /* XXX? more bit in 802.11 frame header */ 3767 } 3768 3769 /* 3770 * Calculate miscellaneous flags. 3771 */ 3772 if (ismcast) { 3773 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3774 } else if (pktlen > ic->ic_rtsthreshold) { 3775 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3776 cix = rt->info[rix].controlRate; 3777 sc->sc_stats.ast_tx_rts++; 3778 } 3779 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3780 sc->sc_stats.ast_tx_noack++; 3781 3782 /* 3783 * If 802.11g protection is enabled, determine whether 3784 * to use RTS/CTS or just CTS. Note that this is only 3785 * done for OFDM unicast frames. 3786 */ 3787 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3788 rt->info[rix].phy == IEEE80211_T_OFDM && 3789 (flags & HAL_TXDESC_NOACK) == 0) { 3790 /* XXX fragments must use CCK rates w/ protection */ 3791 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3792 flags |= HAL_TXDESC_RTSENA; 3793 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3794 flags |= HAL_TXDESC_CTSENA; 3795 cix = rt->info[sc->sc_protrix].controlRate; 3796 sc->sc_stats.ast_tx_protect++; 3797 } 3798 3799 /* 3800 * Calculate duration. This logically belongs in the 802.11 3801 * layer but it lacks sufficient information to calculate it. 3802 */ 3803 if ((flags & HAL_TXDESC_NOACK) == 0 && 3804 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3805 u_int16_t dur; 3806 /* 3807 * XXX not right with fragmentation. 3808 */ 3809 if (shortPreamble) 3810 dur = rt->info[rix].spAckDuration; 3811 else 3812 dur = rt->info[rix].lpAckDuration; 3813 *(u_int16_t *)wh->i_dur = htole16(dur); 3814 } 3815 3816 /* 3817 * Calculate RTS/CTS rate and duration if needed. 3818 */ 3819 ctsduration = 0; 3820 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3821 /* 3822 * CTS transmit rate is derived from the transmit rate 3823 * by looking in the h/w rate table. We must also factor 3824 * in whether or not a short preamble is to be used. 3825 */ 3826 /* NB: cix is set above where RTS/CTS is enabled */ 3827 KASSERT(cix != 0xff, ("cix not setup")); 3828 ctsrate = rt->info[cix].rateCode; 3829 /* 3830 * Compute the transmit duration based on the frame 3831 * size and the size of an ACK frame. We call into the 3832 * HAL to do the computation since it depends on the 3833 * characteristics of the actual PHY being used. 3834 * 3835 * NB: CTS is assumed the same size as an ACK so we can 3836 * use the precalculated ACK durations. 3837 */ 3838 if (shortPreamble) { 3839 ctsrate |= rt->info[cix].shortPreamble; 3840 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3841 ctsduration += rt->info[cix].spAckDuration; 3842 ctsduration += ath_hal_computetxtime(ah, 3843 rt, pktlen, rix, AH_TRUE); 3844 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3845 ctsduration += rt->info[rix].spAckDuration; 3846 } else { 3847 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3848 ctsduration += rt->info[cix].lpAckDuration; 3849 ctsduration += ath_hal_computetxtime(ah, 3850 rt, pktlen, rix, AH_FALSE); 3851 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3852 ctsduration += rt->info[rix].lpAckDuration; 3853 } 3854 /* 3855 * Must disable multi-rate retry when using RTS/CTS. 3856 */ 3857 ismrr = 0; 3858 try0 = ATH_TXMGTTRY; /* XXX */ 3859 } else 3860 ctsrate = 0; 3861 3862 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3863 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3864 sc->sc_hwmap[txrate].ieeerate, -1); 3865 3866 if (bpf_peers_present(ic->ic_rawbpf)) 3867 bpf_mtap(ic->ic_rawbpf, m0); 3868 if (bpf_peers_present(sc->sc_drvbpf)) { 3869 u_int64_t tsf = ath_hal_gettsf64(ah); 3870 3871 sc->sc_tx_th.wt_tsf = htole64(tsf); 3872 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3873 if (iswep) 3874 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3875 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3876 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3877 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3878 3879 bpf_mtap2(sc->sc_drvbpf, 3880 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3881 } 3882 3883 /* 3884 * Determine if a tx interrupt should be generated for 3885 * this descriptor. We take a tx interrupt to reap 3886 * descriptors when the h/w hits an EOL condition or 3887 * when the descriptor is specifically marked to generate 3888 * an interrupt. We periodically mark descriptors in this 3889 * way to insure timely replenishing of the supply needed 3890 * for sending frames. Defering interrupts reduces system 3891 * load and potentially allows more concurrent work to be 3892 * done but if done to aggressively can cause senders to 3893 * backup. 3894 * 3895 * NB: use >= to deal with sc_txintrperiod changing 3896 * dynamically through sysctl. 3897 */ 3898 if (flags & HAL_TXDESC_INTREQ) { 3899 txq->axq_intrcnt = 0; 3900 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3901 flags |= HAL_TXDESC_INTREQ; 3902 txq->axq_intrcnt = 0; 3903 } 3904 3905 /* 3906 * Formulate first tx descriptor with tx controls. 3907 */ 3908 /* XXX check return value? */ 3909 ath_hal_setuptxdesc(ah, ds 3910 , pktlen /* packet length */ 3911 , hdrlen /* header length */ 3912 , atype /* Atheros packet type */ 3913 , ni->ni_txpower /* txpower */ 3914 , txrate, try0 /* series 0 rate/tries */ 3915 , keyix /* key cache index */ 3916 , sc->sc_txantenna /* antenna mode */ 3917 , flags /* flags */ 3918 , ctsrate /* rts/cts rate */ 3919 , ctsduration /* rts/cts duration */ 3920 ); 3921 bf->bf_flags = flags; 3922 /* 3923 * Setup the multi-rate retry state only when we're 3924 * going to use it. This assumes ath_hal_setuptxdesc 3925 * initializes the descriptors (so we don't have to) 3926 * when the hardware supports multi-rate retry and 3927 * we don't use it. 3928 */ 3929 if (ismrr) 3930 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3931 3932 ath_tx_handoff(sc, txq, bf); 3933 return 0; 3934} 3935 3936/* 3937 * Process completed xmit descriptors from the specified queue. 3938 */ 3939static int 3940ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3941{ 3942 struct ath_hal *ah = sc->sc_ah; 3943 struct ieee80211com *ic = &sc->sc_ic; 3944 struct ath_buf *bf; 3945 struct ath_desc *ds, *ds0; 3946 struct ath_tx_status *ts; 3947 struct ieee80211_node *ni; 3948 struct ath_node *an; 3949 int sr, lr, pri, nacked; 3950 HAL_STATUS status; 3951 3952 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3953 __func__, txq->axq_qnum, 3954 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3955 txq->axq_link); 3956 nacked = 0; 3957 for (;;) { 3958 ATH_TXQ_LOCK(txq); 3959 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3960 bf = STAILQ_FIRST(&txq->axq_q); 3961 if (bf == NULL) { 3962 ATH_TXQ_UNLOCK(txq); 3963 break; 3964 } 3965 ds0 = &bf->bf_desc[0]; 3966 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3967 ts = &bf->bf_status.ds_txstat; 3968 status = ath_hal_txprocdesc(ah, ds, ts); 3969#ifdef ATH_DEBUG 3970 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3971 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK); 3972#endif 3973 if (status == HAL_EINPROGRESS) { 3974 ATH_TXQ_UNLOCK(txq); 3975 break; 3976 } 3977 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3978 if (txq->axq_depth == 0) 3979 txq->axq_link = NULL; 3980 ATH_TXQ_UNLOCK(txq); 3981 3982 ni = bf->bf_node; 3983 if (ni != NULL) { 3984 an = ATH_NODE(ni); 3985 if (ts->ts_status == 0) { 3986 u_int8_t txant = ts->ts_antenna; 3987 sc->sc_stats.ast_ant_tx[txant]++; 3988 sc->sc_ant_tx[txant]++; 3989 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 3990 sc->sc_stats.ast_tx_altrate++; 3991 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 3992 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3993 ts->ts_rssi); 3994 pri = M_WME_GETAC(bf->bf_m); 3995 if (pri >= WME_AC_VO) 3996 ic->ic_wme.wme_hipri_traffic++; 3997 ni->ni_inact = ni->ni_inact_reload; 3998 } else { 3999 if (ts->ts_status & HAL_TXERR_XRETRY) 4000 sc->sc_stats.ast_tx_xretries++; 4001 if (ts->ts_status & HAL_TXERR_FIFO) 4002 sc->sc_stats.ast_tx_fifoerr++; 4003 if (ts->ts_status & HAL_TXERR_FILT) 4004 sc->sc_stats.ast_tx_filtered++; 4005 } 4006 sr = ts->ts_shortretry; 4007 lr = ts->ts_longretry; 4008 sc->sc_stats.ast_tx_shortretry += sr; 4009 sc->sc_stats.ast_tx_longretry += lr; 4010 /* 4011 * Hand the descriptor to the rate control algorithm. 4012 */ 4013 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4014 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4015 /* 4016 * If frame was ack'd update the last rx time 4017 * used to workaround phantom bmiss interrupts. 4018 */ 4019 if (ts->ts_status == 0) 4020 nacked++; 4021 ath_rate_tx_complete(sc, an, bf); 4022 } 4023 /* 4024 * Reclaim reference to node. 4025 * 4026 * NB: the node may be reclaimed here if, for example 4027 * this is a DEAUTH message that was sent and the 4028 * node was timed out due to inactivity. 4029 */ 4030 ieee80211_free_node(ni); 4031 } 4032 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4033 BUS_DMASYNC_POSTWRITE); 4034 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4035 m_freem(bf->bf_m); 4036 bf->bf_m = NULL; 4037 bf->bf_node = NULL; 4038 4039 ATH_TXBUF_LOCK(sc); 4040 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4041 ATH_TXBUF_UNLOCK(sc); 4042 } 4043 return nacked; 4044} 4045 4046static __inline int 4047txqactive(struct ath_hal *ah, int qnum) 4048{ 4049 u_int32_t txqs = 1<<qnum; 4050 ath_hal_gettxintrtxqs(ah, &txqs); 4051 return (txqs & (1<<qnum)); 4052} 4053 4054/* 4055 * Deferred processing of transmit interrupt; special-cased 4056 * for a single hardware transmit queue (e.g. 5210 and 5211). 4057 */ 4058static void 4059ath_tx_proc_q0(void *arg, int npending) 4060{ 4061 struct ath_softc *sc = arg; 4062 struct ifnet *ifp = sc->sc_ifp; 4063 4064 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 4065 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4066 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4067 ath_tx_processq(sc, sc->sc_cabq); 4068 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4069 sc->sc_tx_timer = 0; 4070 4071 if (sc->sc_softled) 4072 ath_led_event(sc, ATH_LED_TX); 4073 4074 ath_start(ifp); 4075} 4076 4077/* 4078 * Deferred processing of transmit interrupt; special-cased 4079 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4080 */ 4081static void 4082ath_tx_proc_q0123(void *arg, int npending) 4083{ 4084 struct ath_softc *sc = arg; 4085 struct ifnet *ifp = sc->sc_ifp; 4086 int nacked; 4087 4088 /* 4089 * Process each active queue. 4090 */ 4091 nacked = 0; 4092 if (txqactive(sc->sc_ah, 0)) 4093 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4094 if (txqactive(sc->sc_ah, 1)) 4095 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4096 if (txqactive(sc->sc_ah, 2)) 4097 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4098 if (txqactive(sc->sc_ah, 3)) 4099 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4100 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4101 ath_tx_processq(sc, sc->sc_cabq); 4102 if (nacked) 4103 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4104 4105 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4106 sc->sc_tx_timer = 0; 4107 4108 if (sc->sc_softled) 4109 ath_led_event(sc, ATH_LED_TX); 4110 4111 ath_start(ifp); 4112} 4113 4114/* 4115 * Deferred processing of transmit interrupt. 4116 */ 4117static void 4118ath_tx_proc(void *arg, int npending) 4119{ 4120 struct ath_softc *sc = arg; 4121 struct ifnet *ifp = sc->sc_ifp; 4122 int i, nacked; 4123 4124 /* 4125 * Process each active queue. 4126 */ 4127 nacked = 0; 4128 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4129 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4130 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4131 if (nacked) 4132 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4133 4134 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4135 sc->sc_tx_timer = 0; 4136 4137 if (sc->sc_softled) 4138 ath_led_event(sc, ATH_LED_TX); 4139 4140 ath_start(ifp); 4141} 4142 4143static void 4144ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4145{ 4146#ifdef ATH_DEBUG 4147 struct ath_hal *ah = sc->sc_ah; 4148#endif 4149 struct ieee80211_node *ni; 4150 struct ath_buf *bf; 4151 u_int ix; 4152 4153 /* 4154 * NB: this assumes output has been stopped and 4155 * we do not need to block ath_tx_tasklet 4156 */ 4157 for (ix = 0;; ix++) { 4158 ATH_TXQ_LOCK(txq); 4159 bf = STAILQ_FIRST(&txq->axq_q); 4160 if (bf == NULL) { 4161 txq->axq_link = NULL; 4162 ATH_TXQ_UNLOCK(txq); 4163 break; 4164 } 4165 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4166 ATH_TXQ_UNLOCK(txq); 4167#ifdef ATH_DEBUG 4168 if (sc->sc_debug & ATH_DEBUG_RESET) { 4169 ath_printtxbuf(bf, txq->axq_qnum, ix, 4170 ath_hal_txprocdesc(ah, bf->bf_desc, 4171 &bf->bf_status.ds_txstat) == HAL_OK); 4172 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t), 4173 bf->bf_m->m_len, 0, -1); 4174 } 4175#endif /* ATH_DEBUG */ 4176 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4177 m_freem(bf->bf_m); 4178 bf->bf_m = NULL; 4179 ni = bf->bf_node; 4180 bf->bf_node = NULL; 4181 if (ni != NULL) { 4182 /* 4183 * Reclaim node reference. 4184 */ 4185 ieee80211_free_node(ni); 4186 } 4187 ATH_TXBUF_LOCK(sc); 4188 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4189 ATH_TXBUF_UNLOCK(sc); 4190 } 4191} 4192 4193static void 4194ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4195{ 4196 struct ath_hal *ah = sc->sc_ah; 4197 4198 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4199 __func__, txq->axq_qnum, 4200 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4201 txq->axq_link); 4202 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4203} 4204 4205/* 4206 * Drain the transmit queues and reclaim resources. 4207 */ 4208static void 4209ath_draintxq(struct ath_softc *sc) 4210{ 4211 struct ath_hal *ah = sc->sc_ah; 4212 struct ifnet *ifp = sc->sc_ifp; 4213 int i; 4214 4215 /* XXX return value */ 4216 if (!sc->sc_invalid) { 4217 /* don't touch the hardware if marked invalid */ 4218 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4219 __func__, sc->sc_bhalq, 4220 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4221 NULL); 4222 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4223 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4224 if (ATH_TXQ_SETUP(sc, i)) 4225 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4226 } 4227 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4228 if (ATH_TXQ_SETUP(sc, i)) 4229 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4230 ath_tx_draintxq(sc, &sc->sc_mcastq); 4231#ifdef ATH_DEBUG 4232 if (sc->sc_debug & ATH_DEBUG_RESET) { 4233 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 4234 if (bf != NULL && bf->bf_m != NULL) { 4235 ath_printtxbuf(bf, sc->sc_bhalq, 0, 4236 ath_hal_txprocdesc(ah, bf->bf_desc, 4237 &bf->bf_status.ds_txstat) == HAL_OK); 4238 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t), 4239 bf->bf_m->m_len, 0, -1); 4240 } 4241 } 4242#endif /* ATH_DEBUG */ 4243 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4244 sc->sc_tx_timer = 0; 4245} 4246 4247/* 4248 * Disable the receive h/w in preparation for a reset. 4249 */ 4250static void 4251ath_stoprecv(struct ath_softc *sc) 4252{ 4253#define PA2DESC(_sc, _pa) \ 4254 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4255 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4256 struct ath_hal *ah = sc->sc_ah; 4257 4258 ath_hal_stoppcurecv(ah); /* disable PCU */ 4259 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4260 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4261 DELAY(3000); /* 3ms is long enough for 1 frame */ 4262#ifdef ATH_DEBUG 4263 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4264 struct ath_buf *bf; 4265 u_int ix; 4266 4267 printf("%s: rx queue %p, link %p\n", __func__, 4268 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4269 ix = 0; 4270 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4271 struct ath_desc *ds = bf->bf_desc; 4272 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 4273 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4274 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 4275 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4276 ath_printrxbuf(bf, ix, status == HAL_OK); 4277 ix++; 4278 } 4279 } 4280#endif 4281 sc->sc_rxlink = NULL; /* just in case */ 4282#undef PA2DESC 4283} 4284 4285/* 4286 * Enable the receive h/w following a reset. 4287 */ 4288static int 4289ath_startrecv(struct ath_softc *sc) 4290{ 4291 struct ath_hal *ah = sc->sc_ah; 4292 struct ath_buf *bf; 4293 4294 sc->sc_rxlink = NULL; 4295 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4296 int error = ath_rxbuf_init(sc, bf); 4297 if (error != 0) { 4298 DPRINTF(sc, ATH_DEBUG_RECV, 4299 "%s: ath_rxbuf_init failed %d\n", 4300 __func__, error); 4301 return error; 4302 } 4303 } 4304 4305 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4306 ath_hal_putrxbuf(ah, bf->bf_daddr); 4307 ath_hal_rxena(ah); /* enable recv descriptors */ 4308 ath_mode_init(sc); /* set filters, etc. */ 4309 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4310 return 0; 4311} 4312 4313/* 4314 * Update internal state after a channel change. 4315 */ 4316static void 4317ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4318{ 4319 struct ieee80211com *ic = &sc->sc_ic; 4320 enum ieee80211_phymode mode; 4321 u_int16_t flags; 4322 4323 /* 4324 * Change channels and update the h/w rate map 4325 * if we're switching; e.g. 11a to 11b/g. 4326 */ 4327 if (IEEE80211_IS_CHAN_HALF(chan)) 4328 mode = IEEE80211_MODE_HALF; 4329 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 4330 mode = IEEE80211_MODE_QUARTER; 4331 else 4332 mode = ieee80211_chan2mode(ic, chan); 4333 if (mode != sc->sc_curmode) 4334 ath_setcurmode(sc, mode); 4335 /* 4336 * Update BPF state. NB: ethereal et. al. don't handle 4337 * merged flags well so pick a unique mode for their use. 4338 */ 4339 if (IEEE80211_IS_CHAN_A(chan)) 4340 flags = IEEE80211_CHAN_A; 4341 /* XXX 11g schizophrenia */ 4342 else if (IEEE80211_IS_CHAN_ANYG(chan)) 4343 flags = IEEE80211_CHAN_G; 4344 else 4345 flags = IEEE80211_CHAN_B; 4346 if (IEEE80211_IS_CHAN_T(chan)) 4347 flags |= IEEE80211_CHAN_TURBO; 4348 if (IEEE80211_IS_CHAN_HALF(chan)) 4349 flags |= IEEE80211_CHAN_HALF; 4350 if (IEEE80211_IS_CHAN_QUARTER(chan)) 4351 flags |= IEEE80211_CHAN_QUARTER; 4352 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4353 htole16(chan->ic_freq); 4354 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4355 htole16(flags); 4356} 4357 4358/* 4359 * Poll for a channel clear indication; this is required 4360 * for channels requiring DFS and not previously visited 4361 * and/or with a recent radar detection. 4362 */ 4363static void 4364ath_dfswait(void *arg) 4365{ 4366 struct ath_softc *sc = arg; 4367 struct ath_hal *ah = sc->sc_ah; 4368 HAL_CHANNEL hchan; 4369 4370 ath_hal_radar_wait(ah, &hchan); 4371 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n", 4372 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags); 4373 4374 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4375 if_printf(sc->sc_ifp, 4376 "channel %u/0x%x/0x%x has interference\n", 4377 hchan.channel, hchan.channelFlags, hchan.privFlags); 4378 return; 4379 } 4380 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4381 /* XXX should not happen */ 4382 return; 4383 } 4384 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4385 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4386 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4387 if_printf(sc->sc_ifp, 4388 "channel %u/0x%x/0x%x marked clear\n", 4389 hchan.channel, hchan.channelFlags, hchan.privFlags); 4390 } else 4391 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4392} 4393 4394/* 4395 * Set/change channels. If the channel is really being changed, 4396 * it's done by reseting the chip. To accomplish this we must 4397 * first cleanup any pending DMA, then restart stuff after a la 4398 * ath_init. 4399 */ 4400static int 4401ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4402{ 4403 struct ath_hal *ah = sc->sc_ah; 4404 struct ieee80211com *ic = &sc->sc_ic; 4405 HAL_CHANNEL hchan; 4406 4407 /* 4408 * Convert to a HAL channel description with 4409 * the flags constrained to reflect the current 4410 * operating mode. 4411 */ 4412 ath_mapchan(ic, &hchan, chan); 4413 4414 DPRINTF(sc, ATH_DEBUG_RESET, 4415 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4416 __func__, 4417 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4418 sc->sc_curchan.channelFlags), 4419 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4420 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4421 hchan.channel, hchan.channelFlags); 4422 if (hchan.channel != sc->sc_curchan.channel || 4423 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4424 HAL_STATUS status; 4425 4426 /* 4427 * To switch channels clear any pending DMA operations; 4428 * wait long enough for the RX fifo to drain, reset the 4429 * hardware at the new frequency, and then re-enable 4430 * the relevant bits of the h/w. 4431 */ 4432 ath_hal_intrset(ah, 0); /* disable interrupts */ 4433 ath_draintxq(sc); /* clear pending tx frames */ 4434 ath_stoprecv(sc); /* turn off frame recv */ 4435 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) { 4436 if_printf(ic->ic_ifp, "%s: unable to reset " 4437 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n", 4438 __func__, ieee80211_chan2ieee(ic, chan), 4439 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4440 return EIO; 4441 } 4442 sc->sc_curchan = hchan; 4443 ath_update_txpow(sc); /* update tx power state */ 4444 sc->sc_diversity = ath_hal_getdiversity(ah); 4445 sc->sc_calinterval = 1; 4446 sc->sc_caltries = 0; 4447 4448 /* 4449 * Re-enable rx framework. 4450 */ 4451 if (ath_startrecv(sc) != 0) { 4452 if_printf(ic->ic_ifp, 4453 "%s: unable to restart recv logic\n", __func__); 4454 return EIO; 4455 } 4456 4457 /* 4458 * Change channels and update the h/w rate map 4459 * if we're switching; e.g. 11a to 11b/g. 4460 */ 4461 ic->ic_ibss_chan = chan; 4462 ath_chan_change(sc, chan); 4463 4464 /* 4465 * Handle DFS required waiting period to determine 4466 * if channel is clear of radar traffic. 4467 */ 4468 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4469#define DFS_AND_NOT_CLEAR(_c) \ 4470 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4471 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4472 if_printf(sc->sc_ifp, 4473 "wait for DFS clear channel signal\n"); 4474 /* XXX stop sndq */ 4475 sc->sc_ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4476 callout_reset(&sc->sc_dfs_ch, 4477 2 * hz, ath_dfswait, sc); 4478 } else 4479 callout_stop(&sc->sc_dfs_ch); 4480#undef DFS_NOT_CLEAR 4481 } 4482 4483 /* 4484 * Re-enable interrupts. 4485 */ 4486 ath_hal_intrset(ah, sc->sc_imask); 4487 } 4488 return 0; 4489} 4490 4491static void 4492ath_next_scan(void *arg) 4493{ 4494 struct ath_softc *sc = arg; 4495 struct ieee80211com *ic = &sc->sc_ic; 4496 4497 if (ic->ic_state == IEEE80211_S_SCAN) 4498 ieee80211_next_scan(ic); 4499} 4500 4501/* 4502 * Periodically recalibrate the PHY to account 4503 * for temperature/environment changes. 4504 */ 4505static void 4506ath_calibrate(void *arg) 4507{ 4508 struct ath_softc *sc = arg; 4509 struct ath_hal *ah = sc->sc_ah; 4510 HAL_BOOL iqCalDone; 4511 4512 sc->sc_stats.ast_per_cal++; 4513 4514 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4515 /* 4516 * Rfgain is out of bounds, reset the chip 4517 * to load new gain values. 4518 */ 4519 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4520 "%s: rfgain change\n", __func__); 4521 sc->sc_stats.ast_per_rfgain++; 4522 ath_reset(sc->sc_ifp); 4523 } 4524 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4525 DPRINTF(sc, ATH_DEBUG_ANY, 4526 "%s: calibration of channel %u failed\n", 4527 __func__, sc->sc_curchan.channel); 4528 sc->sc_stats.ast_per_calfail++; 4529 } 4530 /* 4531 * Calibrate noise floor data again in case of change. 4532 */ 4533 ath_hal_process_noisefloor(ah); 4534 /* 4535 * Poll more frequently when the IQ calibration is in 4536 * progress to speedup loading the final settings. 4537 * We temper this aggressive polling with an exponential 4538 * back off after 4 tries up to ath_calinterval. 4539 */ 4540 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4541 sc->sc_caltries = 0; 4542 sc->sc_calinterval = ath_calinterval; 4543 } else if (sc->sc_caltries > 4) { 4544 sc->sc_caltries = 0; 4545 sc->sc_calinterval <<= 1; 4546 if (sc->sc_calinterval > ath_calinterval) 4547 sc->sc_calinterval = ath_calinterval; 4548 } 4549 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4550 ("bad calibration interval %u", sc->sc_calinterval)); 4551 4552 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4553 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4554 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4555 sc->sc_caltries++; 4556 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4557 ath_calibrate, sc); 4558} 4559 4560static int 4561ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4562{ 4563 struct ifnet *ifp = ic->ic_ifp; 4564 struct ath_softc *sc = ifp->if_softc; 4565 struct ath_hal *ah = sc->sc_ah; 4566 struct ieee80211_node *ni; 4567 int i, error; 4568 const u_int8_t *bssid; 4569 u_int32_t rfilt; 4570 static const HAL_LED_STATE leds[] = { 4571 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4572 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4573 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4574 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4575 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4576 }; 4577 4578 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4579 ieee80211_state_name[ic->ic_state], 4580 ieee80211_state_name[nstate]); 4581 4582 callout_stop(&sc->sc_scan_ch); 4583 callout_stop(&sc->sc_cal_ch); 4584 callout_stop(&sc->sc_dfs_ch); 4585 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4586 4587 if (nstate == IEEE80211_S_INIT) { 4588 /* 4589 * Shutdown host/driver operation: 4590 * o disable interrupts so we don't rx frames 4591 * o clean any pending items on the task q 4592 * o notify the rate control algorithm 4593 */ 4594 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4595 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4596#if 0 4597 /* XXX can't use taskqueue_drain 'cuz we're holding sc_mtx */ 4598 taskqueue_drain(sc->sc_tq, &sc->sc_rxtask); 4599 taskqueue_drain(sc->sc_tq, &sc->sc_rxorntask); 4600 taskqueue_drain(sc->sc_tq, &sc->sc_bmisstask); 4601 taskqueue_drain(sc->sc_tq, &sc->sc_bstucktask); 4602#endif 4603 ath_rate_newstate(sc, nstate); 4604 goto done; 4605 } 4606 ni = ic->ic_bss; 4607 error = ath_chan_set(sc, ic->ic_curchan); 4608 if (error != 0) 4609 goto bad; 4610 rfilt = ath_calcrxfilter(sc, nstate); 4611 if (nstate == IEEE80211_S_SCAN) 4612 bssid = ifp->if_broadcastaddr; 4613 else 4614 bssid = ni->ni_bssid; 4615 ath_hal_setrxfilter(ah, rfilt); 4616 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4617 __func__, rfilt, ether_sprintf(bssid)); 4618 4619 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4620 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4621 else 4622 ath_hal_setassocid(ah, bssid, 0); 4623 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4624 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4625 if (ath_hal_keyisvalid(ah, i)) 4626 ath_hal_keysetmac(ah, i, bssid); 4627 } 4628 4629 /* 4630 * Notify the rate control algorithm so rates 4631 * are setup should ath_beacon_alloc be called. 4632 */ 4633 ath_rate_newstate(sc, nstate); 4634 4635 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4636 /* nothing to do */; 4637 } else if (nstate == IEEE80211_S_RUN) { 4638 DPRINTF(sc, ATH_DEBUG_STATE, 4639 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4640 "capinfo=0x%04x chan=%d\n" 4641 , __func__ 4642 , ic->ic_flags 4643 , ni->ni_intval 4644 , ether_sprintf(ni->ni_bssid) 4645 , ni->ni_capinfo 4646 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4647 4648 switch (ic->ic_opmode) { 4649 case IEEE80211_M_HOSTAP: 4650 case IEEE80211_M_IBSS: 4651 /* 4652 * Allocate and setup the beacon frame. 4653 * 4654 * Stop any previous beacon DMA. This may be 4655 * necessary, for example, when an ibss merge 4656 * causes reconfiguration; there will be a state 4657 * transition from RUN->RUN that means we may 4658 * be called with beacon transmission active. 4659 */ 4660 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4661 ath_beacon_free(sc); 4662 error = ath_beacon_alloc(sc, ni); 4663 if (error != 0) 4664 goto bad; 4665 /* 4666 * If joining an adhoc network defer beacon timer 4667 * configuration to the next beacon frame so we 4668 * have a current TSF to use. Otherwise we're 4669 * starting an ibss/bss so there's no need to delay. 4670 */ 4671 if (ic->ic_opmode == IEEE80211_M_IBSS && 4672 ic->ic_bss->ni_tstamp.tsf != 0) 4673 sc->sc_syncbeacon = 1; 4674 else 4675 ath_beacon_config(sc); 4676 break; 4677 case IEEE80211_M_STA: 4678 /* 4679 * Allocate a key cache slot to the station. 4680 */ 4681 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4682 sc->sc_hasclrkey && 4683 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4684 ath_setup_stationkey(ni); 4685 /* 4686 * Defer beacon timer configuration to the next 4687 * beacon frame so we have a current TSF to use 4688 * (any TSF collected when scanning is likely old). 4689 */ 4690 sc->sc_syncbeacon = 1; 4691 break; 4692 default: 4693 break; 4694 } 4695 4696 /* 4697 * Let the hal process statistics collected during a 4698 * scan so it can provide calibrated noise floor data. 4699 */ 4700 ath_hal_process_noisefloor(ah); 4701 /* 4702 * Reset rssi stats; maybe not the best place... 4703 */ 4704 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4705 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4706 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4707 } else { 4708 ath_hal_intrset(ah, 4709 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4710 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4711 } 4712done: 4713 /* 4714 * Invoke the parent method to complete the work. 4715 */ 4716 error = sc->sc_newstate(ic, nstate, arg); 4717 /* 4718 * Finally, start any timers. 4719 */ 4720 if (nstate == IEEE80211_S_RUN) { 4721 /* start periodic recalibration timer */ 4722 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4723 ath_calibrate, sc); 4724 } else if (nstate == IEEE80211_S_SCAN) { 4725 /* start ap/neighbor scan timer */ 4726 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4727 ath_next_scan, sc); 4728 } 4729bad: 4730 return error; 4731} 4732 4733/* 4734 * Allocate a key cache slot to the station so we can 4735 * setup a mapping from key index to node. The key cache 4736 * slot is needed for managing antenna state and for 4737 * compression when stations do not use crypto. We do 4738 * it uniliaterally here; if crypto is employed this slot 4739 * will be reassigned. 4740 */ 4741static void 4742ath_setup_stationkey(struct ieee80211_node *ni) 4743{ 4744 struct ieee80211com *ic = ni->ni_ic; 4745 struct ath_softc *sc = ic->ic_ifp->if_softc; 4746 ieee80211_keyix keyix, rxkeyix; 4747 4748 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4749 /* 4750 * Key cache is full; we'll fall back to doing 4751 * the more expensive lookup in software. Note 4752 * this also means no h/w compression. 4753 */ 4754 /* XXX msg+statistic */ 4755 } else { 4756 /* XXX locking? */ 4757 ni->ni_ucastkey.wk_keyix = keyix; 4758 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4759 /* NB: this will create a pass-thru key entry */ 4760 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4761 } 4762} 4763 4764/* 4765 * Setup driver-specific state for a newly associated node. 4766 * Note that we're called also on a re-associate, the isnew 4767 * param tells us if this is the first time or not. 4768 */ 4769static void 4770ath_newassoc(struct ieee80211_node *ni, int isnew) 4771{ 4772 struct ieee80211com *ic = ni->ni_ic; 4773 struct ath_softc *sc = ic->ic_ifp->if_softc; 4774 4775 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4776 if (isnew && 4777 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4778 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4779 ("new assoc with a unicast key already setup (keyix %u)", 4780 ni->ni_ucastkey.wk_keyix)); 4781 ath_setup_stationkey(ni); 4782 } 4783} 4784 4785static int 4786ath_getchannels(struct ath_softc *sc, 4787 HAL_REG_DOMAIN rd, HAL_CTRY_CODE cc, HAL_BOOL outdoor, HAL_BOOL xchanmode) 4788{ 4789#define COMPAT \ 4790 (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE|CHANNEL_HALF|CHANNEL_QUARTER) 4791#define IS_CHAN_PUBLIC_SAFETY(_c) \ 4792 (((_c)->channelFlags & CHANNEL_5GHZ) && \ 4793 ((_c)->channel > 4940 && (_c)->channel < 4990)) 4794 struct ieee80211com *ic = &sc->sc_ic; 4795 struct ifnet *ifp = sc->sc_ifp; 4796 struct ath_hal *ah = sc->sc_ah; 4797 HAL_CHANNEL *chans; 4798 int i, ix, nchan; 4799 u_int32_t regdomain; 4800 4801 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4802 M_TEMP, M_NOWAIT); 4803 if (chans == NULL) { 4804 if_printf(ifp, "unable to allocate channel table\n"); 4805 return ENOMEM; 4806 } 4807 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4808 NULL, 0, NULL, cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4809 (void) ath_hal_getregdomain(ah, ®domain); 4810 if_printf(ifp, "unable to collect channel list from hal; " 4811 "regdomain likely %u country code %u\n", regdomain, cc); 4812 free(chans, M_TEMP); 4813 return EINVAL; 4814 } 4815 4816 /* 4817 * Convert HAL channels to ieee80211 ones and insert 4818 * them in the table according to their channel number. 4819 */ 4820 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 4821 for (i = 0; i < nchan; i++) { 4822 HAL_CHANNEL *c = &chans[i]; 4823 u_int16_t flags; 4824 4825 /* 4826 * XXX we're not ready to handle the ieee number mapping 4827 * for public safety channels as they overlap with any 4828 * 2GHz channels; for now use a non-public safety 4829 * numbering that is non-overlapping. 4830 */ 4831 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4832 if (IS_CHAN_PUBLIC_SAFETY(c)) 4833 ix += 37; /* XXX */ 4834 if (ix > IEEE80211_CHAN_MAX) { 4835 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4836 ix, c->channel, c->channelFlags); 4837 continue; 4838 } 4839 if (ix < 0) { 4840 /* XXX can't handle stuff <2400 right now */ 4841 if (bootverbose) 4842 if_printf(ifp, "hal channel %d (%u/%x) " 4843 "cannot be handled; ignored\n", 4844 ix, c->channel, c->channelFlags); 4845 continue; 4846 } 4847 if (bootverbose) 4848 if_printf(ifp, "hal channel %u/%x -> %u\n", 4849 c->channel, c->channelFlags, ix); 4850 /* 4851 * Calculate net80211 flags; most are compatible 4852 * but some need massaging. Note the static turbo 4853 * conversion can be removed once net80211 is updated 4854 * to understand static vs. dynamic turbo. 4855 */ 4856 flags = c->channelFlags & COMPAT; 4857 if (c->channelFlags & CHANNEL_STURBO) 4858 flags |= IEEE80211_CHAN_TURBO; 4859 if (ath_hal_isgsmsku(ah)) { 4860 /* remap to true frequencies */ 4861 c->channel = 922 + (2422 - c->channel); 4862 flags |= IEEE80211_CHAN_GSM; 4863 ix = ieee80211_mhz2ieee(c->channel, flags); 4864 } 4865 if (ic->ic_channels[ix].ic_freq == 0) { 4866 ic->ic_channels[ix].ic_freq = c->channel; 4867 ic->ic_channels[ix].ic_flags = flags; 4868 } else { 4869 /* channels overlap; e.g. 11g and 11b */ 4870 ic->ic_channels[ix].ic_flags |= flags; 4871 } 4872 } 4873 free(chans, M_TEMP); 4874 (void) ath_hal_getregdomain(ah, &sc->sc_regdomain); 4875 ath_hal_getcountrycode(ah, &sc->sc_countrycode); 4876 sc->sc_xchanmode = xchanmode; 4877 sc->sc_outdoor = outdoor; 4878 return 0; 4879#undef IS_CHAN_PUBLIC_SAFETY 4880#undef COMPAT 4881} 4882 4883static void 4884ath_led_done(void *arg) 4885{ 4886 struct ath_softc *sc = arg; 4887 4888 sc->sc_blinking = 0; 4889} 4890 4891/* 4892 * Turn the LED off: flip the pin and then set a timer so no 4893 * update will happen for the specified duration. 4894 */ 4895static void 4896ath_led_off(void *arg) 4897{ 4898 struct ath_softc *sc = arg; 4899 4900 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4901 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4902} 4903 4904/* 4905 * Blink the LED according to the specified on/off times. 4906 */ 4907static void 4908ath_led_blink(struct ath_softc *sc, int on, int off) 4909{ 4910 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4911 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4912 sc->sc_blinking = 1; 4913 sc->sc_ledoff = off; 4914 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4915} 4916 4917static void 4918ath_led_event(struct ath_softc *sc, int event) 4919{ 4920 4921 sc->sc_ledevent = ticks; /* time of last event */ 4922 if (sc->sc_blinking) /* don't interrupt active blink */ 4923 return; 4924 switch (event) { 4925 case ATH_LED_POLL: 4926 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4927 sc->sc_hwmap[0].ledoff); 4928 break; 4929 case ATH_LED_TX: 4930 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4931 sc->sc_hwmap[sc->sc_txrate].ledoff); 4932 break; 4933 case ATH_LED_RX: 4934 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4935 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4936 break; 4937 } 4938} 4939 4940static void 4941ath_update_txpow(struct ath_softc *sc) 4942{ 4943 struct ieee80211com *ic = &sc->sc_ic; 4944 struct ath_hal *ah = sc->sc_ah; 4945 u_int32_t txpow; 4946 4947 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4948 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4949 /* read back in case value is clamped */ 4950 if (ath_hal_gettxpowlimit(ah, &txpow)) 4951 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4952 } 4953 /* 4954 * Fetch max tx power level for status requests. 4955 */ 4956 if (ath_hal_getmaxtxpow(sc->sc_ah, &txpow)) 4957 ic->ic_bss->ni_txpower = txpow; 4958} 4959 4960static int 4961ath_rate_setup(struct ath_softc *sc, u_int mode) 4962{ 4963 struct ath_hal *ah = sc->sc_ah; 4964 const HAL_RATE_TABLE *rt; 4965 4966 switch (mode) { 4967 case IEEE80211_MODE_11A: 4968 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4969 break; 4970 case IEEE80211_MODE_HALF: 4971 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 4972 break; 4973 case IEEE80211_MODE_QUARTER: 4974 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 4975 break; 4976 case IEEE80211_MODE_11B: 4977 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4978 break; 4979 case IEEE80211_MODE_11G: 4980 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4981 break; 4982 case IEEE80211_MODE_TURBO_A: 4983 /* XXX until static/dynamic turbo is fixed */ 4984 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4985 break; 4986 case IEEE80211_MODE_TURBO_G: 4987 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4988 break; 4989 default: 4990 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4991 __func__, mode); 4992 return 0; 4993 } 4994 sc->sc_rates[mode] = rt; 4995 return (rt != NULL); 4996} 4997 4998static void 4999ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5000{ 5001#define N(a) (sizeof(a)/sizeof(a[0])) 5002 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5003 static const struct { 5004 u_int rate; /* tx/rx 802.11 rate */ 5005 u_int16_t timeOn; /* LED on time (ms) */ 5006 u_int16_t timeOff; /* LED off time (ms) */ 5007 } blinkrates[] = { 5008 { 108, 40, 10 }, 5009 { 96, 44, 11 }, 5010 { 72, 50, 13 }, 5011 { 48, 57, 14 }, 5012 { 36, 67, 16 }, 5013 { 24, 80, 20 }, 5014 { 22, 100, 25 }, 5015 { 18, 133, 34 }, 5016 { 12, 160, 40 }, 5017 { 10, 200, 50 }, 5018 { 6, 240, 58 }, 5019 { 4, 267, 66 }, 5020 { 2, 400, 100 }, 5021 { 0, 500, 130 }, 5022 /* XXX half/quarter rates */ 5023 }; 5024 const HAL_RATE_TABLE *rt; 5025 int i, j; 5026 5027 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5028 rt = sc->sc_rates[mode]; 5029 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5030 for (i = 0; i < rt->rateCount; i++) 5031 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5032 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5033 for (i = 0; i < 32; i++) { 5034 u_int8_t ix = rt->rateCodeToIndex[i]; 5035 if (ix == 0xff) { 5036 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5037 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5038 continue; 5039 } 5040 sc->sc_hwmap[i].ieeerate = 5041 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5042 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5043 if (rt->info[ix].shortPreamble || 5044 rt->info[ix].phy == IEEE80211_T_OFDM) 5045 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5046 /* NB: receive frames include FCS */ 5047 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5048 IEEE80211_RADIOTAP_F_FCS; 5049 /* setup blink rate table to avoid per-packet lookup */ 5050 for (j = 0; j < N(blinkrates)-1; j++) 5051 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5052 break; 5053 /* NB: this uses the last entry if the rate isn't found */ 5054 /* XXX beware of overlow */ 5055 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5056 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5057 } 5058 sc->sc_currates = rt; 5059 sc->sc_curmode = mode; 5060 /* 5061 * All protection frames are transmited at 2Mb/s for 5062 * 11g, otherwise at 1Mb/s. 5063 */ 5064 if (mode == IEEE80211_MODE_11G) 5065 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5066 else 5067 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5068 /* rate index used to send management frames */ 5069 sc->sc_minrateix = 0; 5070 /* 5071 * Setup multicast rate state. 5072 */ 5073 /* XXX layering violation */ 5074 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5075 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5076 /* NB: caller is responsible for reseting rate control state */ 5077#undef N 5078} 5079 5080#ifdef ATH_DEBUG 5081static void 5082ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done) 5083{ 5084 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5085 const struct ath_desc *ds; 5086 int i; 5087 5088 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5089 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 5090 " %08x %08x %08x %08x\n", 5091 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 5092 ds->ds_link, ds->ds_data, 5093 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 5094 ds->ds_ctl0, ds->ds_ctl1, 5095 ds->ds_hw[0], ds->ds_hw[1]); 5096 } 5097} 5098 5099static void 5100ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done) 5101{ 5102 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 5103 const struct ath_desc *ds; 5104 int i; 5105 5106 printf("Q%u[%3u]", qnum, ix); 5107 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5108 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 5109 " %08x %08x %08x %08x %08x %08x\n", 5110 ds, (const struct ath_desc *)bf->bf_daddr + i, 5111 ds->ds_link, ds->ds_data, bf->bf_flags, 5112 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 5113 ds->ds_ctl0, ds->ds_ctl1, 5114 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 5115 } 5116} 5117#endif /* ATH_DEBUG */ 5118 5119static void 5120ath_watchdog(struct ifnet *ifp) 5121{ 5122 struct ath_softc *sc = ifp->if_softc; 5123 struct ieee80211com *ic = &sc->sc_ic; 5124 5125 ifp->if_timer = 0; 5126 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 5127 return; 5128 if (sc->sc_tx_timer) { 5129 if (--sc->sc_tx_timer == 0) { 5130 if_printf(ifp, "device timeout\n"); 5131 ath_reset(ifp); 5132 ifp->if_oerrors++; 5133 sc->sc_stats.ast_watchdog++; 5134 } else 5135 ifp->if_timer = 1; 5136 } 5137 ieee80211_watchdog(ic); 5138} 5139 5140#ifdef ATH_DIAGAPI 5141/* 5142 * Diagnostic interface to the HAL. This is used by various 5143 * tools to do things like retrieve register contents for 5144 * debugging. The mechanism is intentionally opaque so that 5145 * it can change frequently w/o concern for compatiblity. 5146 */ 5147static int 5148ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5149{ 5150 struct ath_hal *ah = sc->sc_ah; 5151 u_int id = ad->ad_id & ATH_DIAG_ID; 5152 void *indata = NULL; 5153 void *outdata = NULL; 5154 u_int32_t insize = ad->ad_in_size; 5155 u_int32_t outsize = ad->ad_out_size; 5156 int error = 0; 5157 5158 if (ad->ad_id & ATH_DIAG_IN) { 5159 /* 5160 * Copy in data. 5161 */ 5162 indata = malloc(insize, M_TEMP, M_NOWAIT); 5163 if (indata == NULL) { 5164 error = ENOMEM; 5165 goto bad; 5166 } 5167 error = copyin(ad->ad_in_data, indata, insize); 5168 if (error) 5169 goto bad; 5170 } 5171 if (ad->ad_id & ATH_DIAG_DYN) { 5172 /* 5173 * Allocate a buffer for the results (otherwise the HAL 5174 * returns a pointer to a buffer where we can read the 5175 * results). Note that we depend on the HAL leaving this 5176 * pointer for us to use below in reclaiming the buffer; 5177 * may want to be more defensive. 5178 */ 5179 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5180 if (outdata == NULL) { 5181 error = ENOMEM; 5182 goto bad; 5183 } 5184 } 5185 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5186 if (outsize < ad->ad_out_size) 5187 ad->ad_out_size = outsize; 5188 if (outdata != NULL) 5189 error = copyout(outdata, ad->ad_out_data, 5190 ad->ad_out_size); 5191 } else { 5192 error = EINVAL; 5193 } 5194bad: 5195 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5196 free(indata, M_TEMP); 5197 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5198 free(outdata, M_TEMP); 5199 return error; 5200} 5201#endif /* ATH_DIAGAPI */ 5202 5203static int 5204ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5205{ 5206#define IS_RUNNING(ifp) \ 5207 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5208 struct ath_softc *sc = ifp->if_softc; 5209 struct ieee80211com *ic = &sc->sc_ic; 5210 struct ifreq *ifr = (struct ifreq *)data; 5211 int error = 0; 5212 5213 ATH_LOCK(sc); 5214 switch (cmd) { 5215 case SIOCSIFFLAGS: 5216 if (IS_RUNNING(ifp)) { 5217 /* 5218 * To avoid rescanning another access point, 5219 * do not call ath_init() here. Instead, 5220 * only reflect promisc mode settings. 5221 */ 5222 ath_mode_init(sc); 5223 } else if (ifp->if_flags & IFF_UP) { 5224 /* 5225 * Beware of being called during attach/detach 5226 * to reset promiscuous mode. In that case we 5227 * will still be marked UP but not RUNNING. 5228 * However trying to re-init the interface 5229 * is the wrong thing to do as we've already 5230 * torn down much of our state. There's 5231 * probably a better way to deal with this. 5232 */ 5233 if (!sc->sc_invalid && ic->ic_bss != NULL) 5234 ath_init(sc); /* XXX lose error */ 5235 } else 5236 ath_stop_locked(ifp); 5237 break; 5238 case SIOCADDMULTI: 5239 case SIOCDELMULTI: 5240 /* 5241 * The upper layer has already installed/removed 5242 * the multicast address(es), just recalculate the 5243 * multicast filter for the card. 5244 */ 5245 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5246 ath_mode_init(sc); 5247 break; 5248 case SIOCGATHSTATS: 5249 /* NB: embed these numbers to get a consistent view */ 5250 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5251 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5252 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5253 sc->sc_stats.ast_rx_noise = 5254 ath_hal_getchannoise(sc->sc_ah, &sc->sc_curchan); 5255 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate; 5256 ATH_UNLOCK(sc); 5257 /* 5258 * NB: Drop the softc lock in case of a page fault; 5259 * we'll accept any potential inconsisentcy in the 5260 * statistics. The alternative is to copy the data 5261 * to a local structure. 5262 */ 5263 return copyout(&sc->sc_stats, 5264 ifr->ifr_data, sizeof (sc->sc_stats)); 5265#ifdef ATH_DIAGAPI 5266 case SIOCGATHDIAG: 5267 ATH_UNLOCK(sc); 5268 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5269 ATH_LOCK(sc); 5270 break; 5271#endif 5272 default: 5273 error = ieee80211_ioctl(ic, cmd, data); 5274 if (error == ENETRESET) { 5275 if (IS_RUNNING(ifp) && 5276 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5277 ath_init(sc); /* XXX lose error */ 5278 error = 0; 5279 } 5280 if (error == ERESTART) 5281 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5282 break; 5283 } 5284 ATH_UNLOCK(sc); 5285 return error; 5286#undef IS_RUNNING 5287} 5288 5289static int 5290ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 5291{ 5292 struct ath_softc *sc = arg1; 5293 u_int slottime = ath_hal_getslottime(sc->sc_ah); 5294 int error; 5295 5296 error = sysctl_handle_int(oidp, &slottime, 0, req); 5297 if (error || !req->newptr) 5298 return error; 5299 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 5300} 5301 5302static int 5303ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 5304{ 5305 struct ath_softc *sc = arg1; 5306 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 5307 int error; 5308 5309 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 5310 if (error || !req->newptr) 5311 return error; 5312 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 5313} 5314 5315static int 5316ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 5317{ 5318 struct ath_softc *sc = arg1; 5319 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 5320 int error; 5321 5322 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 5323 if (error || !req->newptr) 5324 return error; 5325 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 5326} 5327 5328static int 5329ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 5330{ 5331 struct ath_softc *sc = arg1; 5332 int softled = sc->sc_softled; 5333 int error; 5334 5335 error = sysctl_handle_int(oidp, &softled, 0, req); 5336 if (error || !req->newptr) 5337 return error; 5338 softled = (softled != 0); 5339 if (softled != sc->sc_softled) { 5340 if (softled) { 5341 /* NB: handle any sc_ledpin change */ 5342 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 5343 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 5344 !sc->sc_ledon); 5345 } 5346 sc->sc_softled = softled; 5347 } 5348 return 0; 5349} 5350 5351static int 5352ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 5353{ 5354 struct ath_softc *sc = arg1; 5355 int ledpin = sc->sc_ledpin; 5356 int error; 5357 5358 error = sysctl_handle_int(oidp, &ledpin, 0, req); 5359 if (error || !req->newptr) 5360 return error; 5361 if (ledpin != sc->sc_ledpin) { 5362 sc->sc_ledpin = ledpin; 5363 if (sc->sc_softled) { 5364 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 5365 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 5366 !sc->sc_ledon); 5367 } 5368 } 5369 return 0; 5370} 5371 5372static int 5373ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 5374{ 5375 struct ath_softc *sc = arg1; 5376 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 5377 int error; 5378 5379 error = sysctl_handle_int(oidp, &txantenna, 0, req); 5380 if (!error && req->newptr) { 5381 /* XXX assumes 2 antenna ports */ 5382 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 5383 return EINVAL; 5384 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 5385 /* 5386 * NB: with the switch locked this isn't meaningful, 5387 * but set it anyway so things like radiotap get 5388 * consistent info in their data. 5389 */ 5390 sc->sc_txantenna = txantenna; 5391 } 5392 return error; 5393} 5394 5395static int 5396ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 5397{ 5398 struct ath_softc *sc = arg1; 5399 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 5400 int error; 5401 5402 error = sysctl_handle_int(oidp, &defantenna, 0, req); 5403 if (!error && req->newptr) 5404 ath_hal_setdefantenna(sc->sc_ah, defantenna); 5405 return error; 5406} 5407 5408static int 5409ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 5410{ 5411 struct ath_softc *sc = arg1; 5412 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 5413 int error; 5414 5415 error = sysctl_handle_int(oidp, &diversity, 0, req); 5416 if (error || !req->newptr) 5417 return error; 5418 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 5419 return EINVAL; 5420 sc->sc_diversity = diversity; 5421 return 0; 5422} 5423 5424static int 5425ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 5426{ 5427 struct ath_softc *sc = arg1; 5428 u_int32_t diag; 5429 int error; 5430 5431 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 5432 return EINVAL; 5433 error = sysctl_handle_int(oidp, &diag, 0, req); 5434 if (error || !req->newptr) 5435 return error; 5436 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 5437} 5438 5439static int 5440ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 5441{ 5442 struct ath_softc *sc = arg1; 5443 struct ifnet *ifp = sc->sc_ifp; 5444 u_int32_t scale; 5445 int error; 5446 5447 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 5448 error = sysctl_handle_int(oidp, &scale, 0, req); 5449 if (error || !req->newptr) 5450 return error; 5451 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 5452 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 5453} 5454 5455static int 5456ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 5457{ 5458 struct ath_softc *sc = arg1; 5459 u_int tpc = ath_hal_gettpc(sc->sc_ah); 5460 int error; 5461 5462 error = sysctl_handle_int(oidp, &tpc, 0, req); 5463 if (error || !req->newptr) 5464 return error; 5465 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 5466} 5467 5468static int 5469ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 5470{ 5471 struct ath_softc *sc = arg1; 5472 struct ifnet *ifp = sc->sc_ifp; 5473 struct ath_hal *ah = sc->sc_ah; 5474 u_int rfkill = ath_hal_getrfkill(ah); 5475 int error; 5476 5477 error = sysctl_handle_int(oidp, &rfkill, 0, req); 5478 if (error || !req->newptr) 5479 return error; 5480 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 5481 return 0; 5482 if (!ath_hal_setrfkill(ah, rfkill)) 5483 return EINVAL; 5484 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 5485} 5486 5487static int 5488ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 5489{ 5490 struct ath_softc *sc = arg1; 5491 u_int rfsilent; 5492 int error; 5493 5494 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 5495 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 5496 if (error || !req->newptr) 5497 return error; 5498 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 5499 return EINVAL; 5500 sc->sc_rfsilentpin = rfsilent & 0x1c; 5501 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 5502 return 0; 5503} 5504 5505static int 5506ath_sysctl_countrycode(SYSCTL_HANDLER_ARGS) 5507{ 5508 struct ath_softc *sc = arg1; 5509 u_int32_t cc = sc->sc_countrycode; 5510 struct ieee80211com *ic = &sc->sc_ic; 5511 int error; 5512 5513 error = sysctl_handle_int(oidp, &cc, 0, req); 5514 if (error || !req->newptr) 5515 return error; 5516 error = ath_getchannels(sc, sc->sc_regdomain, cc, 5517 sc->sc_outdoor, sc->sc_xchanmode); 5518 if (error != 0) 5519 return error; 5520 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 5521 /* setcurmode? */ 5522 return 0; 5523} 5524 5525static int 5526ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS) 5527{ 5528 struct ath_softc *sc = arg1; 5529 u_int32_t rd = sc->sc_regdomain; 5530 struct ieee80211com *ic = &sc->sc_ic; 5531 int error; 5532 5533 error = sysctl_handle_int(oidp, &rd, 0, req); 5534 if (error || !req->newptr) 5535 return error; 5536 if (!ath_hal_setregdomain(sc->sc_ah, rd)) 5537 return EINVAL; 5538 error = ath_getchannels(sc, rd, sc->sc_countrycode, 5539 sc->sc_outdoor, sc->sc_xchanmode); 5540 if (error != 0) 5541 return error; 5542 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 5543 /* setcurmode? */ 5544 return 0; 5545} 5546 5547static int 5548ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 5549{ 5550 struct ath_softc *sc = arg1; 5551 u_int32_t tpack; 5552 int error; 5553 5554 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 5555 error = sysctl_handle_int(oidp, &tpack, 0, req); 5556 if (error || !req->newptr) 5557 return error; 5558 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 5559} 5560 5561static int 5562ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 5563{ 5564 struct ath_softc *sc = arg1; 5565 u_int32_t tpcts; 5566 int error; 5567 5568 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 5569 error = sysctl_handle_int(oidp, &tpcts, 0, req); 5570 if (error || !req->newptr) 5571 return error; 5572 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 5573} 5574 5575static void 5576ath_sysctlattach(struct ath_softc *sc) 5577{ 5578 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 5579 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 5580 struct ath_hal *ah = sc->sc_ah; 5581 5582 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5583 "countrycode", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5584 ath_sysctl_countrycode, "I", "country code"); 5585 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5586 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5587 ath_sysctl_regdomain, "I", "EEPROM regdomain code"); 5588#ifdef ATH_DEBUG 5589 sc->sc_debug = ath_debug; 5590 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5591 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 5592 "control debugging printfs"); 5593#endif 5594 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5595 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5596 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 5597 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5598 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5599 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 5600 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5601 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5602 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 5603 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5604 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5605 ath_sysctl_softled, "I", "enable/disable software LED support"); 5606 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5607 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5608 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 5609 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5610 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 5611 "setting to turn LED on"); 5612 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5613 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 5614 "idle time for inactivity LED (ticks)"); 5615 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5616 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5617 ath_sysctl_txantenna, "I", "antenna switch"); 5618 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5619 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5620 ath_sysctl_rxantenna, "I", "default/rx antenna"); 5621 if (ath_hal_hasdiversity(ah)) 5622 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5623 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5624 ath_sysctl_diversity, "I", "antenna diversity"); 5625 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 5626 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5627 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 5628 "tx descriptor batching"); 5629 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5630 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5631 ath_sysctl_diag, "I", "h/w diagnostic control"); 5632 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5633 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5634 ath_sysctl_tpscale, "I", "tx power scaling"); 5635 if (ath_hal_hastpc(ah)) { 5636 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5637 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5638 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 5639 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5640 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5641 ath_sysctl_tpack, "I", "tx power for ack frames"); 5642 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5643 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5644 ath_sysctl_tpcts, "I", "tx power for cts frames"); 5645 } 5646 if (ath_hal_hasrfsilent(ah)) { 5647 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5648 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5649 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 5650 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5651 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5652 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 5653 } 5654 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 5655 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5656 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 5657 "mask of error frames to pass when monitoring"); 5658} 5659 5660static void 5661ath_bpfattach(struct ath_softc *sc) 5662{ 5663 struct ifnet *ifp = sc->sc_ifp; 5664 5665 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5666 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5667 &sc->sc_drvbpf); 5668 /* 5669 * Initialize constant fields. 5670 * XXX make header lengths a multiple of 32-bits so subsequent 5671 * headers are properly aligned; this is a kludge to keep 5672 * certain applications happy. 5673 * 5674 * NB: the channel is setup each time we transition to the 5675 * RUN state to avoid filling it in for each frame. 5676 */ 5677 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5678 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5679 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5680 5681 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5682 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5683 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5684} 5685 5686static int 5687ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 5688 struct ath_buf *bf, struct mbuf *m0, 5689 const struct ieee80211_bpf_params *params) 5690{ 5691 struct ieee80211com *ic = &sc->sc_ic; 5692 struct ath_hal *ah = sc->sc_ah; 5693 int error, ismcast, ismrr; 5694 int hdrlen, pktlen, try0, txantenna; 5695 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 5696 struct ath_txq *txq; 5697 struct ieee80211_frame *wh; 5698 u_int flags, ctsduration; 5699 HAL_PKT_TYPE atype; 5700 const HAL_RATE_TABLE *rt; 5701 struct ath_desc *ds; 5702 u_int pri; 5703 5704 wh = mtod(m0, struct ieee80211_frame *); 5705 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 5706 hdrlen = ieee80211_anyhdrsize(wh); 5707 /* 5708 * Packet length must not include any 5709 * pad bytes; deduct them here. 5710 */ 5711 /* XXX honor IEEE80211_BPF_DATAPAD */ 5712 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 5713 5714 error = ath_tx_dmasetup(sc, bf, m0); 5715 if (error != 0) 5716 return error; 5717 m0 = bf->bf_m; /* NB: may have changed */ 5718 wh = mtod(m0, struct ieee80211_frame *); 5719 bf->bf_node = ni; /* NB: held reference */ 5720 5721 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 5722 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 5723 if (params->ibp_flags & IEEE80211_BPF_RTS) 5724 flags |= HAL_TXDESC_RTSENA; 5725 else if (params->ibp_flags & IEEE80211_BPF_CTS) 5726 flags |= HAL_TXDESC_CTSENA; 5727 /* XXX leave ismcast to injector? */ 5728 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 5729 flags |= HAL_TXDESC_NOACK; 5730 5731 rt = sc->sc_currates; 5732 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 5733 rix = ath_tx_findrix(rt, params->ibp_rate0); 5734 txrate = rt->info[rix].rateCode; 5735 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 5736 txrate |= rt->info[rix].shortPreamble; 5737 sc->sc_txrate = txrate; 5738 try0 = params->ibp_try0; 5739 ismrr = (params->ibp_try1 != 0); 5740 txantenna = params->ibp_pri >> 2; 5741 if (txantenna == 0) /* XXX? */ 5742 txantenna = sc->sc_txantenna; 5743 ctsduration = 0; 5744 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 5745 cix = ath_tx_findrix(rt, params->ibp_ctsrate); 5746 ctsrate = rt->info[cix].rateCode; 5747 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 5748 ctsrate |= rt->info[cix].shortPreamble; 5749 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 5750 ctsduration += rt->info[cix].spAckDuration; 5751 ctsduration += ath_hal_computetxtime(ah, 5752 rt, pktlen, rix, AH_TRUE); 5753 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 5754 ctsduration += rt->info[rix].spAckDuration; 5755 } else { 5756 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 5757 ctsduration += rt->info[cix].lpAckDuration; 5758 ctsduration += ath_hal_computetxtime(ah, 5759 rt, pktlen, rix, AH_FALSE); 5760 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 5761 ctsduration += rt->info[rix].lpAckDuration; 5762 } 5763 ismrr = 0; /* XXX */ 5764 } else 5765 ctsrate = 0; 5766 pri = params->ibp_pri & 3; 5767 /* 5768 * NB: we mark all packets as type PSPOLL so the h/w won't 5769 * set the sequence number, duration, etc. 5770 */ 5771 atype = HAL_PKT_TYPE_PSPOLL; 5772 5773 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 5774 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 5775 sc->sc_hwmap[txrate].ieeerate, -1); 5776 5777 if (bpf_peers_present(ic->ic_rawbpf)) 5778 bpf_mtap(ic->ic_rawbpf, m0); 5779 if (bpf_peers_present(sc->sc_drvbpf)) { 5780 u_int64_t tsf = ath_hal_gettsf64(ah); 5781 5782 sc->sc_tx_th.wt_tsf = htole64(tsf); 5783 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 5784 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 5785 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 5786 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 5787 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 5788 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 5789 5790 bpf_mtap2(sc->sc_drvbpf, 5791 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 5792 } 5793 5794 /* 5795 * Formulate first tx descriptor with tx controls. 5796 */ 5797 ds = bf->bf_desc; 5798 /* XXX check return value? */ 5799 ath_hal_setuptxdesc(ah, ds 5800 , pktlen /* packet length */ 5801 , hdrlen /* header length */ 5802 , atype /* Atheros packet type */ 5803 , params->ibp_power /* txpower */ 5804 , txrate, try0 /* series 0 rate/tries */ 5805 , HAL_TXKEYIX_INVALID /* key cache index */ 5806 , txantenna /* antenna mode */ 5807 , flags /* flags */ 5808 , ctsrate /* rts/cts rate */ 5809 , ctsduration /* rts/cts duration */ 5810 ); 5811 bf->bf_flags = flags; 5812 5813 if (ismrr) { 5814 rix = ath_tx_findrix(rt, params->ibp_rate1); 5815 rate1 = rt->info[rix].rateCode; 5816 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 5817 rate1 |= rt->info[rix].shortPreamble; 5818 if (params->ibp_try2) { 5819 rix = ath_tx_findrix(rt, params->ibp_rate2); 5820 rate2 = rt->info[rix].rateCode; 5821 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 5822 rate2 |= rt->info[rix].shortPreamble; 5823 } else 5824 rate2 = 0; 5825 if (params->ibp_try3) { 5826 rix = ath_tx_findrix(rt, params->ibp_rate3); 5827 rate3 = rt->info[rix].rateCode; 5828 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 5829 rate3 |= rt->info[rix].shortPreamble; 5830 } else 5831 rate3 = 0; 5832 ath_hal_setupxtxdesc(ah, ds 5833 , rate1, params->ibp_try1 /* series 1 */ 5834 , rate2, params->ibp_try2 /* series 2 */ 5835 , rate3, params->ibp_try3 /* series 3 */ 5836 ); 5837 } 5838 5839 /* 5840 * When servicing one or more stations in power-save mode 5841 * (or) if there is some mcast data waiting on the mcast 5842 * queue (to prevent out of order delivery) multicast 5843 * frames must be buffered until after the beacon. 5844 */ 5845 txq = sc->sc_ac2q[pri]; 5846 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) 5847 txq = &sc->sc_mcastq; 5848 ath_tx_handoff(sc, txq, bf); 5849 return 0; 5850} 5851 5852static int 5853ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5854 const struct ieee80211_bpf_params *params) 5855{ 5856 struct ieee80211com *ic = ni->ni_ic; 5857 struct ifnet *ifp = ic->ic_ifp; 5858 struct ath_softc *sc = ifp->if_softc; 5859 struct ath_buf *bf; 5860 5861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 5862 ieee80211_free_node(ni); 5863 m_freem(m); 5864 return ENETDOWN; 5865 } 5866 /* 5867 * Grab a TX buffer and associated resources. 5868 */ 5869 ATH_TXBUF_LOCK(sc); 5870 bf = STAILQ_FIRST(&sc->sc_txbuf); 5871 if (bf != NULL) 5872 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 5873 ATH_TXBUF_UNLOCK(sc); 5874 if (bf == NULL) { 5875 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 5876 __func__); 5877 sc->sc_stats.ast_tx_qstop++; 5878 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5879 ieee80211_free_node(ni); 5880 m_freem(m); 5881 return ENOBUFS; 5882 } 5883 5884 ifp->if_opackets++; 5885 sc->sc_stats.ast_tx_raw++; 5886 5887 if (params == NULL) { 5888 /* 5889 * Legacy path; interpret frame contents to decide 5890 * precisely how to send the frame. 5891 */ 5892 if (ath_tx_start(sc, ni, bf, m)) 5893 goto bad; 5894 } else { 5895 /* 5896 * Caller supplied explicit parameters to use in 5897 * sending the frame. 5898 */ 5899 if (ath_tx_raw_start(sc, ni, bf, m, params)) 5900 goto bad; 5901 } 5902 sc->sc_tx_timer = 5; 5903 ifp->if_timer = 1; 5904 5905 return 0; 5906bad: 5907 ifp->if_oerrors++; 5908 ATH_TXBUF_LOCK(sc); 5909 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5910 ATH_TXBUF_UNLOCK(sc); 5911 ieee80211_free_node(ni); 5912 return EIO; /* XXX */ 5913} 5914 5915/* 5916 * Announce various information on device/driver attach. 5917 */ 5918static void 5919ath_announce(struct ath_softc *sc) 5920{ 5921#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5922 struct ifnet *ifp = sc->sc_ifp; 5923 struct ath_hal *ah = sc->sc_ah; 5924 u_int modes, cc; 5925 5926 if_printf(ifp, "mac %d.%d phy %d.%d", 5927 ah->ah_macVersion, ah->ah_macRev, 5928 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5929 /* 5930 * Print radio revision(s). We check the wireless modes 5931 * to avoid falsely printing revs for inoperable parts. 5932 * Dual-band radio revs are returned in the 5Ghz rev number. 5933 */ 5934 ath_hal_getcountrycode(ah, &cc); 5935 modes = ath_hal_getwirelessmodes(ah, cc); 5936 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5937 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5938 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 5939 ah->ah_analog5GhzRev >> 4, 5940 ah->ah_analog5GhzRev & 0xf, 5941 ah->ah_analog2GhzRev >> 4, 5942 ah->ah_analog2GhzRev & 0xf); 5943 else 5944 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5945 ah->ah_analog5GhzRev & 0xf); 5946 } else 5947 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5948 ah->ah_analog5GhzRev & 0xf); 5949 printf("\n"); 5950 if (bootverbose) { 5951 int i; 5952 for (i = 0; i <= WME_AC_VO; i++) { 5953 struct ath_txq *txq = sc->sc_ac2q[i]; 5954 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5955 txq->axq_qnum, ieee80211_wme_acnames[i]); 5956 } 5957 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5958 sc->sc_cabq->axq_qnum); 5959 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5960 } 5961 if (ath_rxbuf != ATH_RXBUF) 5962 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5963 if (ath_txbuf != ATH_TXBUF) 5964 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5965#undef HAL_MODE_DUALBAND 5966} 5967