if_ath.c revision 159183
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 159183 2006-06-02 23:14:40Z sam $"); 39 40/* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47#include "opt_inet.h" 48#include "opt_ath.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/sysctl.h> 53#include <sys/mbuf.h> 54#include <sys/malloc.h> 55#include <sys/lock.h> 56#include <sys/mutex.h> 57#include <sys/kernel.h> 58#include <sys/socket.h> 59#include <sys/sockio.h> 60#include <sys/errno.h> 61#include <sys/callout.h> 62#include <sys/bus.h> 63#include <sys/endian.h> 64#include <sys/kthread.h> 65#include <sys/taskqueue.h> 66 67#include <machine/bus.h> 68 69#include <net/if.h> 70#include <net/if_dl.h> 71#include <net/if_media.h> 72#include <net/if_types.h> 73#include <net/if_arp.h> 74#include <net/ethernet.h> 75#include <net/if_llc.h> 76 77#include <net80211/ieee80211_var.h> 78 79#include <net/bpf.h> 80 81#ifdef INET 82#include <netinet/in.h> 83#include <netinet/if_ether.h> 84#endif 85 86#include <dev/ath/if_athvar.h> 87#include <contrib/dev/ath/ah_desc.h> 88#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 89 90#ifdef ATH_TX99_DIAG 91#include <dev/ath/ath_tx99/ath_tx99.h> 92#endif 93 94/* unaligned little endian access */ 95#define LE_READ_2(p) \ 96 ((u_int16_t) \ 97 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 98#define LE_READ_4(p) \ 99 ((u_int32_t) \ 100 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 101 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 102 103enum { 104 ATH_LED_TX, 105 ATH_LED_RX, 106 ATH_LED_POLL, 107}; 108 109static void ath_init(void *); 110static void ath_stop_locked(struct ifnet *); 111static void ath_stop(struct ifnet *); 112static void ath_start(struct ifnet *); 113static int ath_reset(struct ifnet *); 114static int ath_media_change(struct ifnet *); 115static void ath_watchdog(struct ifnet *); 116static int ath_ioctl(struct ifnet *, u_long, caddr_t); 117static void ath_fatal_proc(void *, int); 118static void ath_rxorn_proc(void *, int); 119static void ath_bmiss_proc(void *, int); 120static void ath_radar_proc(void *, int); 121static int ath_key_alloc(struct ieee80211com *, 122 const struct ieee80211_key *, 123 ieee80211_keyix *, ieee80211_keyix *); 124static int ath_key_delete(struct ieee80211com *, 125 const struct ieee80211_key *); 126static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 127 const u_int8_t mac[IEEE80211_ADDR_LEN]); 128static void ath_key_update_begin(struct ieee80211com *); 129static void ath_key_update_end(struct ieee80211com *); 130static void ath_mode_init(struct ath_softc *); 131static void ath_setslottime(struct ath_softc *); 132static void ath_updateslot(struct ifnet *); 133static int ath_beaconq_setup(struct ath_hal *); 134static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 135static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 136static void ath_beacon_proc(void *, int); 137static void ath_bstuck_proc(void *, int); 138static void ath_beacon_free(struct ath_softc *); 139static void ath_beacon_config(struct ath_softc *); 140static void ath_descdma_cleanup(struct ath_softc *sc, 141 struct ath_descdma *, ath_bufhead *); 142static int ath_desc_alloc(struct ath_softc *); 143static void ath_desc_free(struct ath_softc *); 144static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 145static void ath_node_free(struct ieee80211_node *); 146static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 147static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 148static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 149 struct ieee80211_node *ni, 150 int subtype, int rssi, u_int32_t rstamp); 151static void ath_setdefantenna(struct ath_softc *, u_int); 152static void ath_rx_proc(void *, int); 153static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 154static int ath_tx_setup(struct ath_softc *, int, int); 155static int ath_wme_update(struct ieee80211com *); 156static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 157static void ath_tx_cleanup(struct ath_softc *); 158static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 159 struct ath_buf *, struct mbuf *); 160static void ath_tx_proc_q0(void *, int); 161static void ath_tx_proc_q0123(void *, int); 162static void ath_tx_proc(void *, int); 163static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 164static void ath_draintxq(struct ath_softc *); 165static void ath_stoprecv(struct ath_softc *); 166static int ath_startrecv(struct ath_softc *); 167static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 168static void ath_next_scan(void *); 169static void ath_calibrate(void *); 170static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 171static void ath_setup_stationkey(struct ieee80211_node *); 172static void ath_newassoc(struct ieee80211_node *, int); 173static int ath_getchannels(struct ath_softc *, u_int cc, 174 HAL_BOOL outdoor, HAL_BOOL xchanmode); 175static void ath_led_event(struct ath_softc *, int); 176static void ath_update_txpow(struct ath_softc *); 177 178static int ath_rate_setup(struct ath_softc *, u_int mode); 179static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 180 181static void ath_sysctlattach(struct ath_softc *); 182static void ath_bpfattach(struct ath_softc *); 183static void ath_announce(struct ath_softc *); 184 185SYSCTL_DECL(_hw_ath); 186 187/* XXX validate sysctl values */ 188static int ath_dwelltime = 200; /* 5 channels/second */ 189SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 190 0, "channel dwell time (ms) for AP/station scanning"); 191static int ath_calinterval = 30; /* calibrate every 30 secs */ 192SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 193 0, "chip calibration interval (secs)"); 194static int ath_outdoor = AH_TRUE; /* outdoor operation */ 195SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 196 0, "outdoor operation"); 197TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 198static int ath_xchanmode = AH_TRUE; /* extended channel use */ 199SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode, 200 0, "extended channel mode"); 201TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 202static int ath_countrycode = CTRY_DEFAULT; /* country code */ 203SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 204 0, "country code"); 205TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 206static int ath_regdomain = 0; /* regulatory domain */ 207SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 208 0, "regulatory domain"); 209 210static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 211SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf, 212 0, "rx buffers allocated"); 213TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 214static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 215SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf, 216 0, "tx buffers allocated"); 217TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 218 219#ifdef ATH_DEBUG 220static int ath_debug = 0; 221SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 222 0, "control debugging printfs"); 223TUNABLE_INT("hw.ath.debug", &ath_debug); 224enum { 225 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 226 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 227 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 228 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 229 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 230 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 231 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 232 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 233 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 234 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 235 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 236 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 237 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 238 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 239 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 240 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 241 ATH_DEBUG_NODE = 0x00080000, /* node management */ 242 ATH_DEBUG_LED = 0x00100000, /* led management */ 243 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 244 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 245 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 246 ATH_DEBUG_ANY = 0xffffffff 247}; 248#define IFF_DUMPPKTS(sc, m) \ 249 ((sc->sc_debug & (m)) || \ 250 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 251#define DPRINTF(sc, m, fmt, ...) do { \ 252 if (sc->sc_debug & (m)) \ 253 printf(fmt, __VA_ARGS__); \ 254} while (0) 255#define KEYPRINTF(sc, ix, hk, mac) do { \ 256 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 257 ath_keyprint(__func__, ix, hk, mac); \ 258} while (0) 259static void ath_printrxbuf(struct ath_buf *bf, u_int ix, int); 260static void ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done); 261#else 262#define IFF_DUMPPKTS(sc, m) \ 263 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 264#define DPRINTF(sc, m, fmt, ...) do { \ 265 (void) sc; \ 266} while (0) 267#define KEYPRINTF(sc, k, ix, mac) do { \ 268 (void) sc; \ 269} while (0) 270#endif 271 272MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 273 274int 275ath_attach(u_int16_t devid, struct ath_softc *sc) 276{ 277 struct ifnet *ifp; 278 struct ieee80211com *ic = &sc->sc_ic; 279 struct ath_hal *ah = NULL; 280 HAL_STATUS status; 281 int error = 0, i; 282 283 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 284 285 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 286 if (ifp == NULL) { 287 device_printf(sc->sc_dev, "can not if_alloc()\n"); 288 error = ENOSPC; 289 goto bad; 290 } 291 292 /* set these up early for if_printf use */ 293 if_initname(ifp, device_get_name(sc->sc_dev), 294 device_get_unit(sc->sc_dev)); 295 296 ah = ath_hal_attach(devid, sc, (HAL_BUS_TAG) sc->sc_st, 297 (HAL_BUS_HANDLE) sc->sc_sh, &status); 298 if (ah == NULL) { 299 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 300 status); 301 error = ENXIO; 302 goto bad; 303 } 304 if (ah->ah_abi != HAL_ABI_VERSION) { 305 if_printf(ifp, "HAL ABI mismatch detected " 306 "(HAL:0x%x != driver:0x%x)\n", 307 ah->ah_abi, HAL_ABI_VERSION); 308 error = ENXIO; 309 goto bad; 310 } 311 sc->sc_ah = ah; 312 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 313 314 /* 315 * Check if the MAC has multi-rate retry support. 316 * We do this by trying to setup a fake extended 317 * descriptor. MAC's that don't have support will 318 * return false w/o doing anything. MAC's that do 319 * support it will return true w/o doing anything. 320 */ 321 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 322 323 /* 324 * Check if the device has hardware counters for PHY 325 * errors. If so we need to enable the MIB interrupt 326 * so we can act on stat triggers. 327 */ 328 if (ath_hal_hwphycounters(ah)) 329 sc->sc_needmib = 1; 330 331 /* 332 * Get the hardware key cache size. 333 */ 334 sc->sc_keymax = ath_hal_keycachesize(ah); 335 if (sc->sc_keymax > ATH_KEYMAX) { 336 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 337 ATH_KEYMAX, sc->sc_keymax); 338 sc->sc_keymax = ATH_KEYMAX; 339 } 340 /* 341 * Reset the key cache since some parts do not 342 * reset the contents on initial power up. 343 */ 344 for (i = 0; i < sc->sc_keymax; i++) 345 ath_hal_keyreset(ah, i); 346 /* 347 * Mark key cache slots associated with global keys 348 * as in use. If we knew TKIP was not to be used we 349 * could leave the +32, +64, and +32+64 slots free. 350 * XXX only for splitmic. 351 */ 352 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 353 setbit(sc->sc_keymap, i); 354 setbit(sc->sc_keymap, i+32); 355 setbit(sc->sc_keymap, i+64); 356 setbit(sc->sc_keymap, i+32+64); 357 } 358 359 /* 360 * Collect the channel list using the default country 361 * code and including outdoor channels. The 802.11 layer 362 * is resposible for filtering this list based on settings 363 * like the phy mode. 364 */ 365 error = ath_getchannels(sc, ath_countrycode, 366 ath_outdoor, ath_xchanmode); 367 if (error != 0) 368 goto bad; 369 370 /* 371 * Setup rate tables for all potential media types. 372 */ 373 ath_rate_setup(sc, IEEE80211_MODE_11A); 374 ath_rate_setup(sc, IEEE80211_MODE_11B); 375 ath_rate_setup(sc, IEEE80211_MODE_11G); 376 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 377 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 378 /* NB: setup here so ath_rate_update is happy */ 379 ath_setcurmode(sc, IEEE80211_MODE_11A); 380 381 /* 382 * Allocate tx+rx descriptors and populate the lists. 383 */ 384 error = ath_desc_alloc(sc); 385 if (error != 0) { 386 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 387 goto bad; 388 } 389 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 390 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 391 callout_init(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 392 393 ATH_TXBUF_LOCK_INIT(sc); 394 395 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 396 taskqueue_thread_enqueue, &sc->sc_tq); 397 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 398 "%s taskq", ifp->if_xname); 399 400 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 401 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 402 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 403 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 404 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 405 406 /* 407 * Allocate hardware transmit queues: one queue for 408 * beacon frames and one data queue for each QoS 409 * priority. Note that the hal handles reseting 410 * these queues at the needed time. 411 * 412 * XXX PS-Poll 413 */ 414 sc->sc_bhalq = ath_beaconq_setup(ah); 415 if (sc->sc_bhalq == (u_int) -1) { 416 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 417 error = EIO; 418 goto bad2; 419 } 420 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 421 if (sc->sc_cabq == NULL) { 422 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 423 error = EIO; 424 goto bad2; 425 } 426 /* NB: insure BK queue is the lowest priority h/w queue */ 427 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 428 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 429 ieee80211_wme_acnames[WME_AC_BK]); 430 error = EIO; 431 goto bad2; 432 } 433 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 434 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 435 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 436 /* 437 * Not enough hardware tx queues to properly do WME; 438 * just punt and assign them all to the same h/w queue. 439 * We could do a better job of this if, for example, 440 * we allocate queues when we switch from station to 441 * AP mode. 442 */ 443 if (sc->sc_ac2q[WME_AC_VI] != NULL) 444 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 445 if (sc->sc_ac2q[WME_AC_BE] != NULL) 446 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 447 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 448 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 449 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 450 } 451 452 /* 453 * Special case certain configurations. Note the 454 * CAB queue is handled by these specially so don't 455 * include them when checking the txq setup mask. 456 */ 457 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 458 case 0x01: 459 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 460 break; 461 case 0x0f: 462 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 463 break; 464 default: 465 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 466 break; 467 } 468 469 /* 470 * Setup rate control. Some rate control modules 471 * call back to change the anntena state so expose 472 * the necessary entry points. 473 * XXX maybe belongs in struct ath_ratectrl? 474 */ 475 sc->sc_setdefantenna = ath_setdefantenna; 476 sc->sc_rc = ath_rate_attach(sc); 477 if (sc->sc_rc == NULL) { 478 error = EIO; 479 goto bad2; 480 } 481 482 sc->sc_blinking = 0; 483 sc->sc_ledstate = 1; 484 sc->sc_ledon = 0; /* low true */ 485 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 486 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 487 /* 488 * Auto-enable soft led processing for IBM cards and for 489 * 5211 minipci cards. Users can also manually enable/disable 490 * support with a sysctl. 491 */ 492 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 493 if (sc->sc_softled) { 494 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 495 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 496 } 497 498 ifp->if_softc = sc; 499 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 500 ifp->if_start = ath_start; 501 ifp->if_watchdog = ath_watchdog; 502 ifp->if_ioctl = ath_ioctl; 503 ifp->if_init = ath_init; 504 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 505 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 506 IFQ_SET_READY(&ifp->if_snd); 507 508 ic->ic_ifp = ifp; 509 ic->ic_reset = ath_reset; 510 ic->ic_newassoc = ath_newassoc; 511 ic->ic_updateslot = ath_updateslot; 512 ic->ic_wme.wme_update = ath_wme_update; 513 /* XXX not right but it's not used anywhere important */ 514 ic->ic_phytype = IEEE80211_T_OFDM; 515 ic->ic_opmode = IEEE80211_M_STA; 516 ic->ic_caps = 517 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 518 | IEEE80211_C_HOSTAP /* hostap mode */ 519 | IEEE80211_C_MONITOR /* monitor mode */ 520 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 521 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 522 | IEEE80211_C_SHSLOT /* short slot time supported */ 523 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 524 ; 525 /* 526 * Query the hal to figure out h/w crypto support. 527 */ 528 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 529 ic->ic_caps |= IEEE80211_C_WEP; 530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 531 ic->ic_caps |= IEEE80211_C_AES; 532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 533 ic->ic_caps |= IEEE80211_C_AES_CCM; 534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 535 ic->ic_caps |= IEEE80211_C_CKIP; 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 537 ic->ic_caps |= IEEE80211_C_TKIP; 538 /* 539 * Check if h/w does the MIC and/or whether the 540 * separate key cache entries are required to 541 * handle both tx+rx MIC keys. 542 */ 543 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 544 ic->ic_caps |= IEEE80211_C_TKIPMIC; 545 if (ath_hal_tkipsplit(ah)) 546 sc->sc_splitmic = 1; 547 } 548 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 549 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 550 /* 551 * TPC support can be done either with a global cap or 552 * per-packet support. The latter is not available on 553 * all parts. We're a bit pedantic here as all parts 554 * support a global cap. 555 */ 556 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 557 ic->ic_caps |= IEEE80211_C_TXPMGT; 558 559 /* 560 * Mark WME capability only if we have sufficient 561 * hardware queues to do proper priority scheduling. 562 */ 563 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 564 ic->ic_caps |= IEEE80211_C_WME; 565 /* 566 * Check for misc other capabilities. 567 */ 568 if (ath_hal_hasbursting(ah)) 569 ic->ic_caps |= IEEE80211_C_BURST; 570 571 /* 572 * Indicate we need the 802.11 header padded to a 573 * 32-bit boundary for 4-address and QoS frames. 574 */ 575 ic->ic_flags |= IEEE80211_F_DATAPAD; 576 577 /* 578 * Query the hal about antenna support. 579 */ 580 sc->sc_defant = ath_hal_getdefantenna(ah); 581 582 /* 583 * Not all chips have the VEOL support we want to 584 * use with IBSS beacons; check here for it. 585 */ 586 sc->sc_hasveol = ath_hal_hasveol(ah); 587 588 /* get mac address from hardware */ 589 ath_hal_getmac(ah, ic->ic_myaddr); 590 591 /* call MI attach routine. */ 592 ieee80211_ifattach(ic); 593 sc->sc_opmode = ic->ic_opmode; 594 /* override default methods */ 595 ic->ic_node_alloc = ath_node_alloc; 596 sc->sc_node_free = ic->ic_node_free; 597 ic->ic_node_free = ath_node_free; 598 ic->ic_node_getrssi = ath_node_getrssi; 599 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 600 ic->ic_recv_mgmt = ath_recv_mgmt; 601 sc->sc_newstate = ic->ic_newstate; 602 ic->ic_newstate = ath_newstate; 603 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 604 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 605 ic->ic_crypto.cs_key_delete = ath_key_delete; 606 ic->ic_crypto.cs_key_set = ath_key_set; 607 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 608 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 609 /* complete initialization */ 610 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 611 612 ath_bpfattach(sc); 613 /* 614 * Setup dynamic sysctl's now that country code and 615 * regdomain are available from the hal. 616 */ 617 ath_sysctlattach(sc); 618 619 if (bootverbose) 620 ieee80211_announce(ic); 621 ath_announce(sc); 622 return 0; 623bad2: 624 ath_tx_cleanup(sc); 625 ath_desc_free(sc); 626bad: 627 if (ah) 628 ath_hal_detach(ah); 629 if (ifp != NULL) 630 if_free(ifp); 631 sc->sc_invalid = 1; 632 return error; 633} 634 635int 636ath_detach(struct ath_softc *sc) 637{ 638 struct ifnet *ifp = sc->sc_ifp; 639 640 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 641 __func__, ifp->if_flags); 642 643 ath_stop(ifp); 644 bpfdetach(ifp); 645 /* 646 * NB: the order of these is important: 647 * o call the 802.11 layer before detaching the hal to 648 * insure callbacks into the driver to delete global 649 * key cache entries can be handled 650 * o reclaim the tx queue data structures after calling 651 * the 802.11 layer as we'll get called back to reclaim 652 * node state and potentially want to use them 653 * o to cleanup the tx queues the hal is called, so detach 654 * it last 655 * Other than that, it's straightforward... 656 */ 657 ieee80211_ifdetach(&sc->sc_ic); 658#ifdef ATH_TX99_DIAG 659 if (sc->sc_tx99 != NULL) 660 sc->sc_tx99->detach(sc->sc_tx99); 661#endif 662 taskqueue_free(sc->sc_tq); 663 ath_rate_detach(sc->sc_rc); 664 ath_desc_free(sc); 665 ath_tx_cleanup(sc); 666 ath_hal_detach(sc->sc_ah); 667 if_free(ifp); 668 669 return 0; 670} 671 672void 673ath_suspend(struct ath_softc *sc) 674{ 675 struct ifnet *ifp = sc->sc_ifp; 676 677 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 678 __func__, ifp->if_flags); 679 680 ath_stop(ifp); 681} 682 683void 684ath_resume(struct ath_softc *sc) 685{ 686 struct ifnet *ifp = sc->sc_ifp; 687 688 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 689 __func__, ifp->if_flags); 690 691 if (ifp->if_flags & IFF_UP) { 692 ath_init(sc); 693 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 694 ath_start(ifp); 695 } 696 if (sc->sc_softled) { 697 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 698 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 699 } 700} 701 702void 703ath_shutdown(struct ath_softc *sc) 704{ 705 struct ifnet *ifp = sc->sc_ifp; 706 707 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 708 __func__, ifp->if_flags); 709 710 ath_stop(ifp); 711} 712 713/* 714 * Interrupt handler. Most of the actual processing is deferred. 715 */ 716void 717ath_intr(void *arg) 718{ 719 struct ath_softc *sc = arg; 720 struct ifnet *ifp = sc->sc_ifp; 721 struct ath_hal *ah = sc->sc_ah; 722 HAL_INT status; 723 724 if (sc->sc_invalid) { 725 /* 726 * The hardware is not ready/present, don't touch anything. 727 * Note this can happen early on if the IRQ is shared. 728 */ 729 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 730 return; 731 } 732 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 733 return; 734 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & 735 IFF_DRV_RUNNING))) { 736 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 737 __func__, ifp->if_flags); 738 ath_hal_getisr(ah, &status); /* clear ISR */ 739 ath_hal_intrset(ah, 0); /* disable further intr's */ 740 return; 741 } 742 /* 743 * Figure out the reason(s) for the interrupt. Note 744 * that the hal returns a pseudo-ISR that may include 745 * bits we haven't explicitly enabled so we mask the 746 * value to insure we only process bits we requested. 747 */ 748 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 749 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 750 status &= sc->sc_imask; /* discard unasked for bits */ 751 if (status & HAL_INT_FATAL) { 752 sc->sc_stats.ast_hardware++; 753 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 754 ath_fatal_proc(sc, 0); 755 } else if (status & HAL_INT_RXORN) { 756 sc->sc_stats.ast_rxorn++; 757 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 758 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask); 759 } else { 760 if (status & HAL_INT_SWBA) { 761 /* 762 * Software beacon alert--time to send a beacon. 763 * Handle beacon transmission directly; deferring 764 * this is too slow to meet timing constraints 765 * under load. 766 */ 767 ath_beacon_proc(sc, 0); 768 } 769 if (status & HAL_INT_RXEOL) { 770 /* 771 * NB: the hardware should re-read the link when 772 * RXE bit is written, but it doesn't work at 773 * least on older hardware revs. 774 */ 775 sc->sc_stats.ast_rxeol++; 776 sc->sc_rxlink = NULL; 777 } 778 if (status & HAL_INT_TXURN) { 779 sc->sc_stats.ast_txurn++; 780 /* bump tx trigger level */ 781 ath_hal_updatetxtriglevel(ah, AH_TRUE); 782 } 783 if (status & HAL_INT_RX) 784 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 785 if (status & HAL_INT_TX) 786 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 787 if (status & HAL_INT_BMISS) { 788 sc->sc_stats.ast_bmiss++; 789 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 790 } 791 if (status & HAL_INT_MIB) { 792 sc->sc_stats.ast_mib++; 793 /* 794 * Disable interrupts until we service the MIB 795 * interrupt; otherwise it will continue to fire. 796 */ 797 ath_hal_intrset(ah, 0); 798 /* 799 * Let the hal handle the event. We assume it will 800 * clear whatever condition caused the interrupt. 801 */ 802 ath_hal_mibevent(ah, &sc->sc_halstats); 803 ath_hal_intrset(ah, sc->sc_imask); 804 } 805 } 806} 807 808static void 809ath_fatal_proc(void *arg, int pending) 810{ 811 struct ath_softc *sc = arg; 812 struct ifnet *ifp = sc->sc_ifp; 813 u_int32_t *state; 814 u_int32_t len; 815 816 if_printf(ifp, "hardware error; resetting\n"); 817 /* 818 * Fatal errors are unrecoverable. Typically these 819 * are caused by DMA errors. Collect h/w state from 820 * the hal so we can diagnose what's going on. 821 */ 822 if (ath_hal_getfatalstate(sc->sc_ah, &state, &len)) { 823 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 824 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 825 state[0], state[1] , state[2], state[3], 826 state[4], state[5]); 827 } 828 ath_reset(ifp); 829} 830 831static void 832ath_rxorn_proc(void *arg, int pending) 833{ 834 struct ath_softc *sc = arg; 835 struct ifnet *ifp = sc->sc_ifp; 836 837 if_printf(ifp, "rx FIFO overrun; resetting\n"); 838 ath_reset(ifp); 839} 840 841static void 842ath_bmiss_proc(void *arg, int pending) 843{ 844 struct ath_softc *sc = arg; 845 struct ieee80211com *ic = &sc->sc_ic; 846 847 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 848 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 849 ("unexpect operating mode %u", ic->ic_opmode)); 850 if (ic->ic_state == IEEE80211_S_RUN) { 851 u_int64_t lastrx = sc->sc_lastrx; 852 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 853 u_int bmisstimeout = 854 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024; 855 856 DPRINTF(sc, ATH_DEBUG_BEACON, 857 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 858 __func__, (unsigned long long) tsf, 859 (unsigned long long)(tsf - lastrx), 860 (unsigned long long) lastrx, bmisstimeout); 861 /* 862 * Workaround phantom bmiss interrupts by sanity-checking 863 * the time of our last rx'd frame. If it is within the 864 * beacon miss interval then ignore the interrupt. If it's 865 * truly a bmiss we'll get another interrupt soon and that'll 866 * be dispatched up for processing. 867 */ 868 if (tsf - lastrx > bmisstimeout) { 869 NET_LOCK_GIANT(); 870 ieee80211_beacon_miss(ic); 871 NET_UNLOCK_GIANT(); 872 } else 873 sc->sc_stats.ast_bmiss_phantom++; 874 } 875} 876 877static void 878ath_radar_proc(void *arg, int pending) 879{ 880 struct ath_softc *sc = arg; 881 struct ifnet *ifp = sc->sc_ifp; 882 struct ath_hal *ah = sc->sc_ah; 883 HAL_CHANNEL hchan; 884 885 if (ath_hal_procdfs(ah, &hchan)) { 886 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 887 hchan.channel, hchan.channelFlags, hchan.privFlags); 888 /* 889 * Initiate channel change. 890 */ 891 /* XXX not yet */ 892 } 893} 894 895static u_int 896ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 897{ 898#define N(a) (sizeof(a) / sizeof(a[0])) 899 static const u_int modeflags[] = { 900 0, /* IEEE80211_MODE_AUTO */ 901 CHANNEL_A, /* IEEE80211_MODE_11A */ 902 CHANNEL_B, /* IEEE80211_MODE_11B */ 903 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 904 0, /* IEEE80211_MODE_FH */ 905 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 906 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 907 }; 908 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 909 910 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 911 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 912 return modeflags[mode]; 913#undef N 914} 915 916static void 917ath_init(void *arg) 918{ 919 struct ath_softc *sc = (struct ath_softc *) arg; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct ifnet *ifp = sc->sc_ifp; 922 struct ath_hal *ah = sc->sc_ah; 923 HAL_STATUS status; 924 925 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 926 __func__, ifp->if_flags); 927 928 ATH_LOCK(sc); 929 /* 930 * Stop anything previously setup. This is safe 931 * whether this is the first time through or not. 932 */ 933 ath_stop_locked(ifp); 934 935 /* 936 * The basic interface to setting the hardware in a good 937 * state is ``reset''. On return the hardware is known to 938 * be powered up and with interrupts disabled. This must 939 * be followed by initialization of the appropriate bits 940 * and then setup of the interrupt mask. 941 */ 942 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 943 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 944 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 945 if_printf(ifp, "unable to reset hardware; hal status %u\n", 946 status); 947 goto done; 948 } 949 950 /* 951 * This is needed only to setup initial state 952 * but it's best done after a reset. 953 */ 954 ath_update_txpow(sc); 955 /* 956 * Likewise this is set during reset so update 957 * state cached in the driver. 958 */ 959 sc->sc_diversity = ath_hal_getdiversity(ah); 960 sc->sc_calinterval = 1; 961 sc->sc_caltries = 0; 962 963 /* 964 * Setup the hardware after reset: the key cache 965 * is filled as needed and the receive engine is 966 * set going. Frame transmit is handled entirely 967 * in the frame output path; there's nothing to do 968 * here except setup the interrupt mask. 969 */ 970 if (ath_startrecv(sc) != 0) { 971 if_printf(ifp, "unable to start recv logic\n"); 972 goto done; 973 } 974 975 /* 976 * Enable interrupts. 977 */ 978 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 979 | HAL_INT_RXEOL | HAL_INT_RXORN 980 | HAL_INT_FATAL | HAL_INT_GLOBAL; 981 /* 982 * Enable MIB interrupts when there are hardware phy counters. 983 * Note we only do this (at the moment) for station mode. 984 */ 985 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 986 sc->sc_imask |= HAL_INT_MIB; 987 ath_hal_intrset(ah, sc->sc_imask); 988 989 ifp->if_drv_flags |= IFF_DRV_RUNNING; 990 ic->ic_state = IEEE80211_S_INIT; 991 992 /* 993 * The hardware should be ready to go now so it's safe 994 * to kick the 802.11 state machine as it's likely to 995 * immediately call back to us to send mgmt frames. 996 */ 997 ath_chan_change(sc, ic->ic_curchan); 998#ifdef ATH_TX99_DIAG 999 if (sc->sc_tx99 != NULL) 1000 sc->sc_tx99->start(sc->sc_tx99); 1001 else 1002#endif 1003 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1004 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1005 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1006 } else 1007 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1008done: 1009 ATH_UNLOCK(sc); 1010} 1011 1012static void 1013ath_stop_locked(struct ifnet *ifp) 1014{ 1015 struct ath_softc *sc = ifp->if_softc; 1016 struct ieee80211com *ic = &sc->sc_ic; 1017 struct ath_hal *ah = sc->sc_ah; 1018 1019 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1020 __func__, sc->sc_invalid, ifp->if_flags); 1021 1022 ATH_LOCK_ASSERT(sc); 1023 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1024 /* 1025 * Shutdown the hardware and driver: 1026 * reset 802.11 state machine 1027 * turn off timers 1028 * disable interrupts 1029 * turn off the radio 1030 * clear transmit machinery 1031 * clear receive machinery 1032 * drain and release tx queues 1033 * reclaim beacon resources 1034 * power down hardware 1035 * 1036 * Note that some of this work is not possible if the 1037 * hardware is gone (invalid). 1038 */ 1039#ifdef ATH_TX99_DIAG 1040 if (sc->sc_tx99 != NULL) 1041 sc->sc_tx99->stop(sc->sc_tx99); 1042#endif 1043 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1044 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1045 ifp->if_timer = 0; 1046 if (!sc->sc_invalid) { 1047 if (sc->sc_softled) { 1048 callout_stop(&sc->sc_ledtimer); 1049 ath_hal_gpioset(ah, sc->sc_ledpin, 1050 !sc->sc_ledon); 1051 sc->sc_blinking = 0; 1052 } 1053 ath_hal_intrset(ah, 0); 1054 } 1055 ath_draintxq(sc); 1056 if (!sc->sc_invalid) { 1057 ath_stoprecv(sc); 1058 ath_hal_phydisable(ah); 1059 } else 1060 sc->sc_rxlink = NULL; 1061 IFQ_DRV_PURGE(&ifp->if_snd); 1062 ath_beacon_free(sc); 1063 } 1064} 1065 1066static void 1067ath_stop(struct ifnet *ifp) 1068{ 1069 struct ath_softc *sc = ifp->if_softc; 1070 1071 ATH_LOCK(sc); 1072 ath_stop_locked(ifp); 1073 if (!sc->sc_invalid) { 1074 /* 1075 * Set the chip in full sleep mode. Note that we are 1076 * careful to do this only when bringing the interface 1077 * completely to a stop. When the chip is in this state 1078 * it must be carefully woken up or references to 1079 * registers in the PCI clock domain may freeze the bus 1080 * (and system). This varies by chip and is mostly an 1081 * issue with newer parts that go to sleep more quickly. 1082 */ 1083 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1084 } 1085 ATH_UNLOCK(sc); 1086} 1087 1088/* 1089 * Reset the hardware w/o losing operational state. This is 1090 * basically a more efficient way of doing ath_stop, ath_init, 1091 * followed by state transitions to the current 802.11 1092 * operational state. Used to recover from various errors and 1093 * to reset or reload hardware state. 1094 */ 1095static int 1096ath_reset(struct ifnet *ifp) 1097{ 1098 struct ath_softc *sc = ifp->if_softc; 1099 struct ieee80211com *ic = &sc->sc_ic; 1100 struct ath_hal *ah = sc->sc_ah; 1101 struct ieee80211_channel *c; 1102 HAL_STATUS status; 1103 1104 /* 1105 * Convert to a HAL channel description with the flags 1106 * constrained to reflect the current operating mode. 1107 */ 1108 c = ic->ic_curchan; 1109 sc->sc_curchan.channel = c->ic_freq; 1110 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1111 1112 ath_hal_intrset(ah, 0); /* disable interrupts */ 1113 ath_draintxq(sc); /* stop xmit side */ 1114 ath_stoprecv(sc); /* stop recv side */ 1115 /* NB: indicate channel change so we do a full reset */ 1116 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1117 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1118 __func__, status); 1119 ath_update_txpow(sc); /* update tx power state */ 1120 sc->sc_diversity = ath_hal_getdiversity(ah); 1121 sc->sc_calinterval = 1; 1122 sc->sc_caltries = 0; 1123 /* 1124 * We may be doing a reset in response to an ioctl 1125 * that changes the channel so update any state that 1126 * might change as a result. 1127 */ 1128 ath_chan_change(sc, c); 1129 if (ath_startrecv(sc) != 0) /* restart recv */ 1130 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1131 if (ic->ic_state == IEEE80211_S_RUN) 1132 ath_beacon_config(sc); /* restart beacons */ 1133 ath_hal_intrset(ah, sc->sc_imask); 1134 1135 ath_start(ifp); /* restart xmit */ 1136 return 0; 1137} 1138 1139static void 1140ath_start(struct ifnet *ifp) 1141{ 1142 struct ath_softc *sc = ifp->if_softc; 1143 struct ath_hal *ah = sc->sc_ah; 1144 struct ieee80211com *ic = &sc->sc_ic; 1145 struct ieee80211_node *ni; 1146 struct ath_buf *bf; 1147 struct mbuf *m; 1148 struct ieee80211_frame *wh; 1149 struct ether_header *eh; 1150 1151 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1152 return; 1153 for (;;) { 1154 /* 1155 * Grab a TX buffer and associated resources. 1156 */ 1157 ATH_TXBUF_LOCK(sc); 1158 bf = STAILQ_FIRST(&sc->sc_txbuf); 1159 if (bf != NULL) 1160 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1161 ATH_TXBUF_UNLOCK(sc); 1162 if (bf == NULL) { 1163 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1164 __func__); 1165 sc->sc_stats.ast_tx_qstop++; 1166 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1167 break; 1168 } 1169 /* 1170 * Poll the management queue for frames; they 1171 * have priority over normal data frames. 1172 */ 1173 IF_DEQUEUE(&ic->ic_mgtq, m); 1174 if (m == NULL) { 1175 /* 1176 * No data frames go out unless we're associated. 1177 */ 1178 if (ic->ic_state != IEEE80211_S_RUN) { 1179 DPRINTF(sc, ATH_DEBUG_XMIT, 1180 "%s: discard data packet, state %s\n", 1181 __func__, 1182 ieee80211_state_name[ic->ic_state]); 1183 sc->sc_stats.ast_tx_discard++; 1184 ATH_TXBUF_LOCK(sc); 1185 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1186 ATH_TXBUF_UNLOCK(sc); 1187 break; 1188 } 1189 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1190 if (m == NULL) { 1191 ATH_TXBUF_LOCK(sc); 1192 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1193 ATH_TXBUF_UNLOCK(sc); 1194 break; 1195 } 1196 /* 1197 * Find the node for the destination so we can do 1198 * things like power save and fast frames aggregation. 1199 */ 1200 if (m->m_len < sizeof(struct ether_header) && 1201 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1202 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1203 ni = NULL; 1204 goto bad; 1205 } 1206 eh = mtod(m, struct ether_header *); 1207 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1208 if (ni == NULL) { 1209 /* NB: ieee80211_find_txnode does stat+msg */ 1210 m_freem(m); 1211 goto bad; 1212 } 1213 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1214 (m->m_flags & M_PWR_SAV) == 0) { 1215 /* 1216 * Station in power save mode; pass the frame 1217 * to the 802.11 layer and continue. We'll get 1218 * the frame back when the time is right. 1219 */ 1220 ieee80211_pwrsave(ic, ni, m); 1221 goto reclaim; 1222 } 1223 /* calculate priority so we can find the tx queue */ 1224 if (ieee80211_classify(ic, m, ni)) { 1225 DPRINTF(sc, ATH_DEBUG_XMIT, 1226 "%s: discard, classification failure\n", 1227 __func__); 1228 m_freem(m); 1229 goto bad; 1230 } 1231 ifp->if_opackets++; 1232 BPF_MTAP(ifp, m); 1233 /* 1234 * Encapsulate the packet in prep for transmission. 1235 */ 1236 m = ieee80211_encap(ic, m, ni); 1237 if (m == NULL) { 1238 DPRINTF(sc, ATH_DEBUG_XMIT, 1239 "%s: encapsulation failure\n", 1240 __func__); 1241 sc->sc_stats.ast_tx_encap++; 1242 goto bad; 1243 } 1244 } else { 1245 /* 1246 * Hack! The referenced node pointer is in the 1247 * rcvif field of the packet header. This is 1248 * placed there by ieee80211_mgmt_output because 1249 * we need to hold the reference with the frame 1250 * and there's no other way (other than packet 1251 * tags which we consider too expensive to use) 1252 * to pass it along. 1253 */ 1254 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1255 m->m_pkthdr.rcvif = NULL; 1256 1257 wh = mtod(m, struct ieee80211_frame *); 1258 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1259 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1260 /* fill time stamp */ 1261 u_int64_t tsf; 1262 u_int32_t *tstamp; 1263 1264 tsf = ath_hal_gettsf64(ah); 1265 /* XXX: adjust 100us delay to xmit */ 1266 tsf += 100; 1267 tstamp = (u_int32_t *)&wh[1]; 1268 tstamp[0] = htole32(tsf & 0xffffffff); 1269 tstamp[1] = htole32(tsf >> 32); 1270 } 1271 sc->sc_stats.ast_tx_mgmt++; 1272 } 1273 1274 if (ath_tx_start(sc, ni, bf, m)) { 1275 bad: 1276 ifp->if_oerrors++; 1277 reclaim: 1278 ATH_TXBUF_LOCK(sc); 1279 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1280 ATH_TXBUF_UNLOCK(sc); 1281 if (ni != NULL) 1282 ieee80211_free_node(ni); 1283 continue; 1284 } 1285 1286 sc->sc_tx_timer = 5; 1287 ifp->if_timer = 1; 1288 } 1289} 1290 1291static int 1292ath_media_change(struct ifnet *ifp) 1293{ 1294#define IS_UP(ifp) \ 1295 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1296 int error; 1297 1298 error = ieee80211_media_change(ifp); 1299 if (error == ENETRESET) { 1300 struct ath_softc *sc = ifp->if_softc; 1301 struct ieee80211com *ic = &sc->sc_ic; 1302 1303 if (ic->ic_opmode == IEEE80211_M_AHDEMO) { 1304 /* 1305 * Adhoc demo mode is just ibss mode w/o beacons 1306 * (mostly). The hal knows nothing about it; 1307 * tell it we're operating in ibss mode. 1308 */ 1309 sc->sc_opmode = HAL_M_IBSS; 1310 } else 1311 sc->sc_opmode = ic->ic_opmode; 1312 if (IS_UP(ifp)) 1313 ath_init(ifp->if_softc); /* XXX lose error */ 1314 error = 0; 1315 } 1316 return error; 1317#undef IS_UP 1318} 1319 1320#ifdef ATH_DEBUG 1321static void 1322ath_keyprint(const char *tag, u_int ix, 1323 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1324{ 1325 static const char *ciphers[] = { 1326 "WEP", 1327 "AES-OCB", 1328 "AES-CCM", 1329 "CKIP", 1330 "TKIP", 1331 "CLR", 1332 }; 1333 int i, n; 1334 1335 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1336 for (i = 0, n = hk->kv_len; i < n; i++) 1337 printf("%02x", hk->kv_val[i]); 1338 printf(" mac %s", ether_sprintf(mac)); 1339 if (hk->kv_type == HAL_CIPHER_TKIP) { 1340 printf(" mic "); 1341 for (i = 0; i < sizeof(hk->kv_mic); i++) 1342 printf("%02x", hk->kv_mic[i]); 1343 } 1344 printf("\n"); 1345} 1346#endif 1347 1348/* 1349 * Set a TKIP key into the hardware. This handles the 1350 * potential distribution of key state to multiple key 1351 * cache slots for TKIP. 1352 */ 1353static int 1354ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1355 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1356{ 1357#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1358 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1359 struct ath_hal *ah = sc->sc_ah; 1360 1361 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1362 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1363 KASSERT(sc->sc_splitmic, ("key cache !split")); 1364 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1365 /* 1366 * TX key goes at first index, RX key at the rx index. 1367 * The hal handles the MIC keys at index+64. 1368 */ 1369 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1370 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1371 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1372 return 0; 1373 1374 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1375 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1376 /* XXX delete tx key on failure? */ 1377 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1378 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1379 /* 1380 * TX/RX key goes at first index. 1381 * The hal handles the MIC keys are index+64. 1382 */ 1383 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1384 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1385 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1386 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1387 } 1388 return 0; 1389#undef IEEE80211_KEY_XR 1390} 1391 1392/* 1393 * Set a net80211 key into the hardware. This handles the 1394 * potential distribution of key state to multiple key 1395 * cache slots for TKIP with hardware MIC support. 1396 */ 1397static int 1398ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1399 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1400 struct ieee80211_node *bss) 1401{ 1402#define N(a) (sizeof(a)/sizeof(a[0])) 1403 static const u_int8_t ciphermap[] = { 1404 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1405 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1406 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1407 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1408 (u_int8_t) -1, /* 4 is not allocated */ 1409 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1410 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1411 }; 1412 struct ath_hal *ah = sc->sc_ah; 1413 const struct ieee80211_cipher *cip = k->wk_cipher; 1414 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1415 const u_int8_t *mac; 1416 HAL_KEYVAL hk; 1417 1418 memset(&hk, 0, sizeof(hk)); 1419 /* 1420 * Software crypto uses a "clear key" so non-crypto 1421 * state kept in the key cache are maintained and 1422 * so that rx frames have an entry to match. 1423 */ 1424 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1425 KASSERT(cip->ic_cipher < N(ciphermap), 1426 ("invalid cipher type %u", cip->ic_cipher)); 1427 hk.kv_type = ciphermap[cip->ic_cipher]; 1428 hk.kv_len = k->wk_keylen; 1429 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1430 } else 1431 hk.kv_type = HAL_CIPHER_CLR; 1432 1433 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1434 /* 1435 * Group keys on hardware that supports multicast frame 1436 * key search use a mac that is the sender's address with 1437 * the high bit set instead of the app-specified address. 1438 */ 1439 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1440 gmac[0] |= 0x80; 1441 mac = gmac; 1442 } else 1443 mac = mac0; 1444 1445 if (hk.kv_type == HAL_CIPHER_TKIP && 1446 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1447 sc->sc_splitmic) { 1448 return ath_keyset_tkip(sc, k, &hk, mac); 1449 } else { 1450 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1451 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1452 } 1453#undef N 1454} 1455 1456/* 1457 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1458 * each key, one for decrypt/encrypt and the other for the MIC. 1459 */ 1460static u_int16_t 1461key_alloc_2pair(struct ath_softc *sc, 1462 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1463{ 1464#define N(a) (sizeof(a)/sizeof(a[0])) 1465 u_int i, keyix; 1466 1467 KASSERT(sc->sc_splitmic, ("key cache !split")); 1468 /* XXX could optimize */ 1469 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1470 u_int8_t b = sc->sc_keymap[i]; 1471 if (b != 0xff) { 1472 /* 1473 * One or more slots in this byte are free. 1474 */ 1475 keyix = i*NBBY; 1476 while (b & 1) { 1477 again: 1478 keyix++; 1479 b >>= 1; 1480 } 1481 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1482 if (isset(sc->sc_keymap, keyix+32) || 1483 isset(sc->sc_keymap, keyix+64) || 1484 isset(sc->sc_keymap, keyix+32+64)) { 1485 /* full pair unavailable */ 1486 /* XXX statistic */ 1487 if (keyix == (i+1)*NBBY) { 1488 /* no slots were appropriate, advance */ 1489 continue; 1490 } 1491 goto again; 1492 } 1493 setbit(sc->sc_keymap, keyix); 1494 setbit(sc->sc_keymap, keyix+64); 1495 setbit(sc->sc_keymap, keyix+32); 1496 setbit(sc->sc_keymap, keyix+32+64); 1497 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1498 "%s: key pair %u,%u %u,%u\n", 1499 __func__, keyix, keyix+64, 1500 keyix+32, keyix+32+64); 1501 *txkeyix = keyix; 1502 *rxkeyix = keyix+32; 1503 return 1; 1504 } 1505 } 1506 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1507 return 0; 1508#undef N 1509} 1510 1511/* 1512 * Allocate a single key cache slot. 1513 */ 1514static int 1515key_alloc_single(struct ath_softc *sc, 1516 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1517{ 1518#define N(a) (sizeof(a)/sizeof(a[0])) 1519 u_int i, keyix; 1520 1521 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1522 for (i = 0; i < N(sc->sc_keymap); i++) { 1523 u_int8_t b = sc->sc_keymap[i]; 1524 if (b != 0xff) { 1525 /* 1526 * One or more slots are free. 1527 */ 1528 keyix = i*NBBY; 1529 while (b & 1) 1530 keyix++, b >>= 1; 1531 setbit(sc->sc_keymap, keyix); 1532 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1533 __func__, keyix); 1534 *txkeyix = *rxkeyix = keyix; 1535 return 1; 1536 } 1537 } 1538 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1539 return 0; 1540#undef N 1541} 1542 1543/* 1544 * Allocate one or more key cache slots for a uniacst key. The 1545 * key itself is needed only to identify the cipher. For hardware 1546 * TKIP with split cipher+MIC keys we allocate two key cache slot 1547 * pairs so that we can setup separate TX and RX MIC keys. Note 1548 * that the MIC key for a TKIP key at slot i is assumed by the 1549 * hardware to be at slot i+64. This limits TKIP keys to the first 1550 * 64 entries. 1551 */ 1552static int 1553ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1554 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1555{ 1556 struct ath_softc *sc = ic->ic_ifp->if_softc; 1557 1558 /* 1559 * Group key allocation must be handled specially for 1560 * parts that do not support multicast key cache search 1561 * functionality. For those parts the key id must match 1562 * the h/w key index so lookups find the right key. On 1563 * parts w/ the key search facility we install the sender's 1564 * mac address (with the high bit set) and let the hardware 1565 * find the key w/o using the key id. This is preferred as 1566 * it permits us to support multiple users for adhoc and/or 1567 * multi-station operation. 1568 */ 1569 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1570 if (!(&ic->ic_nw_keys[0] <= k && 1571 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1572 /* should not happen */ 1573 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1574 "%s: bogus group key\n", __func__); 1575 return 0; 1576 } 1577 /* 1578 * XXX we pre-allocate the global keys so 1579 * have no way to check if they've already been allocated. 1580 */ 1581 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1582 return 1; 1583 } 1584 1585 /* 1586 * We allocate two pair for TKIP when using the h/w to do 1587 * the MIC. For everything else, including software crypto, 1588 * we allocate a single entry. Note that s/w crypto requires 1589 * a pass-through slot on the 5211 and 5212. The 5210 does 1590 * not support pass-through cache entries and we map all 1591 * those requests to slot 0. 1592 */ 1593 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1594 return key_alloc_single(sc, keyix, rxkeyix); 1595 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1596 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1597 return key_alloc_2pair(sc, keyix, rxkeyix); 1598 } else { 1599 return key_alloc_single(sc, keyix, rxkeyix); 1600 } 1601} 1602 1603/* 1604 * Delete an entry in the key cache allocated by ath_key_alloc. 1605 */ 1606static int 1607ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1608{ 1609 struct ath_softc *sc = ic->ic_ifp->if_softc; 1610 struct ath_hal *ah = sc->sc_ah; 1611 const struct ieee80211_cipher *cip = k->wk_cipher; 1612 u_int keyix = k->wk_keyix; 1613 1614 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1615 1616 ath_hal_keyreset(ah, keyix); 1617 /* 1618 * Handle split tx/rx keying required for TKIP with h/w MIC. 1619 */ 1620 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1621 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1622 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1623 if (keyix >= IEEE80211_WEP_NKID) { 1624 /* 1625 * Don't touch keymap entries for global keys so 1626 * they are never considered for dynamic allocation. 1627 */ 1628 clrbit(sc->sc_keymap, keyix); 1629 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1630 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1631 sc->sc_splitmic) { 1632 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1633 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1634 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1635 } 1636 } 1637 return 1; 1638} 1639 1640/* 1641 * Set the key cache contents for the specified key. Key cache 1642 * slot(s) must already have been allocated by ath_key_alloc. 1643 */ 1644static int 1645ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1646 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1647{ 1648 struct ath_softc *sc = ic->ic_ifp->if_softc; 1649 1650 return ath_keyset(sc, k, mac, ic->ic_bss); 1651} 1652 1653/* 1654 * Block/unblock tx+rx processing while a key change is done. 1655 * We assume the caller serializes key management operations 1656 * so we only need to worry about synchronization with other 1657 * uses that originate in the driver. 1658 */ 1659static void 1660ath_key_update_begin(struct ieee80211com *ic) 1661{ 1662 struct ifnet *ifp = ic->ic_ifp; 1663 struct ath_softc *sc = ifp->if_softc; 1664 1665 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1666#if 0 1667 tasklet_disable(&sc->sc_rxtq); 1668#endif 1669 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1670} 1671 1672static void 1673ath_key_update_end(struct ieee80211com *ic) 1674{ 1675 struct ifnet *ifp = ic->ic_ifp; 1676 struct ath_softc *sc = ifp->if_softc; 1677 1678 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1679 IF_UNLOCK(&ifp->if_snd); 1680#if 0 1681 tasklet_enable(&sc->sc_rxtq); 1682#endif 1683} 1684 1685/* 1686 * Calculate the receive filter according to the 1687 * operating mode and state: 1688 * 1689 * o always accept unicast, broadcast, and multicast traffic 1690 * o maintain current state of phy error reception (the hal 1691 * may enable phy error frames for noise immunity work) 1692 * o probe request frames are accepted only when operating in 1693 * hostap, adhoc, or monitor modes 1694 * o enable promiscuous mode according to the interface state 1695 * o accept beacons: 1696 * - when operating in adhoc mode so the 802.11 layer creates 1697 * node table entries for peers, 1698 * - when operating in station mode for collecting rssi data when 1699 * the station is otherwise quiet, or 1700 * - when scanning 1701 */ 1702static u_int32_t 1703ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1704{ 1705#define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR) 1706 struct ieee80211com *ic = &sc->sc_ic; 1707 struct ath_hal *ah = sc->sc_ah; 1708 struct ifnet *ifp = sc->sc_ifp; 1709 u_int32_t rfilt; 1710 1711 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE) 1712 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1713 if (ic->ic_opmode != IEEE80211_M_STA) 1714 rfilt |= HAL_RX_FILTER_PROBEREQ; 1715 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1716 (ifp->if_flags & IFF_PROMISC)) 1717 rfilt |= HAL_RX_FILTER_PROM; 1718 if (ic->ic_opmode == IEEE80211_M_STA || 1719 ic->ic_opmode == IEEE80211_M_IBSS || 1720 state == IEEE80211_S_SCAN) 1721 rfilt |= HAL_RX_FILTER_BEACON; 1722 return rfilt; 1723#undef RX_FILTER_PRESERVE 1724} 1725 1726static void 1727ath_mode_init(struct ath_softc *sc) 1728{ 1729 struct ieee80211com *ic = &sc->sc_ic; 1730 struct ath_hal *ah = sc->sc_ah; 1731 struct ifnet *ifp = sc->sc_ifp; 1732 u_int32_t rfilt, mfilt[2], val; 1733 u_int8_t pos; 1734 struct ifmultiaddr *ifma; 1735 1736 /* configure rx filter */ 1737 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1738 ath_hal_setrxfilter(ah, rfilt); 1739 1740 /* configure operational mode */ 1741 ath_hal_setopmode(ah); 1742 1743 /* 1744 * Handle any link-level address change. Note that we only 1745 * need to force ic_myaddr; any other addresses are handled 1746 * as a byproduct of the ifnet code marking the interface 1747 * down then up. 1748 * 1749 * XXX should get from lladdr instead of arpcom but that's more work 1750 */ 1751 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1752 ath_hal_setmac(ah, ic->ic_myaddr); 1753 1754 /* calculate and install multicast filter */ 1755 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1756 mfilt[0] = mfilt[1] = 0; 1757 IF_ADDR_LOCK(ifp); 1758 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1759 caddr_t dl; 1760 1761 /* calculate XOR of eight 6bit values */ 1762 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1763 val = LE_READ_4(dl + 0); 1764 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1765 val = LE_READ_4(dl + 3); 1766 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1767 pos &= 0x3f; 1768 mfilt[pos / 32] |= (1 << (pos % 32)); 1769 } 1770 IF_ADDR_UNLOCK(ifp); 1771 } else { 1772 mfilt[0] = mfilt[1] = ~0; 1773 } 1774 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1775 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1776 __func__, rfilt, mfilt[0], mfilt[1]); 1777} 1778 1779/* 1780 * Set the slot time based on the current setting. 1781 */ 1782static void 1783ath_setslottime(struct ath_softc *sc) 1784{ 1785 struct ieee80211com *ic = &sc->sc_ic; 1786 struct ath_hal *ah = sc->sc_ah; 1787 1788 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1789 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1790 else 1791 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1792 sc->sc_updateslot = OK; 1793} 1794 1795/* 1796 * Callback from the 802.11 layer to update the 1797 * slot time based on the current setting. 1798 */ 1799static void 1800ath_updateslot(struct ifnet *ifp) 1801{ 1802 struct ath_softc *sc = ifp->if_softc; 1803 struct ieee80211com *ic = &sc->sc_ic; 1804 1805 /* 1806 * When not coordinating the BSS, change the hardware 1807 * immediately. For other operation we defer the change 1808 * until beacon updates have propagated to the stations. 1809 */ 1810 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1811 sc->sc_updateslot = UPDATE; 1812 else 1813 ath_setslottime(sc); 1814} 1815 1816/* 1817 * Setup a h/w transmit queue for beacons. 1818 */ 1819static int 1820ath_beaconq_setup(struct ath_hal *ah) 1821{ 1822 HAL_TXQ_INFO qi; 1823 1824 memset(&qi, 0, sizeof(qi)); 1825 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1826 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1827 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1828 /* NB: for dynamic turbo, don't enable any other interrupts */ 1829 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1830 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1831} 1832 1833/* 1834 * Setup the transmit queue parameters for the beacon queue. 1835 */ 1836static int 1837ath_beaconq_config(struct ath_softc *sc) 1838{ 1839#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1840 struct ieee80211com *ic = &sc->sc_ic; 1841 struct ath_hal *ah = sc->sc_ah; 1842 HAL_TXQ_INFO qi; 1843 1844 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1845 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1846 /* 1847 * Always burst out beacon and CAB traffic. 1848 */ 1849 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1850 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1851 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1852 } else { 1853 struct wmeParams *wmep = 1854 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1855 /* 1856 * Adhoc mode; important thing is to use 2x cwmin. 1857 */ 1858 qi.tqi_aifs = wmep->wmep_aifsn; 1859 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1860 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1861 } 1862 1863 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1864 device_printf(sc->sc_dev, "unable to update parameters for " 1865 "beacon hardware queue!\n"); 1866 return 0; 1867 } else { 1868 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1869 return 1; 1870 } 1871#undef ATH_EXPONENT_TO_VALUE 1872} 1873 1874/* 1875 * Allocate and setup an initial beacon frame. 1876 */ 1877static int 1878ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1879{ 1880 struct ieee80211com *ic = ni->ni_ic; 1881 struct ath_buf *bf; 1882 struct mbuf *m; 1883 int error; 1884 1885 bf = STAILQ_FIRST(&sc->sc_bbuf); 1886 if (bf == NULL) { 1887 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1888 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1889 return ENOMEM; /* XXX */ 1890 } 1891 /* 1892 * NB: the beacon data buffer must be 32-bit aligned; 1893 * we assume the mbuf routines will return us something 1894 * with this alignment (perhaps should assert). 1895 */ 1896 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1897 if (m == NULL) { 1898 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1899 __func__); 1900 sc->sc_stats.ast_be_nombuf++; 1901 return ENOMEM; 1902 } 1903 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1904 bf->bf_segs, &bf->bf_nseg, 1905 BUS_DMA_NOWAIT); 1906 if (error == 0) { 1907 bf->bf_m = m; 1908 bf->bf_node = ieee80211_ref_node(ni); 1909 } else { 1910 m_freem(m); 1911 } 1912 return error; 1913} 1914 1915/* 1916 * Setup the beacon frame for transmit. 1917 */ 1918static void 1919ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1920{ 1921#define USE_SHPREAMBLE(_ic) \ 1922 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1923 == IEEE80211_F_SHPREAMBLE) 1924 struct ieee80211_node *ni = bf->bf_node; 1925 struct ieee80211com *ic = ni->ni_ic; 1926 struct mbuf *m = bf->bf_m; 1927 struct ath_hal *ah = sc->sc_ah; 1928 struct ath_desc *ds; 1929 int flags, antenna; 1930 const HAL_RATE_TABLE *rt; 1931 u_int8_t rix, rate; 1932 1933 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 1934 __func__, m, m->m_len); 1935 1936 /* setup descriptors */ 1937 ds = bf->bf_desc; 1938 1939 flags = HAL_TXDESC_NOACK; 1940 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1941 ds->ds_link = bf->bf_daddr; /* self-linked */ 1942 flags |= HAL_TXDESC_VEOL; 1943 /* 1944 * Let hardware handle antenna switching. 1945 */ 1946 antenna = sc->sc_txantenna; 1947 } else { 1948 ds->ds_link = 0; 1949 /* 1950 * Switch antenna every 4 beacons. 1951 * XXX assumes two antenna 1952 */ 1953 antenna = sc->sc_txantenna != 0 ? sc->sc_txantenna 1954 : (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 1955 } 1956 1957 KASSERT(bf->bf_nseg == 1, 1958 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 1959 ds->ds_data = bf->bf_segs[0].ds_addr; 1960 /* 1961 * Calculate rate code. 1962 * XXX everything at min xmit rate 1963 */ 1964 rix = sc->sc_minrateix; 1965 rt = sc->sc_currates; 1966 rate = rt->info[rix].rateCode; 1967 if (USE_SHPREAMBLE(ic)) 1968 rate |= rt->info[rix].shortPreamble; 1969 ath_hal_setuptxdesc(ah, ds 1970 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 1971 , sizeof(struct ieee80211_frame)/* header length */ 1972 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1973 , ni->ni_txpower /* txpower XXX */ 1974 , rate, 1 /* series 0 rate/tries */ 1975 , HAL_TXKEYIX_INVALID /* no encryption */ 1976 , antenna /* antenna mode */ 1977 , flags /* no ack, veol for beacons */ 1978 , 0 /* rts/cts rate */ 1979 , 0 /* rts/cts duration */ 1980 ); 1981 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1982 ath_hal_filltxdesc(ah, ds 1983 , roundup(m->m_len, 4) /* buffer length */ 1984 , AH_TRUE /* first segment */ 1985 , AH_TRUE /* last segment */ 1986 , ds /* first descriptor */ 1987 ); 1988#undef USE_SHPREAMBLE 1989} 1990 1991/* 1992 * Transmit a beacon frame at SWBA. Dynamic updates to the 1993 * frame contents are done as needed and the slot time is 1994 * also adjusted based on current state. 1995 */ 1996static void 1997ath_beacon_proc(void *arg, int pending) 1998{ 1999 struct ath_softc *sc = arg; 2000 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2001 struct ieee80211_node *ni = bf->bf_node; 2002 struct ieee80211com *ic = ni->ni_ic; 2003 struct ath_hal *ah = sc->sc_ah; 2004 struct mbuf *m; 2005 int ncabq, error, otherant; 2006 2007 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2008 __func__, pending); 2009 2010 if (ic->ic_opmode == IEEE80211_M_STA || 2011 ic->ic_opmode == IEEE80211_M_MONITOR || 2012 bf == NULL || bf->bf_m == NULL) { 2013 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2014 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2015 return; 2016 } 2017 /* 2018 * Check if the previous beacon has gone out. If 2019 * not don't try to post another, skip this period 2020 * and wait for the next. Missed beacons indicate 2021 * a problem and should not occur. If we miss too 2022 * many consecutive beacons reset the device. 2023 */ 2024 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2025 sc->sc_bmisscount++; 2026 DPRINTF(sc, ATH_DEBUG_BEACON, 2027 "%s: missed %u consecutive beacons\n", 2028 __func__, sc->sc_bmisscount); 2029 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2030 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2031 return; 2032 } 2033 if (sc->sc_bmisscount != 0) { 2034 DPRINTF(sc, ATH_DEBUG_BEACON, 2035 "%s: resume beacon xmit after %u misses\n", 2036 __func__, sc->sc_bmisscount); 2037 sc->sc_bmisscount = 0; 2038 } 2039 2040 /* 2041 * Update dynamic beacon contents. If this returns 2042 * non-zero then we need to remap the memory because 2043 * the beacon frame changed size (probably because 2044 * of the TIM bitmap). 2045 */ 2046 m = bf->bf_m; 2047 ncabq = sc->sc_cabq->axq_depth; 2048 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2049 /* XXX too conservative? */ 2050 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2051 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2052 bf->bf_segs, &bf->bf_nseg, 2053 BUS_DMA_NOWAIT); 2054 if (error != 0) { 2055 if_printf(ic->ic_ifp, 2056 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2057 __func__, error); 2058 return; 2059 } 2060 } 2061 2062 /* 2063 * Handle slot time change when a non-ERP station joins/leaves 2064 * an 11g network. The 802.11 layer notifies us via callback, 2065 * we mark updateslot, then wait one beacon before effecting 2066 * the change. This gives associated stations at least one 2067 * beacon interval to note the state change. 2068 */ 2069 /* XXX locking */ 2070 if (sc->sc_updateslot == UPDATE) 2071 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2072 else if (sc->sc_updateslot == COMMIT) 2073 ath_setslottime(sc); /* commit change to h/w */ 2074 2075 /* 2076 * Check recent per-antenna transmit statistics and flip 2077 * the default antenna if noticeably more frames went out 2078 * on the non-default antenna. 2079 * XXX assumes 2 anntenae 2080 */ 2081 otherant = sc->sc_defant & 1 ? 2 : 1; 2082 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2083 ath_setdefantenna(sc, otherant); 2084 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2085 2086 /* 2087 * Construct tx descriptor. 2088 */ 2089 ath_beacon_setup(sc, bf); 2090 2091 /* 2092 * Stop any current dma and put the new frame on the queue. 2093 * This should never fail since we check above that no frames 2094 * are still pending on the queue. 2095 */ 2096 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2097 DPRINTF(sc, ATH_DEBUG_ANY, 2098 "%s: beacon queue %u did not stop?\n", 2099 __func__, sc->sc_bhalq); 2100 } 2101 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2102 2103 /* 2104 * Enable the CAB queue before the beacon queue to 2105 * insure cab frames are triggered by this beacon. 2106 */ 2107 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2108 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2109 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2110 ath_hal_txstart(ah, sc->sc_bhalq); 2111 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2112 "%s: TXDP[%u] = %p (%p)\n", __func__, 2113 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2114 2115 sc->sc_stats.ast_be_xmit++; 2116} 2117 2118/* 2119 * Reset the hardware after detecting beacons have stopped. 2120 */ 2121static void 2122ath_bstuck_proc(void *arg, int pending) 2123{ 2124 struct ath_softc *sc = arg; 2125 struct ifnet *ifp = sc->sc_ifp; 2126 2127 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2128 sc->sc_bmisscount); 2129 ath_reset(ifp); 2130} 2131 2132/* 2133 * Reclaim beacon resources. 2134 */ 2135static void 2136ath_beacon_free(struct ath_softc *sc) 2137{ 2138 struct ath_buf *bf; 2139 2140 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2141 if (bf->bf_m != NULL) { 2142 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2143 m_freem(bf->bf_m); 2144 bf->bf_m = NULL; 2145 } 2146 if (bf->bf_node != NULL) { 2147 ieee80211_free_node(bf->bf_node); 2148 bf->bf_node = NULL; 2149 } 2150 } 2151} 2152 2153/* 2154 * Configure the beacon and sleep timers. 2155 * 2156 * When operating as an AP this resets the TSF and sets 2157 * up the hardware to notify us when we need to issue beacons. 2158 * 2159 * When operating in station mode this sets up the beacon 2160 * timers according to the timestamp of the last received 2161 * beacon and the current TSF, configures PCF and DTIM 2162 * handling, programs the sleep registers so the hardware 2163 * will wakeup in time to receive beacons, and configures 2164 * the beacon miss handling so we'll receive a BMISS 2165 * interrupt when we stop seeing beacons from the AP 2166 * we've associated with. 2167 */ 2168static void 2169ath_beacon_config(struct ath_softc *sc) 2170{ 2171#define TSF_TO_TU(_h,_l) \ 2172 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2173#define FUDGE 2 2174 struct ath_hal *ah = sc->sc_ah; 2175 struct ieee80211com *ic = &sc->sc_ic; 2176 struct ieee80211_node *ni = ic->ic_bss; 2177 u_int32_t nexttbtt, intval, tsftu; 2178 u_int64_t tsf; 2179 2180 /* extract tstamp from last beacon and convert to TU */ 2181 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2182 LE_READ_4(ni->ni_tstamp.data)); 2183 /* NB: the beacon interval is kept internally in TU's */ 2184 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2185 if (nexttbtt == 0) /* e.g. for ap mode */ 2186 nexttbtt = intval; 2187 else if (intval) /* NB: can be 0 for monitor mode */ 2188 nexttbtt = roundup(nexttbtt, intval); 2189 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2190 __func__, nexttbtt, intval, ni->ni_intval); 2191 if (ic->ic_opmode == IEEE80211_M_STA) { 2192 HAL_BEACON_STATE bs; 2193 int dtimperiod, dtimcount; 2194 int cfpperiod, cfpcount; 2195 2196 /* 2197 * Setup dtim and cfp parameters according to 2198 * last beacon we received (which may be none). 2199 */ 2200 dtimperiod = ni->ni_dtim_period; 2201 if (dtimperiod <= 0) /* NB: 0 if not known */ 2202 dtimperiod = 1; 2203 dtimcount = ni->ni_dtim_count; 2204 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2205 dtimcount = 0; /* XXX? */ 2206 cfpperiod = 1; /* NB: no PCF support yet */ 2207 cfpcount = 0; 2208 /* 2209 * Pull nexttbtt forward to reflect the current 2210 * TSF and calculate dtim+cfp state for the result. 2211 */ 2212 tsf = ath_hal_gettsf64(ah); 2213 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2214 do { 2215 nexttbtt += intval; 2216 if (--dtimcount < 0) { 2217 dtimcount = dtimperiod - 1; 2218 if (--cfpcount < 0) 2219 cfpcount = cfpperiod - 1; 2220 } 2221 } while (nexttbtt < tsftu); 2222 memset(&bs, 0, sizeof(bs)); 2223 bs.bs_intval = intval; 2224 bs.bs_nexttbtt = nexttbtt; 2225 bs.bs_dtimperiod = dtimperiod*intval; 2226 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2227 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2228 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2229 bs.bs_cfpmaxduration = 0; 2230#if 0 2231 /* 2232 * The 802.11 layer records the offset to the DTIM 2233 * bitmap while receiving beacons; use it here to 2234 * enable h/w detection of our AID being marked in 2235 * the bitmap vector (to indicate frames for us are 2236 * pending at the AP). 2237 * XXX do DTIM handling in s/w to WAR old h/w bugs 2238 * XXX enable based on h/w rev for newer chips 2239 */ 2240 bs.bs_timoffset = ni->ni_timoff; 2241#endif 2242 /* 2243 * Calculate the number of consecutive beacons to miss 2244 * before taking a BMISS interrupt. The configuration 2245 * is specified in ms, so we need to convert that to 2246 * TU's and then calculate based on the beacon interval. 2247 * Note that we clamp the result to at most 10 beacons. 2248 */ 2249 bs.bs_bmissthreshold = ic->ic_bmissthreshold; 2250 if (bs.bs_bmissthreshold > 10) 2251 bs.bs_bmissthreshold = 10; 2252 else if (bs.bs_bmissthreshold <= 0) 2253 bs.bs_bmissthreshold = 1; 2254 2255 /* 2256 * Calculate sleep duration. The configuration is 2257 * given in ms. We insure a multiple of the beacon 2258 * period is used. Also, if the sleep duration is 2259 * greater than the DTIM period then it makes senses 2260 * to make it a multiple of that. 2261 * 2262 * XXX fixed at 100ms 2263 */ 2264 bs.bs_sleepduration = 2265 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2266 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2267 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2268 2269 DPRINTF(sc, ATH_DEBUG_BEACON, 2270 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2271 , __func__ 2272 , tsf, tsftu 2273 , bs.bs_intval 2274 , bs.bs_nexttbtt 2275 , bs.bs_dtimperiod 2276 , bs.bs_nextdtim 2277 , bs.bs_bmissthreshold 2278 , bs.bs_sleepduration 2279 , bs.bs_cfpperiod 2280 , bs.bs_cfpmaxduration 2281 , bs.bs_cfpnext 2282 , bs.bs_timoffset 2283 ); 2284 ath_hal_intrset(ah, 0); 2285 ath_hal_beacontimers(ah, &bs); 2286 sc->sc_imask |= HAL_INT_BMISS; 2287 ath_hal_intrset(ah, sc->sc_imask); 2288 } else { 2289 ath_hal_intrset(ah, 0); 2290 if (nexttbtt == intval) 2291 intval |= HAL_BEACON_RESET_TSF; 2292 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2293 /* 2294 * In IBSS mode enable the beacon timers but only 2295 * enable SWBA interrupts if we need to manually 2296 * prepare beacon frames. Otherwise we use a 2297 * self-linked tx descriptor and let the hardware 2298 * deal with things. 2299 */ 2300 intval |= HAL_BEACON_ENA; 2301 if (!sc->sc_hasveol) 2302 sc->sc_imask |= HAL_INT_SWBA; 2303 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2304 /* 2305 * Pull nexttbtt forward to reflect 2306 * the current TSF. 2307 */ 2308 tsf = ath_hal_gettsf64(ah); 2309 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2310 do { 2311 nexttbtt += intval; 2312 } while (nexttbtt < tsftu); 2313 } 2314 ath_beaconq_config(sc); 2315 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2316 /* 2317 * In AP mode we enable the beacon timers and 2318 * SWBA interrupts to prepare beacon frames. 2319 */ 2320 intval |= HAL_BEACON_ENA; 2321 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2322 ath_beaconq_config(sc); 2323 } 2324 ath_hal_beaconinit(ah, nexttbtt, intval); 2325 sc->sc_bmisscount = 0; 2326 ath_hal_intrset(ah, sc->sc_imask); 2327 /* 2328 * When using a self-linked beacon descriptor in 2329 * ibss mode load it once here. 2330 */ 2331 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2332 ath_beacon_proc(sc, 0); 2333 } 2334 sc->sc_syncbeacon = 0; 2335#undef FUDGE 2336#undef TSF_TO_TU 2337} 2338 2339static void 2340ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2341{ 2342 bus_addr_t *paddr = (bus_addr_t*) arg; 2343 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2344 *paddr = segs->ds_addr; 2345} 2346 2347static int 2348ath_descdma_setup(struct ath_softc *sc, 2349 struct ath_descdma *dd, ath_bufhead *head, 2350 const char *name, int nbuf, int ndesc) 2351{ 2352#define DS2PHYS(_dd, _ds) \ 2353 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2354 struct ifnet *ifp = sc->sc_ifp; 2355 struct ath_desc *ds; 2356 struct ath_buf *bf; 2357 int i, bsize, error; 2358 2359 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2360 __func__, name, nbuf, ndesc); 2361 2362 dd->dd_name = name; 2363 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2364 2365 /* 2366 * Setup DMA descriptor area. 2367 */ 2368 error = bus_dma_tag_create(NULL, /* parent */ 2369 PAGE_SIZE, 0, /* alignment, bounds */ 2370 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2371 BUS_SPACE_MAXADDR, /* highaddr */ 2372 NULL, NULL, /* filter, filterarg */ 2373 dd->dd_desc_len, /* maxsize */ 2374 1, /* nsegments */ 2375 dd->dd_desc_len, /* maxsegsize */ 2376 BUS_DMA_ALLOCNOW, /* flags */ 2377 NULL, /* lockfunc */ 2378 NULL, /* lockarg */ 2379 &dd->dd_dmat); 2380 if (error != 0) { 2381 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2382 return error; 2383 } 2384 2385 /* allocate descriptors */ 2386 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2387 if (error != 0) { 2388 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2389 "error %u\n", dd->dd_name, error); 2390 goto fail0; 2391 } 2392 2393 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2394 BUS_DMA_NOWAIT, &dd->dd_dmamap); 2395 if (error != 0) { 2396 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2397 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2398 goto fail1; 2399 } 2400 2401 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2402 dd->dd_desc, dd->dd_desc_len, 2403 ath_load_cb, &dd->dd_desc_paddr, 2404 BUS_DMA_NOWAIT); 2405 if (error != 0) { 2406 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2407 dd->dd_name, error); 2408 goto fail2; 2409 } 2410 2411 ds = dd->dd_desc; 2412 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2413 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2414 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2415 2416 /* allocate rx buffers */ 2417 bsize = sizeof(struct ath_buf) * nbuf; 2418 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2419 if (bf == NULL) { 2420 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2421 dd->dd_name, bsize); 2422 goto fail3; 2423 } 2424 dd->dd_bufptr = bf; 2425 2426 STAILQ_INIT(head); 2427 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2428 bf->bf_desc = ds; 2429 bf->bf_daddr = DS2PHYS(dd, ds); 2430 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2431 &bf->bf_dmamap); 2432 if (error != 0) { 2433 if_printf(ifp, "unable to create dmamap for %s " 2434 "buffer %u, error %u\n", dd->dd_name, i, error); 2435 ath_descdma_cleanup(sc, dd, head); 2436 return error; 2437 } 2438 STAILQ_INSERT_TAIL(head, bf, bf_list); 2439 } 2440 return 0; 2441fail3: 2442 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2443fail2: 2444 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2445fail1: 2446 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2447fail0: 2448 bus_dma_tag_destroy(dd->dd_dmat); 2449 memset(dd, 0, sizeof(*dd)); 2450 return error; 2451#undef DS2PHYS 2452} 2453 2454static void 2455ath_descdma_cleanup(struct ath_softc *sc, 2456 struct ath_descdma *dd, ath_bufhead *head) 2457{ 2458 struct ath_buf *bf; 2459 struct ieee80211_node *ni; 2460 2461 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2462 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2463 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2464 bus_dma_tag_destroy(dd->dd_dmat); 2465 2466 STAILQ_FOREACH(bf, head, bf_list) { 2467 if (bf->bf_m) { 2468 m_freem(bf->bf_m); 2469 bf->bf_m = NULL; 2470 } 2471 if (bf->bf_dmamap != NULL) { 2472 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2473 bf->bf_dmamap = NULL; 2474 } 2475 ni = bf->bf_node; 2476 bf->bf_node = NULL; 2477 if (ni != NULL) { 2478 /* 2479 * Reclaim node reference. 2480 */ 2481 ieee80211_free_node(ni); 2482 } 2483 } 2484 2485 STAILQ_INIT(head); 2486 free(dd->dd_bufptr, M_ATHDEV); 2487 memset(dd, 0, sizeof(*dd)); 2488} 2489 2490static int 2491ath_desc_alloc(struct ath_softc *sc) 2492{ 2493 int error; 2494 2495 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2496 "rx", ath_rxbuf, 1); 2497 if (error != 0) 2498 return error; 2499 2500 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2501 "tx", ath_txbuf, ATH_TXDESC); 2502 if (error != 0) { 2503 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2504 return error; 2505 } 2506 2507 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2508 "beacon", 1, 1); 2509 if (error != 0) { 2510 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2511 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2512 return error; 2513 } 2514 return 0; 2515} 2516 2517static void 2518ath_desc_free(struct ath_softc *sc) 2519{ 2520 2521 if (sc->sc_bdma.dd_desc_len != 0) 2522 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2523 if (sc->sc_txdma.dd_desc_len != 0) 2524 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2525 if (sc->sc_rxdma.dd_desc_len != 0) 2526 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2527} 2528 2529static struct ieee80211_node * 2530ath_node_alloc(struct ieee80211_node_table *nt) 2531{ 2532 struct ieee80211com *ic = nt->nt_ic; 2533 struct ath_softc *sc = ic->ic_ifp->if_softc; 2534 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2535 struct ath_node *an; 2536 2537 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2538 if (an == NULL) { 2539 /* XXX stat+msg */ 2540 return NULL; 2541 } 2542 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2543 ath_rate_node_init(sc, an); 2544 2545 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2546 return &an->an_node; 2547} 2548 2549static void 2550ath_node_free(struct ieee80211_node *ni) 2551{ 2552 struct ieee80211com *ic = ni->ni_ic; 2553 struct ath_softc *sc = ic->ic_ifp->if_softc; 2554 2555 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2556 2557 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2558 sc->sc_node_free(ni); 2559} 2560 2561static u_int8_t 2562ath_node_getrssi(const struct ieee80211_node *ni) 2563{ 2564#define HAL_EP_RND(x, mul) \ 2565 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2566 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2567 int32_t rssi; 2568 2569 /* 2570 * When only one frame is received there will be no state in 2571 * avgrssi so fallback on the value recorded by the 802.11 layer. 2572 */ 2573 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2574 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2575 else 2576 rssi = ni->ni_rssi; 2577 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2578#undef HAL_EP_RND 2579} 2580 2581static int 2582ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2583{ 2584 struct ath_hal *ah = sc->sc_ah; 2585 int error; 2586 struct mbuf *m; 2587 struct ath_desc *ds; 2588 2589 m = bf->bf_m; 2590 if (m == NULL) { 2591 /* 2592 * NB: by assigning a page to the rx dma buffer we 2593 * implicitly satisfy the Atheros requirement that 2594 * this buffer be cache-line-aligned and sized to be 2595 * multiple of the cache line size. Not doing this 2596 * causes weird stuff to happen (for the 5210 at least). 2597 */ 2598 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2599 if (m == NULL) { 2600 DPRINTF(sc, ATH_DEBUG_ANY, 2601 "%s: no mbuf/cluster\n", __func__); 2602 sc->sc_stats.ast_rx_nombuf++; 2603 return ENOMEM; 2604 } 2605 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2606 2607 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 2608 bf->bf_dmamap, m, 2609 bf->bf_segs, &bf->bf_nseg, 2610 BUS_DMA_NOWAIT); 2611 if (error != 0) { 2612 DPRINTF(sc, ATH_DEBUG_ANY, 2613 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 2614 __func__, error); 2615 sc->sc_stats.ast_rx_busdma++; 2616 m_freem(m); 2617 return error; 2618 } 2619 KASSERT(bf->bf_nseg == 1, 2620 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2621 bf->bf_m = m; 2622 } 2623 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 2624 2625 /* 2626 * Setup descriptors. For receive we always terminate 2627 * the descriptor list with a self-linked entry so we'll 2628 * not get overrun under high load (as can happen with a 2629 * 5212 when ANI processing enables PHY error frames). 2630 * 2631 * To insure the last descriptor is self-linked we create 2632 * each descriptor as self-linked and add it to the end. As 2633 * each additional descriptor is added the previous self-linked 2634 * entry is ``fixed'' naturally. This should be safe even 2635 * if DMA is happening. When processing RX interrupts we 2636 * never remove/process the last, self-linked, entry on the 2637 * descriptor list. This insures the hardware always has 2638 * someplace to write a new frame. 2639 */ 2640 ds = bf->bf_desc; 2641 ds->ds_link = bf->bf_daddr; /* link to self */ 2642 ds->ds_data = bf->bf_segs[0].ds_addr; 2643 ds->ds_vdata = mtod(m, void *); /* for radar */ 2644 ath_hal_setuprxdesc(ah, ds 2645 , m->m_len /* buffer size */ 2646 , 0 2647 ); 2648 2649 if (sc->sc_rxlink != NULL) 2650 *sc->sc_rxlink = bf->bf_daddr; 2651 sc->sc_rxlink = &ds->ds_link; 2652 return 0; 2653} 2654 2655/* 2656 * Extend 15-bit time stamp from rx descriptor to 2657 * a full 64-bit TSF using the specified TSF. 2658 */ 2659static __inline u_int64_t 2660ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2661{ 2662 if ((tsf & 0x7fff) < rstamp) 2663 tsf -= 0x8000; 2664 return ((tsf &~ 0x7fff) | rstamp); 2665} 2666 2667/* 2668 * Intercept management frames to collect beacon rssi data 2669 * and to do ibss merges. 2670 */ 2671static void 2672ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2673 struct ieee80211_node *ni, 2674 int subtype, int rssi, u_int32_t rstamp) 2675{ 2676 struct ath_softc *sc = ic->ic_ifp->if_softc; 2677 2678 /* 2679 * Call up first so subsequent work can use information 2680 * potentially stored in the node (e.g. for ibss merge). 2681 */ 2682 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2683 switch (subtype) { 2684 case IEEE80211_FC0_SUBTYPE_BEACON: 2685 /* update rssi statistics for use by the hal */ 2686 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2687 if (sc->sc_syncbeacon && 2688 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2689 /* 2690 * Resync beacon timers using the tsf of the beacon 2691 * frame we just received. 2692 */ 2693 ath_beacon_config(sc); 2694 } 2695 /* fall thru... */ 2696 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2697 if (ic->ic_opmode == IEEE80211_M_IBSS && 2698 ic->ic_state == IEEE80211_S_RUN) { 2699 u_int64_t tsf = ath_extend_tsf(rstamp, 2700 ath_hal_gettsf64(sc->sc_ah)); 2701 /* 2702 * Handle ibss merge as needed; check the tsf on the 2703 * frame before attempting the merge. The 802.11 spec 2704 * says the station should change it's bssid to match 2705 * the oldest station with the same ssid, where oldest 2706 * is determined by the tsf. Note that hardware 2707 * reconfiguration happens through callback to 2708 * ath_newstate as the state machine will go from 2709 * RUN -> RUN when this happens. 2710 */ 2711 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2712 DPRINTF(sc, ATH_DEBUG_STATE, 2713 "ibss merge, rstamp %u tsf %ju " 2714 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2715 (uintmax_t)ni->ni_tstamp.tsf); 2716 (void) ieee80211_ibss_merge(ni); 2717 } 2718 } 2719 break; 2720 } 2721} 2722 2723/* 2724 * Set the default antenna. 2725 */ 2726static void 2727ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2728{ 2729 struct ath_hal *ah = sc->sc_ah; 2730 2731 /* XXX block beacon interrupts */ 2732 ath_hal_setdefantenna(ah, antenna); 2733 if (sc->sc_defant != antenna) 2734 sc->sc_stats.ast_ant_defswitch++; 2735 sc->sc_defant = antenna; 2736 sc->sc_rxotherant = 0; 2737} 2738 2739static int 2740ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 2741 const struct ath_desc *ds, u_int64_t tsf, int16_t nf) 2742{ 2743 u_int8_t rix; 2744 2745 KASSERT(sc->sc_drvbpf != NULL, ("no tap")); 2746 2747 /* 2748 * Discard anything shorter than an ack or cts. 2749 */ 2750 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 2751 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 2752 __func__, m->m_pkthdr.len); 2753 sc->sc_stats.ast_rx_tooshort++; 2754 return 0; 2755 } 2756 sc->sc_rx_th.wr_tsf = htole64( 2757 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 2758 rix = ds->ds_rxstat.rs_rate; 2759 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2760 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2761 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2762 /* XXX propagate other error flags from descriptor */ 2763 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2764 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 2765 sc->sc_rx_th.wr_antnoise = nf; 2766 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2767 2768 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 2769 2770 return 1; 2771} 2772 2773static void 2774ath_rx_proc(void *arg, int npending) 2775{ 2776#define PA2DESC(_sc, _pa) \ 2777 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2778 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2779 struct ath_softc *sc = arg; 2780 struct ath_buf *bf; 2781 struct ieee80211com *ic = &sc->sc_ic; 2782 struct ifnet *ifp = sc->sc_ifp; 2783 struct ath_hal *ah = sc->sc_ah; 2784 struct ath_desc *ds; 2785 struct mbuf *m; 2786 struct ieee80211_node *ni; 2787 struct ath_node *an; 2788 int len, type, ngood; 2789 u_int phyerr; 2790 HAL_STATUS status; 2791 int16_t nf; 2792 u_int64_t tsf; 2793 2794 NET_LOCK_GIANT(); /* XXX */ 2795 2796 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2797 ngood = 0; 2798 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2799 tsf = ath_hal_gettsf64(ah); 2800 do { 2801 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2802 if (bf == NULL) { /* NB: shouldn't happen */ 2803 if_printf(ifp, "%s: no buffer!\n", __func__); 2804 break; 2805 } 2806 m = bf->bf_m; 2807 if (m == NULL) { /* NB: shouldn't happen */ 2808 /* 2809 * If mbuf allocation failed previously there 2810 * will be no mbuf; try again to re-populate it. 2811 */ 2812 /* XXX make debug msg */ 2813 if_printf(ifp, "%s: no mbuf!\n", __func__); 2814 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2815 goto rx_next; 2816 } 2817 ds = bf->bf_desc; 2818 if (ds->ds_link == bf->bf_daddr) { 2819 /* NB: never process the self-linked entry at the end */ 2820 break; 2821 } 2822 /* XXX sync descriptor memory */ 2823 /* 2824 * Must provide the virtual address of the current 2825 * descriptor, the physical address, and the virtual 2826 * address of the next descriptor in the h/w chain. 2827 * This allows the HAL to look ahead to see if the 2828 * hardware is done with a descriptor by checking the 2829 * done bit in the following descriptor and the address 2830 * of the current descriptor the DMA engine is working 2831 * on. All this is necessary because of our use of 2832 * a self-linked list to avoid rx overruns. 2833 */ 2834 status = ath_hal_rxprocdesc(ah, ds, 2835 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2836#ifdef ATH_DEBUG 2837 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2838 ath_printrxbuf(bf, 0, status == HAL_OK); 2839#endif 2840 if (status == HAL_EINPROGRESS) 2841 break; 2842 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2843 if (ds->ds_rxstat.rs_more) { 2844 /* 2845 * Frame spans multiple descriptors; this 2846 * cannot happen yet as we don't support 2847 * jumbograms. If not in monitor mode, 2848 * discard the frame. 2849 */ 2850 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2851 sc->sc_stats.ast_rx_toobig++; 2852 goto rx_next; 2853 } 2854 /* fall thru for monitor mode handling... */ 2855 } else if (ds->ds_rxstat.rs_status != 0) { 2856 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2857 sc->sc_stats.ast_rx_crcerr++; 2858 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2859 sc->sc_stats.ast_rx_fifoerr++; 2860 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2861 sc->sc_stats.ast_rx_phyerr++; 2862 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2863 sc->sc_stats.ast_rx_phy[phyerr]++; 2864 goto rx_next; 2865 } 2866 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2867 /* 2868 * Decrypt error. If the error occurred 2869 * because there was no hardware key, then 2870 * let the frame through so the upper layers 2871 * can process it. This is necessary for 5210 2872 * parts which have no way to setup a ``clear'' 2873 * key cache entry. 2874 * 2875 * XXX do key cache faulting 2876 */ 2877 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2878 goto rx_accept; 2879 sc->sc_stats.ast_rx_badcrypt++; 2880 } 2881 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2882 sc->sc_stats.ast_rx_badmic++; 2883 /* 2884 * Do minimal work required to hand off 2885 * the 802.11 header for notifcation. 2886 */ 2887 /* XXX frag's and qos frames */ 2888 len = ds->ds_rxstat.rs_datalen; 2889 if (len >= sizeof (struct ieee80211_frame)) { 2890 bus_dmamap_sync(sc->sc_dmat, 2891 bf->bf_dmamap, 2892 BUS_DMASYNC_POSTREAD); 2893 ieee80211_notify_michael_failure(ic, 2894 mtod(m, struct ieee80211_frame *), 2895 sc->sc_splitmic ? 2896 ds->ds_rxstat.rs_keyix-32 : 2897 ds->ds_rxstat.rs_keyix 2898 ); 2899 } 2900 } 2901 ifp->if_ierrors++; 2902 /* 2903 * When a tap is present pass error frames 2904 * that have been requested. By default we 2905 * pass decrypt+mic errors but others may be 2906 * interesting (e.g. crc). 2907 */ 2908 if (bpf_peers_present(sc->sc_drvbpf) && 2909 (ds->ds_rxstat.rs_status & sc->sc_monpass)) { 2910 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2911 BUS_DMASYNC_POSTREAD); 2912 /* NB: bpf needs the mbuf length setup */ 2913 len = ds->ds_rxstat.rs_datalen; 2914 m->m_pkthdr.len = m->m_len = len; 2915 (void) ath_rx_tap(sc, m, ds, tsf, nf); 2916 } 2917 /* XXX pass MIC errors up for s/w reclaculation */ 2918 goto rx_next; 2919 } 2920rx_accept: 2921 /* 2922 * Sync and unmap the frame. At this point we're 2923 * committed to passing the mbuf somewhere so clear 2924 * bf_m; this means a new mbuf must be allocated 2925 * when the rx descriptor is setup again to receive 2926 * another frame. 2927 */ 2928 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2929 BUS_DMASYNC_POSTREAD); 2930 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2931 bf->bf_m = NULL; 2932 2933 m->m_pkthdr.rcvif = ifp; 2934 len = ds->ds_rxstat.rs_datalen; 2935 m->m_pkthdr.len = m->m_len = len; 2936 2937 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2938 2939 if (bpf_peers_present(sc->sc_drvbpf) && 2940 !ath_rx_tap(sc, m, ds, tsf, nf)) { 2941 m_freem(m); /* XXX reclaim */ 2942 goto rx_next; 2943 } 2944 2945 /* 2946 * From this point on we assume the frame is at least 2947 * as large as ieee80211_frame_min; verify that. 2948 */ 2949 if (len < IEEE80211_MIN_LEN) { 2950 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2951 __func__, len); 2952 sc->sc_stats.ast_rx_tooshort++; 2953 m_freem(m); 2954 goto rx_next; 2955 } 2956 2957 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2958 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2959 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2960 ds->ds_rxstat.rs_rssi); 2961 } 2962 2963 m_adj(m, -IEEE80211_CRC_LEN); 2964 2965 /* 2966 * Locate the node for sender, track state, and then 2967 * pass the (referenced) node up to the 802.11 layer 2968 * for its use. 2969 */ 2970 ni = ieee80211_find_rxnode_withkey(ic, 2971 mtod(m, const struct ieee80211_frame_min *), 2972 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 2973 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 2974 /* 2975 * Track rx rssi and do any rx antenna management. 2976 */ 2977 an = ATH_NODE(ni); 2978 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2979 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 2980 /* 2981 * Send frame up for processing. 2982 */ 2983 type = ieee80211_input(ic, m, ni, 2984 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2985 ieee80211_free_node(ni); 2986 if (sc->sc_diversity) { 2987 /* 2988 * When using fast diversity, change the default rx 2989 * antenna if diversity chooses the other antenna 3 2990 * times in a row. 2991 */ 2992 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2993 if (++sc->sc_rxotherant >= 3) 2994 ath_setdefantenna(sc, 2995 ds->ds_rxstat.rs_antenna); 2996 } else 2997 sc->sc_rxotherant = 0; 2998 } 2999 if (sc->sc_softled) { 3000 /* 3001 * Blink for any data frame. Otherwise do a 3002 * heartbeat-style blink when idle. The latter 3003 * is mainly for station mode where we depend on 3004 * periodic beacon frames to trigger the poll event. 3005 */ 3006 if (type == IEEE80211_FC0_TYPE_DATA) { 3007 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3008 ath_led_event(sc, ATH_LED_RX); 3009 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3010 ath_led_event(sc, ATH_LED_POLL); 3011 } 3012 /* 3013 * Arrange to update the last rx timestamp only for 3014 * frames from our ap when operating in station mode. 3015 * This assumes the rx key is always setup when associated. 3016 */ 3017 if (ic->ic_opmode == IEEE80211_M_STA && 3018 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3019 ngood++; 3020rx_next: 3021 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3022 } while (ath_rxbuf_init(sc, bf) == 0); 3023 3024 /* rx signal state monitoring */ 3025 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3026 if (ath_hal_radar_event(ah)) 3027 taskqueue_enqueue(sc->sc_tq, &sc->sc_radartask); 3028 if (ngood) 3029 sc->sc_lastrx = tsf; 3030 3031 NET_UNLOCK_GIANT(); /* XXX */ 3032#undef PA2DESC 3033} 3034 3035/* 3036 * Setup a h/w transmit queue. 3037 */ 3038static struct ath_txq * 3039ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3040{ 3041#define N(a) (sizeof(a)/sizeof(a[0])) 3042 struct ath_hal *ah = sc->sc_ah; 3043 HAL_TXQ_INFO qi; 3044 int qnum; 3045 3046 memset(&qi, 0, sizeof(qi)); 3047 qi.tqi_subtype = subtype; 3048 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3049 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3050 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3051 /* 3052 * Enable interrupts only for EOL and DESC conditions. 3053 * We mark tx descriptors to receive a DESC interrupt 3054 * when a tx queue gets deep; otherwise waiting for the 3055 * EOL to reap descriptors. Note that this is done to 3056 * reduce interrupt load and this only defers reaping 3057 * descriptors, never transmitting frames. Aside from 3058 * reducing interrupts this also permits more concurrency. 3059 * The only potential downside is if the tx queue backs 3060 * up in which case the top half of the kernel may backup 3061 * due to a lack of tx descriptors. 3062 */ 3063 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3064 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3065 if (qnum == -1) { 3066 /* 3067 * NB: don't print a message, this happens 3068 * normally on parts with too few tx queues 3069 */ 3070 return NULL; 3071 } 3072 if (qnum >= N(sc->sc_txq)) { 3073 device_printf(sc->sc_dev, 3074 "hal qnum %u out of range, max %zu!\n", 3075 qnum, N(sc->sc_txq)); 3076 ath_hal_releasetxqueue(ah, qnum); 3077 return NULL; 3078 } 3079 if (!ATH_TXQ_SETUP(sc, qnum)) { 3080 struct ath_txq *txq = &sc->sc_txq[qnum]; 3081 3082 txq->axq_qnum = qnum; 3083 txq->axq_depth = 0; 3084 txq->axq_intrcnt = 0; 3085 txq->axq_link = NULL; 3086 STAILQ_INIT(&txq->axq_q); 3087 ATH_TXQ_LOCK_INIT(sc, txq); 3088 sc->sc_txqsetup |= 1<<qnum; 3089 } 3090 return &sc->sc_txq[qnum]; 3091#undef N 3092} 3093 3094/* 3095 * Setup a hardware data transmit queue for the specified 3096 * access control. The hal may not support all requested 3097 * queues in which case it will return a reference to a 3098 * previously setup queue. We record the mapping from ac's 3099 * to h/w queues for use by ath_tx_start and also track 3100 * the set of h/w queues being used to optimize work in the 3101 * transmit interrupt handler and related routines. 3102 */ 3103static int 3104ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3105{ 3106#define N(a) (sizeof(a)/sizeof(a[0])) 3107 struct ath_txq *txq; 3108 3109 if (ac >= N(sc->sc_ac2q)) { 3110 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3111 ac, N(sc->sc_ac2q)); 3112 return 0; 3113 } 3114 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3115 if (txq != NULL) { 3116 sc->sc_ac2q[ac] = txq; 3117 return 1; 3118 } else 3119 return 0; 3120#undef N 3121} 3122 3123/* 3124 * Update WME parameters for a transmit queue. 3125 */ 3126static int 3127ath_txq_update(struct ath_softc *sc, int ac) 3128{ 3129#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3130#define ATH_TXOP_TO_US(v) (v<<5) 3131 struct ieee80211com *ic = &sc->sc_ic; 3132 struct ath_txq *txq = sc->sc_ac2q[ac]; 3133 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3134 struct ath_hal *ah = sc->sc_ah; 3135 HAL_TXQ_INFO qi; 3136 3137 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3138 qi.tqi_aifs = wmep->wmep_aifsn; 3139 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3140 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3141 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3142 3143 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3144 device_printf(sc->sc_dev, "unable to update hardware queue " 3145 "parameters for %s traffic!\n", 3146 ieee80211_wme_acnames[ac]); 3147 return 0; 3148 } else { 3149 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3150 return 1; 3151 } 3152#undef ATH_TXOP_TO_US 3153#undef ATH_EXPONENT_TO_VALUE 3154} 3155 3156/* 3157 * Callback from the 802.11 layer to update WME parameters. 3158 */ 3159static int 3160ath_wme_update(struct ieee80211com *ic) 3161{ 3162 struct ath_softc *sc = ic->ic_ifp->if_softc; 3163 3164 return !ath_txq_update(sc, WME_AC_BE) || 3165 !ath_txq_update(sc, WME_AC_BK) || 3166 !ath_txq_update(sc, WME_AC_VI) || 3167 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3168} 3169 3170/* 3171 * Reclaim resources for a setup queue. 3172 */ 3173static void 3174ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3175{ 3176 3177 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3178 ATH_TXQ_LOCK_DESTROY(txq); 3179 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3180} 3181 3182/* 3183 * Reclaim all tx queue resources. 3184 */ 3185static void 3186ath_tx_cleanup(struct ath_softc *sc) 3187{ 3188 int i; 3189 3190 ATH_TXBUF_LOCK_DESTROY(sc); 3191 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3192 if (ATH_TXQ_SETUP(sc, i)) 3193 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3194} 3195 3196/* 3197 * Defragment an mbuf chain, returning at most maxfrags separate 3198 * mbufs+clusters. If this is not possible NULL is returned and 3199 * the original mbuf chain is left in it's present (potentially 3200 * modified) state. We use two techniques: collapsing consecutive 3201 * mbufs and replacing consecutive mbufs by a cluster. 3202 */ 3203static struct mbuf * 3204ath_defrag(struct mbuf *m0, int how, int maxfrags) 3205{ 3206 struct mbuf *m, *n, *n2, **prev; 3207 u_int curfrags; 3208 3209 /* 3210 * Calculate the current number of frags. 3211 */ 3212 curfrags = 0; 3213 for (m = m0; m != NULL; m = m->m_next) 3214 curfrags++; 3215 /* 3216 * First, try to collapse mbufs. Note that we always collapse 3217 * towards the front so we don't need to deal with moving the 3218 * pkthdr. This may be suboptimal if the first mbuf has much 3219 * less data than the following. 3220 */ 3221 m = m0; 3222again: 3223 for (;;) { 3224 n = m->m_next; 3225 if (n == NULL) 3226 break; 3227 if ((m->m_flags & M_RDONLY) == 0 && 3228 n->m_len < M_TRAILINGSPACE(m)) { 3229 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3230 n->m_len); 3231 m->m_len += n->m_len; 3232 m->m_next = n->m_next; 3233 m_free(n); 3234 if (--curfrags <= maxfrags) 3235 return m0; 3236 } else 3237 m = n; 3238 } 3239 KASSERT(maxfrags > 1, 3240 ("maxfrags %u, but normal collapse failed", maxfrags)); 3241 /* 3242 * Collapse consecutive mbufs to a cluster. 3243 */ 3244 prev = &m0->m_next; /* NB: not the first mbuf */ 3245 while ((n = *prev) != NULL) { 3246 if ((n2 = n->m_next) != NULL && 3247 n->m_len + n2->m_len < MCLBYTES) { 3248 m = m_getcl(how, MT_DATA, 0); 3249 if (m == NULL) 3250 goto bad; 3251 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3252 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3253 n2->m_len); 3254 m->m_len = n->m_len + n2->m_len; 3255 m->m_next = n2->m_next; 3256 *prev = m; 3257 m_free(n); 3258 m_free(n2); 3259 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3260 return m0; 3261 /* 3262 * Still not there, try the normal collapse 3263 * again before we allocate another cluster. 3264 */ 3265 goto again; 3266 } 3267 prev = &n->m_next; 3268 } 3269 /* 3270 * No place where we can collapse to a cluster; punt. 3271 * This can occur if, for example, you request 2 frags 3272 * but the packet requires that both be clusters (we 3273 * never reallocate the first mbuf to avoid moving the 3274 * packet header). 3275 */ 3276bad: 3277 return NULL; 3278} 3279 3280/* 3281 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3282 */ 3283static int 3284ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3285{ 3286 int i; 3287 3288 for (i = 0; i < rt->rateCount; i++) 3289 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3290 return i; 3291 return 0; /* NB: lowest rate */ 3292} 3293 3294static int 3295ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3296 struct mbuf *m0) 3297{ 3298 struct ieee80211com *ic = &sc->sc_ic; 3299 struct ath_hal *ah = sc->sc_ah; 3300 struct ifnet *ifp = sc->sc_ifp; 3301 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3302 int i, error, iswep, ismcast, ismrr; 3303 int keyix, hdrlen, pktlen, try0; 3304 u_int8_t rix, txrate, ctsrate; 3305 u_int8_t cix = 0xff; /* NB: silence compiler */ 3306 struct ath_desc *ds, *ds0; 3307 struct ath_txq *txq; 3308 struct ieee80211_frame *wh; 3309 u_int subtype, flags, ctsduration; 3310 HAL_PKT_TYPE atype; 3311 const HAL_RATE_TABLE *rt; 3312 HAL_BOOL shortPreamble; 3313 struct ath_node *an; 3314 struct mbuf *m; 3315 u_int pri; 3316 3317 wh = mtod(m0, struct ieee80211_frame *); 3318 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3319 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3320 hdrlen = ieee80211_anyhdrsize(wh); 3321 /* 3322 * Packet length must not include any 3323 * pad bytes; deduct them here. 3324 */ 3325 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3326 3327 if (iswep) { 3328 const struct ieee80211_cipher *cip; 3329 struct ieee80211_key *k; 3330 3331 /* 3332 * Construct the 802.11 header+trailer for an encrypted 3333 * frame. The only reason this can fail is because of an 3334 * unknown or unsupported cipher/key type. 3335 */ 3336 k = ieee80211_crypto_encap(ic, ni, m0); 3337 if (k == NULL) { 3338 /* 3339 * This can happen when the key is yanked after the 3340 * frame was queued. Just discard the frame; the 3341 * 802.11 layer counts failures and provides 3342 * debugging/diagnostics. 3343 */ 3344 m_freem(m0); 3345 return EIO; 3346 } 3347 /* 3348 * Adjust the packet + header lengths for the crypto 3349 * additions and calculate the h/w key index. When 3350 * a s/w mic is done the frame will have had any mic 3351 * added to it prior to entry so m0->m_pkthdr.len above will 3352 * account for it. Otherwise we need to add it to the 3353 * packet length. 3354 */ 3355 cip = k->wk_cipher; 3356 hdrlen += cip->ic_header; 3357 pktlen += cip->ic_header + cip->ic_trailer; 3358 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3359 pktlen += cip->ic_miclen; 3360 keyix = k->wk_keyix; 3361 3362 /* packet header may have moved, reset our local pointer */ 3363 wh = mtod(m0, struct ieee80211_frame *); 3364 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3365 /* 3366 * Use station key cache slot, if assigned. 3367 */ 3368 keyix = ni->ni_ucastkey.wk_keyix; 3369 if (keyix == IEEE80211_KEYIX_NONE) 3370 keyix = HAL_TXKEYIX_INVALID; 3371 } else 3372 keyix = HAL_TXKEYIX_INVALID; 3373 3374 pktlen += IEEE80211_CRC_LEN; 3375 3376 /* 3377 * Load the DMA map so any coalescing is done. This 3378 * also calculates the number of descriptors we need. 3379 */ 3380 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3381 bf->bf_segs, &bf->bf_nseg, 3382 BUS_DMA_NOWAIT); 3383 if (error == EFBIG) { 3384 /* XXX packet requires too many descriptors */ 3385 bf->bf_nseg = ATH_TXDESC+1; 3386 } else if (error != 0) { 3387 sc->sc_stats.ast_tx_busdma++; 3388 m_freem(m0); 3389 return error; 3390 } 3391 /* 3392 * Discard null packets and check for packets that 3393 * require too many TX descriptors. We try to convert 3394 * the latter to a cluster. 3395 */ 3396 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 3397 sc->sc_stats.ast_tx_linear++; 3398 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3399 if (m == NULL) { 3400 m_freem(m0); 3401 sc->sc_stats.ast_tx_nombuf++; 3402 return ENOMEM; 3403 } 3404 m0 = m; 3405 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3406 bf->bf_segs, &bf->bf_nseg, 3407 BUS_DMA_NOWAIT); 3408 if (error != 0) { 3409 sc->sc_stats.ast_tx_busdma++; 3410 m_freem(m0); 3411 return error; 3412 } 3413 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3414 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3415 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3416 sc->sc_stats.ast_tx_nodata++; 3417 m_freem(m0); 3418 return EIO; 3419 } 3420 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3421 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3422 bf->bf_m = m0; 3423 bf->bf_node = ni; /* NB: held reference */ 3424 3425 /* setup descriptors */ 3426 ds = bf->bf_desc; 3427 rt = sc->sc_currates; 3428 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3429 3430 /* 3431 * NB: the 802.11 layer marks whether or not we should 3432 * use short preamble based on the current mode and 3433 * negotiated parameters. 3434 */ 3435 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3436 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3437 shortPreamble = AH_TRUE; 3438 sc->sc_stats.ast_tx_shortpre++; 3439 } else { 3440 shortPreamble = AH_FALSE; 3441 } 3442 3443 an = ATH_NODE(ni); 3444 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3445 ismrr = 0; /* default no multi-rate retry*/ 3446 /* 3447 * Calculate Atheros packet type from IEEE80211 packet header, 3448 * setup for rate calculations, and select h/w transmit queue. 3449 */ 3450 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3451 case IEEE80211_FC0_TYPE_MGT: 3452 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3453 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3454 atype = HAL_PKT_TYPE_BEACON; 3455 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3456 atype = HAL_PKT_TYPE_PROBE_RESP; 3457 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3458 atype = HAL_PKT_TYPE_ATIM; 3459 else 3460 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3461 rix = sc->sc_minrateix; 3462 txrate = rt->info[rix].rateCode; 3463 if (shortPreamble) 3464 txrate |= rt->info[rix].shortPreamble; 3465 try0 = ATH_TXMGTTRY; 3466 /* NB: force all management frames to highest queue */ 3467 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3468 /* NB: force all management frames to highest queue */ 3469 pri = WME_AC_VO; 3470 } else 3471 pri = WME_AC_BE; 3472 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3473 break; 3474 case IEEE80211_FC0_TYPE_CTL: 3475 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3476 rix = sc->sc_minrateix; 3477 txrate = rt->info[rix].rateCode; 3478 if (shortPreamble) 3479 txrate |= rt->info[rix].shortPreamble; 3480 try0 = ATH_TXMGTTRY; 3481 /* NB: force all ctl frames to highest queue */ 3482 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3483 /* NB: force all ctl frames to highest queue */ 3484 pri = WME_AC_VO; 3485 } else 3486 pri = WME_AC_BE; 3487 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3488 break; 3489 case IEEE80211_FC0_TYPE_DATA: 3490 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3491 /* 3492 * Data frames: multicast frames go out at a fixed rate, 3493 * otherwise consult the rate control module for the 3494 * rate to use. 3495 */ 3496 if (ismcast) { 3497 /* 3498 * Check mcast rate setting in case it's changed. 3499 * XXX move out of fastpath 3500 */ 3501 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3502 sc->sc_mcastrix = 3503 ath_tx_findrix(rt, ic->ic_mcast_rate); 3504 sc->sc_mcastrate = ic->ic_mcast_rate; 3505 } 3506 rix = sc->sc_mcastrix; 3507 txrate = rt->info[rix].rateCode; 3508 if (shortPreamble) 3509 txrate |= rt->info[rix].shortPreamble; 3510 try0 = 1; 3511 } else { 3512 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3513 &rix, &try0, &txrate); 3514 sc->sc_txrate = txrate; /* for LED blinking */ 3515 if (try0 != ATH_TXMAXTRY) 3516 ismrr = 1; 3517 } 3518 pri = M_WME_GETAC(m0); 3519 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3520 flags |= HAL_TXDESC_NOACK; 3521 break; 3522 default: 3523 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3524 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3525 /* XXX statistic */ 3526 m_freem(m0); 3527 return EIO; 3528 } 3529 txq = sc->sc_ac2q[pri]; 3530 3531 /* 3532 * When servicing one or more stations in power-save mode 3533 * multicast frames must be buffered until after the beacon. 3534 * We use the CAB queue for that. 3535 */ 3536 if (ismcast && ic->ic_ps_sta) { 3537 txq = sc->sc_cabq; 3538 /* XXX? more bit in 802.11 frame header */ 3539 } 3540 3541 /* 3542 * Calculate miscellaneous flags. 3543 */ 3544 if (ismcast) { 3545 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3546 } else if (pktlen > ic->ic_rtsthreshold) { 3547 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3548 cix = rt->info[rix].controlRate; 3549 sc->sc_stats.ast_tx_rts++; 3550 } 3551 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3552 sc->sc_stats.ast_tx_noack++; 3553 3554 /* 3555 * If 802.11g protection is enabled, determine whether 3556 * to use RTS/CTS or just CTS. Note that this is only 3557 * done for OFDM unicast frames. 3558 */ 3559 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3560 rt->info[rix].phy == IEEE80211_T_OFDM && 3561 (flags & HAL_TXDESC_NOACK) == 0) { 3562 /* XXX fragments must use CCK rates w/ protection */ 3563 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3564 flags |= HAL_TXDESC_RTSENA; 3565 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3566 flags |= HAL_TXDESC_CTSENA; 3567 cix = rt->info[sc->sc_protrix].controlRate; 3568 sc->sc_stats.ast_tx_protect++; 3569 } 3570 3571 /* 3572 * Calculate duration. This logically belongs in the 802.11 3573 * layer but it lacks sufficient information to calculate it. 3574 */ 3575 if ((flags & HAL_TXDESC_NOACK) == 0 && 3576 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3577 u_int16_t dur; 3578 /* 3579 * XXX not right with fragmentation. 3580 */ 3581 if (shortPreamble) 3582 dur = rt->info[rix].spAckDuration; 3583 else 3584 dur = rt->info[rix].lpAckDuration; 3585 *(u_int16_t *)wh->i_dur = htole16(dur); 3586 } 3587 3588 /* 3589 * Calculate RTS/CTS rate and duration if needed. 3590 */ 3591 ctsduration = 0; 3592 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3593 /* 3594 * CTS transmit rate is derived from the transmit rate 3595 * by looking in the h/w rate table. We must also factor 3596 * in whether or not a short preamble is to be used. 3597 */ 3598 /* NB: cix is set above where RTS/CTS is enabled */ 3599 KASSERT(cix != 0xff, ("cix not setup")); 3600 ctsrate = rt->info[cix].rateCode; 3601 /* 3602 * Compute the transmit duration based on the frame 3603 * size and the size of an ACK frame. We call into the 3604 * HAL to do the computation since it depends on the 3605 * characteristics of the actual PHY being used. 3606 * 3607 * NB: CTS is assumed the same size as an ACK so we can 3608 * use the precalculated ACK durations. 3609 */ 3610 if (shortPreamble) { 3611 ctsrate |= rt->info[cix].shortPreamble; 3612 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3613 ctsduration += rt->info[cix].spAckDuration; 3614 ctsduration += ath_hal_computetxtime(ah, 3615 rt, pktlen, rix, AH_TRUE); 3616 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3617 ctsduration += rt->info[rix].spAckDuration; 3618 } else { 3619 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3620 ctsduration += rt->info[cix].lpAckDuration; 3621 ctsduration += ath_hal_computetxtime(ah, 3622 rt, pktlen, rix, AH_FALSE); 3623 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3624 ctsduration += rt->info[rix].lpAckDuration; 3625 } 3626 /* 3627 * Must disable multi-rate retry when using RTS/CTS. 3628 */ 3629 ismrr = 0; 3630 try0 = ATH_TXMGTTRY; /* XXX */ 3631 } else 3632 ctsrate = 0; 3633 3634 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3635 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3636 sc->sc_hwmap[txrate].ieeerate, -1); 3637 3638 if (bpf_peers_present(ic->ic_rawbpf)) 3639 bpf_mtap(ic->ic_rawbpf, m0); 3640 if (bpf_peers_present(sc->sc_drvbpf)) { 3641 u_int64_t tsf = ath_hal_gettsf64(ah); 3642 3643 sc->sc_tx_th.wt_tsf = htole64(tsf); 3644 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3645 if (iswep) 3646 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3647 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3648 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3649 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3650 3651 bpf_mtap2(sc->sc_drvbpf, 3652 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3653 } 3654 3655 /* 3656 * Determine if a tx interrupt should be generated for 3657 * this descriptor. We take a tx interrupt to reap 3658 * descriptors when the h/w hits an EOL condition or 3659 * when the descriptor is specifically marked to generate 3660 * an interrupt. We periodically mark descriptors in this 3661 * way to insure timely replenishing of the supply needed 3662 * for sending frames. Defering interrupts reduces system 3663 * load and potentially allows more concurrent work to be 3664 * done but if done to aggressively can cause senders to 3665 * backup. 3666 * 3667 * NB: use >= to deal with sc_txintrperiod changing 3668 * dynamically through sysctl. 3669 */ 3670 if (flags & HAL_TXDESC_INTREQ) { 3671 txq->axq_intrcnt = 0; 3672 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3673 flags |= HAL_TXDESC_INTREQ; 3674 txq->axq_intrcnt = 0; 3675 } 3676 3677 /* 3678 * Formulate first tx descriptor with tx controls. 3679 */ 3680 /* XXX check return value? */ 3681 ath_hal_setuptxdesc(ah, ds 3682 , pktlen /* packet length */ 3683 , hdrlen /* header length */ 3684 , atype /* Atheros packet type */ 3685 , ni->ni_txpower /* txpower */ 3686 , txrate, try0 /* series 0 rate/tries */ 3687 , keyix /* key cache index */ 3688 , sc->sc_txantenna /* antenna mode */ 3689 , flags /* flags */ 3690 , ctsrate /* rts/cts rate */ 3691 , ctsduration /* rts/cts duration */ 3692 ); 3693 bf->bf_flags = flags; 3694 /* 3695 * Setup the multi-rate retry state only when we're 3696 * going to use it. This assumes ath_hal_setuptxdesc 3697 * initializes the descriptors (so we don't have to) 3698 * when the hardware supports multi-rate retry and 3699 * we don't use it. 3700 */ 3701 if (ismrr) 3702 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3703 3704 /* 3705 * Fillin the remainder of the descriptor info. 3706 */ 3707 ds0 = ds; 3708 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3709 ds->ds_data = bf->bf_segs[i].ds_addr; 3710 if (i == bf->bf_nseg - 1) 3711 ds->ds_link = 0; 3712 else 3713 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3714 ath_hal_filltxdesc(ah, ds 3715 , bf->bf_segs[i].ds_len /* segment length */ 3716 , i == 0 /* first segment */ 3717 , i == bf->bf_nseg - 1 /* last segment */ 3718 , ds0 /* first descriptor */ 3719 ); 3720 DPRINTF(sc, ATH_DEBUG_XMIT, 3721 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3722 __func__, i, ds->ds_link, ds->ds_data, 3723 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3724 } 3725 /* 3726 * Insert the frame on the outbound list and 3727 * pass it on to the hardware. 3728 */ 3729 ATH_TXQ_LOCK(txq); 3730 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3731 if (txq->axq_link == NULL) { 3732 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3733 DPRINTF(sc, ATH_DEBUG_XMIT, 3734 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3735 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3736 txq->axq_depth); 3737 } else { 3738 *txq->axq_link = bf->bf_daddr; 3739 DPRINTF(sc, ATH_DEBUG_XMIT, 3740 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3741 txq->axq_qnum, txq->axq_link, 3742 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3743 } 3744 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3745 /* 3746 * The CAB queue is started from the SWBA handler since 3747 * frames only go out on DTIM and to avoid possible races. 3748 */ 3749 if (txq != sc->sc_cabq) 3750 ath_hal_txstart(ah, txq->axq_qnum); 3751 ATH_TXQ_UNLOCK(txq); 3752 3753 return 0; 3754} 3755 3756/* 3757 * Process completed xmit descriptors from the specified queue. 3758 */ 3759static int 3760ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3761{ 3762 struct ath_hal *ah = sc->sc_ah; 3763 struct ieee80211com *ic = &sc->sc_ic; 3764 struct ath_buf *bf; 3765 struct ath_desc *ds, *ds0; 3766 struct ieee80211_node *ni; 3767 struct ath_node *an; 3768 int sr, lr, pri, nacked; 3769 HAL_STATUS status; 3770 3771 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3772 __func__, txq->axq_qnum, 3773 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3774 txq->axq_link); 3775 nacked = 0; 3776 for (;;) { 3777 ATH_TXQ_LOCK(txq); 3778 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3779 bf = STAILQ_FIRST(&txq->axq_q); 3780 if (bf == NULL) { 3781 ATH_TXQ_UNLOCK(txq); 3782 break; 3783 } 3784 ds0 = &bf->bf_desc[0]; 3785 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3786 status = ath_hal_txprocdesc(ah, ds); 3787#ifdef ATH_DEBUG 3788 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3789 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK); 3790#endif 3791 if (status == HAL_EINPROGRESS) { 3792 ATH_TXQ_UNLOCK(txq); 3793 break; 3794 } 3795 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3796 if (txq->axq_depth == 0) 3797 txq->axq_link = NULL; 3798 ATH_TXQ_UNLOCK(txq); 3799 3800 ni = bf->bf_node; 3801 if (ni != NULL) { 3802 an = ATH_NODE(ni); 3803 if (ds->ds_txstat.ts_status == 0) { 3804 u_int8_t txant = ds->ds_txstat.ts_antenna; 3805 sc->sc_stats.ast_ant_tx[txant]++; 3806 sc->sc_ant_tx[txant]++; 3807 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3808 sc->sc_stats.ast_tx_altrate++; 3809 sc->sc_stats.ast_tx_rssi = 3810 ds->ds_txstat.ts_rssi; 3811 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3812 ds->ds_txstat.ts_rssi); 3813 pri = M_WME_GETAC(bf->bf_m); 3814 if (pri >= WME_AC_VO) 3815 ic->ic_wme.wme_hipri_traffic++; 3816 ni->ni_inact = ni->ni_inact_reload; 3817 } else { 3818 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3819 sc->sc_stats.ast_tx_xretries++; 3820 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3821 sc->sc_stats.ast_tx_fifoerr++; 3822 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3823 sc->sc_stats.ast_tx_filtered++; 3824 } 3825 sr = ds->ds_txstat.ts_shortretry; 3826 lr = ds->ds_txstat.ts_longretry; 3827 sc->sc_stats.ast_tx_shortretry += sr; 3828 sc->sc_stats.ast_tx_longretry += lr; 3829 /* 3830 * Hand the descriptor to the rate control algorithm. 3831 */ 3832 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3833 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 3834 /* 3835 * If frame was ack'd update the last rx time 3836 * used to workaround phantom bmiss interrupts. 3837 */ 3838 if (ds->ds_txstat.ts_status == 0) 3839 nacked++; 3840 ath_rate_tx_complete(sc, an, ds, ds0); 3841 } 3842 /* 3843 * Reclaim reference to node. 3844 * 3845 * NB: the node may be reclaimed here if, for example 3846 * this is a DEAUTH message that was sent and the 3847 * node was timed out due to inactivity. 3848 */ 3849 ieee80211_free_node(ni); 3850 } 3851 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3852 BUS_DMASYNC_POSTWRITE); 3853 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3854 m_freem(bf->bf_m); 3855 bf->bf_m = NULL; 3856 bf->bf_node = NULL; 3857 3858 ATH_TXBUF_LOCK(sc); 3859 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3860 ATH_TXBUF_UNLOCK(sc); 3861 } 3862 return nacked; 3863} 3864 3865static __inline int 3866txqactive(struct ath_hal *ah, int qnum) 3867{ 3868 u_int32_t txqs = 1<<qnum; 3869 ath_hal_gettxintrtxqs(ah, &txqs); 3870 return (txqs & (1<<qnum)); 3871} 3872 3873/* 3874 * Deferred processing of transmit interrupt; special-cased 3875 * for a single hardware transmit queue (e.g. 5210 and 5211). 3876 */ 3877static void 3878ath_tx_proc_q0(void *arg, int npending) 3879{ 3880 struct ath_softc *sc = arg; 3881 struct ifnet *ifp = sc->sc_ifp; 3882 3883 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 3884 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3885 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 3886 ath_tx_processq(sc, sc->sc_cabq); 3887 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3888 sc->sc_tx_timer = 0; 3889 3890 if (sc->sc_softled) 3891 ath_led_event(sc, ATH_LED_TX); 3892 3893 ath_start(ifp); 3894} 3895 3896/* 3897 * Deferred processing of transmit interrupt; special-cased 3898 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3899 */ 3900static void 3901ath_tx_proc_q0123(void *arg, int npending) 3902{ 3903 struct ath_softc *sc = arg; 3904 struct ifnet *ifp = sc->sc_ifp; 3905 int nacked; 3906 3907 /* 3908 * Process each active queue. 3909 */ 3910 nacked = 0; 3911 if (txqactive(sc->sc_ah, 0)) 3912 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 3913 if (txqactive(sc->sc_ah, 1)) 3914 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 3915 if (txqactive(sc->sc_ah, 2)) 3916 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 3917 if (txqactive(sc->sc_ah, 3)) 3918 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 3919 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 3920 ath_tx_processq(sc, sc->sc_cabq); 3921 if (nacked) 3922 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3923 3924 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3925 sc->sc_tx_timer = 0; 3926 3927 if (sc->sc_softled) 3928 ath_led_event(sc, ATH_LED_TX); 3929 3930 ath_start(ifp); 3931} 3932 3933/* 3934 * Deferred processing of transmit interrupt. 3935 */ 3936static void 3937ath_tx_proc(void *arg, int npending) 3938{ 3939 struct ath_softc *sc = arg; 3940 struct ifnet *ifp = sc->sc_ifp; 3941 int i, nacked; 3942 3943 /* 3944 * Process each active queue. 3945 */ 3946 nacked = 0; 3947 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3948 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 3949 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 3950 if (nacked) 3951 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3952 3953 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3954 sc->sc_tx_timer = 0; 3955 3956 if (sc->sc_softled) 3957 ath_led_event(sc, ATH_LED_TX); 3958 3959 ath_start(ifp); 3960} 3961 3962static void 3963ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3964{ 3965#ifdef ATH_DEBUG 3966 struct ath_hal *ah = sc->sc_ah; 3967#endif 3968 struct ieee80211_node *ni; 3969 struct ath_buf *bf; 3970 u_int ix; 3971 3972 /* 3973 * NB: this assumes output has been stopped and 3974 * we do not need to block ath_tx_tasklet 3975 */ 3976 for (ix = 0;; ix++) { 3977 ATH_TXQ_LOCK(txq); 3978 bf = STAILQ_FIRST(&txq->axq_q); 3979 if (bf == NULL) { 3980 txq->axq_link = NULL; 3981 ATH_TXQ_UNLOCK(txq); 3982 break; 3983 } 3984 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3985 ATH_TXQ_UNLOCK(txq); 3986#ifdef ATH_DEBUG 3987 if (sc->sc_debug & ATH_DEBUG_RESET) { 3988 ath_printtxbuf(bf, txq->axq_qnum, ix, 3989 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3990 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t), 3991 bf->bf_m->m_len, 0, -1); 3992 } 3993#endif /* ATH_DEBUG */ 3994 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3995 m_freem(bf->bf_m); 3996 bf->bf_m = NULL; 3997 ni = bf->bf_node; 3998 bf->bf_node = NULL; 3999 if (ni != NULL) { 4000 /* 4001 * Reclaim node reference. 4002 */ 4003 ieee80211_free_node(ni); 4004 } 4005 ATH_TXBUF_LOCK(sc); 4006 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4007 ATH_TXBUF_UNLOCK(sc); 4008 } 4009} 4010 4011static void 4012ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4013{ 4014 struct ath_hal *ah = sc->sc_ah; 4015 4016 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4017 __func__, txq->axq_qnum, 4018 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4019 txq->axq_link); 4020 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4021} 4022 4023/* 4024 * Drain the transmit queues and reclaim resources. 4025 */ 4026static void 4027ath_draintxq(struct ath_softc *sc) 4028{ 4029 struct ath_hal *ah = sc->sc_ah; 4030 struct ifnet *ifp = sc->sc_ifp; 4031 int i; 4032 4033 /* XXX return value */ 4034 if (!sc->sc_invalid) { 4035 /* don't touch the hardware if marked invalid */ 4036 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4037 __func__, sc->sc_bhalq, 4038 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4039 NULL); 4040 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4041 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4042 if (ATH_TXQ_SETUP(sc, i)) 4043 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4044 } 4045 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4046 if (ATH_TXQ_SETUP(sc, i)) 4047 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4048#ifdef ATH_DEBUG 4049 if (sc->sc_debug & ATH_DEBUG_RESET) { 4050 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 4051 if (bf != NULL && bf->bf_m != NULL) { 4052 ath_printtxbuf(bf, sc->sc_bhalq, 0, 4053 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4054 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t), 4055 bf->bf_m->m_len, 0, -1); 4056 } 4057 } 4058#endif /* ATH_DEBUG */ 4059 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4060 sc->sc_tx_timer = 0; 4061} 4062 4063/* 4064 * Disable the receive h/w in preparation for a reset. 4065 */ 4066static void 4067ath_stoprecv(struct ath_softc *sc) 4068{ 4069#define PA2DESC(_sc, _pa) \ 4070 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4071 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4072 struct ath_hal *ah = sc->sc_ah; 4073 4074 ath_hal_stoppcurecv(ah); /* disable PCU */ 4075 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4076 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4077 DELAY(3000); /* 3ms is long enough for 1 frame */ 4078#ifdef ATH_DEBUG 4079 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4080 struct ath_buf *bf; 4081 u_int ix; 4082 4083 printf("%s: rx queue %p, link %p\n", __func__, 4084 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4085 ix = 0; 4086 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4087 struct ath_desc *ds = bf->bf_desc; 4088 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4089 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4090 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4091 ath_printrxbuf(bf, ix, status == HAL_OK); 4092 ix++; 4093 } 4094 } 4095#endif 4096 sc->sc_rxlink = NULL; /* just in case */ 4097#undef PA2DESC 4098} 4099 4100/* 4101 * Enable the receive h/w following a reset. 4102 */ 4103static int 4104ath_startrecv(struct ath_softc *sc) 4105{ 4106 struct ath_hal *ah = sc->sc_ah; 4107 struct ath_buf *bf; 4108 4109 sc->sc_rxlink = NULL; 4110 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4111 int error = ath_rxbuf_init(sc, bf); 4112 if (error != 0) { 4113 DPRINTF(sc, ATH_DEBUG_RECV, 4114 "%s: ath_rxbuf_init failed %d\n", 4115 __func__, error); 4116 return error; 4117 } 4118 } 4119 4120 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4121 ath_hal_putrxbuf(ah, bf->bf_daddr); 4122 ath_hal_rxena(ah); /* enable recv descriptors */ 4123 ath_mode_init(sc); /* set filters, etc. */ 4124 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4125 return 0; 4126} 4127 4128/* 4129 * Update internal state after a channel change. 4130 */ 4131static void 4132ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4133{ 4134 struct ieee80211com *ic = &sc->sc_ic; 4135 enum ieee80211_phymode mode; 4136 u_int16_t flags; 4137 4138 /* 4139 * Change channels and update the h/w rate map 4140 * if we're switching; e.g. 11a to 11b/g. 4141 */ 4142 mode = ieee80211_chan2mode(ic, chan); 4143 if (mode != sc->sc_curmode) 4144 ath_setcurmode(sc, mode); 4145 /* 4146 * Update BPF state. NB: ethereal et. al. don't handle 4147 * merged flags well so pick a unique mode for their use. 4148 */ 4149 if (IEEE80211_IS_CHAN_A(chan)) 4150 flags = IEEE80211_CHAN_A; 4151 /* XXX 11g schizophrenia */ 4152 else if (IEEE80211_IS_CHAN_G(chan) || 4153 IEEE80211_IS_CHAN_PUREG(chan)) 4154 flags = IEEE80211_CHAN_G; 4155 else 4156 flags = IEEE80211_CHAN_B; 4157 if (IEEE80211_IS_CHAN_T(chan)) 4158 flags |= IEEE80211_CHAN_TURBO; 4159 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4160 htole16(chan->ic_freq); 4161 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4162 htole16(flags); 4163} 4164 4165/* 4166 * Poll for a channel clear indication; this is required 4167 * for channels requiring DFS and not previously visited 4168 * and/or with a recent radar detection. 4169 */ 4170static void 4171ath_dfswait(void *arg) 4172{ 4173 struct ath_softc *sc = arg; 4174 struct ath_hal *ah = sc->sc_ah; 4175 HAL_CHANNEL hchan; 4176 4177 ath_hal_radar_wait(ah, &hchan); 4178 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n", 4179 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags); 4180 4181 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4182 if_printf(sc->sc_ifp, 4183 "channel %u/0x%x/0x%x has interference\n", 4184 hchan.channel, hchan.channelFlags, hchan.privFlags); 4185 return; 4186 } 4187 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4188 /* XXX should not happen */ 4189 return; 4190 } 4191 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4192 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4193 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4194 if_printf(sc->sc_ifp, 4195 "channel %u/0x%x/0x%x marked clear\n", 4196 hchan.channel, hchan.channelFlags, hchan.privFlags); 4197 } else 4198 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4199} 4200 4201/* 4202 * Set/change channels. If the channel is really being changed, 4203 * it's done by reseting the chip. To accomplish this we must 4204 * first cleanup any pending DMA, then restart stuff after a la 4205 * ath_init. 4206 */ 4207static int 4208ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4209{ 4210 struct ath_hal *ah = sc->sc_ah; 4211 struct ieee80211com *ic = &sc->sc_ic; 4212 HAL_CHANNEL hchan; 4213 4214 /* 4215 * Convert to a HAL channel description with 4216 * the flags constrained to reflect the current 4217 * operating mode. 4218 */ 4219 hchan.channel = chan->ic_freq; 4220 hchan.channelFlags = ath_chan2flags(ic, chan); 4221 4222 DPRINTF(sc, ATH_DEBUG_RESET, 4223 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4224 __func__, 4225 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4226 sc->sc_curchan.channelFlags), 4227 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4228 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4229 hchan.channel, hchan.channelFlags); 4230 if (hchan.channel != sc->sc_curchan.channel || 4231 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4232 HAL_STATUS status; 4233 4234 /* 4235 * To switch channels clear any pending DMA operations; 4236 * wait long enough for the RX fifo to drain, reset the 4237 * hardware at the new frequency, and then re-enable 4238 * the relevant bits of the h/w. 4239 */ 4240 ath_hal_intrset(ah, 0); /* disable interrupts */ 4241 ath_draintxq(sc); /* clear pending tx frames */ 4242 ath_stoprecv(sc); /* turn off frame recv */ 4243 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) { 4244 if_printf(ic->ic_ifp, "%s: unable to reset " 4245 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n", 4246 __func__, ieee80211_chan2ieee(ic, chan), 4247 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4248 return EIO; 4249 } 4250 sc->sc_curchan = hchan; 4251 ath_update_txpow(sc); /* update tx power state */ 4252 sc->sc_diversity = ath_hal_getdiversity(ah); 4253 sc->sc_calinterval = 1; 4254 sc->sc_caltries = 0; 4255 4256 /* 4257 * Re-enable rx framework. 4258 */ 4259 if (ath_startrecv(sc) != 0) { 4260 if_printf(ic->ic_ifp, 4261 "%s: unable to restart recv logic\n", __func__); 4262 return EIO; 4263 } 4264 4265 /* 4266 * Change channels and update the h/w rate map 4267 * if we're switching; e.g. 11a to 11b/g. 4268 */ 4269 ic->ic_ibss_chan = chan; 4270 ath_chan_change(sc, chan); 4271 4272 /* 4273 * Handle DFS required waiting period to determine 4274 * if channel is clear of radar traffic. 4275 */ 4276 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4277#define DFS_AND_NOT_CLEAR(_c) \ 4278 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4279 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4280 if_printf(sc->sc_ifp, 4281 "wait for DFS clear channel signal\n"); 4282 /* XXX stop sndq */ 4283 sc->sc_ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4284 callout_reset(&sc->sc_dfs_ch, 4285 2 * hz, ath_dfswait, sc); 4286 } else 4287 callout_stop(&sc->sc_dfs_ch); 4288#undef DFS_NOT_CLEAR 4289 } 4290 4291 /* 4292 * Re-enable interrupts. 4293 */ 4294 ath_hal_intrset(ah, sc->sc_imask); 4295 } 4296 return 0; 4297} 4298 4299static void 4300ath_next_scan(void *arg) 4301{ 4302 struct ath_softc *sc = arg; 4303 struct ieee80211com *ic = &sc->sc_ic; 4304 4305 if (ic->ic_state == IEEE80211_S_SCAN) 4306 ieee80211_next_scan(ic); 4307} 4308 4309/* 4310 * Periodically recalibrate the PHY to account 4311 * for temperature/environment changes. 4312 */ 4313static void 4314ath_calibrate(void *arg) 4315{ 4316 struct ath_softc *sc = arg; 4317 struct ath_hal *ah = sc->sc_ah; 4318 HAL_BOOL iqCalDone; 4319 4320 sc->sc_stats.ast_per_cal++; 4321 4322 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4323 /* 4324 * Rfgain is out of bounds, reset the chip 4325 * to load new gain values. 4326 */ 4327 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4328 "%s: rfgain change\n", __func__); 4329 sc->sc_stats.ast_per_rfgain++; 4330 ath_reset(sc->sc_ifp); 4331 } 4332 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4333 DPRINTF(sc, ATH_DEBUG_ANY, 4334 "%s: calibration of channel %u failed\n", 4335 __func__, sc->sc_curchan.channel); 4336 sc->sc_stats.ast_per_calfail++; 4337 } 4338 /* 4339 * Calibrate noise floor data again in case of change. 4340 */ 4341 ath_hal_process_noisefloor(ah); 4342 /* 4343 * Poll more frequently when the IQ calibration is in 4344 * progress to speedup loading the final settings. 4345 * We temper this aggressive polling with an exponential 4346 * back off after 4 tries up to ath_calinterval. 4347 */ 4348 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4349 sc->sc_caltries = 0; 4350 sc->sc_calinterval = ath_calinterval; 4351 } else if (sc->sc_caltries > 4) { 4352 sc->sc_caltries = 0; 4353 sc->sc_calinterval <<= 1; 4354 if (sc->sc_calinterval > ath_calinterval) 4355 sc->sc_calinterval = ath_calinterval; 4356 } 4357 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4358 ("bad calibration interval %u", sc->sc_calinterval)); 4359 4360 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4361 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4362 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4363 sc->sc_caltries++; 4364 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4365 ath_calibrate, sc); 4366} 4367 4368static int 4369ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4370{ 4371 struct ifnet *ifp = ic->ic_ifp; 4372 struct ath_softc *sc = ifp->if_softc; 4373 struct ath_hal *ah = sc->sc_ah; 4374 struct ieee80211_node *ni; 4375 int i, error; 4376 const u_int8_t *bssid; 4377 u_int32_t rfilt; 4378 static const HAL_LED_STATE leds[] = { 4379 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4380 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4381 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4382 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4383 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4384 }; 4385 4386 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4387 ieee80211_state_name[ic->ic_state], 4388 ieee80211_state_name[nstate]); 4389 4390 callout_stop(&sc->sc_scan_ch); 4391 callout_stop(&sc->sc_cal_ch); 4392 callout_stop(&sc->sc_dfs_ch); 4393 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4394 4395 if (nstate == IEEE80211_S_INIT) { 4396 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4397 /* 4398 * NB: disable interrupts so we don't rx frames. 4399 */ 4400 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4401 /* 4402 * Notify the rate control algorithm. 4403 */ 4404 ath_rate_newstate(sc, nstate); 4405 goto done; 4406 } 4407 ni = ic->ic_bss; 4408 error = ath_chan_set(sc, ic->ic_curchan); 4409 if (error != 0) 4410 goto bad; 4411 rfilt = ath_calcrxfilter(sc, nstate); 4412 if (nstate == IEEE80211_S_SCAN) 4413 bssid = ifp->if_broadcastaddr; 4414 else 4415 bssid = ni->ni_bssid; 4416 ath_hal_setrxfilter(ah, rfilt); 4417 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4418 __func__, rfilt, ether_sprintf(bssid)); 4419 4420 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4421 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4422 else 4423 ath_hal_setassocid(ah, bssid, 0); 4424 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4425 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4426 if (ath_hal_keyisvalid(ah, i)) 4427 ath_hal_keysetmac(ah, i, bssid); 4428 } 4429 4430 /* 4431 * Notify the rate control algorithm so rates 4432 * are setup should ath_beacon_alloc be called. 4433 */ 4434 ath_rate_newstate(sc, nstate); 4435 4436 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4437 /* nothing to do */; 4438 } else if (nstate == IEEE80211_S_RUN) { 4439 DPRINTF(sc, ATH_DEBUG_STATE, 4440 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4441 "capinfo=0x%04x chan=%d\n" 4442 , __func__ 4443 , ic->ic_flags 4444 , ni->ni_intval 4445 , ether_sprintf(ni->ni_bssid) 4446 , ni->ni_capinfo 4447 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4448 4449 switch (ic->ic_opmode) { 4450 case IEEE80211_M_HOSTAP: 4451 case IEEE80211_M_IBSS: 4452 /* 4453 * Allocate and setup the beacon frame. 4454 * 4455 * Stop any previous beacon DMA. This may be 4456 * necessary, for example, when an ibss merge 4457 * causes reconfiguration; there will be a state 4458 * transition from RUN->RUN that means we may 4459 * be called with beacon transmission active. 4460 */ 4461 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4462 ath_beacon_free(sc); 4463 error = ath_beacon_alloc(sc, ni); 4464 if (error != 0) 4465 goto bad; 4466 /* 4467 * If joining an adhoc network defer beacon timer 4468 * configuration to the next beacon frame so we 4469 * have a current TSF to use. Otherwise we're 4470 * starting an ibss/bss so there's no need to delay. 4471 */ 4472 if (ic->ic_opmode == IEEE80211_M_IBSS && 4473 ic->ic_bss->ni_tstamp.tsf != 0) 4474 sc->sc_syncbeacon = 1; 4475 else 4476 ath_beacon_config(sc); 4477 break; 4478 case IEEE80211_M_STA: 4479 /* 4480 * Allocate a key cache slot to the station. 4481 */ 4482 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4483 sc->sc_hasclrkey && 4484 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4485 ath_setup_stationkey(ni); 4486 /* 4487 * Defer beacon timer configuration to the next 4488 * beacon frame so we have a current TSF to use 4489 * (any TSF collected when scanning is likely old). 4490 */ 4491 sc->sc_syncbeacon = 1; 4492 break; 4493 default: 4494 break; 4495 } 4496 4497 /* 4498 * Let the hal process statistics collected during a 4499 * scan so it can provide calibrated noise floor data. 4500 */ 4501 ath_hal_process_noisefloor(ah); 4502 /* 4503 * Reset rssi stats; maybe not the best place... 4504 */ 4505 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4506 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4507 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4508 } else { 4509 ath_hal_intrset(ah, 4510 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4511 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4512 } 4513done: 4514 /* 4515 * Invoke the parent method to complete the work. 4516 */ 4517 error = sc->sc_newstate(ic, nstate, arg); 4518 /* 4519 * Finally, start any timers. 4520 */ 4521 if (nstate == IEEE80211_S_RUN) { 4522 /* start periodic recalibration timer */ 4523 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4524 ath_calibrate, sc); 4525 } else if (nstate == IEEE80211_S_SCAN) { 4526 /* start ap/neighbor scan timer */ 4527 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4528 ath_next_scan, sc); 4529 } 4530bad: 4531 return error; 4532} 4533 4534/* 4535 * Allocate a key cache slot to the station so we can 4536 * setup a mapping from key index to node. The key cache 4537 * slot is needed for managing antenna state and for 4538 * compression when stations do not use crypto. We do 4539 * it uniliaterally here; if crypto is employed this slot 4540 * will be reassigned. 4541 */ 4542static void 4543ath_setup_stationkey(struct ieee80211_node *ni) 4544{ 4545 struct ieee80211com *ic = ni->ni_ic; 4546 struct ath_softc *sc = ic->ic_ifp->if_softc; 4547 ieee80211_keyix keyix, rxkeyix; 4548 4549 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4550 /* 4551 * Key cache is full; we'll fall back to doing 4552 * the more expensive lookup in software. Note 4553 * this also means no h/w compression. 4554 */ 4555 /* XXX msg+statistic */ 4556 } else { 4557 /* XXX locking? */ 4558 ni->ni_ucastkey.wk_keyix = keyix; 4559 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4560 /* NB: this will create a pass-thru key entry */ 4561 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4562 } 4563} 4564 4565/* 4566 * Setup driver-specific state for a newly associated node. 4567 * Note that we're called also on a re-associate, the isnew 4568 * param tells us if this is the first time or not. 4569 */ 4570static void 4571ath_newassoc(struct ieee80211_node *ni, int isnew) 4572{ 4573 struct ieee80211com *ic = ni->ni_ic; 4574 struct ath_softc *sc = ic->ic_ifp->if_softc; 4575 4576 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4577 if (isnew && 4578 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4579 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4580 ("new assoc with a unicast key already setup (keyix %u)", 4581 ni->ni_ucastkey.wk_keyix)); 4582 ath_setup_stationkey(ni); 4583 } 4584} 4585 4586static int 4587ath_getchannels(struct ath_softc *sc, u_int cc, 4588 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4589{ 4590#define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4591#define IS_CHAN_PUBLIC_SAFETY(_c) \ 4592 (((_c)->channelFlags & CHANNEL_5GHZ) && \ 4593 ((_c)->channel > 4940 && (_c)->channel < 4990)) 4594 struct ieee80211com *ic = &sc->sc_ic; 4595 struct ifnet *ifp = sc->sc_ifp; 4596 struct ath_hal *ah = sc->sc_ah; 4597 HAL_CHANNEL *chans; 4598 int i, ix, nchan; 4599 4600 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4601 M_TEMP, M_NOWAIT); 4602 if (chans == NULL) { 4603 if_printf(ifp, "unable to allocate channel table\n"); 4604 return ENOMEM; 4605 } 4606 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4607 NULL, 0, NULL, 4608 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4609 u_int32_t rd; 4610 4611 ath_hal_getregdomain(ah, &rd); 4612 if_printf(ifp, "unable to collect channel list from hal; " 4613 "regdomain likely %u country code %u\n", rd, cc); 4614 free(chans, M_TEMP); 4615 return EINVAL; 4616 } 4617 4618 /* 4619 * Convert HAL channels to ieee80211 ones and insert 4620 * them in the table according to their channel number. 4621 */ 4622 for (i = 0; i < nchan; i++) { 4623 HAL_CHANNEL *c = &chans[i]; 4624 u_int16_t flags; 4625 4626 /* 4627 * XXX we're not ready to handle the ieee number mapping 4628 * for public safety channels as they overlap with any 4629 * 2GHz channels; for now use the non-public safety 4630 * numbering which is non-overlapping. 4631 */ 4632 if (IS_CHAN_PUBLIC_SAFETY(c)) 4633 ix = (c->channel - 4000) / 5; 4634 else 4635 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4636 if (ix > IEEE80211_CHAN_MAX) { 4637 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4638 ix, c->channel, c->channelFlags); 4639 continue; 4640 } 4641 if (ix < 0) { 4642 /* XXX can't handle stuff <2400 right now */ 4643 if (bootverbose) 4644 if_printf(ifp, "hal channel %d (%u/%x) " 4645 "cannot be handled; ignored\n", 4646 ix, c->channel, c->channelFlags); 4647 continue; 4648 } 4649 /* 4650 * Calculate net80211 flags; most are compatible 4651 * but some need massaging. Note the static turbo 4652 * conversion can be removed once net80211 is updated 4653 * to understand static vs. dynamic turbo. 4654 */ 4655 flags = c->channelFlags & COMPAT; 4656 if (c->channelFlags & CHANNEL_STURBO) 4657 flags |= IEEE80211_CHAN_TURBO; 4658 if (ic->ic_channels[ix].ic_freq == 0) { 4659 ic->ic_channels[ix].ic_freq = c->channel; 4660 ic->ic_channels[ix].ic_flags = flags; 4661 } else { 4662 /* channels overlap; e.g. 11g and 11b */ 4663 ic->ic_channels[ix].ic_flags |= flags; 4664 } 4665 } 4666 free(chans, M_TEMP); 4667 return 0; 4668#undef IS_CHAN_PUBLIC_SAFETY 4669#undef COMPAT 4670} 4671 4672static void 4673ath_led_done(void *arg) 4674{ 4675 struct ath_softc *sc = arg; 4676 4677 sc->sc_blinking = 0; 4678} 4679 4680/* 4681 * Turn the LED off: flip the pin and then set a timer so no 4682 * update will happen for the specified duration. 4683 */ 4684static void 4685ath_led_off(void *arg) 4686{ 4687 struct ath_softc *sc = arg; 4688 4689 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4690 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4691} 4692 4693/* 4694 * Blink the LED according to the specified on/off times. 4695 */ 4696static void 4697ath_led_blink(struct ath_softc *sc, int on, int off) 4698{ 4699 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4700 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4701 sc->sc_blinking = 1; 4702 sc->sc_ledoff = off; 4703 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4704} 4705 4706static void 4707ath_led_event(struct ath_softc *sc, int event) 4708{ 4709 4710 sc->sc_ledevent = ticks; /* time of last event */ 4711 if (sc->sc_blinking) /* don't interrupt active blink */ 4712 return; 4713 switch (event) { 4714 case ATH_LED_POLL: 4715 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4716 sc->sc_hwmap[0].ledoff); 4717 break; 4718 case ATH_LED_TX: 4719 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4720 sc->sc_hwmap[sc->sc_txrate].ledoff); 4721 break; 4722 case ATH_LED_RX: 4723 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4724 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4725 break; 4726 } 4727} 4728 4729static void 4730ath_update_txpow(struct ath_softc *sc) 4731{ 4732 struct ieee80211com *ic = &sc->sc_ic; 4733 struct ath_hal *ah = sc->sc_ah; 4734 u_int32_t txpow; 4735 4736 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4737 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4738 /* read back in case value is clamped */ 4739 ath_hal_gettxpowlimit(ah, &txpow); 4740 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4741 } 4742 /* 4743 * Fetch max tx power level for status requests. 4744 */ 4745 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4746 ic->ic_bss->ni_txpower = txpow; 4747} 4748 4749static void 4750rate_setup(struct ath_softc *sc, 4751 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4752{ 4753 int i, maxrates; 4754 4755 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4756 DPRINTF(sc, ATH_DEBUG_ANY, 4757 "%s: rate table too small (%u > %u)\n", 4758 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4759 maxrates = IEEE80211_RATE_MAXSIZE; 4760 } else 4761 maxrates = rt->rateCount; 4762 for (i = 0; i < maxrates; i++) 4763 rs->rs_rates[i] = rt->info[i].dot11Rate; 4764 rs->rs_nrates = maxrates; 4765} 4766 4767static int 4768ath_rate_setup(struct ath_softc *sc, u_int mode) 4769{ 4770 struct ath_hal *ah = sc->sc_ah; 4771 struct ieee80211com *ic = &sc->sc_ic; 4772 const HAL_RATE_TABLE *rt; 4773 4774 switch (mode) { 4775 case IEEE80211_MODE_11A: 4776 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4777 break; 4778 case IEEE80211_MODE_11B: 4779 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4780 break; 4781 case IEEE80211_MODE_11G: 4782 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4783 break; 4784 case IEEE80211_MODE_TURBO_A: 4785 /* XXX until static/dynamic turbo is fixed */ 4786 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4787 break; 4788 case IEEE80211_MODE_TURBO_G: 4789 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4790 break; 4791 default: 4792 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4793 __func__, mode); 4794 return 0; 4795 } 4796 sc->sc_rates[mode] = rt; 4797 if (rt != NULL) { 4798 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 4799 return 1; 4800 } else 4801 return 0; 4802} 4803 4804static void 4805ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4806{ 4807#define N(a) (sizeof(a)/sizeof(a[0])) 4808 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4809 static const struct { 4810 u_int rate; /* tx/rx 802.11 rate */ 4811 u_int16_t timeOn; /* LED on time (ms) */ 4812 u_int16_t timeOff; /* LED off time (ms) */ 4813 } blinkrates[] = { 4814 { 108, 40, 10 }, 4815 { 96, 44, 11 }, 4816 { 72, 50, 13 }, 4817 { 48, 57, 14 }, 4818 { 36, 67, 16 }, 4819 { 24, 80, 20 }, 4820 { 22, 100, 25 }, 4821 { 18, 133, 34 }, 4822 { 12, 160, 40 }, 4823 { 10, 200, 50 }, 4824 { 6, 240, 58 }, 4825 { 4, 267, 66 }, 4826 { 2, 400, 100 }, 4827 { 0, 500, 130 }, 4828 }; 4829 const HAL_RATE_TABLE *rt; 4830 int i, j; 4831 4832 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4833 rt = sc->sc_rates[mode]; 4834 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4835 for (i = 0; i < rt->rateCount; i++) 4836 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4837 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4838 for (i = 0; i < 32; i++) { 4839 u_int8_t ix = rt->rateCodeToIndex[i]; 4840 if (ix == 0xff) { 4841 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4842 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4843 continue; 4844 } 4845 sc->sc_hwmap[i].ieeerate = 4846 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4847 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4848 if (rt->info[ix].shortPreamble || 4849 rt->info[ix].phy == IEEE80211_T_OFDM) 4850 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4851 /* NB: receive frames include FCS */ 4852 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4853 IEEE80211_RADIOTAP_F_FCS; 4854 /* setup blink rate table to avoid per-packet lookup */ 4855 for (j = 0; j < N(blinkrates)-1; j++) 4856 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4857 break; 4858 /* NB: this uses the last entry if the rate isn't found */ 4859 /* XXX beware of overlow */ 4860 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4861 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4862 } 4863 sc->sc_currates = rt; 4864 sc->sc_curmode = mode; 4865 /* 4866 * All protection frames are transmited at 2Mb/s for 4867 * 11g, otherwise at 1Mb/s. 4868 */ 4869 if (mode == IEEE80211_MODE_11G) 4870 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 4871 else 4872 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 4873 /* rate index used to send management frames */ 4874 sc->sc_minrateix = 0; 4875 /* 4876 * Setup multicast rate state. 4877 */ 4878 /* XXX layering violation */ 4879 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 4880 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 4881 /* NB: caller is responsible for reseting rate control state */ 4882#undef N 4883} 4884 4885#ifdef ATH_DEBUG 4886static void 4887ath_printrxbuf(struct ath_buf *bf, u_int ix, int done) 4888{ 4889 struct ath_desc *ds; 4890 int i; 4891 4892 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4893 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 4894 " %08x %08x %08x %08x\n", 4895 ix, ds, (struct ath_desc *)bf->bf_daddr + i, 4896 ds->ds_link, ds->ds_data, 4897 !done ? "" : (ds->ds_rxstat.rs_status == 0) ? " *" : " !", 4898 ds->ds_ctl0, ds->ds_ctl1, 4899 ds->ds_hw[0], ds->ds_hw[1]); 4900 } 4901} 4902 4903static void 4904ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done) 4905{ 4906 struct ath_desc *ds; 4907 int i; 4908 4909 printf("Q%u[%3u]", qnum, ix); 4910 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4911 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 4912 " %08x %08x %08x %08x %08x %08x\n", 4913 ds, (struct ath_desc *)bf->bf_daddr + i, 4914 ds->ds_link, ds->ds_data, bf->bf_flags, 4915 !done ? "" : (ds->ds_txstat.ts_status == 0) ? " *" : " !", 4916 ds->ds_ctl0, ds->ds_ctl1, 4917 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 4918 } 4919} 4920#endif /* ATH_DEBUG */ 4921 4922static void 4923ath_watchdog(struct ifnet *ifp) 4924{ 4925 struct ath_softc *sc = ifp->if_softc; 4926 struct ieee80211com *ic = &sc->sc_ic; 4927 4928 ifp->if_timer = 0; 4929 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 4930 return; 4931 if (sc->sc_tx_timer) { 4932 if (--sc->sc_tx_timer == 0) { 4933 if_printf(ifp, "device timeout\n"); 4934 ath_reset(ifp); 4935 ifp->if_oerrors++; 4936 sc->sc_stats.ast_watchdog++; 4937 } else 4938 ifp->if_timer = 1; 4939 } 4940 ieee80211_watchdog(ic); 4941} 4942 4943#ifdef ATH_DIAGAPI 4944/* 4945 * Diagnostic interface to the HAL. This is used by various 4946 * tools to do things like retrieve register contents for 4947 * debugging. The mechanism is intentionally opaque so that 4948 * it can change frequently w/o concern for compatiblity. 4949 */ 4950static int 4951ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4952{ 4953 struct ath_hal *ah = sc->sc_ah; 4954 u_int id = ad->ad_id & ATH_DIAG_ID; 4955 void *indata = NULL; 4956 void *outdata = NULL; 4957 u_int32_t insize = ad->ad_in_size; 4958 u_int32_t outsize = ad->ad_out_size; 4959 int error = 0; 4960 4961 if (ad->ad_id & ATH_DIAG_IN) { 4962 /* 4963 * Copy in data. 4964 */ 4965 indata = malloc(insize, M_TEMP, M_NOWAIT); 4966 if (indata == NULL) { 4967 error = ENOMEM; 4968 goto bad; 4969 } 4970 error = copyin(ad->ad_in_data, indata, insize); 4971 if (error) 4972 goto bad; 4973 } 4974 if (ad->ad_id & ATH_DIAG_DYN) { 4975 /* 4976 * Allocate a buffer for the results (otherwise the HAL 4977 * returns a pointer to a buffer where we can read the 4978 * results). Note that we depend on the HAL leaving this 4979 * pointer for us to use below in reclaiming the buffer; 4980 * may want to be more defensive. 4981 */ 4982 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4983 if (outdata == NULL) { 4984 error = ENOMEM; 4985 goto bad; 4986 } 4987 } 4988 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4989 if (outsize < ad->ad_out_size) 4990 ad->ad_out_size = outsize; 4991 if (outdata != NULL) 4992 error = copyout(outdata, ad->ad_out_data, 4993 ad->ad_out_size); 4994 } else { 4995 error = EINVAL; 4996 } 4997bad: 4998 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4999 free(indata, M_TEMP); 5000 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5001 free(outdata, M_TEMP); 5002 return error; 5003} 5004#endif /* ATH_DIAGAPI */ 5005 5006static int 5007ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5008{ 5009#define IS_RUNNING(ifp) \ 5010 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5011 struct ath_softc *sc = ifp->if_softc; 5012 struct ieee80211com *ic = &sc->sc_ic; 5013 struct ifreq *ifr = (struct ifreq *)data; 5014 int error = 0; 5015 5016 ATH_LOCK(sc); 5017 switch (cmd) { 5018 case SIOCSIFFLAGS: 5019 if (IS_RUNNING(ifp)) { 5020 /* 5021 * To avoid rescanning another access point, 5022 * do not call ath_init() here. Instead, 5023 * only reflect promisc mode settings. 5024 */ 5025 ath_mode_init(sc); 5026 } else if (ifp->if_flags & IFF_UP) { 5027 /* 5028 * Beware of being called during attach/detach 5029 * to reset promiscuous mode. In that case we 5030 * will still be marked UP but not RUNNING. 5031 * However trying to re-init the interface 5032 * is the wrong thing to do as we've already 5033 * torn down much of our state. There's 5034 * probably a better way to deal with this. 5035 */ 5036 if (!sc->sc_invalid && ic->ic_bss != NULL) 5037 ath_init(sc); /* XXX lose error */ 5038 } else 5039 ath_stop_locked(ifp); 5040 break; 5041 case SIOCADDMULTI: 5042 case SIOCDELMULTI: 5043 /* 5044 * The upper layer has already installed/removed 5045 * the multicast address(es), just recalculate the 5046 * multicast filter for the card. 5047 */ 5048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5049 ath_mode_init(sc); 5050 break; 5051 case SIOCGATHSTATS: 5052 /* NB: embed these numbers to get a consistent view */ 5053 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5054 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5055 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5056 ATH_UNLOCK(sc); 5057 /* 5058 * NB: Drop the softc lock in case of a page fault; 5059 * we'll accept any potential inconsisentcy in the 5060 * statistics. The alternative is to copy the data 5061 * to a local structure. 5062 */ 5063 return copyout(&sc->sc_stats, 5064 ifr->ifr_data, sizeof (sc->sc_stats)); 5065#ifdef ATH_DIAGAPI 5066 case SIOCGATHDIAG: 5067 ATH_UNLOCK(sc); 5068 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5069 ATH_LOCK(sc); 5070 break; 5071#endif 5072 default: 5073 error = ieee80211_ioctl(ic, cmd, data); 5074 if (error == ENETRESET) { 5075 if (IS_RUNNING(ifp) && 5076 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5077 ath_init(sc); /* XXX lose error */ 5078 error = 0; 5079 } 5080 if (error == ERESTART) 5081 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5082 break; 5083 } 5084 ATH_UNLOCK(sc); 5085 return error; 5086#undef IS_RUNNING 5087} 5088 5089static int 5090ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 5091{ 5092 struct ath_softc *sc = arg1; 5093 u_int slottime = ath_hal_getslottime(sc->sc_ah); 5094 int error; 5095 5096 error = sysctl_handle_int(oidp, &slottime, 0, req); 5097 if (error || !req->newptr) 5098 return error; 5099 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 5100} 5101 5102static int 5103ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 5104{ 5105 struct ath_softc *sc = arg1; 5106 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 5107 int error; 5108 5109 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 5110 if (error || !req->newptr) 5111 return error; 5112 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 5113} 5114 5115static int 5116ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 5117{ 5118 struct ath_softc *sc = arg1; 5119 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 5120 int error; 5121 5122 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 5123 if (error || !req->newptr) 5124 return error; 5125 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 5126} 5127 5128static int 5129ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 5130{ 5131 struct ath_softc *sc = arg1; 5132 int softled = sc->sc_softled; 5133 int error; 5134 5135 error = sysctl_handle_int(oidp, &softled, 0, req); 5136 if (error || !req->newptr) 5137 return error; 5138 softled = (softled != 0); 5139 if (softled != sc->sc_softled) { 5140 if (softled) { 5141 /* NB: handle any sc_ledpin change */ 5142 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 5143 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 5144 !sc->sc_ledon); 5145 } 5146 sc->sc_softled = softled; 5147 } 5148 return 0; 5149} 5150 5151static int 5152ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 5153{ 5154 struct ath_softc *sc = arg1; 5155 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 5156 int error; 5157 5158 error = sysctl_handle_int(oidp, &defantenna, 0, req); 5159 if (!error && req->newptr) 5160 ath_hal_setdefantenna(sc->sc_ah, defantenna); 5161 return error; 5162} 5163 5164static int 5165ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 5166{ 5167 struct ath_softc *sc = arg1; 5168 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 5169 int error; 5170 5171 error = sysctl_handle_int(oidp, &diversity, 0, req); 5172 if (error || !req->newptr) 5173 return error; 5174 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 5175 return EINVAL; 5176 sc->sc_diversity = diversity; 5177 return 0; 5178} 5179 5180static int 5181ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 5182{ 5183 struct ath_softc *sc = arg1; 5184 u_int32_t diag; 5185 int error; 5186 5187 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 5188 return EINVAL; 5189 error = sysctl_handle_int(oidp, &diag, 0, req); 5190 if (error || !req->newptr) 5191 return error; 5192 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 5193} 5194 5195static int 5196ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 5197{ 5198 struct ath_softc *sc = arg1; 5199 struct ifnet *ifp = sc->sc_ifp; 5200 u_int32_t scale; 5201 int error; 5202 5203 ath_hal_gettpscale(sc->sc_ah, &scale); 5204 error = sysctl_handle_int(oidp, &scale, 0, req); 5205 if (error || !req->newptr) 5206 return error; 5207 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp); 5208} 5209 5210static int 5211ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 5212{ 5213 struct ath_softc *sc = arg1; 5214 u_int tpc = ath_hal_gettpc(sc->sc_ah); 5215 int error; 5216 5217 error = sysctl_handle_int(oidp, &tpc, 0, req); 5218 if (error || !req->newptr) 5219 return error; 5220 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 5221} 5222 5223static int 5224ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 5225{ 5226 struct ath_softc *sc = arg1; 5227 struct ath_hal *ah = sc->sc_ah; 5228 u_int rfkill = ath_hal_getrfkill(ah); 5229 int error; 5230 5231 error = sysctl_handle_int(oidp, &rfkill, 0, req); 5232 if (error || !req->newptr) 5233 return error; 5234 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 5235 return 0; 5236 if (!ath_hal_setrfkill(ah, rfkill) || ath_reset(sc->sc_ifp) != 0) 5237 return EINVAL; 5238 else 5239 return 0; 5240} 5241 5242static int 5243ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 5244{ 5245 struct ath_softc *sc = arg1; 5246 u_int rfsilent; 5247 int error; 5248 5249 ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 5250 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 5251 if (error || !req->newptr) 5252 return error; 5253 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 5254 return EINVAL; 5255 sc->sc_rfsilentpin = rfsilent & 0x1c; 5256 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 5257 return 0; 5258} 5259 5260static int 5261ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS) 5262{ 5263 struct ath_softc *sc = arg1; 5264 u_int32_t rd; 5265 int error; 5266 5267 if (!ath_hal_getregdomain(sc->sc_ah, &rd)) 5268 return EINVAL; 5269 error = sysctl_handle_int(oidp, &rd, 0, req); 5270 if (error || !req->newptr) 5271 return error; 5272 return !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0; 5273} 5274 5275static int 5276ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 5277{ 5278 struct ath_softc *sc = arg1; 5279 u_int32_t tpack; 5280 int error; 5281 5282 ath_hal_gettpack(sc->sc_ah, &tpack); 5283 error = sysctl_handle_int(oidp, &tpack, 0, req); 5284 if (error || !req->newptr) 5285 return error; 5286 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 5287} 5288 5289static int 5290ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 5291{ 5292 struct ath_softc *sc = arg1; 5293 u_int32_t tpcts; 5294 int error; 5295 5296 ath_hal_gettpcts(sc->sc_ah, &tpcts); 5297 error = sysctl_handle_int(oidp, &tpcts, 0, req); 5298 if (error || !req->newptr) 5299 return error; 5300 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 5301} 5302 5303static void 5304ath_sysctlattach(struct ath_softc *sc) 5305{ 5306 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 5307 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 5308 struct ath_hal *ah = sc->sc_ah; 5309 5310 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode); 5311 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5312 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0, 5313 "EEPROM country code"); 5314 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5315 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5316 ath_sysctl_regdomain, "I", "EEPROM regdomain code"); 5317#ifdef ATH_DEBUG 5318 sc->sc_debug = ath_debug; 5319 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5320 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 5321 "control debugging printfs"); 5322#endif 5323 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5324 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5325 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 5326 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5327 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5328 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 5329 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5330 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5331 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 5332 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5333 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5334 ath_sysctl_softled, "I", "enable/disable software LED support"); 5335 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5336 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0, 5337 "GPIO pin connected to LED"); 5338 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5339 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 5340 "setting to turn LED on"); 5341 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5342 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 5343 "idle time for inactivity LED (ticks)"); 5344 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5345 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0, 5346 "tx antenna (0=auto)"); 5347 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5348 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5349 ath_sysctl_rxantenna, "I", "default/rx antenna"); 5350 if (ath_hal_hasdiversity(ah)) 5351 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5352 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5353 ath_sysctl_diversity, "I", "antenna diversity"); 5354 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 5355 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5356 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 5357 "tx descriptor batching"); 5358 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5359 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5360 ath_sysctl_diag, "I", "h/w diagnostic control"); 5361 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5362 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5363 ath_sysctl_tpscale, "I", "tx power scaling"); 5364 if (ath_hal_hastpc(ah)) { 5365 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5366 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5367 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 5368 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5369 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5370 ath_sysctl_tpack, "I", "tx power for ack frames"); 5371 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5372 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5373 ath_sysctl_tpcts, "I", "tx power for cts frames"); 5374 } 5375 if (ath_hal_hasrfsilent(ah)) { 5376 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5377 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5378 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 5379 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5380 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 5381 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 5382 } 5383 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 5384 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 5385 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 5386 "mask of error frames to pass when monitoring"); 5387} 5388 5389static void 5390ath_bpfattach(struct ath_softc *sc) 5391{ 5392 struct ifnet *ifp = sc->sc_ifp; 5393 5394 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5395 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5396 &sc->sc_drvbpf); 5397 /* 5398 * Initialize constant fields. 5399 * XXX make header lengths a multiple of 32-bits so subsequent 5400 * headers are properly aligned; this is a kludge to keep 5401 * certain applications happy. 5402 * 5403 * NB: the channel is setup each time we transition to the 5404 * RUN state to avoid filling it in for each frame. 5405 */ 5406 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5407 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5408 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5409 5410 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5411 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5412 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5413} 5414 5415/* 5416 * Announce various information on device/driver attach. 5417 */ 5418static void 5419ath_announce(struct ath_softc *sc) 5420{ 5421#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5422 struct ifnet *ifp = sc->sc_ifp; 5423 struct ath_hal *ah = sc->sc_ah; 5424 u_int modes, cc; 5425 5426 if_printf(ifp, "mac %d.%d phy %d.%d", 5427 ah->ah_macVersion, ah->ah_macRev, 5428 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5429 /* 5430 * Print radio revision(s). We check the wireless modes 5431 * to avoid falsely printing revs for inoperable parts. 5432 * Dual-band radio revs are returned in the 5Ghz rev number. 5433 */ 5434 ath_hal_getcountrycode(ah, &cc); 5435 modes = ath_hal_getwirelessmodes(ah, cc); 5436 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5437 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5438 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 5439 ah->ah_analog5GhzRev >> 4, 5440 ah->ah_analog5GhzRev & 0xf, 5441 ah->ah_analog2GhzRev >> 4, 5442 ah->ah_analog2GhzRev & 0xf); 5443 else 5444 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5445 ah->ah_analog5GhzRev & 0xf); 5446 } else 5447 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5448 ah->ah_analog5GhzRev & 0xf); 5449 printf("\n"); 5450 if (bootverbose) { 5451 int i; 5452 for (i = 0; i <= WME_AC_VO; i++) { 5453 struct ath_txq *txq = sc->sc_ac2q[i]; 5454 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5455 txq->axq_qnum, ieee80211_wme_acnames[i]); 5456 } 5457 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5458 sc->sc_cabq->axq_qnum); 5459 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5460 } 5461 if (ath_rxbuf != ATH_RXBUF) 5462 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5463 if (ath_txbuf != ATH_TXBUF) 5464 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5465#undef HAL_MODE_DUALBAND 5466} 5467