if_ath.c revision 144350
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 144350 2005-03-30 20:29:02Z sam $"); 39 40/* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47#include "opt_inet.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/sysctl.h> 52#include <sys/mbuf.h> 53#include <sys/malloc.h> 54#include <sys/lock.h> 55#include <sys/mutex.h> 56#include <sys/kernel.h> 57#include <sys/socket.h> 58#include <sys/sockio.h> 59#include <sys/errno.h> 60#include <sys/callout.h> 61#include <sys/bus.h> 62#include <sys/endian.h> 63 64#include <machine/bus.h> 65 66#include <net/if.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_arp.h> 70#include <net/ethernet.h> 71#include <net/if_llc.h> 72 73#include <net80211/ieee80211_var.h> 74 75#include <net/bpf.h> 76 77#ifdef INET 78#include <netinet/in.h> 79#include <netinet/if_ether.h> 80#endif 81 82#define AR_DEBUG 83#include <dev/ath/if_athvar.h> 84#include <contrib/dev/ath/ah_desc.h> 85#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 86 87/* unalligned little endian access */ 88#define LE_READ_2(p) \ 89 ((u_int16_t) \ 90 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 91#define LE_READ_4(p) \ 92 ((u_int32_t) \ 93 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 94 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 95 96enum { 97 ATH_LED_TX, 98 ATH_LED_RX, 99 ATH_LED_POLL, 100}; 101 102static void ath_init(void *); 103static void ath_stop_locked(struct ifnet *); 104static void ath_stop(struct ifnet *); 105static void ath_start(struct ifnet *); 106static int ath_reset(struct ifnet *); 107static int ath_media_change(struct ifnet *); 108static void ath_watchdog(struct ifnet *); 109static int ath_ioctl(struct ifnet *, u_long, caddr_t); 110static void ath_fatal_proc(void *, int); 111static void ath_rxorn_proc(void *, int); 112static void ath_bmiss_proc(void *, int); 113static void ath_initkeytable(struct ath_softc *); 114static int ath_key_alloc(struct ieee80211com *, 115 const struct ieee80211_key *); 116static int ath_key_delete(struct ieee80211com *, 117 const struct ieee80211_key *); 118static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 119 const u_int8_t mac[IEEE80211_ADDR_LEN]); 120static void ath_key_update_begin(struct ieee80211com *); 121static void ath_key_update_end(struct ieee80211com *); 122static void ath_mode_init(struct ath_softc *); 123static void ath_setslottime(struct ath_softc *); 124static void ath_updateslot(struct ifnet *); 125static int ath_beaconq_setup(struct ath_hal *); 126static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 127static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 128static void ath_beacon_proc(void *, int); 129static void ath_bstuck_proc(void *, int); 130static void ath_beacon_free(struct ath_softc *); 131static void ath_beacon_config(struct ath_softc *); 132static void ath_descdma_cleanup(struct ath_softc *sc, 133 struct ath_descdma *, ath_bufhead *); 134static int ath_desc_alloc(struct ath_softc *); 135static void ath_desc_free(struct ath_softc *); 136static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 137static void ath_node_free(struct ieee80211_node *); 138static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 139static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 140static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 141 struct ieee80211_node *ni, 142 int subtype, int rssi, u_int32_t rstamp); 143static void ath_setdefantenna(struct ath_softc *, u_int); 144static void ath_rx_proc(void *, int); 145static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 146static int ath_tx_setup(struct ath_softc *, int, int); 147static int ath_wme_update(struct ieee80211com *); 148static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 149static void ath_tx_cleanup(struct ath_softc *); 150static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 151 struct ath_buf *, struct mbuf *); 152static void ath_tx_proc_q0(void *, int); 153static void ath_tx_proc_q0123(void *, int); 154static void ath_tx_proc(void *, int); 155static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 156static void ath_draintxq(struct ath_softc *); 157static void ath_stoprecv(struct ath_softc *); 158static int ath_startrecv(struct ath_softc *); 159static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 160static void ath_next_scan(void *); 161static void ath_calibrate(void *); 162static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 163static void ath_newassoc(struct ieee80211com *, 164 struct ieee80211_node *, int); 165static int ath_getchannels(struct ath_softc *, u_int cc, 166 HAL_BOOL outdoor, HAL_BOOL xchanmode); 167static void ath_led_event(struct ath_softc *, int); 168static void ath_update_txpow(struct ath_softc *); 169 170static int ath_rate_setup(struct ath_softc *, u_int mode); 171static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 172 173static void ath_sysctlattach(struct ath_softc *); 174static void ath_bpfattach(struct ath_softc *); 175static void ath_announce(struct ath_softc *); 176 177SYSCTL_DECL(_hw_ath); 178 179/* XXX validate sysctl values */ 180static int ath_dwelltime = 200; /* 5 channels/second */ 181SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 182 0, "channel dwell time (ms) for AP/station scanning"); 183static int ath_calinterval = 30; /* calibrate every 30 secs */ 184SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 185 0, "chip calibration interval (secs)"); 186static int ath_outdoor = AH_TRUE; /* outdoor operation */ 187SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 188 0, "outdoor operation"); 189TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 190static int ath_xchanmode = AH_TRUE; /* extended channel use */ 191SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode, 192 0, "extended channel mode"); 193TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 194static int ath_countrycode = CTRY_DEFAULT; /* country code */ 195SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 196 0, "country code"); 197TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 198static int ath_regdomain = 0; /* regulatory domain */ 199SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 200 0, "regulatory domain"); 201 202#ifdef AR_DEBUG 203static int ath_debug = 0; 204SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 205 0, "control debugging printfs"); 206TUNABLE_INT("hw.ath.debug", &ath_debug); 207enum { 208 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 209 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 210 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 211 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 212 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 213 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 214 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 215 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 216 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 217 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 218 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 219 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 220 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 221 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 222 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 223 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 224 ATH_DEBUG_NODE = 0x00080000, /* node management */ 225 ATH_DEBUG_LED = 0x00100000, /* led management */ 226 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 227 ATH_DEBUG_ANY = 0xffffffff 228}; 229#define IFF_DUMPPKTS(sc, m) \ 230 ((sc->sc_debug & (m)) || \ 231 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 232#define DPRINTF(sc, m, fmt, ...) do { \ 233 if (sc->sc_debug & (m)) \ 234 printf(fmt, __VA_ARGS__); \ 235} while (0) 236#define KEYPRINTF(sc, ix, hk, mac) do { \ 237 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 238 ath_keyprint(__func__, ix, hk, mac); \ 239} while (0) 240static void ath_printrxbuf(struct ath_buf *bf, int); 241static void ath_printtxbuf(struct ath_buf *bf, int); 242#else 243#define IFF_DUMPPKTS(sc, m) \ 244 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245#define DPRINTF(m, fmt, ...) 246#define KEYPRINTF(sc, k, ix, mac) 247#endif 248 249MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 250 251int 252ath_attach(u_int16_t devid, struct ath_softc *sc) 253{ 254 struct ifnet *ifp = &sc->sc_if; 255 struct ieee80211com *ic = &sc->sc_ic; 256 struct ath_hal *ah; 257 HAL_STATUS status; 258 int error = 0, i; 259 260 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 261 262 /* set these up early for if_printf use */ 263 if_initname(ifp, device_get_name(sc->sc_dev), 264 device_get_unit(sc->sc_dev)); 265 266 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 267 if (ah == NULL) { 268 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 269 status); 270 error = ENXIO; 271 goto bad; 272 } 273 if (ah->ah_abi != HAL_ABI_VERSION) { 274 if_printf(ifp, "HAL ABI mismatch detected " 275 "(HAL:0x%x != driver:0x%x)\n", 276 ah->ah_abi, HAL_ABI_VERSION); 277 error = ENXIO; 278 goto bad; 279 } 280 sc->sc_ah = ah; 281 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 282 283 /* 284 * Check if the MAC has multi-rate retry support. 285 * We do this by trying to setup a fake extended 286 * descriptor. MAC's that don't have support will 287 * return false w/o doing anything. MAC's that do 288 * support it will return true w/o doing anything. 289 */ 290 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 291 292 /* 293 * Check if the device has hardware counters for PHY 294 * errors. If so we need to enable the MIB interrupt 295 * so we can act on stat triggers. 296 */ 297 if (ath_hal_hwphycounters(ah)) 298 sc->sc_needmib = 1; 299 300 /* 301 * Get the hardware key cache size. 302 */ 303 sc->sc_keymax = ath_hal_keycachesize(ah); 304 if (sc->sc_keymax > sizeof(sc->sc_keymap) * NBBY) { 305 if_printf(ifp, 306 "Warning, using only %zu of %u key cache slots\n", 307 sizeof(sc->sc_keymap) * NBBY, sc->sc_keymax); 308 sc->sc_keymax = sizeof(sc->sc_keymap) * NBBY; 309 } 310 /* 311 * Reset the key cache since some parts do not 312 * reset the contents on initial power up. 313 */ 314 for (i = 0; i < sc->sc_keymax; i++) 315 ath_hal_keyreset(ah, i); 316 /* 317 * Mark key cache slots associated with global keys 318 * as in use. If we knew TKIP was not to be used we 319 * could leave the +32, +64, and +32+64 slots free. 320 * XXX only for splitmic. 321 */ 322 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 323 setbit(sc->sc_keymap, i); 324 setbit(sc->sc_keymap, i+32); 325 setbit(sc->sc_keymap, i+64); 326 setbit(sc->sc_keymap, i+32+64); 327 } 328 329 /* 330 * Collect the channel list using the default country 331 * code and including outdoor channels. The 802.11 layer 332 * is resposible for filtering this list based on settings 333 * like the phy mode. 334 */ 335 error = ath_getchannels(sc, ath_countrycode, 336 ath_outdoor, ath_xchanmode); 337 if (error != 0) 338 goto bad; 339 /* 340 * Setup dynamic sysctl's now that country code and 341 * regdomain are available from the hal. 342 */ 343 ath_sysctlattach(sc); 344 345 /* 346 * Setup rate tables for all potential media types. 347 */ 348 ath_rate_setup(sc, IEEE80211_MODE_11A); 349 ath_rate_setup(sc, IEEE80211_MODE_11B); 350 ath_rate_setup(sc, IEEE80211_MODE_11G); 351 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 352 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 353 /* NB: setup here so ath_rate_update is happy */ 354 ath_setcurmode(sc, IEEE80211_MODE_11A); 355 356 /* 357 * Allocate tx+rx descriptors and populate the lists. 358 */ 359 error = ath_desc_alloc(sc); 360 if (error != 0) { 361 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 362 goto bad; 363 } 364 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 365 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 366 367 ATH_TXBUF_LOCK_INIT(sc); 368 369 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 370 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 371 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 372 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 373 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 374 375 /* 376 * Allocate hardware transmit queues: one queue for 377 * beacon frames and one data queue for each QoS 378 * priority. Note that the hal handles reseting 379 * these queues at the needed time. 380 * 381 * XXX PS-Poll 382 */ 383 sc->sc_bhalq = ath_beaconq_setup(ah); 384 if (sc->sc_bhalq == (u_int) -1) { 385 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 386 error = EIO; 387 goto bad2; 388 } 389 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 390 if (sc->sc_cabq == NULL) { 391 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 392 error = EIO; 393 goto bad2; 394 } 395 /* NB: insure BK queue is the lowest priority h/w queue */ 396 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 397 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 398 ieee80211_wme_acnames[WME_AC_BK]); 399 error = EIO; 400 goto bad2; 401 } 402 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 403 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 404 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 405 /* 406 * Not enough hardware tx queues to properly do WME; 407 * just punt and assign them all to the same h/w queue. 408 * We could do a better job of this if, for example, 409 * we allocate queues when we switch from station to 410 * AP mode. 411 */ 412 if (sc->sc_ac2q[WME_AC_VI] != NULL) 413 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 414 if (sc->sc_ac2q[WME_AC_BE] != NULL) 415 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 416 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 417 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 418 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 419 } 420 421 /* 422 * Special case certain configurations. Note the 423 * CAB queue is handled by these specially so don't 424 * include them when checking the txq setup mask. 425 */ 426 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 427 case 0x01: 428 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 429 break; 430 case 0x0f: 431 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 432 break; 433 default: 434 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 435 break; 436 } 437 438 /* 439 * Setup rate control. Some rate control modules 440 * call back to change the anntena state so expose 441 * the necessary entry points. 442 * XXX maybe belongs in struct ath_ratectrl? 443 */ 444 sc->sc_setdefantenna = ath_setdefantenna; 445 sc->sc_rc = ath_rate_attach(sc); 446 if (sc->sc_rc == NULL) { 447 error = EIO; 448 goto bad2; 449 } 450 451 sc->sc_blinking = 0; 452 sc->sc_ledstate = 1; 453 sc->sc_ledon = 0; /* low true */ 454 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 455 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 456 /* 457 * Auto-enable soft led processing for IBM cards and for 458 * 5211 minipci cards. Users can also manually enable/disable 459 * support with a sysctl. 460 */ 461 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 462 if (sc->sc_softled) { 463 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 464 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 465 } 466 467 ifp->if_softc = sc; 468 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 469 ifp->if_start = ath_start; 470 ifp->if_watchdog = ath_watchdog; 471 ifp->if_ioctl = ath_ioctl; 472 ifp->if_init = ath_init; 473 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 474 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 475 IFQ_SET_READY(&ifp->if_snd); 476 477 ic->ic_ifp = ifp; 478 ic->ic_reset = ath_reset; 479 ic->ic_newassoc = ath_newassoc; 480 ic->ic_updateslot = ath_updateslot; 481 ic->ic_wme.wme_update = ath_wme_update; 482 /* XXX not right but it's not used anywhere important */ 483 ic->ic_phytype = IEEE80211_T_OFDM; 484 ic->ic_opmode = IEEE80211_M_STA; 485 ic->ic_caps = 486 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 487 | IEEE80211_C_HOSTAP /* hostap mode */ 488 | IEEE80211_C_MONITOR /* monitor mode */ 489 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 490 | IEEE80211_C_SHSLOT /* short slot time supported */ 491 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 492 ; 493 /* 494 * Query the hal to figure out h/w crypto support. 495 */ 496 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 497 ic->ic_caps |= IEEE80211_C_WEP; 498 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 499 ic->ic_caps |= IEEE80211_C_AES; 500 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 501 ic->ic_caps |= IEEE80211_C_AES_CCM; 502 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 503 ic->ic_caps |= IEEE80211_C_CKIP; 504 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 505 ic->ic_caps |= IEEE80211_C_TKIP; 506 /* 507 * Check if h/w does the MIC and/or whether the 508 * separate key cache entries are required to 509 * handle both tx+rx MIC keys. 510 */ 511 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 512 ic->ic_caps |= IEEE80211_C_TKIPMIC; 513 if (ath_hal_tkipsplit(ah)) 514 sc->sc_splitmic = 1; 515 } 516 /* 517 * TPC support can be done either with a global cap or 518 * per-packet support. The latter is not available on 519 * all parts. We're a bit pedantic here as all parts 520 * support a global cap. 521 */ 522 sc->sc_hastpc = ath_hal_hastpc(ah); 523 if (sc->sc_hastpc || ath_hal_hastxpowlimit(ah)) 524 ic->ic_caps |= IEEE80211_C_TXPMGT; 525 526 /* 527 * Mark WME capability only if we have sufficient 528 * hardware queues to do proper priority scheduling. 529 */ 530 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 531 ic->ic_caps |= IEEE80211_C_WME; 532 /* 533 * Check for frame bursting capability. 534 */ 535 if (ath_hal_hasbursting(ah)) 536 ic->ic_caps |= IEEE80211_C_BURST; 537 538 /* 539 * Indicate we need the 802.11 header padded to a 540 * 32-bit boundary for 4-address and QoS frames. 541 */ 542 ic->ic_flags |= IEEE80211_F_DATAPAD; 543 544 /* 545 * Query the hal about antenna support. 546 */ 547 if (ath_hal_hasdiversity(ah)) { 548 sc->sc_hasdiversity = 1; 549 sc->sc_diversity = ath_hal_getdiversity(ah); 550 } 551 sc->sc_defant = ath_hal_getdefantenna(ah); 552 553 /* 554 * Not all chips have the VEOL support we want to 555 * use with IBSS beacons; check here for it. 556 */ 557 sc->sc_hasveol = ath_hal_hasveol(ah); 558 559 /* get mac address from hardware */ 560 ath_hal_getmac(ah, ic->ic_myaddr); 561 562 /* call MI attach routine. */ 563 ieee80211_ifattach(ic); 564 /* override default methods */ 565 ic->ic_node_alloc = ath_node_alloc; 566 sc->sc_node_free = ic->ic_node_free; 567 ic->ic_node_free = ath_node_free; 568 ic->ic_node_getrssi = ath_node_getrssi; 569 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 570 ic->ic_recv_mgmt = ath_recv_mgmt; 571 sc->sc_newstate = ic->ic_newstate; 572 ic->ic_newstate = ath_newstate; 573 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 574 ic->ic_crypto.cs_key_delete = ath_key_delete; 575 ic->ic_crypto.cs_key_set = ath_key_set; 576 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 577 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 578 /* complete initialization */ 579 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 580 581 ath_bpfattach(sc); 582 583 if (bootverbose) 584 ieee80211_announce(ic); 585 ath_announce(sc); 586 return 0; 587bad2: 588 ath_tx_cleanup(sc); 589 ath_desc_free(sc); 590bad: 591 if (ah) 592 ath_hal_detach(ah); 593 sc->sc_invalid = 1; 594 return error; 595} 596 597int 598ath_detach(struct ath_softc *sc) 599{ 600 struct ifnet *ifp = &sc->sc_if; 601 602 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 603 __func__, ifp->if_flags); 604 605 ath_stop(ifp); 606 bpfdetach(ifp); 607 /* 608 * NB: the order of these is important: 609 * o call the 802.11 layer before detaching the hal to 610 * insure callbacks into the driver to delete global 611 * key cache entries can be handled 612 * o reclaim the tx queue data structures after calling 613 * the 802.11 layer as we'll get called back to reclaim 614 * node state and potentially want to use them 615 * o to cleanup the tx queues the hal is called, so detach 616 * it last 617 * Other than that, it's straightforward... 618 */ 619 ieee80211_ifdetach(&sc->sc_ic); 620 ath_rate_detach(sc->sc_rc); 621 ath_desc_free(sc); 622 ath_tx_cleanup(sc); 623 ath_hal_detach(sc->sc_ah); 624 625 return 0; 626} 627 628void 629ath_suspend(struct ath_softc *sc) 630{ 631 struct ifnet *ifp = &sc->sc_if; 632 633 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 634 __func__, ifp->if_flags); 635 636 ath_stop(ifp); 637} 638 639void 640ath_resume(struct ath_softc *sc) 641{ 642 struct ifnet *ifp = &sc->sc_if; 643 644 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 645 __func__, ifp->if_flags); 646 647 if (ifp->if_flags & IFF_UP) { 648 ath_init(ifp); 649 if (ifp->if_flags & IFF_RUNNING) 650 ath_start(ifp); 651 } 652} 653 654void 655ath_shutdown(struct ath_softc *sc) 656{ 657 struct ifnet *ifp = &sc->sc_if; 658 659 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 660 __func__, ifp->if_flags); 661 662 ath_stop(ifp); 663} 664 665/* 666 * Interrupt handler. Most of the actual processing is deferred. 667 */ 668void 669ath_intr(void *arg) 670{ 671 struct ath_softc *sc = arg; 672 struct ifnet *ifp = &sc->sc_if; 673 struct ath_hal *ah = sc->sc_ah; 674 HAL_INT status; 675 676 if (sc->sc_invalid) { 677 /* 678 * The hardware is not ready/present, don't touch anything. 679 * Note this can happen early on if the IRQ is shared. 680 */ 681 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 682 return; 683 } 684 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 685 return; 686 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 687 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 688 __func__, ifp->if_flags); 689 ath_hal_getisr(ah, &status); /* clear ISR */ 690 ath_hal_intrset(ah, 0); /* disable further intr's */ 691 return; 692 } 693 /* 694 * Figure out the reason(s) for the interrupt. Note 695 * that the hal returns a pseudo-ISR that may include 696 * bits we haven't explicitly enabled so we mask the 697 * value to insure we only process bits we requested. 698 */ 699 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 700 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 701 status &= sc->sc_imask; /* discard unasked for bits */ 702 if (status & HAL_INT_FATAL) { 703 /* 704 * Fatal errors are unrecoverable. Typically 705 * these are caused by DMA errors. Unfortunately 706 * the exact reason is not (presently) returned 707 * by the hal. 708 */ 709 sc->sc_stats.ast_hardware++; 710 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 711 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 712 } else if (status & HAL_INT_RXORN) { 713 sc->sc_stats.ast_rxorn++; 714 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 715 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 716 } else { 717 if (status & HAL_INT_SWBA) { 718 /* 719 * Software beacon alert--time to send a beacon. 720 * Handle beacon transmission directly; deferring 721 * this is too slow to meet timing constraints 722 * under load. 723 */ 724 ath_beacon_proc(sc, 0); 725 } 726 if (status & HAL_INT_RXEOL) { 727 /* 728 * NB: the hardware should re-read the link when 729 * RXE bit is written, but it doesn't work at 730 * least on older hardware revs. 731 */ 732 sc->sc_stats.ast_rxeol++; 733 sc->sc_rxlink = NULL; 734 } 735 if (status & HAL_INT_TXURN) { 736 sc->sc_stats.ast_txurn++; 737 /* bump tx trigger level */ 738 ath_hal_updatetxtriglevel(ah, AH_TRUE); 739 } 740 if (status & HAL_INT_RX) 741 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 742 if (status & HAL_INT_TX) 743 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 744 if (status & HAL_INT_BMISS) { 745 sc->sc_stats.ast_bmiss++; 746 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 747 } 748 if (status & HAL_INT_MIB) { 749 sc->sc_stats.ast_mib++; 750 /* 751 * Disable interrupts until we service the MIB 752 * interrupt; otherwise it will continue to fire. 753 */ 754 ath_hal_intrset(ah, 0); 755 /* 756 * Let the hal handle the event. We assume it will 757 * clear whatever condition caused the interrupt. 758 */ 759 ath_hal_mibevent(ah, 760 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 761 ath_hal_intrset(ah, sc->sc_imask); 762 } 763 } 764} 765 766static void 767ath_fatal_proc(void *arg, int pending) 768{ 769 struct ath_softc *sc = arg; 770 struct ifnet *ifp = &sc->sc_if; 771 772 if_printf(ifp, "hardware error; resetting\n"); 773 ath_reset(ifp); 774} 775 776static void 777ath_rxorn_proc(void *arg, int pending) 778{ 779 struct ath_softc *sc = arg; 780 struct ifnet *ifp = &sc->sc_if; 781 782 if_printf(ifp, "rx FIFO overrun; resetting\n"); 783 ath_reset(ifp); 784} 785 786static void 787ath_bmiss_proc(void *arg, int pending) 788{ 789 struct ath_softc *sc = arg; 790 struct ieee80211com *ic = &sc->sc_ic; 791 792 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 793 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 794 ("unexpect operating mode %u", ic->ic_opmode)); 795 if (ic->ic_state == IEEE80211_S_RUN) { 796 /* 797 * Rather than go directly to scan state, try to 798 * reassociate first. If that fails then the state 799 * machine will drop us into scanning after timing 800 * out waiting for a probe response. 801 */ 802 NET_LOCK_GIANT(); 803 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 804 NET_UNLOCK_GIANT(); 805 } 806} 807 808static u_int 809ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 810{ 811#define N(a) (sizeof(a) / sizeof(a[0])) 812 static const u_int modeflags[] = { 813 0, /* IEEE80211_MODE_AUTO */ 814 CHANNEL_A, /* IEEE80211_MODE_11A */ 815 CHANNEL_B, /* IEEE80211_MODE_11B */ 816 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 817 0, /* IEEE80211_MODE_FH */ 818 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 819 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 820 }; 821 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 822 823 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 824 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 825 return modeflags[mode]; 826#undef N 827} 828 829static void 830ath_init(void *arg) 831{ 832 struct ath_softc *sc = (struct ath_softc *) arg; 833 struct ieee80211com *ic = &sc->sc_ic; 834 struct ifnet *ifp = &sc->sc_if; 835 struct ieee80211_node *ni; 836 struct ath_hal *ah = sc->sc_ah; 837 HAL_STATUS status; 838 839 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 840 __func__, ifp->if_flags); 841 842 ATH_LOCK(sc); 843 /* 844 * Stop anything previously setup. This is safe 845 * whether this is the first time through or not. 846 */ 847 ath_stop_locked(ifp); 848 849 /* 850 * The basic interface to setting the hardware in a good 851 * state is ``reset''. On return the hardware is known to 852 * be powered up and with interrupts disabled. This must 853 * be followed by initialization of the appropriate bits 854 * and then setup of the interrupt mask. 855 */ 856 sc->sc_curchan.channel = ic->ic_ibss_chan->ic_freq; 857 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 858 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 859 if_printf(ifp, "unable to reset hardware; hal status %u\n", 860 status); 861 goto done; 862 } 863 864 /* 865 * This is needed only to setup initial state 866 * but it's best done after a reset. 867 */ 868 ath_update_txpow(sc); 869 870 /* 871 * Setup the hardware after reset: the key cache 872 * is filled as needed and the receive engine is 873 * set going. Frame transmit is handled entirely 874 * in the frame output path; there's nothing to do 875 * here except setup the interrupt mask. 876 */ 877 ath_initkeytable(sc); /* XXX still needed? */ 878 if (ath_startrecv(sc) != 0) { 879 if_printf(ifp, "unable to start recv logic\n"); 880 goto done; 881 } 882 883 /* 884 * Enable interrupts. 885 */ 886 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 887 | HAL_INT_RXEOL | HAL_INT_RXORN 888 | HAL_INT_FATAL | HAL_INT_GLOBAL; 889 /* 890 * Enable MIB interrupts when there are hardware phy counters. 891 * Note we only do this (at the moment) for station mode. 892 */ 893 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 894 sc->sc_imask |= HAL_INT_MIB; 895 ath_hal_intrset(ah, sc->sc_imask); 896 897 ifp->if_flags |= IFF_RUNNING; 898 ic->ic_state = IEEE80211_S_INIT; 899 900 /* 901 * The hardware should be ready to go now so it's safe 902 * to kick the 802.11 state machine as it's likely to 903 * immediately call back to us to send mgmt frames. 904 */ 905 ni = ic->ic_bss; 906 ni->ni_chan = ic->ic_ibss_chan; 907 ath_chan_change(sc, ni->ni_chan); 908 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 909 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 910 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 911 } else 912 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 913done: 914 ATH_UNLOCK(sc); 915} 916 917static void 918ath_stop_locked(struct ifnet *ifp) 919{ 920 struct ath_softc *sc = ifp->if_softc; 921 struct ieee80211com *ic = &sc->sc_ic; 922 struct ath_hal *ah = sc->sc_ah; 923 924 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 925 __func__, sc->sc_invalid, ifp->if_flags); 926 927 ATH_LOCK_ASSERT(sc); 928 if (ifp->if_flags & IFF_RUNNING) { 929 /* 930 * Shutdown the hardware and driver: 931 * reset 802.11 state machine 932 * turn off timers 933 * disable interrupts 934 * turn off the radio 935 * clear transmit machinery 936 * clear receive machinery 937 * drain and release tx queues 938 * reclaim beacon resources 939 * power down hardware 940 * 941 * Note that some of this work is not possible if the 942 * hardware is gone (invalid). 943 */ 944 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 945 ifp->if_flags &= ~IFF_RUNNING; 946 ifp->if_timer = 0; 947 if (!sc->sc_invalid) { 948 if (sc->sc_softled) { 949 callout_stop(&sc->sc_ledtimer); 950 ath_hal_gpioset(ah, sc->sc_ledpin, 951 !sc->sc_ledon); 952 sc->sc_blinking = 0; 953 } 954 ath_hal_intrset(ah, 0); 955 } 956 ath_draintxq(sc); 957 if (!sc->sc_invalid) { 958 ath_stoprecv(sc); 959 ath_hal_phydisable(ah); 960 } else 961 sc->sc_rxlink = NULL; 962 IFQ_DRV_PURGE(&ifp->if_snd); 963 ath_beacon_free(sc); 964 } 965} 966 967static void 968ath_stop(struct ifnet *ifp) 969{ 970 struct ath_softc *sc = ifp->if_softc; 971 972 ATH_LOCK(sc); 973 ath_stop_locked(ifp); 974 if (!sc->sc_invalid) { 975 /* 976 * Set the chip in full sleep mode. Note that we are 977 * careful to do this only when bringing the interface 978 * completely to a stop. When the chip is in this state 979 * it must be carefully woken up or references to 980 * registers in the PCI clock domain may freeze the bus 981 * (and system). This varies by chip and is mostly an 982 * issue with newer parts that go to sleep more quickly. 983 */ 984 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 985 } 986 ATH_UNLOCK(sc); 987} 988 989/* 990 * Reset the hardware w/o losing operational state. This is 991 * basically a more efficient way of doing ath_stop, ath_init, 992 * followed by state transitions to the current 802.11 993 * operational state. Used to recover from various errors and 994 * to reset or reload hardware state. 995 */ 996static int 997ath_reset(struct ifnet *ifp) 998{ 999 struct ath_softc *sc = ifp->if_softc; 1000 struct ieee80211com *ic = &sc->sc_ic; 1001 struct ath_hal *ah = sc->sc_ah; 1002 struct ieee80211_channel *c; 1003 HAL_STATUS status; 1004 1005 /* 1006 * Convert to a HAL channel description with the flags 1007 * constrained to reflect the current operating mode. 1008 */ 1009 c = ic->ic_ibss_chan; 1010 sc->sc_curchan.channel = c->ic_freq; 1011 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1012 1013 ath_hal_intrset(ah, 0); /* disable interrupts */ 1014 ath_draintxq(sc); /* stop xmit side */ 1015 ath_stoprecv(sc); /* stop recv side */ 1016 /* NB: indicate channel change so we do a full reset */ 1017 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1018 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1019 __func__, status); 1020 ath_update_txpow(sc); /* update tx power state */ 1021 if (ath_startrecv(sc) != 0) /* restart recv */ 1022 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1023 /* 1024 * We may be doing a reset in response to an ioctl 1025 * that changes the channel so update any state that 1026 * might change as a result. 1027 */ 1028 ath_chan_change(sc, c); 1029 if (ic->ic_state == IEEE80211_S_RUN) 1030 ath_beacon_config(sc); /* restart beacons */ 1031 ath_hal_intrset(ah, sc->sc_imask); 1032 1033 ath_start(ifp); /* restart xmit */ 1034 return 0; 1035} 1036 1037static void 1038ath_start(struct ifnet *ifp) 1039{ 1040 struct ath_softc *sc = ifp->if_softc; 1041 struct ath_hal *ah = sc->sc_ah; 1042 struct ieee80211com *ic = &sc->sc_ic; 1043 struct ieee80211_node *ni; 1044 struct ath_buf *bf; 1045 struct mbuf *m; 1046 struct ieee80211_frame *wh; 1047 struct ether_header *eh; 1048 1049 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1050 return; 1051 for (;;) { 1052 /* 1053 * Grab a TX buffer and associated resources. 1054 */ 1055 ATH_TXBUF_LOCK(sc); 1056 bf = STAILQ_FIRST(&sc->sc_txbuf); 1057 if (bf != NULL) 1058 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1059 ATH_TXBUF_UNLOCK(sc); 1060 if (bf == NULL) { 1061 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1062 __func__); 1063 sc->sc_stats.ast_tx_qstop++; 1064 ifp->if_flags |= IFF_OACTIVE; 1065 break; 1066 } 1067 /* 1068 * Poll the management queue for frames; they 1069 * have priority over normal data frames. 1070 */ 1071 IF_DEQUEUE(&ic->ic_mgtq, m); 1072 if (m == NULL) { 1073 /* 1074 * No data frames go out unless we're associated. 1075 */ 1076 if (ic->ic_state != IEEE80211_S_RUN) { 1077 DPRINTF(sc, ATH_DEBUG_ANY, 1078 "%s: ignore data packet, state %u\n", 1079 __func__, ic->ic_state); 1080 sc->sc_stats.ast_tx_discard++; 1081 ATH_TXBUF_LOCK(sc); 1082 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1083 ATH_TXBUF_UNLOCK(sc); 1084 break; 1085 } 1086 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1087 if (m == NULL) { 1088 ATH_TXBUF_LOCK(sc); 1089 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1090 ATH_TXBUF_UNLOCK(sc); 1091 break; 1092 } 1093 /* 1094 * Find the node for the destination so we can do 1095 * things like power save and fast frames aggregation. 1096 */ 1097 if (m->m_len < sizeof(struct ether_header) && 1098 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1099 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1100 ni = NULL; 1101 goto bad; 1102 } 1103 eh = mtod(m, struct ether_header *); 1104 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1105 if (ni == NULL) { 1106 /* NB: ieee80211_find_txnode does stat+msg */ 1107 goto bad; 1108 } 1109 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1110 (m->m_flags & M_PWR_SAV) == 0) { 1111 /* 1112 * Station in power save mode; pass the frame 1113 * to the 802.11 layer and continue. We'll get 1114 * the frame back when the time is right. 1115 */ 1116 ieee80211_pwrsave(ic, ni, m); 1117 goto reclaim; 1118 } 1119 /* calculate priority so we can find the tx queue */ 1120 if (ieee80211_classify(ic, m, ni)) { 1121 DPRINTF(sc, ATH_DEBUG_XMIT, 1122 "%s: discard, classification failure\n", 1123 __func__); 1124 goto bad; 1125 } 1126 ifp->if_opackets++; 1127 BPF_MTAP(ifp, m); 1128 /* 1129 * Encapsulate the packet in prep for transmission. 1130 */ 1131 m = ieee80211_encap(ic, m, ni); 1132 if (m == NULL) { 1133 DPRINTF(sc, ATH_DEBUG_ANY, 1134 "%s: encapsulation failure\n", 1135 __func__); 1136 sc->sc_stats.ast_tx_encap++; 1137 goto bad; 1138 } 1139 } else { 1140 /* 1141 * Hack! The referenced node pointer is in the 1142 * rcvif field of the packet header. This is 1143 * placed there by ieee80211_mgmt_output because 1144 * we need to hold the reference with the frame 1145 * and there's no other way (other than packet 1146 * tags which we consider too expensive to use) 1147 * to pass it along. 1148 */ 1149 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1150 m->m_pkthdr.rcvif = NULL; 1151 1152 wh = mtod(m, struct ieee80211_frame *); 1153 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1154 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1155 /* fill time stamp */ 1156 u_int64_t tsf; 1157 u_int32_t *tstamp; 1158 1159 tsf = ath_hal_gettsf64(ah); 1160 /* XXX: adjust 100us delay to xmit */ 1161 tsf += 100; 1162 tstamp = (u_int32_t *)&wh[1]; 1163 tstamp[0] = htole32(tsf & 0xffffffff); 1164 tstamp[1] = htole32(tsf >> 32); 1165 } 1166 sc->sc_stats.ast_tx_mgmt++; 1167 } 1168 1169 if (ath_tx_start(sc, ni, bf, m)) { 1170 bad: 1171 ifp->if_oerrors++; 1172 reclaim: 1173 ATH_TXBUF_LOCK(sc); 1174 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1175 ATH_TXBUF_UNLOCK(sc); 1176 if (ni != NULL) 1177 ieee80211_free_node(ni); 1178 continue; 1179 } 1180 1181 sc->sc_tx_timer = 5; 1182 ifp->if_timer = 1; 1183 } 1184} 1185 1186static int 1187ath_media_change(struct ifnet *ifp) 1188{ 1189#define IS_UP(ifp) \ 1190 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 1191 int error; 1192 1193 error = ieee80211_media_change(ifp); 1194 if (error == ENETRESET) { 1195 if (IS_UP(ifp)) 1196 ath_init(ifp); /* XXX lose error */ 1197 error = 0; 1198 } 1199 return error; 1200#undef IS_UP 1201} 1202 1203#ifdef AR_DEBUG 1204static void 1205ath_keyprint(const char *tag, u_int ix, 1206 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1207{ 1208 static const char *ciphers[] = { 1209 "WEP", 1210 "AES-OCB", 1211 "AES-CCM", 1212 "CKIP", 1213 "TKIP", 1214 "CLR", 1215 }; 1216 int i, n; 1217 1218 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1219 for (i = 0, n = hk->kv_len; i < n; i++) 1220 printf("%02x", hk->kv_val[i]); 1221 printf(" mac %s", ether_sprintf(mac)); 1222 if (hk->kv_type == HAL_CIPHER_TKIP) { 1223 printf(" mic "); 1224 for (i = 0; i < sizeof(hk->kv_mic); i++) 1225 printf("%02x", hk->kv_mic[i]); 1226 } 1227 printf("\n"); 1228} 1229#endif 1230 1231/* 1232 * Set a TKIP key into the hardware. This handles the 1233 * potential distribution of key state to multiple key 1234 * cache slots for TKIP. 1235 */ 1236static int 1237ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1238 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1239{ 1240#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1241 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1242 struct ath_hal *ah = sc->sc_ah; 1243 1244 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1245 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1246 KASSERT(sc->sc_splitmic, ("key cache !split")); 1247 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1248 /* 1249 * TX key goes at first index, RX key at +32. 1250 * The hal handles the MIC keys at index+64. 1251 */ 1252 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1253 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1254 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1255 return 0; 1256 1257 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1258 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1259 /* XXX delete tx key on failure? */ 1260 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1261 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1262 /* 1263 * TX/RX key goes at first index. 1264 * The hal handles the MIC keys are index+64. 1265 */ 1266 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID, 1267 ("group key at index %u", k->wk_keyix)); 1268 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1269 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1270 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1271 return ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid); 1272 } 1273 /* XXX key w/o xmit/recv; need this for compression? */ 1274 return 0; 1275#undef IEEE80211_KEY_XR 1276} 1277 1278/* 1279 * Set a net80211 key into the hardware. This handles the 1280 * potential distribution of key state to multiple key 1281 * cache slots for TKIP with hardware MIC support. 1282 */ 1283static int 1284ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1285 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1286{ 1287#define N(a) (sizeof(a)/sizeof(a[0])) 1288 static const u_int8_t ciphermap[] = { 1289 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1290 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1291 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1292 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1293 (u_int8_t) -1, /* 4 is not allocated */ 1294 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1295 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1296 }; 1297 struct ath_hal *ah = sc->sc_ah; 1298 const struct ieee80211_cipher *cip = k->wk_cipher; 1299 HAL_KEYVAL hk; 1300 1301 memset(&hk, 0, sizeof(hk)); 1302 /* 1303 * Software crypto uses a "clear key" so non-crypto 1304 * state kept in the key cache are maintained and 1305 * so that rx frames have an entry to match. 1306 */ 1307 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1308 KASSERT(cip->ic_cipher < N(ciphermap), 1309 ("invalid cipher type %u", cip->ic_cipher)); 1310 hk.kv_type = ciphermap[cip->ic_cipher]; 1311 hk.kv_len = k->wk_keylen; 1312 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1313 } else 1314 hk.kv_type = HAL_CIPHER_CLR; 1315 1316 if (hk.kv_type == HAL_CIPHER_TKIP && 1317 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1318 sc->sc_splitmic) { 1319 return ath_keyset_tkip(sc, k, &hk, mac); 1320 } else { 1321 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1322 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1323 } 1324#undef N 1325} 1326 1327/* 1328 * Fill the hardware key cache with key entries. 1329 */ 1330static void 1331ath_initkeytable(struct ath_softc *sc) 1332{ 1333 struct ieee80211com *ic = &sc->sc_ic; 1334 struct ifnet *ifp = &sc->sc_if; 1335 struct ath_hal *ah = sc->sc_ah; 1336 const u_int8_t *bssid; 1337 int i; 1338 1339 /* XXX maybe should reset all keys when !PRIVACY */ 1340 if (ic->ic_state == IEEE80211_S_SCAN) 1341 bssid = ifp->if_broadcastaddr; 1342 else 1343 bssid = ic->ic_bss->ni_bssid; 1344 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1345 struct ieee80211_key *k = &ic->ic_nw_keys[i]; 1346 1347 if (k->wk_keylen == 0) { 1348 ath_hal_keyreset(ah, i); 1349 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: reset key %u\n", 1350 __func__, i); 1351 } else { 1352 ath_keyset(sc, k, bssid); 1353 } 1354 } 1355} 1356 1357/* 1358 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1359 * each key, one for decrypt/encrypt and the other for the MIC. 1360 */ 1361static u_int16_t 1362key_alloc_2pair(struct ath_softc *sc) 1363{ 1364#define N(a) (sizeof(a)/sizeof(a[0])) 1365 u_int i, keyix; 1366 1367 KASSERT(sc->sc_splitmic, ("key cache !split")); 1368 /* XXX could optimize */ 1369 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1370 u_int8_t b = sc->sc_keymap[i]; 1371 if (b != 0xff) { 1372 /* 1373 * One or more slots in this byte are free. 1374 */ 1375 keyix = i*NBBY; 1376 while (b & 1) { 1377 again: 1378 keyix++; 1379 b >>= 1; 1380 } 1381 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1382 if (isset(sc->sc_keymap, keyix+32) || 1383 isset(sc->sc_keymap, keyix+64) || 1384 isset(sc->sc_keymap, keyix+32+64)) { 1385 /* full pair unavailable */ 1386 /* XXX statistic */ 1387 if (keyix == (i+1)*NBBY) { 1388 /* no slots were appropriate, advance */ 1389 continue; 1390 } 1391 goto again; 1392 } 1393 setbit(sc->sc_keymap, keyix); 1394 setbit(sc->sc_keymap, keyix+64); 1395 setbit(sc->sc_keymap, keyix+32); 1396 setbit(sc->sc_keymap, keyix+32+64); 1397 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1398 "%s: key pair %u,%u %u,%u\n", 1399 __func__, keyix, keyix+64, 1400 keyix+32, keyix+32+64); 1401 return keyix; 1402 } 1403 } 1404 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1405 return IEEE80211_KEYIX_NONE; 1406#undef N 1407} 1408 1409/* 1410 * Allocate a single key cache slot. 1411 */ 1412static u_int16_t 1413key_alloc_single(struct ath_softc *sc) 1414{ 1415#define N(a) (sizeof(a)/sizeof(a[0])) 1416 u_int i, keyix; 1417 1418 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1419 for (i = 0; i < N(sc->sc_keymap); i++) { 1420 u_int8_t b = sc->sc_keymap[i]; 1421 if (b != 0xff) { 1422 /* 1423 * One or more slots are free. 1424 */ 1425 keyix = i*NBBY; 1426 while (b & 1) 1427 keyix++, b >>= 1; 1428 setbit(sc->sc_keymap, keyix); 1429 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1430 __func__, keyix); 1431 return keyix; 1432 } 1433 } 1434 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1435 return IEEE80211_KEYIX_NONE; 1436#undef N 1437} 1438 1439/* 1440 * Allocate one or more key cache slots for a uniacst key. The 1441 * key itself is needed only to identify the cipher. For hardware 1442 * TKIP with split cipher+MIC keys we allocate two key cache slot 1443 * pairs so that we can setup separate TX and RX MIC keys. Note 1444 * that the MIC key for a TKIP key at slot i is assumed by the 1445 * hardware to be at slot i+64. This limits TKIP keys to the first 1446 * 64 entries. 1447 */ 1448static int 1449ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k) 1450{ 1451 struct ath_softc *sc = ic->ic_ifp->if_softc; 1452 1453 /* 1454 * We allocate two pair for TKIP when using the h/w to do 1455 * the MIC. For everything else, including software crypto, 1456 * we allocate a single entry. Note that s/w crypto requires 1457 * a pass-through slot on the 5211 and 5212. The 5210 does 1458 * not support pass-through cache entries and we map all 1459 * those requests to slot 0. 1460 */ 1461 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1462 return key_alloc_single(sc); 1463 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1464 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1465 return key_alloc_2pair(sc); 1466 } else { 1467 return key_alloc_single(sc); 1468 } 1469} 1470 1471/* 1472 * Delete an entry in the key cache allocated by ath_key_alloc. 1473 */ 1474static int 1475ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1476{ 1477 struct ath_softc *sc = ic->ic_ifp->if_softc; 1478 struct ath_hal *ah = sc->sc_ah; 1479 const struct ieee80211_cipher *cip = k->wk_cipher; 1480 u_int keyix = k->wk_keyix; 1481 1482 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1483 1484 ath_hal_keyreset(ah, keyix); 1485 /* 1486 * Handle split tx/rx keying required for TKIP with h/w MIC. 1487 */ 1488 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1489 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1490 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1491 if (keyix >= IEEE80211_WEP_NKID) { 1492 /* 1493 * Don't touch keymap entries for global keys so 1494 * they are never considered for dynamic allocation. 1495 */ 1496 clrbit(sc->sc_keymap, keyix); 1497 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1498 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1499 sc->sc_splitmic) { 1500 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1501 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1502 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1503 } 1504 } 1505 return 1; 1506} 1507 1508/* 1509 * Set the key cache contents for the specified key. Key cache 1510 * slot(s) must already have been allocated by ath_key_alloc. 1511 */ 1512static int 1513ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1514 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1515{ 1516 struct ath_softc *sc = ic->ic_ifp->if_softc; 1517 1518 return ath_keyset(sc, k, mac); 1519} 1520 1521/* 1522 * Block/unblock tx+rx processing while a key change is done. 1523 * We assume the caller serializes key management operations 1524 * so we only need to worry about synchronization with other 1525 * uses that originate in the driver. 1526 */ 1527static void 1528ath_key_update_begin(struct ieee80211com *ic) 1529{ 1530 struct ifnet *ifp = ic->ic_ifp; 1531 struct ath_softc *sc = ifp->if_softc; 1532 1533 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1534#if 0 1535 tasklet_disable(&sc->sc_rxtq); 1536#endif 1537 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1538} 1539 1540static void 1541ath_key_update_end(struct ieee80211com *ic) 1542{ 1543 struct ifnet *ifp = ic->ic_ifp; 1544 struct ath_softc *sc = ifp->if_softc; 1545 1546 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1547 IF_UNLOCK(&ifp->if_snd); 1548#if 0 1549 tasklet_enable(&sc->sc_rxtq); 1550#endif 1551} 1552 1553/* 1554 * Calculate the receive filter according to the 1555 * operating mode and state: 1556 * 1557 * o always accept unicast, broadcast, and multicast traffic 1558 * o maintain current state of phy error reception (the hal 1559 * may enable phy error frames for noise immunity work) 1560 * o probe request frames are accepted only when operating in 1561 * hostap, adhoc, or monitor modes 1562 * o enable promiscuous mode according to the interface state 1563 * o accept beacons: 1564 * - when operating in adhoc mode so the 802.11 layer creates 1565 * node table entries for peers, 1566 * - when operating in station mode for collecting rssi data when 1567 * the station is otherwise quiet, or 1568 * - when scanning 1569 */ 1570static u_int32_t 1571ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1572{ 1573 struct ieee80211com *ic = &sc->sc_ic; 1574 struct ath_hal *ah = sc->sc_ah; 1575 struct ifnet *ifp = &sc->sc_if; 1576 u_int32_t rfilt; 1577 1578 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1579 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1580 if (ic->ic_opmode != IEEE80211_M_STA) 1581 rfilt |= HAL_RX_FILTER_PROBEREQ; 1582 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1583 (ifp->if_flags & IFF_PROMISC)) 1584 rfilt |= HAL_RX_FILTER_PROM; 1585 if (ic->ic_opmode == IEEE80211_M_STA || 1586 ic->ic_opmode == IEEE80211_M_IBSS || 1587 state == IEEE80211_S_SCAN) 1588 rfilt |= HAL_RX_FILTER_BEACON; 1589 return rfilt; 1590} 1591 1592static void 1593ath_mode_init(struct ath_softc *sc) 1594{ 1595 struct ieee80211com *ic = &sc->sc_ic; 1596 struct ath_hal *ah = sc->sc_ah; 1597 struct ifnet *ifp = &sc->sc_if; 1598 u_int32_t rfilt, mfilt[2], val; 1599 u_int8_t pos; 1600 struct ifmultiaddr *ifma; 1601 1602 /* configure rx filter */ 1603 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1604 ath_hal_setrxfilter(ah, rfilt); 1605 1606 /* configure operational mode */ 1607 ath_hal_setopmode(ah); 1608 1609 /* 1610 * Handle any link-level address change. Note that we only 1611 * need to force ic_myaddr; any other addresses are handled 1612 * as a byproduct of the ifnet code marking the interface 1613 * down then up. 1614 * 1615 * XXX should get from lladdr instead of arpcom but that's more work 1616 */ 1617 IEEE80211_ADDR_COPY(ic->ic_myaddr, IFP2AC(ifp)->ac_enaddr); 1618 ath_hal_setmac(ah, ic->ic_myaddr); 1619 1620 /* calculate and install multicast filter */ 1621 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1622 mfilt[0] = mfilt[1] = 0; 1623 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1624 caddr_t dl; 1625 1626 /* calculate XOR of eight 6bit values */ 1627 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1628 val = LE_READ_4(dl + 0); 1629 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1630 val = LE_READ_4(dl + 3); 1631 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1632 pos &= 0x3f; 1633 mfilt[pos / 32] |= (1 << (pos % 32)); 1634 } 1635 } else { 1636 mfilt[0] = mfilt[1] = ~0; 1637 } 1638 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1639 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1640 __func__, rfilt, mfilt[0], mfilt[1]); 1641} 1642 1643/* 1644 * Set the slot time based on the current setting. 1645 */ 1646static void 1647ath_setslottime(struct ath_softc *sc) 1648{ 1649 struct ieee80211com *ic = &sc->sc_ic; 1650 struct ath_hal *ah = sc->sc_ah; 1651 1652 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1653 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1654 else 1655 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1656 sc->sc_updateslot = OK; 1657} 1658 1659/* 1660 * Callback from the 802.11 layer to update the 1661 * slot time based on the current setting. 1662 */ 1663static void 1664ath_updateslot(struct ifnet *ifp) 1665{ 1666 struct ath_softc *sc = ifp->if_softc; 1667 struct ieee80211com *ic = &sc->sc_ic; 1668 1669 /* 1670 * When not coordinating the BSS, change the hardware 1671 * immediately. For other operation we defer the change 1672 * until beacon updates have propagated to the stations. 1673 */ 1674 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1675 sc->sc_updateslot = UPDATE; 1676 else 1677 ath_setslottime(sc); 1678} 1679 1680/* 1681 * Setup a h/w transmit queue for beacons. 1682 */ 1683static int 1684ath_beaconq_setup(struct ath_hal *ah) 1685{ 1686 HAL_TXQ_INFO qi; 1687 1688 memset(&qi, 0, sizeof(qi)); 1689 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1690 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1691 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1692 /* NB: don't enable any interrupts */ 1693 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1694} 1695 1696/* 1697 * Allocate and setup an initial beacon frame. 1698 */ 1699static int 1700ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1701{ 1702 struct ieee80211com *ic = ni->ni_ic; 1703 struct ath_buf *bf; 1704 struct mbuf *m; 1705 int error; 1706 1707 bf = STAILQ_FIRST(&sc->sc_bbuf); 1708 if (bf == NULL) { 1709 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1710 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1711 return ENOMEM; /* XXX */ 1712 } 1713 /* 1714 * NB: the beacon data buffer must be 32-bit aligned; 1715 * we assume the mbuf routines will return us something 1716 * with this alignment (perhaps should assert). 1717 */ 1718 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1719 if (m == NULL) { 1720 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1721 __func__); 1722 sc->sc_stats.ast_be_nombuf++; 1723 return ENOMEM; 1724 } 1725 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1726 bf->bf_segs, &bf->bf_nseg, 1727 BUS_DMA_NOWAIT); 1728 if (error == 0) { 1729 bf->bf_m = m; 1730 bf->bf_node = ieee80211_ref_node(ni); 1731 } else { 1732 m_freem(m); 1733 } 1734 return error; 1735} 1736 1737/* 1738 * Setup the beacon frame for transmit. 1739 */ 1740static void 1741ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1742{ 1743#define USE_SHPREAMBLE(_ic) \ 1744 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1745 == IEEE80211_F_SHPREAMBLE) 1746 struct ieee80211_node *ni = bf->bf_node; 1747 struct ieee80211com *ic = ni->ni_ic; 1748 struct mbuf *m = bf->bf_m; 1749 struct ath_hal *ah = sc->sc_ah; 1750 struct ath_node *an = ATH_NODE(ni); 1751 struct ath_desc *ds; 1752 int flags, antenna; 1753 u_int8_t rate; 1754 1755 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1756 __func__, m, m->m_len); 1757 1758 /* setup descriptors */ 1759 ds = bf->bf_desc; 1760 1761 flags = HAL_TXDESC_NOACK; 1762 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1763 ds->ds_link = bf->bf_daddr; /* self-linked */ 1764 flags |= HAL_TXDESC_VEOL; 1765 /* 1766 * Let hardware handle antenna switching. 1767 */ 1768 antenna = 0; 1769 } else { 1770 ds->ds_link = 0; 1771 /* 1772 * Switch antenna every 4 beacons. 1773 * XXX assumes two antenna 1774 */ 1775 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 1776 } 1777 1778 KASSERT(bf->bf_nseg == 1, 1779 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 1780 ds->ds_data = bf->bf_segs[0].ds_addr; 1781 /* 1782 * Calculate rate code. 1783 * XXX everything at min xmit rate 1784 */ 1785 if (USE_SHPREAMBLE(ic)) 1786 rate = an->an_tx_mgtratesp; 1787 else 1788 rate = an->an_tx_mgtrate; 1789 ath_hal_setuptxdesc(ah, ds 1790 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 1791 , sizeof(struct ieee80211_frame)/* header length */ 1792 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1793 , ni->ni_txpower /* txpower XXX */ 1794 , rate, 1 /* series 0 rate/tries */ 1795 , HAL_TXKEYIX_INVALID /* no encryption */ 1796 , antenna /* antenna mode */ 1797 , flags /* no ack, veol for beacons */ 1798 , 0 /* rts/cts rate */ 1799 , 0 /* rts/cts duration */ 1800 ); 1801 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1802 ath_hal_filltxdesc(ah, ds 1803 , roundup(m->m_len, 4) /* buffer length */ 1804 , AH_TRUE /* first segment */ 1805 , AH_TRUE /* last segment */ 1806 , ds /* first descriptor */ 1807 ); 1808#undef USE_SHPREAMBLE 1809} 1810 1811/* 1812 * Transmit a beacon frame at SWBA. Dynamic updates to the 1813 * frame contents are done as needed and the slot time is 1814 * also adjusted based on current state. 1815 */ 1816static void 1817ath_beacon_proc(void *arg, int pending) 1818{ 1819 struct ath_softc *sc = arg; 1820 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 1821 struct ieee80211_node *ni = bf->bf_node; 1822 struct ieee80211com *ic = ni->ni_ic; 1823 struct ath_hal *ah = sc->sc_ah; 1824 struct mbuf *m; 1825 int ncabq, error, otherant; 1826 1827 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 1828 __func__, pending); 1829 1830 if (ic->ic_opmode == IEEE80211_M_STA || 1831 ic->ic_opmode == IEEE80211_M_MONITOR || 1832 bf == NULL || bf->bf_m == NULL) { 1833 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 1834 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 1835 return; 1836 } 1837 /* 1838 * Check if the previous beacon has gone out. If 1839 * not don't don't try to post another, skip this 1840 * period and wait for the next. Missed beacons 1841 * indicate a problem and should not occur. If we 1842 * miss too many consecutive beacons reset the device. 1843 */ 1844 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 1845 sc->sc_bmisscount++; 1846 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 1847 "%s: missed %u consecutive beacons\n", 1848 __func__, sc->sc_bmisscount); 1849 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 1850 taskqueue_enqueue(taskqueue_swi, &sc->sc_bstucktask); 1851 return; 1852 } 1853 if (sc->sc_bmisscount != 0) { 1854 DPRINTF(sc, ATH_DEBUG_BEACON, 1855 "%s: resume beacon xmit after %u misses\n", 1856 __func__, sc->sc_bmisscount); 1857 sc->sc_bmisscount = 0; 1858 } 1859 1860 /* 1861 * Update dynamic beacon contents. If this returns 1862 * non-zero then we need to remap the memory because 1863 * the beacon frame changed size (probably because 1864 * of the TIM bitmap). 1865 */ 1866 m = bf->bf_m; 1867 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 1868 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 1869 /* XXX too conservative? */ 1870 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1871 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1872 bf->bf_segs, &bf->bf_nseg, 1873 BUS_DMA_NOWAIT); 1874 if (error != 0) { 1875 if_printf(ic->ic_ifp, 1876 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 1877 __func__, error); 1878 return; 1879 } 1880 } 1881 1882 /* 1883 * Handle slot time change when a non-ERP station joins/leaves 1884 * an 11g network. The 802.11 layer notifies us via callback, 1885 * we mark updateslot, then wait one beacon before effecting 1886 * the change. This gives associated stations at least one 1887 * beacon interval to note the state change. 1888 */ 1889 /* XXX locking */ 1890 if (sc->sc_updateslot == UPDATE) 1891 sc->sc_updateslot = COMMIT; /* commit next beacon */ 1892 else if (sc->sc_updateslot == COMMIT) 1893 ath_setslottime(sc); /* commit change to h/w */ 1894 1895 /* 1896 * Check recent per-antenna transmit statistics and flip 1897 * the default antenna if noticeably more frames went out 1898 * on the non-default antenna. 1899 * XXX assumes 2 anntenae 1900 */ 1901 otherant = sc->sc_defant & 1 ? 2 : 1; 1902 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 1903 ath_setdefantenna(sc, otherant); 1904 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 1905 1906 /* 1907 * Construct tx descriptor. 1908 */ 1909 ath_beacon_setup(sc, bf); 1910 1911 /* 1912 * Stop any current dma and put the new frame on the queue. 1913 * This should never fail since we check above that no frames 1914 * are still pending on the queue. 1915 */ 1916 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1917 DPRINTF(sc, ATH_DEBUG_ANY, 1918 "%s: beacon queue %u did not stop?\n", 1919 __func__, sc->sc_bhalq); 1920 } 1921 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1922 1923 /* 1924 * Enable the CAB queue before the beacon queue to 1925 * insure cab frames are triggered by this beacon. 1926 */ 1927 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 1928 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 1929 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1930 ath_hal_txstart(ah, sc->sc_bhalq); 1931 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 1932 "%s: TXDP[%u] = %p (%p)\n", __func__, 1933 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 1934 1935 sc->sc_stats.ast_be_xmit++; 1936} 1937 1938/* 1939 * Reset the hardware after detecting beacons have stopped. 1940 */ 1941static void 1942ath_bstuck_proc(void *arg, int pending) 1943{ 1944 struct ath_softc *sc = arg; 1945 struct ifnet *ifp = &sc->sc_if; 1946 1947 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 1948 sc->sc_bmisscount); 1949 ath_reset(ifp); 1950} 1951 1952/* 1953 * Reclaim beacon resources. 1954 */ 1955static void 1956ath_beacon_free(struct ath_softc *sc) 1957{ 1958 struct ath_buf *bf; 1959 1960 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 1961 if (bf->bf_m != NULL) { 1962 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1963 m_freem(bf->bf_m); 1964 bf->bf_m = NULL; 1965 } 1966 if (bf->bf_node != NULL) { 1967 ieee80211_free_node(bf->bf_node); 1968 bf->bf_node = NULL; 1969 } 1970 } 1971} 1972 1973/* 1974 * Configure the beacon and sleep timers. 1975 * 1976 * When operating as an AP this resets the TSF and sets 1977 * up the hardware to notify us when we need to issue beacons. 1978 * 1979 * When operating in station mode this sets up the beacon 1980 * timers according to the timestamp of the last received 1981 * beacon and the current TSF, configures PCF and DTIM 1982 * handling, programs the sleep registers so the hardware 1983 * will wakeup in time to receive beacons, and configures 1984 * the beacon miss handling so we'll receive a BMISS 1985 * interrupt when we stop seeing beacons from the AP 1986 * we've associated with. 1987 */ 1988static void 1989ath_beacon_config(struct ath_softc *sc) 1990{ 1991 struct ath_hal *ah = sc->sc_ah; 1992 struct ieee80211com *ic = &sc->sc_ic; 1993 struct ieee80211_node *ni = ic->ic_bss; 1994 u_int32_t nexttbtt, intval; 1995 1996 nexttbtt = (LE_READ_4(ni->ni_tstamp.data + 4) << 22) | 1997 (LE_READ_4(ni->ni_tstamp.data) >> 10); 1998 intval = ni->ni_intval & HAL_BEACON_PERIOD; 1999 if (nexttbtt == 0) /* e.g. for ap mode */ 2000 nexttbtt = intval; 2001 else if (intval) /* NB: can be 0 for monitor mode */ 2002 nexttbtt = roundup(nexttbtt, intval); 2003 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2004 __func__, nexttbtt, intval, ni->ni_intval); 2005 if (ic->ic_opmode == IEEE80211_M_STA) { 2006 HAL_BEACON_STATE bs; 2007 2008 /* NB: no PCF support right now */ 2009 memset(&bs, 0, sizeof(bs)); 2010 bs.bs_intval = intval; 2011 bs.bs_nexttbtt = nexttbtt; 2012 bs.bs_dtimperiod = bs.bs_intval; 2013 bs.bs_nextdtim = nexttbtt; 2014 /* 2015 * The 802.11 layer records the offset to the DTIM 2016 * bitmap while receiving beacons; use it here to 2017 * enable h/w detection of our AID being marked in 2018 * the bitmap vector (to indicate frames for us are 2019 * pending at the AP). 2020 */ 2021 bs.bs_timoffset = ni->ni_timoff; 2022 /* 2023 * Calculate the number of consecutive beacons to miss 2024 * before taking a BMISS interrupt. The configuration 2025 * is specified in ms, so we need to convert that to 2026 * TU's and then calculate based on the beacon interval. 2027 * Note that we clamp the result to at most 10 beacons. 2028 */ 2029 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2030 if (bs.bs_bmissthreshold > 10) 2031 bs.bs_bmissthreshold = 10; 2032 else if (bs.bs_bmissthreshold <= 0) 2033 bs.bs_bmissthreshold = 1; 2034 2035 /* 2036 * Calculate sleep duration. The configuration is 2037 * given in ms. We insure a multiple of the beacon 2038 * period is used. Also, if the sleep duration is 2039 * greater than the DTIM period then it makes senses 2040 * to make it a multiple of that. 2041 * 2042 * XXX fixed at 100ms 2043 */ 2044 bs.bs_sleepduration = 2045 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2046 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2047 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2048 2049 DPRINTF(sc, ATH_DEBUG_BEACON, 2050 "%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2051 , __func__ 2052 , bs.bs_intval 2053 , bs.bs_nexttbtt 2054 , bs.bs_dtimperiod 2055 , bs.bs_nextdtim 2056 , bs.bs_bmissthreshold 2057 , bs.bs_sleepduration 2058 , bs.bs_cfpperiod 2059 , bs.bs_cfpmaxduration 2060 , bs.bs_cfpnext 2061 , bs.bs_timoffset 2062 ); 2063 ath_hal_intrset(ah, 0); 2064 ath_hal_beacontimers(ah, &bs); 2065 sc->sc_imask |= HAL_INT_BMISS; 2066 ath_hal_intrset(ah, sc->sc_imask); 2067 } else { 2068 ath_hal_intrset(ah, 0); 2069 if (nexttbtt == intval) 2070 intval |= HAL_BEACON_RESET_TSF; 2071 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2072 /* 2073 * In IBSS mode enable the beacon timers but only 2074 * enable SWBA interrupts if we need to manually 2075 * prepare beacon frames. Otherwise we use a 2076 * self-linked tx descriptor and let the hardware 2077 * deal with things. 2078 */ 2079 intval |= HAL_BEACON_ENA; 2080 if (!sc->sc_hasveol) 2081 sc->sc_imask |= HAL_INT_SWBA; 2082 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2083 /* 2084 * In AP mode we enable the beacon timers and 2085 * SWBA interrupts to prepare beacon frames. 2086 */ 2087 intval |= HAL_BEACON_ENA; 2088 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2089 } 2090 ath_hal_beaconinit(ah, nexttbtt, intval); 2091 sc->sc_bmisscount = 0; 2092 ath_hal_intrset(ah, sc->sc_imask); 2093 /* 2094 * When using a self-linked beacon descriptor in 2095 * ibss mode load it once here. 2096 */ 2097 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2098 ath_beacon_proc(sc, 0); 2099 } 2100} 2101 2102static void 2103ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2104{ 2105 bus_addr_t *paddr = (bus_addr_t*) arg; 2106 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2107 *paddr = segs->ds_addr; 2108} 2109 2110static int 2111ath_descdma_setup(struct ath_softc *sc, 2112 struct ath_descdma *dd, ath_bufhead *head, 2113 const char *name, int nbuf, int ndesc) 2114{ 2115#define DS2PHYS(_dd, _ds) \ 2116 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2117 struct ifnet *ifp = &sc->sc_if; 2118 struct ath_desc *ds; 2119 struct ath_buf *bf; 2120 int i, bsize, error; 2121 2122 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2123 __func__, name, nbuf, ndesc); 2124 2125 dd->dd_name = name; 2126 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2127 2128 /* 2129 * Setup DMA descriptor area. 2130 */ 2131 error = bus_dma_tag_create(NULL, /* parent */ 2132 PAGE_SIZE, 0, /* alignment, bounds */ 2133 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2134 BUS_SPACE_MAXADDR, /* highaddr */ 2135 NULL, NULL, /* filter, filterarg */ 2136 dd->dd_desc_len, /* maxsize */ 2137 1, /* nsegments */ 2138 BUS_SPACE_MAXADDR, /* maxsegsize */ 2139 BUS_DMA_ALLOCNOW, /* flags */ 2140 NULL, /* lockfunc */ 2141 NULL, /* lockarg */ 2142 &dd->dd_dmat); 2143 if (error != 0) { 2144 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2145 return error; 2146 } 2147 2148 /* allocate descriptors */ 2149 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2150 if (error != 0) { 2151 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2152 "error %u\n", dd->dd_name, error); 2153 goto fail0; 2154 } 2155 2156 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2157 BUS_DMA_NOWAIT, &dd->dd_dmamap); 2158 if (error != 0) { 2159 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2160 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2161 goto fail1; 2162 } 2163 2164 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2165 dd->dd_desc, dd->dd_desc_len, 2166 ath_load_cb, &dd->dd_desc_paddr, 2167 BUS_DMA_NOWAIT); 2168 if (error != 0) { 2169 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2170 dd->dd_name, error); 2171 goto fail2; 2172 } 2173 2174 ds = dd->dd_desc; 2175 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2176 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2177 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2178 2179 /* allocate rx buffers */ 2180 bsize = sizeof(struct ath_buf) * nbuf; 2181 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2182 if (bf == NULL) { 2183 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2184 dd->dd_name, bsize); 2185 goto fail3; 2186 } 2187 dd->dd_bufptr = bf; 2188 2189 STAILQ_INIT(head); 2190 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2191 bf->bf_desc = ds; 2192 bf->bf_daddr = DS2PHYS(dd, ds); 2193 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2194 &bf->bf_dmamap); 2195 if (error != 0) { 2196 if_printf(ifp, "unable to create dmamap for %s " 2197 "buffer %u, error %u\n", dd->dd_name, i, error); 2198 ath_descdma_cleanup(sc, dd, head); 2199 return error; 2200 } 2201 STAILQ_INSERT_TAIL(head, bf, bf_list); 2202 } 2203 return 0; 2204fail3: 2205 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2206fail2: 2207 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2208fail1: 2209 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2210fail0: 2211 bus_dma_tag_destroy(dd->dd_dmat); 2212 memset(dd, 0, sizeof(*dd)); 2213 return error; 2214#undef DS2PHYS 2215} 2216 2217static void 2218ath_descdma_cleanup(struct ath_softc *sc, 2219 struct ath_descdma *dd, ath_bufhead *head) 2220{ 2221 struct ath_buf *bf; 2222 struct ieee80211_node *ni; 2223 2224 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2225 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2226 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2227 bus_dma_tag_destroy(dd->dd_dmat); 2228 2229 STAILQ_FOREACH(bf, head, bf_list) { 2230 if (bf->bf_m) { 2231 m_freem(bf->bf_m); 2232 bf->bf_m = NULL; 2233 } 2234 if (bf->bf_dmamap != NULL) { 2235 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2236 bf->bf_dmamap = NULL; 2237 } 2238 ni = bf->bf_node; 2239 bf->bf_node = NULL; 2240 if (ni != NULL) { 2241 /* 2242 * Reclaim node reference. 2243 */ 2244 ieee80211_free_node(ni); 2245 } 2246 } 2247 2248 STAILQ_INIT(head); 2249 free(dd->dd_bufptr, M_ATHDEV); 2250 memset(dd, 0, sizeof(*dd)); 2251} 2252 2253static int 2254ath_desc_alloc(struct ath_softc *sc) 2255{ 2256 int error; 2257 2258 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2259 "rx", ATH_RXBUF, 1); 2260 if (error != 0) 2261 return error; 2262 2263 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2264 "tx", ATH_TXBUF, ATH_TXDESC); 2265 if (error != 0) { 2266 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2267 return error; 2268 } 2269 2270 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2271 "beacon", 1, 1); 2272 if (error != 0) { 2273 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2274 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2275 return error; 2276 } 2277 return 0; 2278} 2279 2280static void 2281ath_desc_free(struct ath_softc *sc) 2282{ 2283 2284 if (sc->sc_bdma.dd_desc_len != 0) 2285 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2286 if (sc->sc_txdma.dd_desc_len != 0) 2287 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2288 if (sc->sc_rxdma.dd_desc_len != 0) 2289 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2290} 2291 2292static struct ieee80211_node * 2293ath_node_alloc(struct ieee80211_node_table *nt) 2294{ 2295 struct ieee80211com *ic = nt->nt_ic; 2296 struct ath_softc *sc = ic->ic_ifp->if_softc; 2297 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2298 struct ath_node *an; 2299 2300 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2301 if (an == NULL) { 2302 /* XXX stat+msg */ 2303 return NULL; 2304 } 2305 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2306 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2307 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2308 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2309 ath_rate_node_init(sc, an); 2310 2311 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2312 return &an->an_node; 2313} 2314 2315static void 2316ath_node_free(struct ieee80211_node *ni) 2317{ 2318 struct ieee80211com *ic = ni->ni_ic; 2319 struct ath_softc *sc = ic->ic_ifp->if_softc; 2320 2321 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2322 2323 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2324 sc->sc_node_free(ni); 2325} 2326 2327static u_int8_t 2328ath_node_getrssi(const struct ieee80211_node *ni) 2329{ 2330#define HAL_EP_RND(x, mul) \ 2331 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2332 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2333 int32_t rssi; 2334 2335 /* 2336 * When only one frame is received there will be no state in 2337 * avgrssi so fallback on the value recorded by the 802.11 layer. 2338 */ 2339 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2340 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2341 else 2342 rssi = ni->ni_rssi; 2343 /* NB: theoretically we shouldn't need this, but be paranoid */ 2344 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2345#undef HAL_EP_RND 2346} 2347 2348static int 2349ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2350{ 2351 struct ath_hal *ah = sc->sc_ah; 2352 int error; 2353 struct mbuf *m; 2354 struct ath_desc *ds; 2355 2356 m = bf->bf_m; 2357 if (m == NULL) { 2358 /* 2359 * NB: by assigning a page to the rx dma buffer we 2360 * implicitly satisfy the Atheros requirement that 2361 * this buffer be cache-line-aligned and sized to be 2362 * multiple of the cache line size. Not doing this 2363 * causes weird stuff to happen (for the 5210 at least). 2364 */ 2365 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2366 if (m == NULL) { 2367 DPRINTF(sc, ATH_DEBUG_ANY, 2368 "%s: no mbuf/cluster\n", __func__); 2369 sc->sc_stats.ast_rx_nombuf++; 2370 return ENOMEM; 2371 } 2372 bf->bf_m = m; 2373 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2374 2375 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 2376 bf->bf_dmamap, m, 2377 bf->bf_segs, &bf->bf_nseg, 2378 BUS_DMA_NOWAIT); 2379 if (error != 0) { 2380 DPRINTF(sc, ATH_DEBUG_ANY, 2381 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 2382 __func__, error); 2383 sc->sc_stats.ast_rx_busdma++; 2384 return error; 2385 } 2386 KASSERT(bf->bf_nseg == 1, 2387 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2388 } 2389 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 2390 2391 /* 2392 * Setup descriptors. For receive we always terminate 2393 * the descriptor list with a self-linked entry so we'll 2394 * not get overrun under high load (as can happen with a 2395 * 5212 when ANI processing enables PHY error frames). 2396 * 2397 * To insure the last descriptor is self-linked we create 2398 * each descriptor as self-linked and add it to the end. As 2399 * each additional descriptor is added the previous self-linked 2400 * entry is ``fixed'' naturally. This should be safe even 2401 * if DMA is happening. When processing RX interrupts we 2402 * never remove/process the last, self-linked, entry on the 2403 * descriptor list. This insures the hardware always has 2404 * someplace to write a new frame. 2405 */ 2406 ds = bf->bf_desc; 2407 ds->ds_link = bf->bf_daddr; /* link to self */ 2408 ds->ds_data = bf->bf_segs[0].ds_addr; 2409 ath_hal_setuprxdesc(ah, ds 2410 , m->m_len /* buffer size */ 2411 , 0 2412 ); 2413 2414 if (sc->sc_rxlink != NULL) 2415 *sc->sc_rxlink = bf->bf_daddr; 2416 sc->sc_rxlink = &ds->ds_link; 2417 return 0; 2418} 2419 2420/* 2421 * Extend 15-bit time stamp from rx descriptor to 2422 * a full 64-bit TSF using the current h/w TSF. 2423 */ 2424static __inline u_int64_t 2425ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp) 2426{ 2427 u_int64_t tsf; 2428 2429 tsf = ath_hal_gettsf64(ah); 2430 if ((tsf & 0x7fff) < rstamp) 2431 tsf -= 0x8000; 2432 return ((tsf &~ 0x7fff) | rstamp); 2433} 2434 2435/* 2436 * Intercept management frames to collect beacon rssi data 2437 * and to do ibss merges. 2438 */ 2439static void 2440ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2441 struct ieee80211_node *ni, 2442 int subtype, int rssi, u_int32_t rstamp) 2443{ 2444 struct ath_softc *sc = ic->ic_ifp->if_softc; 2445 2446 /* 2447 * Call up first so subsequent work can use information 2448 * potentially stored in the node (e.g. for ibss merge). 2449 */ 2450 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2451 switch (subtype) { 2452 case IEEE80211_FC0_SUBTYPE_BEACON: 2453 /* update rssi statistics for use by the hal */ 2454 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2455 /* fall thru... */ 2456 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2457 if (ic->ic_opmode == IEEE80211_M_IBSS && 2458 ic->ic_state == IEEE80211_S_RUN) { 2459 u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp); 2460 /* 2461 * Handle ibss merge as needed; check the tsf on the 2462 * frame before attempting the merge. The 802.11 spec 2463 * says the station should change it's bssid to match 2464 * the oldest station with the same ssid, where oldest 2465 * is determined by the tsf. Note that hardware 2466 * reconfiguration happens through callback to 2467 * ath_newstate as the state machine will go from 2468 * RUN -> RUN when this happens. 2469 */ 2470 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2471 DPRINTF(sc, ATH_DEBUG_STATE, 2472 "ibss merge, rstamp %u tsf %ju " 2473 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2474 (uintmax_t)ni->ni_tstamp.tsf); 2475 (void) ieee80211_ibss_merge(ic, ni); 2476 } 2477 } 2478 break; 2479 } 2480} 2481 2482/* 2483 * Set the default antenna. 2484 */ 2485static void 2486ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2487{ 2488 struct ath_hal *ah = sc->sc_ah; 2489 2490 /* XXX block beacon interrupts */ 2491 ath_hal_setdefantenna(ah, antenna); 2492 if (sc->sc_defant != antenna) 2493 sc->sc_stats.ast_ant_defswitch++; 2494 sc->sc_defant = antenna; 2495 sc->sc_rxotherant = 0; 2496} 2497 2498static void 2499ath_rx_proc(void *arg, int npending) 2500{ 2501#define PA2DESC(_sc, _pa) \ 2502 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2503 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2504 struct ath_softc *sc = arg; 2505 struct ath_buf *bf; 2506 struct ieee80211com *ic = &sc->sc_ic; 2507 struct ifnet *ifp = &sc->sc_if; 2508 struct ath_hal *ah = sc->sc_ah; 2509 struct ath_desc *ds; 2510 struct mbuf *m; 2511 struct ieee80211_node *ni; 2512 struct ath_node *an; 2513 int len; 2514 u_int phyerr; 2515 HAL_STATUS status; 2516 2517 NET_LOCK_GIANT(); /* XXX */ 2518 2519 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2520 do { 2521 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2522 if (bf == NULL) { /* NB: shouldn't happen */ 2523 if_printf(ifp, "%s: no buffer!\n", __func__); 2524 break; 2525 } 2526 ds = bf->bf_desc; 2527 if (ds->ds_link == bf->bf_daddr) { 2528 /* NB: never process the self-linked entry at the end */ 2529 break; 2530 } 2531 m = bf->bf_m; 2532 if (m == NULL) { /* NB: shouldn't happen */ 2533 if_printf(ifp, "%s: no mbuf!\n", __func__); 2534 continue; 2535 } 2536 /* XXX sync descriptor memory */ 2537 /* 2538 * Must provide the virtual address of the current 2539 * descriptor, the physical address, and the virtual 2540 * address of the next descriptor in the h/w chain. 2541 * This allows the HAL to look ahead to see if the 2542 * hardware is done with a descriptor by checking the 2543 * done bit in the following descriptor and the address 2544 * of the current descriptor the DMA engine is working 2545 * on. All this is necessary because of our use of 2546 * a self-linked list to avoid rx overruns. 2547 */ 2548 status = ath_hal_rxprocdesc(ah, ds, 2549 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2550#ifdef AR_DEBUG 2551 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2552 ath_printrxbuf(bf, status == HAL_OK); 2553#endif 2554 if (status == HAL_EINPROGRESS) 2555 break; 2556 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2557 if (ds->ds_rxstat.rs_more) { 2558 /* 2559 * Frame spans multiple descriptors; this 2560 * cannot happen yet as we don't support 2561 * jumbograms. If not in monitor mode, 2562 * discard the frame. 2563 */ 2564 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2565 sc->sc_stats.ast_rx_toobig++; 2566 goto rx_next; 2567 } 2568 /* fall thru for monitor mode handling... */ 2569 } else if (ds->ds_rxstat.rs_status != 0) { 2570 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2571 sc->sc_stats.ast_rx_crcerr++; 2572 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2573 sc->sc_stats.ast_rx_fifoerr++; 2574 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2575 sc->sc_stats.ast_rx_phyerr++; 2576 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2577 sc->sc_stats.ast_rx_phy[phyerr]++; 2578 goto rx_next; 2579 } 2580 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2581 /* 2582 * Decrypt error. If the error occurred 2583 * because there was no hardware key, then 2584 * let the frame through so the upper layers 2585 * can process it. This is necessary for 5210 2586 * parts which have no way to setup a ``clear'' 2587 * key cache entry. 2588 * 2589 * XXX do key cache faulting 2590 */ 2591 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2592 goto rx_accept; 2593 sc->sc_stats.ast_rx_badcrypt++; 2594 } 2595 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2596 sc->sc_stats.ast_rx_badmic++; 2597 /* 2598 * Do minimal work required to hand off 2599 * the 802.11 header for notifcation. 2600 */ 2601 /* XXX frag's and qos frames */ 2602 len = ds->ds_rxstat.rs_datalen; 2603 if (len >= sizeof (struct ieee80211_frame)) { 2604 bus_dmamap_sync(sc->sc_dmat, 2605 bf->bf_dmamap, 2606 BUS_DMASYNC_POSTREAD); 2607 ieee80211_notify_michael_failure(ic, 2608 mtod(m, struct ieee80211_frame *), 2609 sc->sc_splitmic ? 2610 ds->ds_rxstat.rs_keyix-32 : 2611 ds->ds_rxstat.rs_keyix 2612 ); 2613 } 2614 } 2615 ifp->if_ierrors++; 2616 /* 2617 * Reject error frames, we normally don't want 2618 * to see them in monitor mode (in monitor mode 2619 * allow through packets that have crypto problems). 2620 */ 2621 if ((ds->ds_rxstat.rs_status &~ 2622 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2623 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2624 goto rx_next; 2625 } 2626rx_accept: 2627 /* 2628 * Sync and unmap the frame. At this point we're 2629 * committed to passing the mbuf somewhere so clear 2630 * bf_m; this means a new sk_buff must be allocated 2631 * when the rx descriptor is setup again to receive 2632 * another frame. 2633 */ 2634 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2635 BUS_DMASYNC_POSTREAD); 2636 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2637 bf->bf_m = NULL; 2638 2639 m->m_pkthdr.rcvif = ifp; 2640 len = ds->ds_rxstat.rs_datalen; 2641 m->m_pkthdr.len = m->m_len = len; 2642 2643 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2644 2645 if (sc->sc_drvbpf) { 2646 u_int8_t rix; 2647 2648 /* 2649 * Discard anything shorter than an ack or cts. 2650 */ 2651 if (len < IEEE80211_ACK_LEN) { 2652 DPRINTF(sc, ATH_DEBUG_RECV, 2653 "%s: runt packet %d\n", 2654 __func__, len); 2655 sc->sc_stats.ast_rx_tooshort++; 2656 m_freem(m); 2657 goto rx_next; 2658 } 2659 rix = ds->ds_rxstat.rs_rate; 2660 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2661 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2662 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2663 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2664 /* XXX TSF */ 2665 2666 bpf_mtap2(sc->sc_drvbpf, 2667 &sc->sc_rx_th, sc->sc_rx_th_len, m); 2668 } 2669 2670 /* 2671 * From this point on we assume the frame is at least 2672 * as large as ieee80211_frame_min; verify that. 2673 */ 2674 if (len < IEEE80211_MIN_LEN) { 2675 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2676 __func__, len); 2677 sc->sc_stats.ast_rx_tooshort++; 2678 m_freem(m); 2679 goto rx_next; 2680 } 2681 2682 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2683 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2684 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2685 ds->ds_rxstat.rs_rssi); 2686 } 2687 2688 m_adj(m, -IEEE80211_CRC_LEN); 2689 2690 /* 2691 * Locate the node for sender, track state, and then 2692 * pass the (referenced) node up to the 802.11 layer 2693 * for its use. 2694 */ 2695 ni = ieee80211_find_rxnode(ic, 2696 mtod(m, const struct ieee80211_frame_min *)); 2697 2698 /* 2699 * Track rx rssi and do any rx antenna management. 2700 */ 2701 an = ATH_NODE(ni); 2702 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2703 if (sc->sc_diversity) { 2704 /* 2705 * When using fast diversity, change the default rx 2706 * antenna if diversity chooses the other antenna 3 2707 * times in a row. 2708 */ 2709 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2710 if (++sc->sc_rxotherant >= 3) 2711 ath_setdefantenna(sc, 2712 ds->ds_rxstat.rs_antenna); 2713 } else 2714 sc->sc_rxotherant = 0; 2715 } 2716 2717 /* 2718 * Send frame up for processing. 2719 */ 2720 ieee80211_input(ic, m, ni, 2721 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2722 2723 if (sc->sc_softled) { 2724 /* 2725 * Blink for any data frame. Otherwise do a 2726 * heartbeat-style blink when idle. The latter 2727 * is mainly for station mode where we depend on 2728 * periodic beacon frames to trigger the poll event. 2729 */ 2730 if (sc->sc_ipackets != ifp->if_ipackets) { 2731 sc->sc_ipackets = ifp->if_ipackets; 2732 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 2733 ath_led_event(sc, ATH_LED_RX); 2734 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 2735 ath_led_event(sc, ATH_LED_POLL); 2736 } 2737 2738 /* 2739 * Reclaim node reference. 2740 */ 2741 ieee80211_free_node(ni); 2742rx_next: 2743 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2744 } while (ath_rxbuf_init(sc, bf) == 0); 2745 2746 /* rx signal state monitoring */ 2747 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 2748 2749 NET_UNLOCK_GIANT(); /* XXX */ 2750#undef PA2DESC 2751} 2752 2753/* 2754 * Setup a h/w transmit queue. 2755 */ 2756static struct ath_txq * 2757ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 2758{ 2759#define N(a) (sizeof(a)/sizeof(a[0])) 2760 struct ath_hal *ah = sc->sc_ah; 2761 HAL_TXQ_INFO qi; 2762 int qnum; 2763 2764 memset(&qi, 0, sizeof(qi)); 2765 qi.tqi_subtype = subtype; 2766 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2767 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2768 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2769 /* 2770 * Enable interrupts only for EOL and DESC conditions. 2771 * We mark tx descriptors to receive a DESC interrupt 2772 * when a tx queue gets deep; otherwise waiting for the 2773 * EOL to reap descriptors. Note that this is done to 2774 * reduce interrupt load and this only defers reaping 2775 * descriptors, never transmitting frames. Aside from 2776 * reducing interrupts this also permits more concurrency. 2777 * The only potential downside is if the tx queue backs 2778 * up in which case the top half of the kernel may backup 2779 * due to a lack of tx descriptors. 2780 */ 2781 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 2782 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 2783 if (qnum == -1) { 2784 /* 2785 * NB: don't print a message, this happens 2786 * normally on parts with too few tx queues 2787 */ 2788 return NULL; 2789 } 2790 if (qnum >= N(sc->sc_txq)) { 2791 device_printf(sc->sc_dev, 2792 "hal qnum %u out of range, max %zu!\n", 2793 qnum, N(sc->sc_txq)); 2794 ath_hal_releasetxqueue(ah, qnum); 2795 return NULL; 2796 } 2797 if (!ATH_TXQ_SETUP(sc, qnum)) { 2798 struct ath_txq *txq = &sc->sc_txq[qnum]; 2799 2800 txq->axq_qnum = qnum; 2801 txq->axq_depth = 0; 2802 txq->axq_intrcnt = 0; 2803 txq->axq_link = NULL; 2804 STAILQ_INIT(&txq->axq_q); 2805 ATH_TXQ_LOCK_INIT(sc, txq); 2806 sc->sc_txqsetup |= 1<<qnum; 2807 } 2808 return &sc->sc_txq[qnum]; 2809#undef N 2810} 2811 2812/* 2813 * Setup a hardware data transmit queue for the specified 2814 * access control. The hal may not support all requested 2815 * queues in which case it will return a reference to a 2816 * previously setup queue. We record the mapping from ac's 2817 * to h/w queues for use by ath_tx_start and also track 2818 * the set of h/w queues being used to optimize work in the 2819 * transmit interrupt handler and related routines. 2820 */ 2821static int 2822ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 2823{ 2824#define N(a) (sizeof(a)/sizeof(a[0])) 2825 struct ath_txq *txq; 2826 2827 if (ac >= N(sc->sc_ac2q)) { 2828 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 2829 ac, N(sc->sc_ac2q)); 2830 return 0; 2831 } 2832 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 2833 if (txq != NULL) { 2834 sc->sc_ac2q[ac] = txq; 2835 return 1; 2836 } else 2837 return 0; 2838#undef N 2839} 2840 2841/* 2842 * Update WME parameters for a transmit queue. 2843 */ 2844static int 2845ath_txq_update(struct ath_softc *sc, int ac) 2846{ 2847#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 2848#define ATH_TXOP_TO_US(v) (v<<5) 2849 struct ieee80211com *ic = &sc->sc_ic; 2850 struct ath_txq *txq = sc->sc_ac2q[ac]; 2851 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2852 struct ath_hal *ah = sc->sc_ah; 2853 HAL_TXQ_INFO qi; 2854 2855 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 2856 qi.tqi_aifs = wmep->wmep_aifsn; 2857 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2858 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2859 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 2860 2861 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 2862 device_printf(sc->sc_dev, "unable to update hardware queue " 2863 "parameters for %s traffic!\n", 2864 ieee80211_wme_acnames[ac]); 2865 return 0; 2866 } else { 2867 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 2868 return 1; 2869 } 2870#undef ATH_TXOP_TO_US 2871#undef ATH_EXPONENT_TO_VALUE 2872} 2873 2874/* 2875 * Callback from the 802.11 layer to update WME parameters. 2876 */ 2877static int 2878ath_wme_update(struct ieee80211com *ic) 2879{ 2880 struct ath_softc *sc = ic->ic_ifp->if_softc; 2881 2882 return !ath_txq_update(sc, WME_AC_BE) || 2883 !ath_txq_update(sc, WME_AC_BK) || 2884 !ath_txq_update(sc, WME_AC_VI) || 2885 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 2886} 2887 2888/* 2889 * Reclaim resources for a setup queue. 2890 */ 2891static void 2892ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 2893{ 2894 2895 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 2896 ATH_TXQ_LOCK_DESTROY(txq); 2897 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 2898} 2899 2900/* 2901 * Reclaim all tx queue resources. 2902 */ 2903static void 2904ath_tx_cleanup(struct ath_softc *sc) 2905{ 2906 int i; 2907 2908 ATH_TXBUF_LOCK_DESTROY(sc); 2909 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 2910 if (ATH_TXQ_SETUP(sc, i)) 2911 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 2912} 2913 2914/* 2915 * Defragment an mbuf chain, returning at most maxfrags separate 2916 * mbufs+clusters. If this is not possible NULL is returned and 2917 * the original mbuf chain is left in it's present (potentially 2918 * modified) state. We use two techniques: collapsing consecutive 2919 * mbufs and replacing consecutive mbufs by a cluster. 2920 */ 2921static struct mbuf * 2922ath_defrag(struct mbuf *m0, int how, int maxfrags) 2923{ 2924 struct mbuf *m, *n, *n2, **prev; 2925 u_int curfrags; 2926 2927 /* 2928 * Calculate the current number of frags. 2929 */ 2930 curfrags = 0; 2931 for (m = m0; m != NULL; m = m->m_next) 2932 curfrags++; 2933 /* 2934 * First, try to collapse mbufs. Note that we always collapse 2935 * towards the front so we don't need to deal with moving the 2936 * pkthdr. This may be suboptimal if the first mbuf has much 2937 * less data than the following. 2938 */ 2939 m = m0; 2940again: 2941 for (;;) { 2942 n = m->m_next; 2943 if (n == NULL) 2944 break; 2945 if ((m->m_flags & M_RDONLY) == 0 && 2946 n->m_len < M_TRAILINGSPACE(m)) { 2947 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 2948 n->m_len); 2949 m->m_len += n->m_len; 2950 m->m_next = n->m_next; 2951 m_free(n); 2952 if (--curfrags <= maxfrags) 2953 return m0; 2954 } else 2955 m = n; 2956 } 2957 KASSERT(maxfrags > 1, 2958 ("maxfrags %u, but normal collapse failed", maxfrags)); 2959 /* 2960 * Collapse consecutive mbufs to a cluster. 2961 */ 2962 prev = &m0->m_next; /* NB: not the first mbuf */ 2963 while ((n = *prev) != NULL) { 2964 if ((n2 = n->m_next) != NULL && 2965 n->m_len + n2->m_len < MCLBYTES) { 2966 m = m_getcl(how, MT_DATA, 0); 2967 if (m == NULL) 2968 goto bad; 2969 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 2970 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 2971 n2->m_len); 2972 m->m_len = n->m_len + n2->m_len; 2973 m->m_next = n2->m_next; 2974 *prev = m; 2975 m_free(n); 2976 m_free(n2); 2977 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 2978 return m0; 2979 /* 2980 * Still not there, try the normal collapse 2981 * again before we allocate another cluster. 2982 */ 2983 goto again; 2984 } 2985 prev = &n->m_next; 2986 } 2987 /* 2988 * No place where we can collapse to a cluster; punt. 2989 * This can occur if, for example, you request 2 frags 2990 * but the packet requires that both be clusters (we 2991 * never reallocate the first mbuf to avoid moving the 2992 * packet header). 2993 */ 2994bad: 2995 return NULL; 2996} 2997 2998static int 2999ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3000 struct mbuf *m0) 3001{ 3002#define CTS_DURATION \ 3003 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE) 3004#define updateCTSForBursting(_ah, _ds, _txq) \ 3005 ath_hal_updateCTSForBursting(_ah, _ds, \ 3006 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ 3007 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ 3008 txopLimit, CTS_DURATION) 3009 struct ieee80211com *ic = &sc->sc_ic; 3010 struct ath_hal *ah = sc->sc_ah; 3011 struct ifnet *ifp = &sc->sc_if; 3012 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3013 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3014 u_int8_t rix, txrate, ctsrate; 3015 u_int8_t cix = 0xff; /* NB: silence compiler */ 3016 struct ath_desc *ds, *ds0; 3017 struct ath_txq *txq; 3018 struct ieee80211_frame *wh; 3019 u_int subtype, flags, ctsduration; 3020 HAL_PKT_TYPE atype; 3021 const HAL_RATE_TABLE *rt; 3022 HAL_BOOL shortPreamble; 3023 struct ath_node *an; 3024 struct mbuf *m; 3025 u_int pri; 3026 3027 wh = mtod(m0, struct ieee80211_frame *); 3028 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3029 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3030 hdrlen = ieee80211_anyhdrsize(wh); 3031 /* 3032 * Packet length must not include any 3033 * pad bytes; deduct them here. 3034 */ 3035 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3036 3037 if (iswep) { 3038 const struct ieee80211_cipher *cip; 3039 struct ieee80211_key *k; 3040 3041 /* 3042 * Construct the 802.11 header+trailer for an encrypted 3043 * frame. The only reason this can fail is because of an 3044 * unknown or unsupported cipher/key type. 3045 */ 3046 k = ieee80211_crypto_encap(ic, ni, m0); 3047 if (k == NULL) { 3048 /* 3049 * This can happen when the key is yanked after the 3050 * frame was queued. Just discard the frame; the 3051 * 802.11 layer counts failures and provides 3052 * debugging/diagnostics. 3053 */ 3054 m_freem(m0); 3055 return EIO; 3056 } 3057 /* 3058 * Adjust the packet + header lengths for the crypto 3059 * additions and calculate the h/w key index. When 3060 * a s/w mic is done the frame will have had any mic 3061 * added to it prior to entry so skb->len above will 3062 * account for it. Otherwise we need to add it to the 3063 * packet length. 3064 */ 3065 cip = k->wk_cipher; 3066 hdrlen += cip->ic_header; 3067 pktlen += cip->ic_header + cip->ic_trailer; 3068 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3069 pktlen += cip->ic_miclen; 3070 keyix = k->wk_keyix; 3071 3072 /* packet header may have moved, reset our local pointer */ 3073 wh = mtod(m0, struct ieee80211_frame *); 3074 } else 3075 keyix = HAL_TXKEYIX_INVALID; 3076 3077 pktlen += IEEE80211_CRC_LEN; 3078 3079 /* 3080 * Load the DMA map so any coalescing is done. This 3081 * also calculates the number of descriptors we need. 3082 */ 3083 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3084 bf->bf_segs, &bf->bf_nseg, 3085 BUS_DMA_NOWAIT); 3086 if (error == EFBIG) { 3087 /* XXX packet requires too many descriptors */ 3088 bf->bf_nseg = ATH_TXDESC+1; 3089 } else if (error != 0) { 3090 sc->sc_stats.ast_tx_busdma++; 3091 m_freem(m0); 3092 return error; 3093 } 3094 /* 3095 * Discard null packets and check for packets that 3096 * require too many TX descriptors. We try to convert 3097 * the latter to a cluster. 3098 */ 3099 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 3100 sc->sc_stats.ast_tx_linear++; 3101 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3102 if (m == NULL) { 3103 m_freem(m0); 3104 sc->sc_stats.ast_tx_nombuf++; 3105 return ENOMEM; 3106 } 3107 m0 = m; 3108 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3109 bf->bf_segs, &bf->bf_nseg, 3110 BUS_DMA_NOWAIT); 3111 if (error != 0) { 3112 sc->sc_stats.ast_tx_busdma++; 3113 m_freem(m0); 3114 return error; 3115 } 3116 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3117 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3118 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3119 sc->sc_stats.ast_tx_nodata++; 3120 m_freem(m0); 3121 return EIO; 3122 } 3123 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3124 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3125 bf->bf_m = m0; 3126 bf->bf_node = ni; /* NB: held reference */ 3127 3128 /* setup descriptors */ 3129 ds = bf->bf_desc; 3130 rt = sc->sc_currates; 3131 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3132 3133 /* 3134 * NB: the 802.11 layer marks whether or not we should 3135 * use short preamble based on the current mode and 3136 * negotiated parameters. 3137 */ 3138 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3139 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3140 shortPreamble = AH_TRUE; 3141 sc->sc_stats.ast_tx_shortpre++; 3142 } else { 3143 shortPreamble = AH_FALSE; 3144 } 3145 3146 an = ATH_NODE(ni); 3147 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3148 /* 3149 * Calculate Atheros packet type from IEEE80211 packet header, 3150 * setup for rate calculations, and select h/w transmit queue. 3151 */ 3152 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3153 case IEEE80211_FC0_TYPE_MGT: 3154 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3155 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3156 atype = HAL_PKT_TYPE_BEACON; 3157 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3158 atype = HAL_PKT_TYPE_PROBE_RESP; 3159 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3160 atype = HAL_PKT_TYPE_ATIM; 3161 else 3162 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3163 rix = 0; /* XXX lowest rate */ 3164 try0 = ATH_TXMAXTRY; 3165 if (shortPreamble) 3166 txrate = an->an_tx_mgtratesp; 3167 else 3168 txrate = an->an_tx_mgtrate; 3169 /* NB: force all management frames to highest queue */ 3170 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3171 /* NB: force all management frames to highest queue */ 3172 pri = WME_AC_VO; 3173 } else 3174 pri = WME_AC_BE; 3175 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3176 break; 3177 case IEEE80211_FC0_TYPE_CTL: 3178 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3179 rix = 0; /* XXX lowest rate */ 3180 try0 = ATH_TXMAXTRY; 3181 if (shortPreamble) 3182 txrate = an->an_tx_mgtratesp; 3183 else 3184 txrate = an->an_tx_mgtrate; 3185 /* NB: force all ctl frames to highest queue */ 3186 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3187 /* NB: force all ctl frames to highest queue */ 3188 pri = WME_AC_VO; 3189 } else 3190 pri = WME_AC_BE; 3191 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3192 break; 3193 case IEEE80211_FC0_TYPE_DATA: 3194 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3195 /* 3196 * Data frames; consult the rate control module. 3197 */ 3198 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3199 &rix, &try0, &txrate); 3200 sc->sc_txrate = txrate; /* for LED blinking */ 3201 /* 3202 * Default all non-QoS traffic to the background queue. 3203 */ 3204 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3205 pri = M_WME_GETAC(m0); 3206 if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3207 flags |= HAL_TXDESC_NOACK; 3208 sc->sc_stats.ast_tx_noack++; 3209 } 3210 } else 3211 pri = WME_AC_BE; 3212 break; 3213 default: 3214 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3215 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3216 /* XXX statistic */ 3217 m_freem(m0); 3218 return EIO; 3219 } 3220 txq = sc->sc_ac2q[pri]; 3221 3222 /* 3223 * When servicing one or more stations in power-save mode 3224 * multicast frames must be buffered until after the beacon. 3225 * We use the CAB queue for that. 3226 */ 3227 if (ismcast && ic->ic_ps_sta) { 3228 txq = sc->sc_cabq; 3229 /* XXX? more bit in 802.11 frame header */ 3230 } 3231 3232 /* 3233 * Calculate miscellaneous flags. 3234 */ 3235 if (ismcast) { 3236 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3237 sc->sc_stats.ast_tx_noack++; 3238 } else if (pktlen > ic->ic_rtsthreshold) { 3239 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3240 cix = rt->info[rix].controlRate; 3241 sc->sc_stats.ast_tx_rts++; 3242 } 3243 3244 /* 3245 * If 802.11g protection is enabled, determine whether 3246 * to use RTS/CTS or just CTS. Note that this is only 3247 * done for OFDM unicast frames. 3248 */ 3249 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3250 rt->info[rix].phy == IEEE80211_T_OFDM && 3251 (flags & HAL_TXDESC_NOACK) == 0) { 3252 /* XXX fragments must use CCK rates w/ protection */ 3253 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3254 flags |= HAL_TXDESC_RTSENA; 3255 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3256 flags |= HAL_TXDESC_CTSENA; 3257 cix = rt->info[sc->sc_protrix].controlRate; 3258 sc->sc_stats.ast_tx_protect++; 3259 } 3260 3261 /* 3262 * Calculate duration. This logically belongs in the 802.11 3263 * layer but it lacks sufficient information to calculate it. 3264 */ 3265 if ((flags & HAL_TXDESC_NOACK) == 0 && 3266 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3267 u_int16_t dur; 3268 /* 3269 * XXX not right with fragmentation. 3270 */ 3271 if (shortPreamble) 3272 dur = rt->info[rix].spAckDuration; 3273 else 3274 dur = rt->info[rix].lpAckDuration; 3275 *(u_int16_t *)wh->i_dur = htole16(dur); 3276 } 3277 3278 /* 3279 * Calculate RTS/CTS rate and duration if needed. 3280 */ 3281 ctsduration = 0; 3282 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3283 /* 3284 * CTS transmit rate is derived from the transmit rate 3285 * by looking in the h/w rate table. We must also factor 3286 * in whether or not a short preamble is to be used. 3287 */ 3288 /* NB: cix is set above where RTS/CTS is enabled */ 3289 KASSERT(cix != 0xff, ("cix not setup")); 3290 ctsrate = rt->info[cix].rateCode; 3291 /* 3292 * Compute the transmit duration based on the frame 3293 * size and the size of an ACK frame. We call into the 3294 * HAL to do the computation since it depends on the 3295 * characteristics of the actual PHY being used. 3296 * 3297 * NB: CTS is assumed the same size as an ACK so we can 3298 * use the precalculated ACK durations. 3299 */ 3300 if (shortPreamble) { 3301 ctsrate |= rt->info[cix].shortPreamble; 3302 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3303 ctsduration += rt->info[cix].spAckDuration; 3304 ctsduration += ath_hal_computetxtime(ah, 3305 rt, pktlen, rix, AH_TRUE); 3306 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3307 ctsduration += rt->info[cix].spAckDuration; 3308 } else { 3309 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3310 ctsduration += rt->info[cix].lpAckDuration; 3311 ctsduration += ath_hal_computetxtime(ah, 3312 rt, pktlen, rix, AH_FALSE); 3313 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3314 ctsduration += rt->info[cix].lpAckDuration; 3315 } 3316 /* 3317 * Must disable multi-rate retry when using RTS/CTS. 3318 */ 3319 try0 = ATH_TXMAXTRY; 3320 } else 3321 ctsrate = 0; 3322 3323 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3324 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3325 sc->sc_hwmap[txrate].ieeerate, -1); 3326 3327 if (ic->ic_rawbpf) 3328 bpf_mtap(ic->ic_rawbpf, m0); 3329 if (sc->sc_drvbpf) { 3330 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3331 if (iswep) 3332 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3333 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3334 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3335 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3336 3337 bpf_mtap2(sc->sc_drvbpf, 3338 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3339 } 3340 3341 /* 3342 * Determine if a tx interrupt should be generated for 3343 * this descriptor. We take a tx interrupt to reap 3344 * descriptors when the h/w hits an EOL condition or 3345 * when the descriptor is specifically marked to generate 3346 * an interrupt. We periodically mark descriptors in this 3347 * way to insure timely replenishing of the supply needed 3348 * for sending frames. Defering interrupts reduces system 3349 * load and potentially allows more concurrent work to be 3350 * done but if done to aggressively can cause senders to 3351 * backup. 3352 * 3353 * NB: use >= to deal with sc_txintrperiod changing 3354 * dynamically through sysctl. 3355 */ 3356 if (flags & HAL_TXDESC_INTREQ) { 3357 txq->axq_intrcnt = 0; 3358 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3359 flags |= HAL_TXDESC_INTREQ; 3360 txq->axq_intrcnt = 0; 3361 } 3362 3363 /* 3364 * Formulate first tx descriptor with tx controls. 3365 */ 3366 /* XXX check return value? */ 3367 ath_hal_setuptxdesc(ah, ds 3368 , pktlen /* packet length */ 3369 , hdrlen /* header length */ 3370 , atype /* Atheros packet type */ 3371 , ni->ni_txpower /* txpower */ 3372 , txrate, try0 /* series 0 rate/tries */ 3373 , keyix /* key cache index */ 3374 , sc->sc_txantenna /* antenna mode */ 3375 , flags /* flags */ 3376 , ctsrate /* rts/cts rate */ 3377 , ctsduration /* rts/cts duration */ 3378 ); 3379 /* 3380 * Setup the multi-rate retry state only when we're 3381 * going to use it. This assumes ath_hal_setuptxdesc 3382 * initializes the descriptors (so we don't have to) 3383 * when the hardware supports multi-rate retry and 3384 * we don't use it. 3385 */ 3386 if (try0 != ATH_TXMAXTRY) 3387 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3388 3389 /* 3390 * Fillin the remainder of the descriptor info. 3391 */ 3392 ds0 = ds; 3393 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3394 ds->ds_data = bf->bf_segs[i].ds_addr; 3395 if (i == bf->bf_nseg - 1) 3396 ds->ds_link = 0; 3397 else 3398 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3399 ath_hal_filltxdesc(ah, ds 3400 , bf->bf_segs[i].ds_len /* segment length */ 3401 , i == 0 /* first segment */ 3402 , i == bf->bf_nseg - 1 /* last segment */ 3403 , ds0 /* first descriptor */ 3404 ); 3405 DPRINTF(sc, ATH_DEBUG_XMIT, 3406 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3407 __func__, i, ds->ds_link, ds->ds_data, 3408 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3409 } 3410 /* 3411 * Insert the frame on the outbound list and 3412 * pass it on to the hardware. 3413 */ 3414 ATH_TXQ_LOCK(txq); 3415 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 3416 u_int32_t txopLimit = IEEE80211_TXOP_TO_US( 3417 cap->cap_wmeParams[pri].wmep_txopLimit); 3418 /* 3419 * When bursting, potentially extend the CTS duration 3420 * of a previously queued frame to cover this frame 3421 * and not exceed the txopLimit. If that can be done 3422 * then disable RTS/CTS on this frame since it's now 3423 * covered (burst extension). Otherwise we must terminate 3424 * the burst before this frame goes out so as not to 3425 * violate the WME parameters. All this is complicated 3426 * as we need to update the state of packets on the 3427 * (live) hardware queue. The logic is buried in the hal 3428 * because it's highly chip-specific. 3429 */ 3430 if (txopLimit != 0) { 3431 sc->sc_stats.ast_tx_ctsburst++; 3432 if (updateCTSForBursting(ah, ds0, txq) == 0) { 3433 /* 3434 * This frame was not covered by RTS/CTS from 3435 * the previous frame in the burst; update the 3436 * descriptor pointers so this frame is now 3437 * treated as the last frame for extending a 3438 * burst. 3439 */ 3440 txq->axq_lastdsWithCTS = ds0; 3441 /* set gating Desc to final desc */ 3442 txq->axq_gatingds = 3443 (struct ath_desc *)txq->axq_link; 3444 } else 3445 sc->sc_stats.ast_tx_ctsext++; 3446 } 3447 } 3448 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3449 if (txq->axq_link == NULL) { 3450 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3451 DPRINTF(sc, ATH_DEBUG_XMIT, 3452 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3453 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3454 txq->axq_depth); 3455 } else { 3456 *txq->axq_link = bf->bf_daddr; 3457 DPRINTF(sc, ATH_DEBUG_XMIT, 3458 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3459 txq->axq_qnum, txq->axq_link, 3460 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3461 } 3462 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3463 ATH_TXQ_UNLOCK(txq); 3464 3465 /* 3466 * The CAB queue is started from the SWBA handler since 3467 * frames only go out on DTIM and to avoid possible races. 3468 */ 3469 if (txq != sc->sc_cabq) 3470 ath_hal_txstart(ah, txq->axq_qnum); 3471 return 0; 3472#undef updateCTSForBursting 3473#undef CTS_DURATION 3474} 3475 3476/* 3477 * Process completed xmit descriptors from the specified queue. 3478 */ 3479static void 3480ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3481{ 3482 struct ath_hal *ah = sc->sc_ah; 3483 struct ieee80211com *ic = &sc->sc_ic; 3484 struct ath_buf *bf; 3485 struct ath_desc *ds, *ds0; 3486 struct ieee80211_node *ni; 3487 struct ath_node *an; 3488 int sr, lr, pri; 3489 HAL_STATUS status; 3490 3491 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3492 __func__, txq->axq_qnum, 3493 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3494 txq->axq_link); 3495 for (;;) { 3496 ATH_TXQ_LOCK(txq); 3497 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3498 bf = STAILQ_FIRST(&txq->axq_q); 3499 if (bf == NULL) { 3500 txq->axq_link = NULL; 3501 ATH_TXQ_UNLOCK(txq); 3502 break; 3503 } 3504 ds0 = &bf->bf_desc[0]; 3505 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3506 status = ath_hal_txprocdesc(ah, ds); 3507#ifdef AR_DEBUG 3508 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3509 ath_printtxbuf(bf, status == HAL_OK); 3510#endif 3511 if (status == HAL_EINPROGRESS) { 3512 ATH_TXQ_UNLOCK(txq); 3513 break; 3514 } 3515 if (ds0 == txq->axq_lastdsWithCTS) 3516 txq->axq_lastdsWithCTS = NULL; 3517 if (ds == txq->axq_gatingds) 3518 txq->axq_gatingds = NULL; 3519 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3520 ATH_TXQ_UNLOCK(txq); 3521 3522 ni = bf->bf_node; 3523 if (ni != NULL) { 3524 an = ATH_NODE(ni); 3525 if (ds->ds_txstat.ts_status == 0) { 3526 u_int8_t txant = ds->ds_txstat.ts_antenna; 3527 sc->sc_stats.ast_ant_tx[txant]++; 3528 sc->sc_ant_tx[txant]++; 3529 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3530 sc->sc_stats.ast_tx_altrate++; 3531 sc->sc_stats.ast_tx_rssi = 3532 ds->ds_txstat.ts_rssi; 3533 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3534 ds->ds_txstat.ts_rssi); 3535 pri = M_WME_GETAC(bf->bf_m); 3536 if (pri >= WME_AC_VO) 3537 ic->ic_wme.wme_hipri_traffic++; 3538 ni->ni_inact = ni->ni_inact_reload; 3539 } else { 3540 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3541 sc->sc_stats.ast_tx_xretries++; 3542 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3543 sc->sc_stats.ast_tx_fifoerr++; 3544 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3545 sc->sc_stats.ast_tx_filtered++; 3546 } 3547 sr = ds->ds_txstat.ts_shortretry; 3548 lr = ds->ds_txstat.ts_longretry; 3549 sc->sc_stats.ast_tx_shortretry += sr; 3550 sc->sc_stats.ast_tx_longretry += lr; 3551 /* 3552 * Hand the descriptor to the rate control algorithm. 3553 */ 3554 ath_rate_tx_complete(sc, an, ds, ds0); 3555 /* 3556 * Reclaim reference to node. 3557 * 3558 * NB: the node may be reclaimed here if, for example 3559 * this is a DEAUTH message that was sent and the 3560 * node was timed out due to inactivity. 3561 */ 3562 ieee80211_free_node(ni); 3563 } 3564 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3565 BUS_DMASYNC_POSTWRITE); 3566 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3567 m_freem(bf->bf_m); 3568 bf->bf_m = NULL; 3569 bf->bf_node = NULL; 3570 3571 ATH_TXBUF_LOCK(sc); 3572 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3573 ATH_TXBUF_UNLOCK(sc); 3574 } 3575} 3576 3577/* 3578 * Deferred processing of transmit interrupt; special-cased 3579 * for a single hardware transmit queue (e.g. 5210 and 5211). 3580 */ 3581static void 3582ath_tx_proc_q0(void *arg, int npending) 3583{ 3584 struct ath_softc *sc = arg; 3585 struct ifnet *ifp = &sc->sc_if; 3586 3587 ath_tx_processq(sc, &sc->sc_txq[0]); 3588 ath_tx_processq(sc, sc->sc_cabq); 3589 ifp->if_flags &= ~IFF_OACTIVE; 3590 sc->sc_tx_timer = 0; 3591 3592 if (sc->sc_softled) 3593 ath_led_event(sc, ATH_LED_TX); 3594 3595 ath_start(ifp); 3596} 3597 3598/* 3599 * Deferred processing of transmit interrupt; special-cased 3600 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3601 */ 3602static void 3603ath_tx_proc_q0123(void *arg, int npending) 3604{ 3605 struct ath_softc *sc = arg; 3606 struct ifnet *ifp = &sc->sc_if; 3607 3608 /* 3609 * Process each active queue. 3610 */ 3611 ath_tx_processq(sc, &sc->sc_txq[0]); 3612 ath_tx_processq(sc, &sc->sc_txq[1]); 3613 ath_tx_processq(sc, &sc->sc_txq[2]); 3614 ath_tx_processq(sc, &sc->sc_txq[3]); 3615 ath_tx_processq(sc, sc->sc_cabq); 3616 3617 ifp->if_flags &= ~IFF_OACTIVE; 3618 sc->sc_tx_timer = 0; 3619 3620 if (sc->sc_softled) 3621 ath_led_event(sc, ATH_LED_TX); 3622 3623 ath_start(ifp); 3624} 3625 3626/* 3627 * Deferred processing of transmit interrupt. 3628 */ 3629static void 3630ath_tx_proc(void *arg, int npending) 3631{ 3632 struct ath_softc *sc = arg; 3633 struct ifnet *ifp = &sc->sc_if; 3634 int i; 3635 3636 /* 3637 * Process each active queue. 3638 */ 3639 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3640 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3641 if (ATH_TXQ_SETUP(sc, i)) 3642 ath_tx_processq(sc, &sc->sc_txq[i]); 3643 3644 ifp->if_flags &= ~IFF_OACTIVE; 3645 sc->sc_tx_timer = 0; 3646 3647 if (sc->sc_softled) 3648 ath_led_event(sc, ATH_LED_TX); 3649 3650 ath_start(ifp); 3651} 3652 3653static void 3654ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3655{ 3656 struct ath_hal *ah = sc->sc_ah; 3657 struct ieee80211_node *ni; 3658 struct ath_buf *bf; 3659 3660 /* 3661 * NB: this assumes output has been stopped and 3662 * we do not need to block ath_tx_tasklet 3663 */ 3664 for (;;) { 3665 ATH_TXQ_LOCK(txq); 3666 bf = STAILQ_FIRST(&txq->axq_q); 3667 if (bf == NULL) { 3668 txq->axq_link = NULL; 3669 ATH_TXQ_UNLOCK(txq); 3670 break; 3671 } 3672 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3673 ATH_TXQ_UNLOCK(txq); 3674#ifdef AR_DEBUG 3675 if (sc->sc_debug & ATH_DEBUG_RESET) 3676 ath_printtxbuf(bf, 3677 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3678#endif /* AR_DEBUG */ 3679 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3680 m_freem(bf->bf_m); 3681 bf->bf_m = NULL; 3682 ni = bf->bf_node; 3683 bf->bf_node = NULL; 3684 if (ni != NULL) { 3685 /* 3686 * Reclaim node reference. 3687 */ 3688 ieee80211_free_node(ni); 3689 } 3690 ATH_TXBUF_LOCK(sc); 3691 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3692 ATH_TXBUF_UNLOCK(sc); 3693 } 3694} 3695 3696static void 3697ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3698{ 3699 struct ath_hal *ah = sc->sc_ah; 3700 3701 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 3702 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3703 __func__, txq->axq_qnum, 3704 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 3705 txq->axq_link); 3706} 3707 3708/* 3709 * Drain the transmit queues and reclaim resources. 3710 */ 3711static void 3712ath_draintxq(struct ath_softc *sc) 3713{ 3714 struct ath_hal *ah = sc->sc_ah; 3715 struct ifnet *ifp = &sc->sc_if; 3716 int i; 3717 3718 /* XXX return value */ 3719 if (!sc->sc_invalid) { 3720 /* don't touch the hardware if marked invalid */ 3721 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 3722 DPRINTF(sc, ATH_DEBUG_RESET, 3723 "%s: beacon queue %p\n", __func__, 3724 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 3725 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3726 if (ATH_TXQ_SETUP(sc, i)) 3727 ath_tx_stopdma(sc, &sc->sc_txq[i]); 3728 } 3729 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3730 if (ATH_TXQ_SETUP(sc, i)) 3731 ath_tx_draintxq(sc, &sc->sc_txq[i]); 3732 ifp->if_flags &= ~IFF_OACTIVE; 3733 sc->sc_tx_timer = 0; 3734} 3735 3736/* 3737 * Disable the receive h/w in preparation for a reset. 3738 */ 3739static void 3740ath_stoprecv(struct ath_softc *sc) 3741{ 3742#define PA2DESC(_sc, _pa) \ 3743 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3744 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3745 struct ath_hal *ah = sc->sc_ah; 3746 3747 ath_hal_stoppcurecv(ah); /* disable PCU */ 3748 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 3749 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 3750 DELAY(3000); /* 3ms is long enough for 1 frame */ 3751#ifdef AR_DEBUG 3752 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 3753 struct ath_buf *bf; 3754 3755 printf("%s: rx queue %p, link %p\n", __func__, 3756 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 3757 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3758 struct ath_desc *ds = bf->bf_desc; 3759 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 3760 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3761 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 3762 ath_printrxbuf(bf, status == HAL_OK); 3763 } 3764 } 3765#endif 3766 sc->sc_rxlink = NULL; /* just in case */ 3767#undef PA2DESC 3768} 3769 3770/* 3771 * Enable the receive h/w following a reset. 3772 */ 3773static int 3774ath_startrecv(struct ath_softc *sc) 3775{ 3776 struct ath_hal *ah = sc->sc_ah; 3777 struct ath_buf *bf; 3778 3779 sc->sc_rxlink = NULL; 3780 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3781 int error = ath_rxbuf_init(sc, bf); 3782 if (error != 0) { 3783 DPRINTF(sc, ATH_DEBUG_RECV, 3784 "%s: ath_rxbuf_init failed %d\n", 3785 __func__, error); 3786 return error; 3787 } 3788 } 3789 3790 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3791 ath_hal_putrxbuf(ah, bf->bf_daddr); 3792 ath_hal_rxena(ah); /* enable recv descriptors */ 3793 ath_mode_init(sc); /* set filters, etc. */ 3794 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 3795 return 0; 3796} 3797 3798/* 3799 * Update internal state after a channel change. 3800 */ 3801static void 3802ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 3803{ 3804 struct ieee80211com *ic = &sc->sc_ic; 3805 enum ieee80211_phymode mode; 3806 u_int16_t flags; 3807 3808 /* 3809 * Change channels and update the h/w rate map 3810 * if we're switching; e.g. 11a to 11b/g. 3811 */ 3812 mode = ieee80211_chan2mode(ic, chan); 3813 if (mode != sc->sc_curmode) 3814 ath_setcurmode(sc, mode); 3815 /* 3816 * Update BPF state. NB: ethereal et. al. don't handle 3817 * merged flags well so pick a unique mode for their use. 3818 */ 3819 if (IEEE80211_IS_CHAN_A(chan)) 3820 flags = IEEE80211_CHAN_A; 3821 /* XXX 11g schizophrenia */ 3822 else if (IEEE80211_IS_CHAN_G(chan) || 3823 IEEE80211_IS_CHAN_PUREG(chan)) 3824 flags = IEEE80211_CHAN_G; 3825 else 3826 flags = IEEE80211_CHAN_B; 3827 if (IEEE80211_IS_CHAN_T(chan)) 3828 flags |= IEEE80211_CHAN_TURBO; 3829 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 3830 htole16(chan->ic_freq); 3831 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 3832 htole16(flags); 3833} 3834 3835/* 3836 * Set/change channels. If the channel is really being changed, 3837 * it's done by reseting the chip. To accomplish this we must 3838 * first cleanup any pending DMA, then restart stuff after a la 3839 * ath_init. 3840 */ 3841static int 3842ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 3843{ 3844 struct ath_hal *ah = sc->sc_ah; 3845 struct ieee80211com *ic = &sc->sc_ic; 3846 HAL_CHANNEL hchan; 3847 3848 /* 3849 * Convert to a HAL channel description with 3850 * the flags constrained to reflect the current 3851 * operating mode. 3852 */ 3853 hchan.channel = chan->ic_freq; 3854 hchan.channelFlags = ath_chan2flags(ic, chan); 3855 3856 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 3857 __func__, 3858 ath_hal_mhz2ieee(sc->sc_curchan.channel, 3859 sc->sc_curchan.channelFlags), 3860 sc->sc_curchan.channel, 3861 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 3862 if (hchan.channel != sc->sc_curchan.channel || 3863 hchan.channelFlags != sc->sc_curchan.channelFlags) { 3864 HAL_STATUS status; 3865 3866 /* 3867 * To switch channels clear any pending DMA operations; 3868 * wait long enough for the RX fifo to drain, reset the 3869 * hardware at the new frequency, and then re-enable 3870 * the relevant bits of the h/w. 3871 */ 3872 ath_hal_intrset(ah, 0); /* disable interrupts */ 3873 ath_draintxq(sc); /* clear pending tx frames */ 3874 ath_stoprecv(sc); /* turn off frame recv */ 3875 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 3876 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset " 3877 "channel %u (%u Mhz)\n", 3878 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 3879 return EIO; 3880 } 3881 sc->sc_curchan = hchan; 3882 ath_update_txpow(sc); /* update tx power state */ 3883 3884 /* 3885 * Re-enable rx framework. 3886 */ 3887 if (ath_startrecv(sc) != 0) { 3888 if_printf(ic->ic_ifp, 3889 "ath_chan_set: unable to restart recv logic\n"); 3890 return EIO; 3891 } 3892 3893 /* 3894 * Change channels and update the h/w rate map 3895 * if we're switching; e.g. 11a to 11b/g. 3896 */ 3897 ic->ic_ibss_chan = chan; 3898 ath_chan_change(sc, chan); 3899 3900 /* 3901 * Re-enable interrupts. 3902 */ 3903 ath_hal_intrset(ah, sc->sc_imask); 3904 } 3905 return 0; 3906} 3907 3908static void 3909ath_next_scan(void *arg) 3910{ 3911 struct ath_softc *sc = arg; 3912 struct ieee80211com *ic = &sc->sc_ic; 3913 3914 if (ic->ic_state == IEEE80211_S_SCAN) 3915 ieee80211_next_scan(ic); 3916} 3917 3918/* 3919 * Periodically recalibrate the PHY to account 3920 * for temperature/environment changes. 3921 */ 3922static void 3923ath_calibrate(void *arg) 3924{ 3925 struct ath_softc *sc = arg; 3926 struct ath_hal *ah = sc->sc_ah; 3927 3928 sc->sc_stats.ast_per_cal++; 3929 3930 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 3931 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 3932 3933 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 3934 /* 3935 * Rfgain is out of bounds, reset the chip 3936 * to load new gain values. 3937 */ 3938 sc->sc_stats.ast_per_rfgain++; 3939 ath_reset(&sc->sc_if); 3940 } 3941 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 3942 DPRINTF(sc, ATH_DEBUG_ANY, 3943 "%s: calibration of channel %u failed\n", 3944 __func__, sc->sc_curchan.channel); 3945 sc->sc_stats.ast_per_calfail++; 3946 } 3947 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 3948} 3949 3950static int 3951ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3952{ 3953 struct ifnet *ifp = ic->ic_ifp; 3954 struct ath_softc *sc = ifp->if_softc; 3955 struct ath_hal *ah = sc->sc_ah; 3956 struct ieee80211_node *ni; 3957 int i, error; 3958 const u_int8_t *bssid; 3959 u_int32_t rfilt; 3960 static const HAL_LED_STATE leds[] = { 3961 HAL_LED_INIT, /* IEEE80211_S_INIT */ 3962 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 3963 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 3964 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 3965 HAL_LED_RUN, /* IEEE80211_S_RUN */ 3966 }; 3967 3968 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 3969 ieee80211_state_name[ic->ic_state], 3970 ieee80211_state_name[nstate]); 3971 3972 callout_stop(&sc->sc_scan_ch); 3973 callout_stop(&sc->sc_cal_ch); 3974 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 3975 3976 if (nstate == IEEE80211_S_INIT) { 3977 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 3978 /* 3979 * NB: disable interrupts so we don't rx frames. 3980 */ 3981 ath_hal_intrset(ah, sc->sc_imask &~ ~HAL_INT_GLOBAL); 3982 /* 3983 * Notify the rate control algorithm. 3984 */ 3985 ath_rate_newstate(sc, nstate); 3986 goto done; 3987 } 3988 ni = ic->ic_bss; 3989 error = ath_chan_set(sc, ni->ni_chan); 3990 if (error != 0) 3991 goto bad; 3992 rfilt = ath_calcrxfilter(sc, nstate); 3993 if (nstate == IEEE80211_S_SCAN) 3994 bssid = ifp->if_broadcastaddr; 3995 else 3996 bssid = ni->ni_bssid; 3997 ath_hal_setrxfilter(ah, rfilt); 3998 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 3999 __func__, rfilt, ether_sprintf(bssid)); 4000 4001 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4002 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4003 else 4004 ath_hal_setassocid(ah, bssid, 0); 4005 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4006 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4007 if (ath_hal_keyisvalid(ah, i)) 4008 ath_hal_keysetmac(ah, i, bssid); 4009 } 4010 4011 /* 4012 * Notify the rate control algorithm so rates 4013 * are setup should ath_beacon_alloc be called. 4014 */ 4015 ath_rate_newstate(sc, nstate); 4016 4017 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4018 /* nothing to do */; 4019 } else if (nstate == IEEE80211_S_RUN) { 4020 DPRINTF(sc, ATH_DEBUG_STATE, 4021 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4022 "capinfo=0x%04x chan=%d\n" 4023 , __func__ 4024 , ic->ic_flags 4025 , ni->ni_intval 4026 , ether_sprintf(ni->ni_bssid) 4027 , ni->ni_capinfo 4028 , ieee80211_chan2ieee(ic, ni->ni_chan)); 4029 4030 /* 4031 * Allocate and setup the beacon frame for AP or adhoc mode. 4032 */ 4033 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 4034 ic->ic_opmode == IEEE80211_M_IBSS) { 4035 /* 4036 * Stop any previous beacon DMA. This may be 4037 * necessary, for example, when an ibss merge 4038 * causes reconfiguration; there will be a state 4039 * transition from RUN->RUN that means we may 4040 * be called with beacon transmission active. 4041 */ 4042 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4043 ath_beacon_free(sc); 4044 error = ath_beacon_alloc(sc, ni); 4045 if (error != 0) 4046 goto bad; 4047 } 4048 4049 /* 4050 * Configure the beacon and sleep timers. 4051 */ 4052 ath_beacon_config(sc); 4053 } else { 4054 ath_hal_intrset(ah, 4055 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4056 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4057 } 4058done: 4059 /* 4060 * Invoke the parent method to complete the work. 4061 */ 4062 error = sc->sc_newstate(ic, nstate, arg); 4063 /* 4064 * Finally, start any timers. 4065 */ 4066 if (nstate == IEEE80211_S_RUN) { 4067 /* start periodic recalibration timer */ 4068 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4069 ath_calibrate, sc); 4070 } else if (nstate == IEEE80211_S_SCAN) { 4071 /* start ap/neighbor scan timer */ 4072 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4073 ath_next_scan, sc); 4074 } 4075bad: 4076 return error; 4077} 4078 4079/* 4080 * Setup driver-specific state for a newly associated node. 4081 * Note that we're called also on a re-associate, the isnew 4082 * param tells us if this is the first time or not. 4083 */ 4084static void 4085ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 4086{ 4087 struct ath_softc *sc = ic->ic_ifp->if_softc; 4088 4089 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4090} 4091 4092static int 4093ath_getchannels(struct ath_softc *sc, u_int cc, 4094 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4095{ 4096 struct ieee80211com *ic = &sc->sc_ic; 4097 struct ifnet *ifp = &sc->sc_if; 4098 struct ath_hal *ah = sc->sc_ah; 4099 HAL_CHANNEL *chans; 4100 int i, ix, nchan; 4101 4102 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4103 M_TEMP, M_NOWAIT); 4104 if (chans == NULL) { 4105 if_printf(ifp, "unable to allocate channel table\n"); 4106 return ENOMEM; 4107 } 4108 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4109 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4110 u_int32_t rd; 4111 4112 ath_hal_getregdomain(ah, &rd); 4113 if_printf(ifp, "unable to collect channel list from hal; " 4114 "regdomain likely %u country code %u\n", rd, cc); 4115 free(chans, M_TEMP); 4116 return EINVAL; 4117 } 4118 4119 /* 4120 * Convert HAL channels to ieee80211 ones and insert 4121 * them in the table according to their channel number. 4122 */ 4123 for (i = 0; i < nchan; i++) { 4124 HAL_CHANNEL *c = &chans[i]; 4125 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4126 if (ix > IEEE80211_CHAN_MAX) { 4127 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4128 ix, c->channel, c->channelFlags); 4129 continue; 4130 } 4131 /* NB: flags are known to be compatible */ 4132 if (ic->ic_channels[ix].ic_freq == 0) { 4133 ic->ic_channels[ix].ic_freq = c->channel; 4134 ic->ic_channels[ix].ic_flags = c->channelFlags; 4135 } else { 4136 /* channels overlap; e.g. 11g and 11b */ 4137 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4138 } 4139 } 4140 free(chans, M_TEMP); 4141 return 0; 4142} 4143 4144static void 4145ath_led_done(void *arg) 4146{ 4147 struct ath_softc *sc = arg; 4148 4149 sc->sc_blinking = 0; 4150} 4151 4152/* 4153 * Turn the LED off: flip the pin and then set a timer so no 4154 * update will happen for the specified duration. 4155 */ 4156static void 4157ath_led_off(void *arg) 4158{ 4159 struct ath_softc *sc = arg; 4160 4161 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4162 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4163} 4164 4165/* 4166 * Blink the LED according to the specified on/off times. 4167 */ 4168static void 4169ath_led_blink(struct ath_softc *sc, int on, int off) 4170{ 4171 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4172 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4173 sc->sc_blinking = 1; 4174 sc->sc_ledoff = off; 4175 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4176} 4177 4178static void 4179ath_led_event(struct ath_softc *sc, int event) 4180{ 4181 4182 sc->sc_ledevent = ticks; /* time of last event */ 4183 if (sc->sc_blinking) /* don't interrupt active blink */ 4184 return; 4185 switch (event) { 4186 case ATH_LED_POLL: 4187 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4188 sc->sc_hwmap[0].ledoff); 4189 break; 4190 case ATH_LED_TX: 4191 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4192 sc->sc_hwmap[sc->sc_txrate].ledoff); 4193 break; 4194 case ATH_LED_RX: 4195 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4196 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4197 break; 4198 } 4199} 4200 4201static void 4202ath_update_txpow(struct ath_softc *sc) 4203{ 4204 struct ieee80211com *ic = &sc->sc_ic; 4205 struct ath_hal *ah = sc->sc_ah; 4206 u_int32_t txpow; 4207 4208 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4209 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4210 /* read back in case value is clamped */ 4211 ath_hal_gettxpowlimit(ah, &txpow); 4212 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4213 } 4214 /* 4215 * Fetch max tx power level for status requests. 4216 */ 4217 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4218 ic->ic_bss->ni_txpower = txpow; 4219} 4220 4221static int 4222ath_rate_setup(struct ath_softc *sc, u_int mode) 4223{ 4224 struct ath_hal *ah = sc->sc_ah; 4225 struct ieee80211com *ic = &sc->sc_ic; 4226 const HAL_RATE_TABLE *rt; 4227 struct ieee80211_rateset *rs; 4228 int i, maxrates; 4229 4230 switch (mode) { 4231 case IEEE80211_MODE_11A: 4232 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4233 break; 4234 case IEEE80211_MODE_11B: 4235 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4236 break; 4237 case IEEE80211_MODE_11G: 4238 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4239 break; 4240 case IEEE80211_MODE_TURBO_A: 4241 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4242 break; 4243 case IEEE80211_MODE_TURBO_G: 4244 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4245 break; 4246 default: 4247 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4248 __func__, mode); 4249 return 0; 4250 } 4251 rt = sc->sc_rates[mode]; 4252 if (rt == NULL) 4253 return 0; 4254 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4255 DPRINTF(sc, ATH_DEBUG_ANY, 4256 "%s: rate table too small (%u > %u)\n", 4257 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4258 maxrates = IEEE80211_RATE_MAXSIZE; 4259 } else 4260 maxrates = rt->rateCount; 4261 rs = &ic->ic_sup_rates[mode]; 4262 for (i = 0; i < maxrates; i++) 4263 rs->rs_rates[i] = rt->info[i].dot11Rate; 4264 rs->rs_nrates = maxrates; 4265 return 1; 4266} 4267 4268static void 4269ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4270{ 4271#define N(a) (sizeof(a)/sizeof(a[0])) 4272 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4273 static const struct { 4274 u_int rate; /* tx/rx 802.11 rate */ 4275 u_int16_t timeOn; /* LED on time (ms) */ 4276 u_int16_t timeOff; /* LED off time (ms) */ 4277 } blinkrates[] = { 4278 { 108, 40, 10 }, 4279 { 96, 44, 11 }, 4280 { 72, 50, 13 }, 4281 { 48, 57, 14 }, 4282 { 36, 67, 16 }, 4283 { 24, 80, 20 }, 4284 { 22, 100, 25 }, 4285 { 18, 133, 34 }, 4286 { 12, 160, 40 }, 4287 { 10, 200, 50 }, 4288 { 6, 240, 58 }, 4289 { 4, 267, 66 }, 4290 { 2, 400, 100 }, 4291 { 0, 500, 130 }, 4292 }; 4293 const HAL_RATE_TABLE *rt; 4294 int i, j; 4295 4296 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4297 rt = sc->sc_rates[mode]; 4298 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4299 for (i = 0; i < rt->rateCount; i++) 4300 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4301 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4302 for (i = 0; i < 32; i++) { 4303 u_int8_t ix = rt->rateCodeToIndex[i]; 4304 if (ix == 0xff) { 4305 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4306 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4307 continue; 4308 } 4309 sc->sc_hwmap[i].ieeerate = 4310 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4311 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4312 if (rt->info[ix].shortPreamble || 4313 rt->info[ix].phy == IEEE80211_T_OFDM) 4314 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4315 /* NB: receive frames include FCS */ 4316 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4317 IEEE80211_RADIOTAP_F_FCS; 4318 /* setup blink rate table to avoid per-packet lookup */ 4319 for (j = 0; j < N(blinkrates)-1; j++) 4320 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4321 break; 4322 /* NB: this uses the last entry if the rate isn't found */ 4323 /* XXX beware of overlow */ 4324 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4325 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4326 } 4327 sc->sc_currates = rt; 4328 sc->sc_curmode = mode; 4329 /* 4330 * All protection frames are transmited at 2Mb/s for 4331 * 11g, otherwise at 1Mb/s. 4332 * XXX select protection rate index from rate table. 4333 */ 4334 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4335 /* NB: caller is responsible for reseting rate control state */ 4336#undef N 4337} 4338 4339#ifdef AR_DEBUG 4340static void 4341ath_printrxbuf(struct ath_buf *bf, int done) 4342{ 4343 struct ath_desc *ds; 4344 int i; 4345 4346 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4347 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4348 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4349 ds->ds_link, ds->ds_data, 4350 ds->ds_ctl0, ds->ds_ctl1, 4351 ds->ds_hw[0], ds->ds_hw[1], 4352 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4353 } 4354} 4355 4356static void 4357ath_printtxbuf(struct ath_buf *bf, int done) 4358{ 4359 struct ath_desc *ds; 4360 int i; 4361 4362 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4363 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4364 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4365 ds->ds_link, ds->ds_data, 4366 ds->ds_ctl0, ds->ds_ctl1, 4367 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4368 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4369 } 4370} 4371#endif /* AR_DEBUG */ 4372 4373static void 4374ath_watchdog(struct ifnet *ifp) 4375{ 4376 struct ath_softc *sc = ifp->if_softc; 4377 struct ieee80211com *ic = &sc->sc_ic; 4378 4379 ifp->if_timer = 0; 4380 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4381 return; 4382 if (sc->sc_tx_timer) { 4383 if (--sc->sc_tx_timer == 0) { 4384 if_printf(ifp, "device timeout\n"); 4385 ath_reset(ifp); 4386 ifp->if_oerrors++; 4387 sc->sc_stats.ast_watchdog++; 4388 } else 4389 ifp->if_timer = 1; 4390 } 4391 ieee80211_watchdog(ic); 4392} 4393 4394/* 4395 * Diagnostic interface to the HAL. This is used by various 4396 * tools to do things like retrieve register contents for 4397 * debugging. The mechanism is intentionally opaque so that 4398 * it can change frequently w/o concern for compatiblity. 4399 */ 4400static int 4401ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4402{ 4403 struct ath_hal *ah = sc->sc_ah; 4404 u_int id = ad->ad_id & ATH_DIAG_ID; 4405 void *indata = NULL; 4406 void *outdata = NULL; 4407 u_int32_t insize = ad->ad_in_size; 4408 u_int32_t outsize = ad->ad_out_size; 4409 int error = 0; 4410 4411 if (ad->ad_id & ATH_DIAG_IN) { 4412 /* 4413 * Copy in data. 4414 */ 4415 indata = malloc(insize, M_TEMP, M_NOWAIT); 4416 if (indata == NULL) { 4417 error = ENOMEM; 4418 goto bad; 4419 } 4420 error = copyin(ad->ad_in_data, indata, insize); 4421 if (error) 4422 goto bad; 4423 } 4424 if (ad->ad_id & ATH_DIAG_DYN) { 4425 /* 4426 * Allocate a buffer for the results (otherwise the HAL 4427 * returns a pointer to a buffer where we can read the 4428 * results). Note that we depend on the HAL leaving this 4429 * pointer for us to use below in reclaiming the buffer; 4430 * may want to be more defensive. 4431 */ 4432 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4433 if (outdata == NULL) { 4434 error = ENOMEM; 4435 goto bad; 4436 } 4437 } 4438 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4439 if (outsize < ad->ad_out_size) 4440 ad->ad_out_size = outsize; 4441 if (outdata != NULL) 4442 error = copyout(outdata, ad->ad_out_data, 4443 ad->ad_out_size); 4444 } else { 4445 error = EINVAL; 4446 } 4447bad: 4448 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4449 free(indata, M_TEMP); 4450 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4451 free(outdata, M_TEMP); 4452 return error; 4453} 4454 4455static int 4456ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4457{ 4458#define IS_RUNNING(ifp) \ 4459 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 4460 struct ath_softc *sc = ifp->if_softc; 4461 struct ieee80211com *ic = &sc->sc_ic; 4462 struct ifreq *ifr = (struct ifreq *)data; 4463 int error = 0; 4464 4465 ATH_LOCK(sc); 4466 switch (cmd) { 4467 case SIOCSIFFLAGS: 4468 if (IS_RUNNING(ifp)) { 4469 /* 4470 * To avoid rescanning another access point, 4471 * do not call ath_init() here. Instead, 4472 * only reflect promisc mode settings. 4473 */ 4474 ath_mode_init(sc); 4475 } else if (ifp->if_flags & IFF_UP) { 4476 /* 4477 * Beware of being called during attach/detach 4478 * to reset promiscuous mode. In that case we 4479 * will still be marked UP but not RUNNING. 4480 * However trying to re-init the interface 4481 * is the wrong thing to do as we've already 4482 * torn down much of our state. There's 4483 * probably a better way to deal with this. 4484 */ 4485 if (!sc->sc_invalid && ic->ic_bss != NULL) 4486 ath_init(ifp); /* XXX lose error */ 4487 } else 4488 ath_stop_locked(ifp); 4489 break; 4490 case SIOCADDMULTI: 4491 case SIOCDELMULTI: 4492 /* 4493 * The upper layer has already installed/removed 4494 * the multicast address(es), just recalculate the 4495 * multicast filter for the card. 4496 */ 4497 if (ifp->if_flags & IFF_RUNNING) 4498 ath_mode_init(sc); 4499 break; 4500 case SIOCGATHSTATS: 4501 /* NB: embed these numbers to get a consistent view */ 4502 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4503 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4504 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4505 ATH_UNLOCK(sc); 4506 /* 4507 * NB: Drop the softc lock in case of a page fault; 4508 * we'll accept any potential inconsisentcy in the 4509 * statistics. The alternative is to copy the data 4510 * to a local structure. 4511 */ 4512 return copyout(&sc->sc_stats, 4513 ifr->ifr_data, sizeof (sc->sc_stats)); 4514 case SIOCGATHDIAG: 4515 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4516 break; 4517 default: 4518 error = ieee80211_ioctl(ic, cmd, data); 4519 if (error == ENETRESET) { 4520 if (IS_RUNNING(ifp) && 4521 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4522 ath_init(ifp); /* XXX lose error */ 4523 error = 0; 4524 } 4525 if (error == ERESTART) 4526 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4527 break; 4528 } 4529 ATH_UNLOCK(sc); 4530 return error; 4531#undef IS_RUNNING 4532} 4533 4534static int 4535ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 4536{ 4537 struct ath_softc *sc = arg1; 4538 u_int slottime = ath_hal_getslottime(sc->sc_ah); 4539 int error; 4540 4541 error = sysctl_handle_int(oidp, &slottime, 0, req); 4542 if (error || !req->newptr) 4543 return error; 4544 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 4545} 4546 4547static int 4548ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 4549{ 4550 struct ath_softc *sc = arg1; 4551 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 4552 int error; 4553 4554 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 4555 if (error || !req->newptr) 4556 return error; 4557 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 4558} 4559 4560static int 4561ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 4562{ 4563 struct ath_softc *sc = arg1; 4564 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 4565 int error; 4566 4567 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 4568 if (error || !req->newptr) 4569 return error; 4570 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 4571} 4572 4573static int 4574ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 4575{ 4576 struct ath_softc *sc = arg1; 4577 int softled = sc->sc_softled; 4578 int error; 4579 4580 error = sysctl_handle_int(oidp, &softled, 0, req); 4581 if (error || !req->newptr) 4582 return error; 4583 softled = (softled != 0); 4584 if (softled != sc->sc_softled) { 4585 if (softled) { 4586 /* NB: handle any sc_ledpin change */ 4587 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 4588 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 4589 !sc->sc_ledon); 4590 } 4591 sc->sc_softled = softled; 4592 } 4593 return 0; 4594} 4595 4596static int 4597ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 4598{ 4599 struct ath_softc *sc = arg1; 4600 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 4601 int error; 4602 4603 error = sysctl_handle_int(oidp, &defantenna, 0, req); 4604 if (!error && req->newptr) 4605 ath_hal_setdefantenna(sc->sc_ah, defantenna); 4606 return error; 4607} 4608 4609static int 4610ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 4611{ 4612 struct ath_softc *sc = arg1; 4613 u_int diversity = sc->sc_diversity; 4614 int error; 4615 4616 error = sysctl_handle_int(oidp, &diversity, 0, req); 4617 if (error || !req->newptr) 4618 return error; 4619 sc->sc_diversity = diversity; 4620 return !ath_hal_setdiversity(sc->sc_ah, diversity) ? EINVAL : 0; 4621} 4622 4623static int 4624ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 4625{ 4626 struct ath_softc *sc = arg1; 4627 u_int32_t diag; 4628 int error; 4629 4630 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 4631 return EINVAL; 4632 error = sysctl_handle_int(oidp, &diag, 0, req); 4633 if (error || !req->newptr) 4634 return error; 4635 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 4636} 4637 4638static int 4639ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 4640{ 4641 struct ath_softc *sc = arg1; 4642 struct ifnet *ifp = &sc->sc_if; 4643 u_int32_t scale; 4644 int error; 4645 4646 ath_hal_gettpscale(sc->sc_ah, &scale); 4647 error = sysctl_handle_int(oidp, &scale, 0, req); 4648 if (error || !req->newptr) 4649 return error; 4650 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp); 4651} 4652 4653static int 4654ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 4655{ 4656 struct ath_softc *sc = arg1; 4657 u_int tpc = ath_hal_gettpc(sc->sc_ah); 4658 int error; 4659 4660 error = sysctl_handle_int(oidp, &tpc, 0, req); 4661 if (error || !req->newptr) 4662 return error; 4663 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 4664} 4665 4666static void 4667ath_sysctlattach(struct ath_softc *sc) 4668{ 4669 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 4670 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 4671 4672 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode); 4673 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4674 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0, 4675 "EEPROM country code"); 4676 ath_hal_getregdomain(sc->sc_ah, &sc->sc_regdomain); 4677 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4678 "regdomain", CTLFLAG_RD, &sc->sc_regdomain, 0, 4679 "EEPROM regdomain code"); 4680 sc->sc_debug = ath_debug; 4681 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4682 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 4683 "control debugging printfs"); 4684 4685 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4686 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4687 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 4688 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4689 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4690 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 4691 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4692 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4693 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 4694 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4695 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4696 ath_sysctl_softled, "I", "enable/disable software LED support"); 4697 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4698 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0, 4699 "GPIO pin connected to LED"); 4700 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4701 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 4702 "setting to turn LED on"); 4703 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4704 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 4705 "idle time for inactivity LED (ticks)"); 4706 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4707 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0, 4708 "tx antenna (0=auto)"); 4709 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4710 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4711 ath_sysctl_rxantenna, "I", "default/rx antenna"); 4712 if (sc->sc_hasdiversity) 4713 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4714 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4715 ath_sysctl_diversity, "I", "antenna diversity"); 4716 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 4717 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4718 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 4719 "tx descriptor batching"); 4720 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4721 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4722 ath_sysctl_diag, "I", "h/w diagnostic control"); 4723 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4724 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4725 ath_sysctl_tpscale, "I", "tx power scaling"); 4726 if (sc->sc_hastpc) 4727 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4728 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4729 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 4730} 4731 4732static void 4733ath_bpfattach(struct ath_softc *sc) 4734{ 4735 struct ifnet *ifp = &sc->sc_if; 4736 4737 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4738 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4739 &sc->sc_drvbpf); 4740 /* 4741 * Initialize constant fields. 4742 * XXX make header lengths a multiple of 32-bits so subsequent 4743 * headers are properly aligned; this is a kludge to keep 4744 * certain applications happy. 4745 * 4746 * NB: the channel is setup each time we transition to the 4747 * RUN state to avoid filling it in for each frame. 4748 */ 4749 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4750 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4751 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4752 4753 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4754 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4755 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4756} 4757 4758/* 4759 * Announce various information on device/driver attach. 4760 */ 4761static void 4762ath_announce(struct ath_softc *sc) 4763{ 4764#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4765 struct ifnet *ifp = &sc->sc_if; 4766 struct ath_hal *ah = sc->sc_ah; 4767 u_int modes, cc; 4768 4769 if_printf(ifp, "mac %d.%d phy %d.%d", 4770 ah->ah_macVersion, ah->ah_macRev, 4771 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4772 /* 4773 * Print radio revision(s). We check the wireless modes 4774 * to avoid falsely printing revs for inoperable parts. 4775 * Dual-band radio revs are returned in the 5Ghz rev number. 4776 */ 4777 ath_hal_getcountrycode(ah, &cc); 4778 modes = ath_hal_getwirelessmodes(ah, cc); 4779 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4780 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4781 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4782 ah->ah_analog5GhzRev >> 4, 4783 ah->ah_analog5GhzRev & 0xf, 4784 ah->ah_analog2GhzRev >> 4, 4785 ah->ah_analog2GhzRev & 0xf); 4786 else 4787 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4788 ah->ah_analog5GhzRev & 0xf); 4789 } else 4790 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4791 ah->ah_analog5GhzRev & 0xf); 4792 printf("\n"); 4793 if (bootverbose) { 4794 int i; 4795 for (i = 0; i <= WME_AC_VO; i++) { 4796 struct ath_txq *txq = sc->sc_ac2q[i]; 4797 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4798 txq->axq_qnum, ieee80211_wme_acnames[i]); 4799 } 4800 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4801 sc->sc_cabq->axq_qnum); 4802 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4803 } 4804#undef HAL_MODE_DUALBAND 4805} 4806