if_ath.c revision 140433
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 140433 2005-01-18 19:10:17Z sam $"); 39 40/* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47#include "opt_inet.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/sysctl.h> 52#include <sys/mbuf.h> 53#include <sys/malloc.h> 54#include <sys/lock.h> 55#include <sys/mutex.h> 56#include <sys/kernel.h> 57#include <sys/socket.h> 58#include <sys/sockio.h> 59#include <sys/errno.h> 60#include <sys/callout.h> 61#include <sys/bus.h> 62#include <sys/endian.h> 63 64#include <machine/bus.h> 65 66#include <net/if.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_arp.h> 70#include <net/ethernet.h> 71#include <net/if_llc.h> 72 73#include <net80211/ieee80211_var.h> 74 75#include <net/bpf.h> 76 77#ifdef INET 78#include <netinet/in.h> 79#include <netinet/if_ether.h> 80#endif 81 82#define AR_DEBUG 83#include <dev/ath/if_athvar.h> 84#include <contrib/dev/ath/ah_desc.h> 85#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 86 87/* unalligned little endian access */ 88#define LE_READ_2(p) \ 89 ((u_int16_t) \ 90 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 91#define LE_READ_4(p) \ 92 ((u_int32_t) \ 93 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 94 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 95 96enum { 97 ATH_LED_TX, 98 ATH_LED_RX, 99 ATH_LED_POLL, 100}; 101 102static void ath_init(void *); 103static void ath_stop_locked(struct ifnet *); 104static void ath_stop(struct ifnet *); 105static void ath_start(struct ifnet *); 106static int ath_reset(struct ifnet *); 107static int ath_media_change(struct ifnet *); 108static void ath_watchdog(struct ifnet *); 109static int ath_ioctl(struct ifnet *, u_long, caddr_t); 110static void ath_fatal_proc(void *, int); 111static void ath_rxorn_proc(void *, int); 112static void ath_bmiss_proc(void *, int); 113static void ath_initkeytable(struct ath_softc *); 114static int ath_key_alloc(struct ieee80211com *, 115 const struct ieee80211_key *); 116static int ath_key_delete(struct ieee80211com *, 117 const struct ieee80211_key *); 118static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 119 const u_int8_t mac[IEEE80211_ADDR_LEN]); 120static void ath_key_update_begin(struct ieee80211com *); 121static void ath_key_update_end(struct ieee80211com *); 122static void ath_mode_init(struct ath_softc *); 123static void ath_setslottime(struct ath_softc *); 124static void ath_updateslot(struct ifnet *); 125static int ath_beaconq_setup(struct ath_hal *); 126static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 127static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 128static void ath_beacon_proc(void *, int); 129static void ath_bstuck_proc(void *, int); 130static void ath_beacon_free(struct ath_softc *); 131static void ath_beacon_config(struct ath_softc *); 132static void ath_descdma_cleanup(struct ath_softc *sc, 133 struct ath_descdma *, ath_bufhead *); 134static int ath_desc_alloc(struct ath_softc *); 135static void ath_desc_free(struct ath_softc *); 136static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 137static void ath_node_free(struct ieee80211_node *); 138static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 139static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 140static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 141 struct ieee80211_node *ni, 142 int subtype, int rssi, u_int32_t rstamp); 143static void ath_setdefantenna(struct ath_softc *, u_int); 144static void ath_rx_proc(void *, int); 145static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 146static int ath_tx_setup(struct ath_softc *, int, int); 147static int ath_wme_update(struct ieee80211com *); 148static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 149static void ath_tx_cleanup(struct ath_softc *); 150static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 151 struct ath_buf *, struct mbuf *); 152static void ath_tx_proc_q0(void *, int); 153static void ath_tx_proc_q0123(void *, int); 154static void ath_tx_proc(void *, int); 155static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 156static void ath_draintxq(struct ath_softc *); 157static void ath_stoprecv(struct ath_softc *); 158static int ath_startrecv(struct ath_softc *); 159static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 160static void ath_next_scan(void *); 161static void ath_calibrate(void *); 162static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 163static void ath_newassoc(struct ieee80211com *, 164 struct ieee80211_node *, int); 165static int ath_getchannels(struct ath_softc *, u_int cc, 166 HAL_BOOL outdoor, HAL_BOOL xchanmode); 167static void ath_led_event(struct ath_softc *, int); 168static void ath_update_txpow(struct ath_softc *); 169 170static int ath_rate_setup(struct ath_softc *, u_int mode); 171static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 172 173static void ath_sysctlattach(struct ath_softc *); 174static void ath_bpfattach(struct ath_softc *); 175static void ath_announce(struct ath_softc *); 176 177SYSCTL_DECL(_hw_ath); 178 179/* XXX validate sysctl values */ 180static int ath_dwelltime = 200; /* 5 channels/second */ 181SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 182 0, "channel dwell time (ms) for AP/station scanning"); 183static int ath_calinterval = 30; /* calibrate every 30 secs */ 184SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 185 0, "chip calibration interval (secs)"); 186static int ath_outdoor = AH_TRUE; /* outdoor operation */ 187SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 188 0, "outdoor operation"); 189TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 190static int ath_xchanmode = AH_TRUE; /* extended channel use */ 191SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode, 192 0, "extended channel mode"); 193TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 194static int ath_countrycode = CTRY_DEFAULT; /* country code */ 195SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 196 0, "country code"); 197TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 198static int ath_regdomain = 0; /* regulatory domain */ 199SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 200 0, "regulatory domain"); 201 202#ifdef AR_DEBUG 203static int ath_debug = 0; 204SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 205 0, "control debugging printfs"); 206TUNABLE_INT("hw.ath.debug", &ath_debug); 207enum { 208 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 209 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 210 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 211 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 212 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 213 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 214 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 215 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 216 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 217 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 218 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 219 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 220 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 221 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 222 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 223 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 224 ATH_DEBUG_NODE = 0x00080000, /* node management */ 225 ATH_DEBUG_LED = 0x00100000, /* led management */ 226 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 227 ATH_DEBUG_ANY = 0xffffffff 228}; 229#define IFF_DUMPPKTS(sc, m) \ 230 ((sc->sc_debug & (m)) || \ 231 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 232#define DPRINTF(sc, m, fmt, ...) do { \ 233 if (sc->sc_debug & (m)) \ 234 printf(fmt, __VA_ARGS__); \ 235} while (0) 236#define KEYPRINTF(sc, ix, hk, mac) do { \ 237 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 238 ath_keyprint(__func__, ix, hk, mac); \ 239} while (0) 240static void ath_printrxbuf(struct ath_buf *bf, int); 241static void ath_printtxbuf(struct ath_buf *bf, int); 242#else 243#define IFF_DUMPPKTS(sc, m) \ 244 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245#define DPRINTF(m, fmt, ...) 246#define KEYPRINTF(sc, k, ix, mac) 247#endif 248 249MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 250 251int 252ath_attach(u_int16_t devid, struct ath_softc *sc) 253{ 254 struct ifnet *ifp = &sc->sc_if; 255 struct ieee80211com *ic = &sc->sc_ic; 256 struct ath_hal *ah; 257 HAL_STATUS status; 258 int error = 0, i; 259 260 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 261 262 /* set these up early for if_printf use */ 263 if_initname(ifp, device_get_name(sc->sc_dev), 264 device_get_unit(sc->sc_dev)); 265 266 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 267 if (ah == NULL) { 268 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 269 status); 270 error = ENXIO; 271 goto bad; 272 } 273 if (ah->ah_abi != HAL_ABI_VERSION) { 274 if_printf(ifp, "HAL ABI mismatch detected " 275 "(HAL:0x%x != driver:0x%x)\n", 276 ah->ah_abi, HAL_ABI_VERSION); 277 error = ENXIO; 278 goto bad; 279 } 280 sc->sc_ah = ah; 281 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 282 283 /* 284 * Check if the MAC has multi-rate retry support. 285 * We do this by trying to setup a fake extended 286 * descriptor. MAC's that don't have support will 287 * return false w/o doing anything. MAC's that do 288 * support it will return true w/o doing anything. 289 */ 290 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 291 292 /* 293 * Check if the device has hardware counters for PHY 294 * errors. If so we need to enable the MIB interrupt 295 * so we can act on stat triggers. 296 */ 297 if (ath_hal_hwphycounters(ah)) 298 sc->sc_needmib = 1; 299 300 /* 301 * Get the hardware key cache size. 302 */ 303 sc->sc_keymax = ath_hal_keycachesize(ah); 304 if (sc->sc_keymax > sizeof(sc->sc_keymap) * NBBY) { 305 if_printf(ifp, 306 "Warning, using only %zu of %u key cache slots\n", 307 sizeof(sc->sc_keymap) * NBBY, sc->sc_keymax); 308 sc->sc_keymax = sizeof(sc->sc_keymap) * NBBY; 309 } 310 /* 311 * Reset the key cache since some parts do not 312 * reset the contents on initial power up. 313 */ 314 for (i = 0; i < sc->sc_keymax; i++) 315 ath_hal_keyreset(ah, i); 316 /* 317 * Mark key cache slots associated with global keys 318 * as in use. If we knew TKIP was not to be used we 319 * could leave the +32, +64, and +32+64 slots free. 320 * XXX only for splitmic. 321 */ 322 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 323 setbit(sc->sc_keymap, i); 324 setbit(sc->sc_keymap, i+32); 325 setbit(sc->sc_keymap, i+64); 326 setbit(sc->sc_keymap, i+32+64); 327 } 328 329 /* 330 * Collect the channel list using the default country 331 * code and including outdoor channels. The 802.11 layer 332 * is resposible for filtering this list based on settings 333 * like the phy mode. 334 */ 335 error = ath_getchannels(sc, ath_countrycode, 336 ath_outdoor, ath_xchanmode); 337 if (error != 0) 338 goto bad; 339 /* 340 * Setup dynamic sysctl's now that country code and 341 * regdomain are available from the hal. 342 */ 343 ath_sysctlattach(sc); 344 345 /* 346 * Setup rate tables for all potential media types. 347 */ 348 ath_rate_setup(sc, IEEE80211_MODE_11A); 349 ath_rate_setup(sc, IEEE80211_MODE_11B); 350 ath_rate_setup(sc, IEEE80211_MODE_11G); 351 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 352 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 353 /* NB: setup here so ath_rate_update is happy */ 354 ath_setcurmode(sc, IEEE80211_MODE_11A); 355 356 /* 357 * Allocate tx+rx descriptors and populate the lists. 358 */ 359 error = ath_desc_alloc(sc); 360 if (error != 0) { 361 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 362 goto bad; 363 } 364 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 365 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 366 367 ATH_TXBUF_LOCK_INIT(sc); 368 369 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 370 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 371 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 372 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 373 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 374 375 /* 376 * Allocate hardware transmit queues: one queue for 377 * beacon frames and one data queue for each QoS 378 * priority. Note that the hal handles reseting 379 * these queues at the needed time. 380 * 381 * XXX PS-Poll 382 */ 383 sc->sc_bhalq = ath_beaconq_setup(ah); 384 if (sc->sc_bhalq == (u_int) -1) { 385 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 386 error = EIO; 387 goto bad2; 388 } 389 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 390 if (sc->sc_cabq == NULL) { 391 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 392 error = EIO; 393 goto bad2; 394 } 395 /* NB: insure BK queue is the lowest priority h/w queue */ 396 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 397 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 398 ieee80211_wme_acnames[WME_AC_BK]); 399 error = EIO; 400 goto bad2; 401 } 402 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 403 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 404 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 405 /* 406 * Not enough hardware tx queues to properly do WME; 407 * just punt and assign them all to the same h/w queue. 408 * We could do a better job of this if, for example, 409 * we allocate queues when we switch from station to 410 * AP mode. 411 */ 412 if (sc->sc_ac2q[WME_AC_VI] != NULL) 413 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 414 if (sc->sc_ac2q[WME_AC_BE] != NULL) 415 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 416 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 417 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 418 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 419 } 420 421 /* 422 * Special case certain configurations. Note the 423 * CAB queue is handled by these specially so don't 424 * include them when checking the txq setup mask. 425 */ 426 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 427 case 0x01: 428 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 429 break; 430 case 0x0f: 431 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 432 break; 433 default: 434 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 435 break; 436 } 437 438 /* 439 * Setup rate control. Some rate control modules 440 * call back to change the anntena state so expose 441 * the necessary entry points. 442 * XXX maybe belongs in struct ath_ratectrl? 443 */ 444 sc->sc_setdefantenna = ath_setdefantenna; 445 sc->sc_rc = ath_rate_attach(sc); 446 if (sc->sc_rc == NULL) { 447 error = EIO; 448 goto bad2; 449 } 450 451 sc->sc_blinking = 0; 452 sc->sc_ledstate = 1; 453 sc->sc_ledon = 0; /* low true */ 454 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 455 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 456 /* 457 * Auto-enable soft led processing for IBM cards and for 458 * 5211 minipci cards. Users can also manually enable/disable 459 * support with a sysctl. 460 */ 461 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 462 if (sc->sc_softled) { 463 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 464 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 465 } 466 467 ifp->if_softc = sc; 468 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 469 ifp->if_start = ath_start; 470 ifp->if_watchdog = ath_watchdog; 471 ifp->if_ioctl = ath_ioctl; 472 ifp->if_init = ath_init; 473 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 474 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 475 IFQ_SET_READY(&ifp->if_snd); 476 477 ic->ic_ifp = ifp; 478 ic->ic_reset = ath_reset; 479 ic->ic_newassoc = ath_newassoc; 480 ic->ic_updateslot = ath_updateslot; 481 ic->ic_wme.wme_update = ath_wme_update; 482 /* XXX not right but it's not used anywhere important */ 483 ic->ic_phytype = IEEE80211_T_OFDM; 484 ic->ic_opmode = IEEE80211_M_STA; 485 ic->ic_caps = 486 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 487 | IEEE80211_C_HOSTAP /* hostap mode */ 488 | IEEE80211_C_MONITOR /* monitor mode */ 489 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 490 | IEEE80211_C_SHSLOT /* short slot time supported */ 491 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 492 ; 493 /* 494 * Query the hal to figure out h/w crypto support. 495 */ 496 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 497 ic->ic_caps |= IEEE80211_C_WEP; 498 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 499 ic->ic_caps |= IEEE80211_C_AES; 500 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 501 ic->ic_caps |= IEEE80211_C_AES_CCM; 502 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 503 ic->ic_caps |= IEEE80211_C_CKIP; 504 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 505 ic->ic_caps |= IEEE80211_C_TKIP; 506 /* 507 * Check if h/w does the MIC and/or whether the 508 * separate key cache entries are required to 509 * handle both tx+rx MIC keys. 510 */ 511 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 512 ic->ic_caps |= IEEE80211_C_TKIPMIC; 513 if (ath_hal_tkipsplit(ah)) 514 sc->sc_splitmic = 1; 515 } 516 /* 517 * TPC support can be done either with a global cap or 518 * per-packet support. The latter is not available on 519 * all parts. We're a bit pedantic here as all parts 520 * support a global cap. 521 */ 522 sc->sc_hastpc = ath_hal_hastpc(ah); 523 if (sc->sc_hastpc || ath_hal_hastxpowlimit(ah)) 524 ic->ic_caps |= IEEE80211_C_TXPMGT; 525 526 /* 527 * Mark WME capability only if we have sufficient 528 * hardware queues to do proper priority scheduling. 529 */ 530 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 531 ic->ic_caps |= IEEE80211_C_WME; 532 /* 533 * Check for frame bursting capability. 534 */ 535 if (ath_hal_hasbursting(ah)) 536 ic->ic_caps |= IEEE80211_C_BURST; 537 538 /* 539 * Indicate we need the 802.11 header padded to a 540 * 32-bit boundary for 4-address and QoS frames. 541 */ 542 ic->ic_flags |= IEEE80211_F_DATAPAD; 543 544 /* 545 * Query the hal about antenna support. 546 */ 547 if (ath_hal_hasdiversity(ah)) { 548 sc->sc_hasdiversity = 1; 549 sc->sc_diversity = ath_hal_getdiversity(ah); 550 } 551 sc->sc_defant = ath_hal_getdefantenna(ah); 552 553 /* 554 * Not all chips have the VEOL support we want to 555 * use with IBSS beacons; check here for it. 556 */ 557 sc->sc_hasveol = ath_hal_hasveol(ah); 558 559 /* get mac address from hardware */ 560 ath_hal_getmac(ah, ic->ic_myaddr); 561 562 /* call MI attach routine. */ 563 ieee80211_ifattach(ic); 564 /* override default methods */ 565 ic->ic_node_alloc = ath_node_alloc; 566 sc->sc_node_free = ic->ic_node_free; 567 ic->ic_node_free = ath_node_free; 568 ic->ic_node_getrssi = ath_node_getrssi; 569 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 570 ic->ic_recv_mgmt = ath_recv_mgmt; 571 sc->sc_newstate = ic->ic_newstate; 572 ic->ic_newstate = ath_newstate; 573 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 574 ic->ic_crypto.cs_key_delete = ath_key_delete; 575 ic->ic_crypto.cs_key_set = ath_key_set; 576 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 577 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 578 /* complete initialization */ 579 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 580 581 ath_bpfattach(sc); 582 583 if (bootverbose) 584 ieee80211_announce(ic); 585 ath_announce(sc); 586 return 0; 587bad2: 588 ath_tx_cleanup(sc); 589 ath_desc_free(sc); 590bad: 591 if (ah) 592 ath_hal_detach(ah); 593 sc->sc_invalid = 1; 594 return error; 595} 596 597int 598ath_detach(struct ath_softc *sc) 599{ 600 struct ifnet *ifp = &sc->sc_if; 601 602 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 603 __func__, ifp->if_flags); 604 605 ath_stop(ifp); 606 bpfdetach(ifp); 607 /* 608 * NB: the order of these is important: 609 * o call the 802.11 layer before detaching the hal to 610 * insure callbacks into the driver to delete global 611 * key cache entries can be handled 612 * o reclaim the tx queue data structures after calling 613 * the 802.11 layer as we'll get called back to reclaim 614 * node state and potentially want to use them 615 * o to cleanup the tx queues the hal is called, so detach 616 * it last 617 * Other than that, it's straightforward... 618 */ 619 ieee80211_ifdetach(&sc->sc_ic); 620 ath_rate_detach(sc->sc_rc); 621 ath_desc_free(sc); 622 ath_tx_cleanup(sc); 623 ath_hal_detach(sc->sc_ah); 624 625 return 0; 626} 627 628void 629ath_suspend(struct ath_softc *sc) 630{ 631 struct ifnet *ifp = &sc->sc_if; 632 633 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 634 __func__, ifp->if_flags); 635 636 ath_stop(ifp); 637} 638 639void 640ath_resume(struct ath_softc *sc) 641{ 642 struct ifnet *ifp = &sc->sc_if; 643 644 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 645 __func__, ifp->if_flags); 646 647 if (ifp->if_flags & IFF_UP) { 648 ath_init(ifp); 649 if (ifp->if_flags & IFF_RUNNING) 650 ath_start(ifp); 651 } 652} 653 654void 655ath_shutdown(struct ath_softc *sc) 656{ 657 struct ifnet *ifp = &sc->sc_if; 658 659 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 660 __func__, ifp->if_flags); 661 662 ath_stop(ifp); 663} 664 665/* 666 * Interrupt handler. Most of the actual processing is deferred. 667 */ 668void 669ath_intr(void *arg) 670{ 671 struct ath_softc *sc = arg; 672 struct ifnet *ifp = &sc->sc_if; 673 struct ath_hal *ah = sc->sc_ah; 674 HAL_INT status; 675 676 if (sc->sc_invalid) { 677 /* 678 * The hardware is not ready/present, don't touch anything. 679 * Note this can happen early on if the IRQ is shared. 680 */ 681 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 682 return; 683 } 684 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 685 return; 686 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 687 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 688 __func__, ifp->if_flags); 689 ath_hal_getisr(ah, &status); /* clear ISR */ 690 ath_hal_intrset(ah, 0); /* disable further intr's */ 691 return; 692 } 693 /* 694 * Figure out the reason(s) for the interrupt. Note 695 * that the hal returns a pseudo-ISR that may include 696 * bits we haven't explicitly enabled so we mask the 697 * value to insure we only process bits we requested. 698 */ 699 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 700 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 701 status &= sc->sc_imask; /* discard unasked for bits */ 702 if (status & HAL_INT_FATAL) { 703 /* 704 * Fatal errors are unrecoverable. Typically 705 * these are caused by DMA errors. Unfortunately 706 * the exact reason is not (presently) returned 707 * by the hal. 708 */ 709 sc->sc_stats.ast_hardware++; 710 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 711 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 712 } else if (status & HAL_INT_RXORN) { 713 sc->sc_stats.ast_rxorn++; 714 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 715 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 716 } else { 717 if (status & HAL_INT_SWBA) { 718 /* 719 * Software beacon alert--time to send a beacon. 720 * Handle beacon transmission directly; deferring 721 * this is too slow to meet timing constraints 722 * under load. 723 */ 724 ath_beacon_proc(sc, 0); 725 } 726 if (status & HAL_INT_RXEOL) { 727 /* 728 * NB: the hardware should re-read the link when 729 * RXE bit is written, but it doesn't work at 730 * least on older hardware revs. 731 */ 732 sc->sc_stats.ast_rxeol++; 733 sc->sc_rxlink = NULL; 734 } 735 if (status & HAL_INT_TXURN) { 736 sc->sc_stats.ast_txurn++; 737 /* bump tx trigger level */ 738 ath_hal_updatetxtriglevel(ah, AH_TRUE); 739 } 740 if (status & HAL_INT_RX) 741 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 742 if (status & HAL_INT_TX) 743 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 744 if (status & HAL_INT_BMISS) { 745 sc->sc_stats.ast_bmiss++; 746 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 747 } 748 if (status & HAL_INT_MIB) { 749 sc->sc_stats.ast_mib++; 750 /* 751 * Disable interrupts until we service the MIB 752 * interrupt; otherwise it will continue to fire. 753 */ 754 ath_hal_intrset(ah, 0); 755 /* 756 * Let the hal handle the event. We assume it will 757 * clear whatever condition caused the interrupt. 758 */ 759 ath_hal_mibevent(ah, 760 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 761 ath_hal_intrset(ah, sc->sc_imask); 762 } 763 } 764} 765 766static void 767ath_fatal_proc(void *arg, int pending) 768{ 769 struct ath_softc *sc = arg; 770 struct ifnet *ifp = &sc->sc_if; 771 772 if_printf(ifp, "hardware error; resetting\n"); 773 ath_reset(ifp); 774} 775 776static void 777ath_rxorn_proc(void *arg, int pending) 778{ 779 struct ath_softc *sc = arg; 780 struct ifnet *ifp = &sc->sc_if; 781 782 if_printf(ifp, "rx FIFO overrun; resetting\n"); 783 ath_reset(ifp); 784} 785 786static void 787ath_bmiss_proc(void *arg, int pending) 788{ 789 struct ath_softc *sc = arg; 790 struct ieee80211com *ic = &sc->sc_ic; 791 792 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 793 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 794 ("unexpect operating mode %u", ic->ic_opmode)); 795 if (ic->ic_state == IEEE80211_S_RUN) { 796 /* 797 * Rather than go directly to scan state, try to 798 * reassociate first. If that fails then the state 799 * machine will drop us into scanning after timing 800 * out waiting for a probe response. 801 */ 802 NET_LOCK_GIANT(); 803 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 804 NET_UNLOCK_GIANT(); 805 } 806} 807 808static u_int 809ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 810{ 811#define N(a) (sizeof(a) / sizeof(a[0])) 812 static const u_int modeflags[] = { 813 0, /* IEEE80211_MODE_AUTO */ 814 CHANNEL_A, /* IEEE80211_MODE_11A */ 815 CHANNEL_B, /* IEEE80211_MODE_11B */ 816 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 817 0, /* IEEE80211_MODE_FH */ 818 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 819 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 820 }; 821 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 822 823 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 824 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 825 return modeflags[mode]; 826#undef N 827} 828 829static void 830ath_init(void *arg) 831{ 832 struct ath_softc *sc = (struct ath_softc *) arg; 833 struct ieee80211com *ic = &sc->sc_ic; 834 struct ifnet *ifp = &sc->sc_if; 835 struct ieee80211_node *ni; 836 struct ath_hal *ah = sc->sc_ah; 837 HAL_STATUS status; 838 839 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 840 __func__, ifp->if_flags); 841 842 ATH_LOCK(sc); 843 /* 844 * Stop anything previously setup. This is safe 845 * whether this is the first time through or not. 846 */ 847 ath_stop_locked(ifp); 848 849 /* 850 * The basic interface to setting the hardware in a good 851 * state is ``reset''. On return the hardware is known to 852 * be powered up and with interrupts disabled. This must 853 * be followed by initialization of the appropriate bits 854 * and then setup of the interrupt mask. 855 */ 856 sc->sc_curchan.channel = ic->ic_ibss_chan->ic_freq; 857 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 858 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 859 if_printf(ifp, "unable to reset hardware; hal status %u\n", 860 status); 861 goto done; 862 } 863 864 /* 865 * This is needed only to setup initial state 866 * but it's best done after a reset. 867 */ 868 ath_update_txpow(sc); 869 870 /* 871 * Setup the hardware after reset: the key cache 872 * is filled as needed and the receive engine is 873 * set going. Frame transmit is handled entirely 874 * in the frame output path; there's nothing to do 875 * here except setup the interrupt mask. 876 */ 877 ath_initkeytable(sc); /* XXX still needed? */ 878 if (ath_startrecv(sc) != 0) { 879 if_printf(ifp, "unable to start recv logic\n"); 880 goto done; 881 } 882 883 /* 884 * Enable interrupts. 885 */ 886 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 887 | HAL_INT_RXEOL | HAL_INT_RXORN 888 | HAL_INT_FATAL | HAL_INT_GLOBAL; 889 /* 890 * Enable MIB interrupts when there are hardware phy counters. 891 * Note we only do this (at the moment) for station mode. 892 */ 893 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 894 sc->sc_imask |= HAL_INT_MIB; 895 ath_hal_intrset(ah, sc->sc_imask); 896 897 ifp->if_flags |= IFF_RUNNING; 898 ic->ic_state = IEEE80211_S_INIT; 899 900 /* 901 * The hardware should be ready to go now so it's safe 902 * to kick the 802.11 state machine as it's likely to 903 * immediately call back to us to send mgmt frames. 904 */ 905 ni = ic->ic_bss; 906 ni->ni_chan = ic->ic_ibss_chan; 907 ath_chan_change(sc, ni->ni_chan); 908 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 909 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 910 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 911 } else 912 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 913done: 914 ATH_UNLOCK(sc); 915} 916 917static void 918ath_stop_locked(struct ifnet *ifp) 919{ 920 struct ath_softc *sc = ifp->if_softc; 921 struct ieee80211com *ic = &sc->sc_ic; 922 struct ath_hal *ah = sc->sc_ah; 923 924 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 925 __func__, sc->sc_invalid, ifp->if_flags); 926 927 ATH_LOCK_ASSERT(sc); 928 if (ifp->if_flags & IFF_RUNNING) { 929 /* 930 * Shutdown the hardware and driver: 931 * reset 802.11 state machine 932 * turn off timers 933 * disable interrupts 934 * turn off the radio 935 * clear transmit machinery 936 * clear receive machinery 937 * drain and release tx queues 938 * reclaim beacon resources 939 * power down hardware 940 * 941 * Note that some of this work is not possible if the 942 * hardware is gone (invalid). 943 */ 944 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 945 ifp->if_flags &= ~IFF_RUNNING; 946 ifp->if_timer = 0; 947 if (!sc->sc_invalid) { 948 if (sc->sc_softled) { 949 callout_stop(&sc->sc_ledtimer); 950 ath_hal_gpioset(ah, sc->sc_ledpin, 951 !sc->sc_ledon); 952 sc->sc_blinking = 0; 953 } 954 ath_hal_intrset(ah, 0); 955 } 956 ath_draintxq(sc); 957 if (!sc->sc_invalid) { 958 ath_stoprecv(sc); 959 ath_hal_phydisable(ah); 960 } else 961 sc->sc_rxlink = NULL; 962 IFQ_DRV_PURGE(&ifp->if_snd); 963 ath_beacon_free(sc); 964 } 965} 966 967static void 968ath_stop(struct ifnet *ifp) 969{ 970 struct ath_softc *sc = ifp->if_softc; 971 972 ATH_LOCK(sc); 973 ath_stop_locked(ifp); 974 if (!sc->sc_invalid) { 975 /* 976 * Set the chip in full sleep mode. Note that we are 977 * careful to do this only when bringing the interface 978 * completely to a stop. When the chip is in this state 979 * it must be carefully woken up or references to 980 * registers in the PCI clock domain may freeze the bus 981 * (and system). This varies by chip and is mostly an 982 * issue with newer parts that go to sleep more quickly. 983 */ 984 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 985 } 986 ATH_UNLOCK(sc); 987} 988 989/* 990 * Reset the hardware w/o losing operational state. This is 991 * basically a more efficient way of doing ath_stop, ath_init, 992 * followed by state transitions to the current 802.11 993 * operational state. Used to recover from various errors and 994 * to reset or reload hardware state. 995 */ 996static int 997ath_reset(struct ifnet *ifp) 998{ 999 struct ath_softc *sc = ifp->if_softc; 1000 struct ieee80211com *ic = &sc->sc_ic; 1001 struct ath_hal *ah = sc->sc_ah; 1002 struct ieee80211_channel *c; 1003 HAL_STATUS status; 1004 1005 /* 1006 * Convert to a HAL channel description with the flags 1007 * constrained to reflect the current operating mode. 1008 */ 1009 c = ic->ic_ibss_chan; 1010 sc->sc_curchan.channel = c->ic_freq; 1011 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1012 1013 ath_hal_intrset(ah, 0); /* disable interrupts */ 1014 ath_draintxq(sc); /* stop xmit side */ 1015 ath_stoprecv(sc); /* stop recv side */ 1016 /* NB: indicate channel change so we do a full reset */ 1017 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1018 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1019 __func__, status); 1020 ath_update_txpow(sc); /* update tx power state */ 1021 if (ath_startrecv(sc) != 0) /* restart recv */ 1022 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1023 /* 1024 * We may be doing a reset in response to an ioctl 1025 * that changes the channel so update any state that 1026 * might change as a result. 1027 */ 1028 ath_chan_change(sc, c); 1029 if (ic->ic_state == IEEE80211_S_RUN) 1030 ath_beacon_config(sc); /* restart beacons */ 1031 ath_hal_intrset(ah, sc->sc_imask); 1032 1033 ath_start(ifp); /* restart xmit */ 1034 return 0; 1035} 1036 1037static void 1038ath_start(struct ifnet *ifp) 1039{ 1040 struct ath_softc *sc = ifp->if_softc; 1041 struct ath_hal *ah = sc->sc_ah; 1042 struct ieee80211com *ic = &sc->sc_ic; 1043 struct ieee80211_node *ni; 1044 struct ath_buf *bf; 1045 struct mbuf *m; 1046 struct ieee80211_frame *wh; 1047 struct ether_header *eh; 1048 1049 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1050 return; 1051 for (;;) { 1052 /* 1053 * Grab a TX buffer and associated resources. 1054 */ 1055 ATH_TXBUF_LOCK(sc); 1056 bf = STAILQ_FIRST(&sc->sc_txbuf); 1057 if (bf != NULL) 1058 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1059 ATH_TXBUF_UNLOCK(sc); 1060 if (bf == NULL) { 1061 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1062 __func__); 1063 sc->sc_stats.ast_tx_qstop++; 1064 ifp->if_flags |= IFF_OACTIVE; 1065 break; 1066 } 1067 /* 1068 * Poll the management queue for frames; they 1069 * have priority over normal data frames. 1070 */ 1071 IF_DEQUEUE(&ic->ic_mgtq, m); 1072 if (m == NULL) { 1073 /* 1074 * No data frames go out unless we're associated. 1075 */ 1076 if (ic->ic_state != IEEE80211_S_RUN) { 1077 DPRINTF(sc, ATH_DEBUG_ANY, 1078 "%s: ignore data packet, state %u\n", 1079 __func__, ic->ic_state); 1080 sc->sc_stats.ast_tx_discard++; 1081 ATH_TXBUF_LOCK(sc); 1082 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1083 ATH_TXBUF_UNLOCK(sc); 1084 break; 1085 } 1086 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1087 if (m == NULL) { 1088 ATH_TXBUF_LOCK(sc); 1089 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1090 ATH_TXBUF_UNLOCK(sc); 1091 break; 1092 } 1093 /* 1094 * Find the node for the destination so we can do 1095 * things like power save and fast frames aggregation. 1096 */ 1097 if (m->m_len < sizeof(struct ether_header) && 1098 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1099 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1100 ni = NULL; 1101 goto bad; 1102 } 1103 eh = mtod(m, struct ether_header *); 1104 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1105 if (ni == NULL) { 1106 /* NB: ieee80211_find_txnode does stat+msg */ 1107 goto bad; 1108 } 1109 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1110 (m->m_flags & M_PWR_SAV) == 0) { 1111 /* 1112 * Station in power save mode; pass the frame 1113 * to the 802.11 layer and continue. We'll get 1114 * the frame back when the time is right. 1115 */ 1116 ieee80211_pwrsave(ic, ni, m); 1117 goto reclaim; 1118 } 1119 /* calculate priority so we can find the tx queue */ 1120 if (ieee80211_classify(ic, m, ni)) { 1121 DPRINTF(sc, ATH_DEBUG_XMIT, 1122 "%s: discard, classification failure\n", 1123 __func__); 1124 goto bad; 1125 } 1126 ifp->if_opackets++; 1127 BPF_MTAP(ifp, m); 1128 /* 1129 * Encapsulate the packet in prep for transmission. 1130 */ 1131 m = ieee80211_encap(ic, m, ni); 1132 if (m == NULL) { 1133 DPRINTF(sc, ATH_DEBUG_ANY, 1134 "%s: encapsulation failure\n", 1135 __func__); 1136 sc->sc_stats.ast_tx_encap++; 1137 goto bad; 1138 } 1139 } else { 1140 /* 1141 * Hack! The referenced node pointer is in the 1142 * rcvif field of the packet header. This is 1143 * placed there by ieee80211_mgmt_output because 1144 * we need to hold the reference with the frame 1145 * and there's no other way (other than packet 1146 * tags which we consider too expensive to use) 1147 * to pass it along. 1148 */ 1149 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1150 m->m_pkthdr.rcvif = NULL; 1151 1152 wh = mtod(m, struct ieee80211_frame *); 1153 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1154 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1155 /* fill time stamp */ 1156 u_int64_t tsf; 1157 u_int32_t *tstamp; 1158 1159 tsf = ath_hal_gettsf64(ah); 1160 /* XXX: adjust 100us delay to xmit */ 1161 tsf += 100; 1162 tstamp = (u_int32_t *)&wh[1]; 1163 tstamp[0] = htole32(tsf & 0xffffffff); 1164 tstamp[1] = htole32(tsf >> 32); 1165 } 1166 sc->sc_stats.ast_tx_mgmt++; 1167 } 1168 1169 if (ath_tx_start(sc, ni, bf, m)) { 1170 bad: 1171 ifp->if_oerrors++; 1172 reclaim: 1173 ATH_TXBUF_LOCK(sc); 1174 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1175 ATH_TXBUF_UNLOCK(sc); 1176 if (ni != NULL) 1177 ieee80211_free_node(ni); 1178 continue; 1179 } 1180 1181 sc->sc_tx_timer = 5; 1182 ifp->if_timer = 1; 1183 } 1184} 1185 1186static int 1187ath_media_change(struct ifnet *ifp) 1188{ 1189#define IS_UP(ifp) \ 1190 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 1191 int error; 1192 1193 error = ieee80211_media_change(ifp); 1194 if (error == ENETRESET) { 1195 if (IS_UP(ifp)) 1196 ath_init(ifp); /* XXX lose error */ 1197 error = 0; 1198 } 1199 return error; 1200#undef IS_UP 1201} 1202 1203#ifdef AR_DEBUG 1204static void 1205ath_keyprint(const char *tag, u_int ix, 1206 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1207{ 1208 static const char *ciphers[] = { 1209 "WEP", 1210 "AES-OCB", 1211 "AES-CCM", 1212 "CKIP", 1213 "TKIP", 1214 "CLR", 1215 }; 1216 int i, n; 1217 1218 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1219 for (i = 0, n = hk->kv_len; i < n; i++) 1220 printf("%02x", hk->kv_val[i]); 1221 printf(" mac %s", ether_sprintf(mac)); 1222 if (hk->kv_type == HAL_CIPHER_TKIP) { 1223 printf(" mic "); 1224 for (i = 0; i < sizeof(hk->kv_mic); i++) 1225 printf("%02x", hk->kv_mic[i]); 1226 } 1227 printf("\n"); 1228} 1229#endif 1230 1231/* 1232 * Set a TKIP key into the hardware. This handles the 1233 * potential distribution of key state to multiple key 1234 * cache slots for TKIP. 1235 */ 1236static int 1237ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1238 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1239{ 1240#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1241 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1242 struct ath_hal *ah = sc->sc_ah; 1243 1244 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1245 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1246 KASSERT(sc->sc_splitmic, ("key cache !split")); 1247 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1248 /* 1249 * TX key goes at first index, RX key at +32. 1250 * The hal handles the MIC keys at index+64. 1251 */ 1252 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1253 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1254 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1255 return 0; 1256 1257 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1258 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1259 /* XXX delete tx key on failure? */ 1260 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1261 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1262 /* 1263 * TX/RX key goes at first index. 1264 * The hal handles the MIC keys are index+64. 1265 */ 1266 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID, 1267 ("group key at index %u", k->wk_keyix)); 1268 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1269 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1270 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1271 return ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid); 1272 } 1273 /* XXX key w/o xmit/recv; need this for compression? */ 1274 return 0; 1275#undef IEEE80211_KEY_XR 1276} 1277 1278/* 1279 * Set a net80211 key into the hardware. This handles the 1280 * potential distribution of key state to multiple key 1281 * cache slots for TKIP with hardware MIC support. 1282 */ 1283static int 1284ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1285 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1286{ 1287#define N(a) (sizeof(a)/sizeof(a[0])) 1288 static const u_int8_t ciphermap[] = { 1289 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1290 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1291 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1292 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1293 (u_int8_t) -1, /* 4 is not allocated */ 1294 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1295 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1296 }; 1297 struct ath_hal *ah = sc->sc_ah; 1298 const struct ieee80211_cipher *cip = k->wk_cipher; 1299 HAL_KEYVAL hk; 1300 1301 memset(&hk, 0, sizeof(hk)); 1302 /* 1303 * Software crypto uses a "clear key" so non-crypto 1304 * state kept in the key cache are maintained and 1305 * so that rx frames have an entry to match. 1306 */ 1307 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1308 KASSERT(cip->ic_cipher < N(ciphermap), 1309 ("invalid cipher type %u", cip->ic_cipher)); 1310 hk.kv_type = ciphermap[cip->ic_cipher]; 1311 hk.kv_len = k->wk_keylen; 1312 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1313 } else 1314 hk.kv_type = HAL_CIPHER_CLR; 1315 1316 if (hk.kv_type == HAL_CIPHER_TKIP && 1317 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1318 sc->sc_splitmic) { 1319 return ath_keyset_tkip(sc, k, &hk, mac); 1320 } else { 1321 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1322 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1323 } 1324#undef N 1325} 1326 1327/* 1328 * Fill the hardware key cache with key entries. 1329 */ 1330static void 1331ath_initkeytable(struct ath_softc *sc) 1332{ 1333 struct ieee80211com *ic = &sc->sc_ic; 1334 struct ifnet *ifp = &sc->sc_if; 1335 struct ath_hal *ah = sc->sc_ah; 1336 const u_int8_t *bssid; 1337 int i; 1338 1339 /* XXX maybe should reset all keys when !PRIVACY */ 1340 if (ic->ic_state == IEEE80211_S_SCAN) 1341 bssid = ifp->if_broadcastaddr; 1342 else 1343 bssid = ic->ic_bss->ni_bssid; 1344 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1345 struct ieee80211_key *k = &ic->ic_nw_keys[i]; 1346 1347 if (k->wk_keylen == 0) { 1348 ath_hal_keyreset(ah, i); 1349 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: reset key %u\n", 1350 __func__, i); 1351 } else { 1352 ath_keyset(sc, k, bssid); 1353 } 1354 } 1355} 1356 1357/* 1358 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1359 * each key, one for decrypt/encrypt and the other for the MIC. 1360 */ 1361static u_int16_t 1362key_alloc_2pair(struct ath_softc *sc) 1363{ 1364#define N(a) (sizeof(a)/sizeof(a[0])) 1365 u_int i, keyix; 1366 1367 KASSERT(sc->sc_splitmic, ("key cache !split")); 1368 /* XXX could optimize */ 1369 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1370 u_int8_t b = sc->sc_keymap[i]; 1371 if (b != 0xff) { 1372 /* 1373 * One or more slots in this byte are free. 1374 */ 1375 keyix = i*NBBY; 1376 while (b & 1) { 1377 again: 1378 keyix++; 1379 b >>= 1; 1380 } 1381 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1382 if (isset(sc->sc_keymap, keyix+32) || 1383 isset(sc->sc_keymap, keyix+64) || 1384 isset(sc->sc_keymap, keyix+32+64)) { 1385 /* full pair unavailable */ 1386 /* XXX statistic */ 1387 if (keyix == (i+1)*NBBY) { 1388 /* no slots were appropriate, advance */ 1389 continue; 1390 } 1391 goto again; 1392 } 1393 setbit(sc->sc_keymap, keyix); 1394 setbit(sc->sc_keymap, keyix+64); 1395 setbit(sc->sc_keymap, keyix+32); 1396 setbit(sc->sc_keymap, keyix+32+64); 1397 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1398 "%s: key pair %u,%u %u,%u\n", 1399 __func__, keyix, keyix+64, 1400 keyix+32, keyix+32+64); 1401 return keyix; 1402 } 1403 } 1404 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1405 return IEEE80211_KEYIX_NONE; 1406#undef N 1407} 1408 1409/* 1410 * Allocate a single key cache slot. 1411 */ 1412static u_int16_t 1413key_alloc_single(struct ath_softc *sc) 1414{ 1415#define N(a) (sizeof(a)/sizeof(a[0])) 1416 u_int i, keyix; 1417 1418 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1419 for (i = 0; i < N(sc->sc_keymap); i++) { 1420 u_int8_t b = sc->sc_keymap[i]; 1421 if (b != 0xff) { 1422 /* 1423 * One or more slots are free. 1424 */ 1425 keyix = i*NBBY; 1426 while (b & 1) 1427 keyix++, b >>= 1; 1428 setbit(sc->sc_keymap, keyix); 1429 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1430 __func__, keyix); 1431 return keyix; 1432 } 1433 } 1434 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1435 return IEEE80211_KEYIX_NONE; 1436#undef N 1437} 1438 1439/* 1440 * Allocate one or more key cache slots for a uniacst key. The 1441 * key itself is needed only to identify the cipher. For hardware 1442 * TKIP with split cipher+MIC keys we allocate two key cache slot 1443 * pairs so that we can setup separate TX and RX MIC keys. Note 1444 * that the MIC key for a TKIP key at slot i is assumed by the 1445 * hardware to be at slot i+64. This limits TKIP keys to the first 1446 * 64 entries. 1447 */ 1448static int 1449ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k) 1450{ 1451 struct ath_softc *sc = ic->ic_ifp->if_softc; 1452 1453 /* 1454 * We allocate two pair for TKIP when using the h/w to do 1455 * the MIC. For everything else, including software crypto, 1456 * we allocate a single entry. Note that s/w crypto requires 1457 * a pass-through slot on the 5211 and 5212. The 5210 does 1458 * not support pass-through cache entries and we map all 1459 * those requests to slot 0. 1460 */ 1461 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1462 return key_alloc_single(sc); 1463 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1464 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1465 return key_alloc_2pair(sc); 1466 } else { 1467 return key_alloc_single(sc); 1468 } 1469} 1470 1471/* 1472 * Delete an entry in the key cache allocated by ath_key_alloc. 1473 */ 1474static int 1475ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1476{ 1477 struct ath_softc *sc = ic->ic_ifp->if_softc; 1478 struct ath_hal *ah = sc->sc_ah; 1479 const struct ieee80211_cipher *cip = k->wk_cipher; 1480 u_int keyix = k->wk_keyix; 1481 1482 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1483 1484 ath_hal_keyreset(ah, keyix); 1485 /* 1486 * Handle split tx/rx keying required for TKIP with h/w MIC. 1487 */ 1488 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1489 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1490 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1491 if (keyix >= IEEE80211_WEP_NKID) { 1492 /* 1493 * Don't touch keymap entries for global keys so 1494 * they are never considered for dynamic allocation. 1495 */ 1496 clrbit(sc->sc_keymap, keyix); 1497 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1498 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1499 sc->sc_splitmic) { 1500 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1501 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1502 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1503 } 1504 } 1505 return 1; 1506} 1507 1508/* 1509 * Set the key cache contents for the specified key. Key cache 1510 * slot(s) must already have been allocated by ath_key_alloc. 1511 */ 1512static int 1513ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1514 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1515{ 1516 struct ath_softc *sc = ic->ic_ifp->if_softc; 1517 1518 return ath_keyset(sc, k, mac); 1519} 1520 1521/* 1522 * Block/unblock tx+rx processing while a key change is done. 1523 * We assume the caller serializes key management operations 1524 * so we only need to worry about synchronization with other 1525 * uses that originate in the driver. 1526 */ 1527static void 1528ath_key_update_begin(struct ieee80211com *ic) 1529{ 1530 struct ifnet *ifp = ic->ic_ifp; 1531 struct ath_softc *sc = ifp->if_softc; 1532 1533 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1534#if 0 1535 tasklet_disable(&sc->sc_rxtq); 1536#endif 1537 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1538} 1539 1540static void 1541ath_key_update_end(struct ieee80211com *ic) 1542{ 1543 struct ifnet *ifp = ic->ic_ifp; 1544 struct ath_softc *sc = ifp->if_softc; 1545 1546 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1547 IF_UNLOCK(&ifp->if_snd); 1548#if 0 1549 tasklet_enable(&sc->sc_rxtq); 1550#endif 1551} 1552 1553/* 1554 * Calculate the receive filter according to the 1555 * operating mode and state: 1556 * 1557 * o always accept unicast, broadcast, and multicast traffic 1558 * o maintain current state of phy error reception (the hal 1559 * may enable phy error frames for noise immunity work) 1560 * o probe request frames are accepted only when operating in 1561 * hostap, adhoc, or monitor modes 1562 * o enable promiscuous mode according to the interface state 1563 * o accept beacons: 1564 * - when operating in adhoc mode so the 802.11 layer creates 1565 * node table entries for peers, 1566 * - when operating in station mode for collecting rssi data when 1567 * the station is otherwise quiet, or 1568 * - when scanning 1569 */ 1570static u_int32_t 1571ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1572{ 1573 struct ieee80211com *ic = &sc->sc_ic; 1574 struct ath_hal *ah = sc->sc_ah; 1575 struct ifnet *ifp = &sc->sc_if; 1576 u_int32_t rfilt; 1577 1578 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1579 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1580 if (ic->ic_opmode != IEEE80211_M_STA) 1581 rfilt |= HAL_RX_FILTER_PROBEREQ; 1582 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1583 (ifp->if_flags & IFF_PROMISC)) 1584 rfilt |= HAL_RX_FILTER_PROM; 1585 if (ic->ic_opmode == IEEE80211_M_STA || 1586 ic->ic_opmode == IEEE80211_M_IBSS || 1587 state == IEEE80211_S_SCAN) 1588 rfilt |= HAL_RX_FILTER_BEACON; 1589 return rfilt; 1590} 1591 1592static void 1593ath_mode_init(struct ath_softc *sc) 1594{ 1595 struct ieee80211com *ic = &sc->sc_ic; 1596 struct ath_hal *ah = sc->sc_ah; 1597 struct ifnet *ifp = &sc->sc_if; 1598 u_int32_t rfilt, mfilt[2], val; 1599 u_int8_t pos; 1600 struct ifmultiaddr *ifma; 1601 1602 /* configure rx filter */ 1603 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1604 ath_hal_setrxfilter(ah, rfilt); 1605 1606 /* configure operational mode */ 1607 ath_hal_setopmode(ah); 1608 1609 /* 1610 * Handle any link-level address change. Note that we only 1611 * need to force ic_myaddr; any other addresses are handled 1612 * as a byproduct of the ifnet code marking the interface 1613 * down then up. 1614 * 1615 * XXX should get from lladdr instead of arpcom but that's more work 1616 */ 1617 IEEE80211_ADDR_COPY(ic->ic_myaddr, IFP2AC(ifp)->ac_enaddr); 1618 ath_hal_setmac(ah, ic->ic_myaddr); 1619 1620 /* calculate and install multicast filter */ 1621 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1622 mfilt[0] = mfilt[1] = 0; 1623 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1624 caddr_t dl; 1625 1626 /* calculate XOR of eight 6bit values */ 1627 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1628 val = LE_READ_4(dl + 0); 1629 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1630 val = LE_READ_4(dl + 3); 1631 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1632 pos &= 0x3f; 1633 mfilt[pos / 32] |= (1 << (pos % 32)); 1634 } 1635 } else { 1636 mfilt[0] = mfilt[1] = ~0; 1637 } 1638 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1639 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1640 __func__, rfilt, mfilt[0], mfilt[1]); 1641} 1642 1643static void 1644ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 1645{ 1646 struct ath_buf *bf = arg; 1647 1648 KASSERT(nseg <= ATH_MAX_SCATTER, ("too many DMA segments %u", nseg)); 1649 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 1650 bf->bf_mapsize = mapsize; 1651 bf->bf_nseg = nseg; 1652 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 1653} 1654 1655/* 1656 * Set the slot time based on the current setting. 1657 */ 1658static void 1659ath_setslottime(struct ath_softc *sc) 1660{ 1661 struct ieee80211com *ic = &sc->sc_ic; 1662 struct ath_hal *ah = sc->sc_ah; 1663 1664 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1665 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1666 else 1667 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1668 sc->sc_updateslot = OK; 1669} 1670 1671/* 1672 * Callback from the 802.11 layer to update the 1673 * slot time based on the current setting. 1674 */ 1675static void 1676ath_updateslot(struct ifnet *ifp) 1677{ 1678 struct ath_softc *sc = ifp->if_softc; 1679 struct ieee80211com *ic = &sc->sc_ic; 1680 1681 /* 1682 * When not coordinating the BSS, change the hardware 1683 * immediately. For other operation we defer the change 1684 * until beacon updates have propagated to the stations. 1685 */ 1686 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1687 sc->sc_updateslot = UPDATE; 1688 else 1689 ath_setslottime(sc); 1690} 1691 1692/* 1693 * Setup a h/w transmit queue for beacons. 1694 */ 1695static int 1696ath_beaconq_setup(struct ath_hal *ah) 1697{ 1698 HAL_TXQ_INFO qi; 1699 1700 memset(&qi, 0, sizeof(qi)); 1701 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1702 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1703 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1704 /* NB: don't enable any interrupts */ 1705 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1706} 1707 1708/* 1709 * Allocate and setup an initial beacon frame. 1710 */ 1711static int 1712ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1713{ 1714 struct ieee80211com *ic = ni->ni_ic; 1715 struct ath_buf *bf; 1716 struct mbuf *m; 1717 int error; 1718 1719 bf = STAILQ_FIRST(&sc->sc_bbuf); 1720 if (bf == NULL) { 1721 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1722 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1723 return ENOMEM; /* XXX */ 1724 } 1725 if (bf->bf_m != NULL) { 1726 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1727 m_freem(bf->bf_m); 1728 bf->bf_m = NULL; 1729 bf->bf_node = NULL; 1730 } 1731 /* 1732 * NB: the beacon data buffer must be 32-bit aligned; 1733 * we assume the mbuf routines will return us something 1734 * with this alignment (perhaps should assert). 1735 */ 1736 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1737 if (m == NULL) { 1738 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1739 __func__); 1740 sc->sc_stats.ast_be_nombuf++; 1741 return ENOMEM; 1742 } 1743 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1744 ath_mbuf_load_cb, bf, 1745 BUS_DMA_NOWAIT); 1746 if (error == 0) { 1747 bf->bf_m = m; 1748 bf->bf_node = ni; /* NB: no held reference */ 1749 } else { 1750 m_freem(m); 1751 } 1752 return error; 1753} 1754 1755/* 1756 * Setup the beacon frame for transmit. 1757 */ 1758static void 1759ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1760{ 1761#define USE_SHPREAMBLE(_ic) \ 1762 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1763 == IEEE80211_F_SHPREAMBLE) 1764 struct ieee80211_node *ni = bf->bf_node; 1765 struct ieee80211com *ic = ni->ni_ic; 1766 struct mbuf *m = bf->bf_m; 1767 struct ath_hal *ah = sc->sc_ah; 1768 struct ath_node *an = ATH_NODE(ni); 1769 struct ath_desc *ds; 1770 int flags, antenna; 1771 u_int8_t rate; 1772 1773 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1774 __func__, m, m->m_len); 1775 1776 /* setup descriptors */ 1777 ds = bf->bf_desc; 1778 1779 flags = HAL_TXDESC_NOACK; 1780 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1781 ds->ds_link = bf->bf_daddr; /* self-linked */ 1782 flags |= HAL_TXDESC_VEOL; 1783 /* 1784 * Let hardware handle antenna switching. 1785 */ 1786 antenna = 0; 1787 } else { 1788 ds->ds_link = 0; 1789 /* 1790 * Switch antenna every 4 beacons. 1791 * XXX assumes two antenna 1792 */ 1793 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 1794 } 1795 1796 KASSERT(bf->bf_nseg == 1, 1797 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 1798 ds->ds_data = bf->bf_segs[0].ds_addr; 1799 /* 1800 * Calculate rate code. 1801 * XXX everything at min xmit rate 1802 */ 1803 if (USE_SHPREAMBLE(ic)) 1804 rate = an->an_tx_mgtratesp; 1805 else 1806 rate = an->an_tx_mgtrate; 1807 ath_hal_setuptxdesc(ah, ds 1808 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 1809 , sizeof(struct ieee80211_frame)/* header length */ 1810 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1811 , ni->ni_txpower /* txpower XXX */ 1812 , rate, 1 /* series 0 rate/tries */ 1813 , HAL_TXKEYIX_INVALID /* no encryption */ 1814 , antenna /* antenna mode */ 1815 , flags /* no ack, veol for beacons */ 1816 , 0 /* rts/cts rate */ 1817 , 0 /* rts/cts duration */ 1818 ); 1819 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1820 ath_hal_filltxdesc(ah, ds 1821 , roundup(m->m_len, 4) /* buffer length */ 1822 , AH_TRUE /* first segment */ 1823 , AH_TRUE /* last segment */ 1824 , ds /* first descriptor */ 1825 ); 1826#undef USE_SHPREAMBLE 1827} 1828 1829/* 1830 * Transmit a beacon frame at SWBA. Dynamic updates to the 1831 * frame contents are done as needed and the slot time is 1832 * also adjusted based on current state. 1833 */ 1834static void 1835ath_beacon_proc(void *arg, int pending) 1836{ 1837 struct ath_softc *sc = arg; 1838 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 1839 struct ieee80211_node *ni = bf->bf_node; 1840 struct ieee80211com *ic = ni->ni_ic; 1841 struct ath_hal *ah = sc->sc_ah; 1842 struct mbuf *m; 1843 int ncabq, error, otherant; 1844 1845 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 1846 __func__, pending); 1847 1848 if (ic->ic_opmode == IEEE80211_M_STA || 1849 ic->ic_opmode == IEEE80211_M_MONITOR || 1850 bf == NULL || bf->bf_m == NULL) { 1851 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 1852 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 1853 return; 1854 } 1855 /* 1856 * Check if the previous beacon has gone out. If 1857 * not don't don't try to post another, skip this 1858 * period and wait for the next. Missed beacons 1859 * indicate a problem and should not occur. If we 1860 * miss too many consecutive beacons reset the device. 1861 */ 1862 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 1863 sc->sc_bmisscount++; 1864 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 1865 "%s: missed %u consecutive beacons\n", 1866 __func__, sc->sc_bmisscount); 1867 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 1868 taskqueue_enqueue(taskqueue_swi, &sc->sc_bstucktask); 1869 return; 1870 } 1871 if (sc->sc_bmisscount != 0) { 1872 DPRINTF(sc, ATH_DEBUG_BEACON, 1873 "%s: resume beacon xmit after %u misses\n", 1874 __func__, sc->sc_bmisscount); 1875 sc->sc_bmisscount = 0; 1876 } 1877 1878 /* 1879 * Update dynamic beacon contents. If this returns 1880 * non-zero then we need to remap the memory because 1881 * the beacon frame changed size (probably because 1882 * of the TIM bitmap). 1883 */ 1884 m = bf->bf_m; 1885 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 1886 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 1887 /* XXX too conservative? */ 1888 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1889 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1890 ath_mbuf_load_cb, bf, 1891 BUS_DMA_NOWAIT); 1892 if (error != 0) { 1893 if_printf(ic->ic_ifp, 1894 "%s: bus_dmamap_load_mbuf failed, error %u\n", 1895 __func__, error); 1896 return; 1897 } 1898 } 1899 1900 /* 1901 * Handle slot time change when a non-ERP station joins/leaves 1902 * an 11g network. The 802.11 layer notifies us via callback, 1903 * we mark updateslot, then wait one beacon before effecting 1904 * the change. This gives associated stations at least one 1905 * beacon interval to note the state change. 1906 */ 1907 /* XXX locking */ 1908 if (sc->sc_updateslot == UPDATE) 1909 sc->sc_updateslot = COMMIT; /* commit next beacon */ 1910 else if (sc->sc_updateslot == COMMIT) 1911 ath_setslottime(sc); /* commit change to h/w */ 1912 1913 /* 1914 * Check recent per-antenna transmit statistics and flip 1915 * the default antenna if noticeably more frames went out 1916 * on the non-default antenna. 1917 * XXX assumes 2 anntenae 1918 */ 1919 otherant = sc->sc_defant & 1 ? 2 : 1; 1920 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 1921 ath_setdefantenna(sc, otherant); 1922 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 1923 1924 /* 1925 * Construct tx descriptor. 1926 */ 1927 ath_beacon_setup(sc, bf); 1928 1929 /* 1930 * Stop any current dma and put the new frame on the queue. 1931 * This should never fail since we check above that no frames 1932 * are still pending on the queue. 1933 */ 1934 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1935 DPRINTF(sc, ATH_DEBUG_ANY, 1936 "%s: beacon queue %u did not stop?\n", 1937 __func__, sc->sc_bhalq); 1938 } 1939 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1940 1941 /* 1942 * Enable the CAB queue before the beacon queue to 1943 * insure cab frames are triggered by this beacon. 1944 */ 1945 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 1946 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 1947 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1948 ath_hal_txstart(ah, sc->sc_bhalq); 1949 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 1950 "%s: TXDP[%u] = %p (%p)\n", __func__, 1951 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 1952 1953 sc->sc_stats.ast_be_xmit++; 1954} 1955 1956/* 1957 * Reset the hardware after detecting beacons have stopped. 1958 */ 1959static void 1960ath_bstuck_proc(void *arg, int pending) 1961{ 1962 struct ath_softc *sc = arg; 1963 struct ifnet *ifp = &sc->sc_if; 1964 1965 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 1966 sc->sc_bmisscount); 1967 ath_reset(ifp); 1968} 1969 1970/* 1971 * Reclaim beacon resources. 1972 */ 1973static void 1974ath_beacon_free(struct ath_softc *sc) 1975{ 1976 struct ath_buf *bf; 1977 1978 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) 1979 if (bf->bf_m != NULL) { 1980 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1981 m_freem(bf->bf_m); 1982 bf->bf_m = NULL; 1983 bf->bf_node = NULL; 1984 } 1985} 1986 1987/* 1988 * Configure the beacon and sleep timers. 1989 * 1990 * When operating as an AP this resets the TSF and sets 1991 * up the hardware to notify us when we need to issue beacons. 1992 * 1993 * When operating in station mode this sets up the beacon 1994 * timers according to the timestamp of the last received 1995 * beacon and the current TSF, configures PCF and DTIM 1996 * handling, programs the sleep registers so the hardware 1997 * will wakeup in time to receive beacons, and configures 1998 * the beacon miss handling so we'll receive a BMISS 1999 * interrupt when we stop seeing beacons from the AP 2000 * we've associated with. 2001 */ 2002static void 2003ath_beacon_config(struct ath_softc *sc) 2004{ 2005#define MS_TO_TU(x) (((x) * 1000) / 1024) 2006 struct ath_hal *ah = sc->sc_ah; 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 struct ieee80211_node *ni = ic->ic_bss; 2009 u_int32_t nexttbtt, intval; 2010 2011 nexttbtt = (LE_READ_4(ni->ni_tstamp.data + 4) << 22) | 2012 (LE_READ_4(ni->ni_tstamp.data) >> 10); 2013 intval = MS_TO_TU(ni->ni_intval) & HAL_BEACON_PERIOD; 2014 if (nexttbtt == 0) /* e.g. for ap mode */ 2015 nexttbtt = intval; 2016 else if (intval) /* NB: can be 0 for monitor mode */ 2017 nexttbtt = roundup(nexttbtt, intval); 2018 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2019 __func__, nexttbtt, intval, ni->ni_intval); 2020 if (ic->ic_opmode == IEEE80211_M_STA) { 2021 HAL_BEACON_STATE bs; 2022 u_int32_t bmisstime; 2023 2024 /* NB: no PCF support right now */ 2025 memset(&bs, 0, sizeof(bs)); 2026 bs.bs_intval = intval; 2027 bs.bs_nexttbtt = nexttbtt; 2028 bs.bs_dtimperiod = bs.bs_intval; 2029 bs.bs_nextdtim = nexttbtt; 2030 /* 2031 * The 802.11 layer records the offset to the DTIM 2032 * bitmap while receiving beacons; use it here to 2033 * enable h/w detection of our AID being marked in 2034 * the bitmap vector (to indicate frames for us are 2035 * pending at the AP). 2036 */ 2037 bs.bs_timoffset = ni->ni_timoff; 2038 /* 2039 * Calculate the number of consecutive beacons to miss 2040 * before taking a BMISS interrupt. The configuration 2041 * is specified in ms, so we need to convert that to 2042 * TU's and then calculate based on the beacon interval. 2043 * Note that we clamp the result to at most 10 beacons. 2044 */ 2045 bmisstime = MS_TO_TU(ic->ic_bmisstimeout); 2046 bs.bs_bmissthreshold = howmany(bmisstime, intval); 2047 if (bs.bs_bmissthreshold > 10) 2048 bs.bs_bmissthreshold = 10; 2049 else if (bs.bs_bmissthreshold <= 0) 2050 bs.bs_bmissthreshold = 1; 2051 2052 /* 2053 * Calculate sleep duration. The configuration is 2054 * given in ms. We insure a multiple of the beacon 2055 * period is used. Also, if the sleep duration is 2056 * greater than the DTIM period then it makes senses 2057 * to make it a multiple of that. 2058 * 2059 * XXX fixed at 100ms 2060 */ 2061 bs.bs_sleepduration = roundup(MS_TO_TU(100), bs.bs_intval); 2062 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2063 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2064 2065 DPRINTF(sc, ATH_DEBUG_BEACON, 2066 "%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2067 , __func__ 2068 , bs.bs_intval 2069 , bs.bs_nexttbtt 2070 , bs.bs_dtimperiod 2071 , bs.bs_nextdtim 2072 , bs.bs_bmissthreshold 2073 , bs.bs_sleepduration 2074 , bs.bs_cfpperiod 2075 , bs.bs_cfpmaxduration 2076 , bs.bs_cfpnext 2077 , bs.bs_timoffset 2078 ); 2079 ath_hal_intrset(ah, 0); 2080 ath_hal_beacontimers(ah, &bs); 2081 sc->sc_imask |= HAL_INT_BMISS; 2082 ath_hal_intrset(ah, sc->sc_imask); 2083 } else { 2084 ath_hal_intrset(ah, 0); 2085 if (nexttbtt == intval) 2086 intval |= HAL_BEACON_RESET_TSF; 2087 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2088 /* 2089 * In IBSS mode enable the beacon timers but only 2090 * enable SWBA interrupts if we need to manually 2091 * prepare beacon frames. Otherwise we use a 2092 * self-linked tx descriptor and let the hardware 2093 * deal with things. 2094 */ 2095 intval |= HAL_BEACON_ENA; 2096 if (!sc->sc_hasveol) 2097 sc->sc_imask |= HAL_INT_SWBA; 2098 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2099 /* 2100 * In AP mode we enable the beacon timers and 2101 * SWBA interrupts to prepare beacon frames. 2102 */ 2103 intval |= HAL_BEACON_ENA; 2104 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2105 } 2106 ath_hal_beaconinit(ah, nexttbtt, intval); 2107 sc->sc_bmisscount = 0; 2108 ath_hal_intrset(ah, sc->sc_imask); 2109 /* 2110 * When using a self-linked beacon descriptor in 2111 * ibss mode load it once here. 2112 */ 2113 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2114 ath_beacon_proc(sc, 0); 2115 } 2116#undef MS_TO_TU 2117} 2118 2119static void 2120ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2121{ 2122 bus_addr_t *paddr = (bus_addr_t*) arg; 2123 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2124 *paddr = segs->ds_addr; 2125} 2126 2127static int 2128ath_descdma_setup(struct ath_softc *sc, 2129 struct ath_descdma *dd, ath_bufhead *head, 2130 const char *name, int nbuf, int ndesc) 2131{ 2132#define DS2PHYS(_dd, _ds) \ 2133 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2134 struct ifnet *ifp = &sc->sc_if; 2135 struct ath_desc *ds; 2136 struct ath_buf *bf; 2137 int i, bsize, error; 2138 2139 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2140 __func__, name, nbuf, ndesc); 2141 2142 dd->dd_name = name; 2143 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2144 2145 /* 2146 * Setup DMA descriptor area. 2147 */ 2148 error = bus_dma_tag_create(NULL, /* parent */ 2149 PAGE_SIZE, 0, /* alignment, bounds */ 2150 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2151 BUS_SPACE_MAXADDR, /* highaddr */ 2152 NULL, NULL, /* filter, filterarg */ 2153 dd->dd_desc_len, /* maxsize */ 2154 1, /* nsegments */ 2155 BUS_SPACE_MAXADDR, /* maxsegsize */ 2156 BUS_DMA_ALLOCNOW, /* flags */ 2157 NULL, /* lockfunc */ 2158 NULL, /* lockarg */ 2159 &dd->dd_dmat); 2160 if (error != 0) { 2161 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2162 return error; 2163 } 2164 2165 /* allocate descriptors */ 2166 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2167 if (error != 0) { 2168 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2169 "error %u\n", dd->dd_name, error); 2170 goto fail0; 2171 } 2172 2173 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2174 BUS_DMA_NOWAIT, &dd->dd_dmamap); 2175 if (error != 0) { 2176 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2177 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2178 goto fail1; 2179 } 2180 2181 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2182 dd->dd_desc, dd->dd_desc_len, 2183 ath_load_cb, &dd->dd_desc_paddr, 2184 BUS_DMA_NOWAIT); 2185 if (error != 0) { 2186 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2187 dd->dd_name, error); 2188 goto fail2; 2189 } 2190 2191 ds = dd->dd_desc; 2192 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2193 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2194 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2195 2196 /* allocate rx buffers */ 2197 bsize = sizeof(struct ath_buf) * nbuf; 2198 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2199 if (bf == NULL) { 2200 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2201 dd->dd_name, bsize); 2202 goto fail3; 2203 } 2204 dd->dd_bufptr = bf; 2205 2206 STAILQ_INIT(head); 2207 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2208 bf->bf_desc = ds; 2209 bf->bf_daddr = DS2PHYS(dd, ds); 2210 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2211 &bf->bf_dmamap); 2212 if (error != 0) { 2213 if_printf(ifp, "unable to create dmamap for %s " 2214 "buffer %u, error %u\n", dd->dd_name, i, error); 2215 ath_descdma_cleanup(sc, dd, head); 2216 return error; 2217 } 2218 STAILQ_INSERT_TAIL(head, bf, bf_list); 2219 } 2220 return 0; 2221fail3: 2222 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2223fail2: 2224 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2225fail1: 2226 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2227fail0: 2228 bus_dma_tag_destroy(dd->dd_dmat); 2229 memset(dd, 0, sizeof(*dd)); 2230 return error; 2231#undef DS2PHYS 2232} 2233 2234static void 2235ath_descdma_cleanup(struct ath_softc *sc, 2236 struct ath_descdma *dd, ath_bufhead *head) 2237{ 2238 struct ath_buf *bf; 2239 struct ieee80211_node *ni; 2240 2241 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2242 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2243 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2244 bus_dma_tag_destroy(dd->dd_dmat); 2245 2246 STAILQ_FOREACH(bf, head, bf_list) { 2247 if (bf->bf_m) { 2248 m_freem(bf->bf_m); 2249 bf->bf_m = NULL; 2250 } 2251 if (bf->bf_dmamap != NULL) { 2252 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2253 bf->bf_dmamap = NULL; 2254 } 2255 ni = bf->bf_node; 2256 bf->bf_node = NULL; 2257 if (ni != NULL) { 2258 /* 2259 * Reclaim node reference. 2260 */ 2261 ieee80211_free_node(ni); 2262 } 2263 } 2264 2265 STAILQ_INIT(head); 2266 free(dd->dd_bufptr, M_ATHDEV); 2267 memset(dd, 0, sizeof(*dd)); 2268} 2269 2270static int 2271ath_desc_alloc(struct ath_softc *sc) 2272{ 2273 int error; 2274 2275 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2276 "rx", ATH_RXBUF, 1); 2277 if (error != 0) 2278 return error; 2279 2280 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2281 "tx", ATH_TXBUF, ATH_TXDESC); 2282 if (error != 0) { 2283 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2284 return error; 2285 } 2286 2287 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2288 "beacon", 1, 1); 2289 if (error != 0) { 2290 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2291 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2292 return error; 2293 } 2294 return 0; 2295} 2296 2297static void 2298ath_desc_free(struct ath_softc *sc) 2299{ 2300 2301 if (sc->sc_bdma.dd_desc_len != 0) 2302 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2303 if (sc->sc_txdma.dd_desc_len != 0) 2304 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2305 if (sc->sc_rxdma.dd_desc_len != 0) 2306 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2307} 2308 2309static struct ieee80211_node * 2310ath_node_alloc(struct ieee80211_node_table *nt) 2311{ 2312 struct ieee80211com *ic = nt->nt_ic; 2313 struct ath_softc *sc = ic->ic_ifp->if_softc; 2314 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2315 struct ath_node *an; 2316 2317 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2318 if (an == NULL) { 2319 /* XXX stat+msg */ 2320 return NULL; 2321 } 2322 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2323 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2324 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2325 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2326 ath_rate_node_init(sc, an); 2327 2328 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2329 return &an->an_node; 2330} 2331 2332static void 2333ath_node_free(struct ieee80211_node *ni) 2334{ 2335 struct ieee80211com *ic = ni->ni_ic; 2336 struct ath_softc *sc = ic->ic_ifp->if_softc; 2337 2338 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2339 2340 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2341 sc->sc_node_free(ni); 2342} 2343 2344static u_int8_t 2345ath_node_getrssi(const struct ieee80211_node *ni) 2346{ 2347#define HAL_EP_RND(x, mul) \ 2348 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2349 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2350 int32_t rssi; 2351 2352 /* 2353 * When only one frame is received there will be no state in 2354 * avgrssi so fallback on the value recorded by the 802.11 layer. 2355 */ 2356 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2357 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2358 else 2359 rssi = ni->ni_rssi; 2360 /* NB: theoretically we shouldn't need this, but be paranoid */ 2361 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2362#undef HAL_EP_RND 2363} 2364 2365static int 2366ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2367{ 2368 struct ath_hal *ah = sc->sc_ah; 2369 int error; 2370 struct mbuf *m; 2371 struct ath_desc *ds; 2372 2373 m = bf->bf_m; 2374 if (m == NULL) { 2375 /* 2376 * NB: by assigning a page to the rx dma buffer we 2377 * implicitly satisfy the Atheros requirement that 2378 * this buffer be cache-line-aligned and sized to be 2379 * multiple of the cache line size. Not doing this 2380 * causes weird stuff to happen (for the 5210 at least). 2381 */ 2382 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2383 if (m == NULL) { 2384 DPRINTF(sc, ATH_DEBUG_ANY, 2385 "%s: no mbuf/cluster\n", __func__); 2386 sc->sc_stats.ast_rx_nombuf++; 2387 return ENOMEM; 2388 } 2389 bf->bf_m = m; 2390 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2391 2392 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2393 bf->bf_dmamap, m, 2394 ath_mbuf_load_cb, bf, 2395 BUS_DMA_NOWAIT); 2396 if (error != 0) { 2397 DPRINTF(sc, ATH_DEBUG_ANY, 2398 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2399 __func__, error); 2400 sc->sc_stats.ast_rx_busdma++; 2401 return error; 2402 } 2403 KASSERT(bf->bf_nseg == 1, 2404 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2405 } 2406 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 2407 2408 /* 2409 * Setup descriptors. For receive we always terminate 2410 * the descriptor list with a self-linked entry so we'll 2411 * not get overrun under high load (as can happen with a 2412 * 5212 when ANI processing enables PHY error frames). 2413 * 2414 * To insure the last descriptor is self-linked we create 2415 * each descriptor as self-linked and add it to the end. As 2416 * each additional descriptor is added the previous self-linked 2417 * entry is ``fixed'' naturally. This should be safe even 2418 * if DMA is happening. When processing RX interrupts we 2419 * never remove/process the last, self-linked, entry on the 2420 * descriptor list. This insures the hardware always has 2421 * someplace to write a new frame. 2422 */ 2423 ds = bf->bf_desc; 2424 ds->ds_link = bf->bf_daddr; /* link to self */ 2425 ds->ds_data = bf->bf_segs[0].ds_addr; 2426 ath_hal_setuprxdesc(ah, ds 2427 , m->m_len /* buffer size */ 2428 , 0 2429 ); 2430 2431 if (sc->sc_rxlink != NULL) 2432 *sc->sc_rxlink = bf->bf_daddr; 2433 sc->sc_rxlink = &ds->ds_link; 2434 return 0; 2435} 2436 2437/* 2438 * Intercept management frames to collect beacon rssi data 2439 * and to do ibss merges. 2440 */ 2441static void 2442ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2443 struct ieee80211_node *ni, 2444 int subtype, int rssi, u_int32_t rstamp) 2445{ 2446 struct ath_softc *sc = ic->ic_ifp->if_softc; 2447 2448 /* 2449 * Call up first so subsequent work can use information 2450 * potentially stored in the node (e.g. for ibss merge). 2451 */ 2452 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2453 switch (subtype) { 2454 case IEEE80211_FC0_SUBTYPE_BEACON: 2455 /* update rssi statistics for use by the hal */ 2456 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2457 /* fall thru... */ 2458 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2459 if (ic->ic_opmode == IEEE80211_M_IBSS && 2460 ic->ic_state == IEEE80211_S_RUN) { 2461 struct ath_hal *ah = sc->sc_ah; 2462 /* XXX extend rstamp */ 2463 u_int64_t tsf = ath_hal_gettsf64(ah); 2464 2465 /* 2466 * Handle ibss merge as needed; check the tsf on the 2467 * frame before attempting the merge. The 802.11 spec 2468 * says the station should change it's bssid to match 2469 * the oldest station with the same ssid, where oldest 2470 * is determined by the tsf. 2471 */ 2472 if (le64toh(ni->ni_tstamp.tsf) >= tsf && 2473 ieee80211_ibss_merge(ic, ni)) 2474 ath_hal_setassocid(ah, ic->ic_bss->ni_bssid, 0); 2475 } 2476 break; 2477 } 2478} 2479 2480/* 2481 * Set the default antenna. 2482 */ 2483static void 2484ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2485{ 2486 struct ath_hal *ah = sc->sc_ah; 2487 2488 /* XXX block beacon interrupts */ 2489 ath_hal_setdefantenna(ah, antenna); 2490 if (sc->sc_defant != antenna) 2491 sc->sc_stats.ast_ant_defswitch++; 2492 sc->sc_defant = antenna; 2493 sc->sc_rxotherant = 0; 2494} 2495 2496static void 2497ath_rx_proc(void *arg, int npending) 2498{ 2499#define PA2DESC(_sc, _pa) \ 2500 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2501 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2502 struct ath_softc *sc = arg; 2503 struct ath_buf *bf; 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 struct ifnet *ifp = &sc->sc_if; 2506 struct ath_hal *ah = sc->sc_ah; 2507 struct ath_desc *ds; 2508 struct mbuf *m; 2509 struct ieee80211_node *ni; 2510 struct ath_node *an; 2511 int len; 2512 u_int phyerr; 2513 HAL_STATUS status; 2514 2515 NET_LOCK_GIANT(); /* XXX */ 2516 2517 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2518 do { 2519 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2520 if (bf == NULL) { /* NB: shouldn't happen */ 2521 if_printf(ifp, "%s: no buffer!\n", __func__); 2522 break; 2523 } 2524 ds = bf->bf_desc; 2525 if (ds->ds_link == bf->bf_daddr) { 2526 /* NB: never process the self-linked entry at the end */ 2527 break; 2528 } 2529 m = bf->bf_m; 2530 if (m == NULL) { /* NB: shouldn't happen */ 2531 if_printf(ifp, "%s: no mbuf!\n", __func__); 2532 continue; 2533 } 2534 /* XXX sync descriptor memory */ 2535 /* 2536 * Must provide the virtual address of the current 2537 * descriptor, the physical address, and the virtual 2538 * address of the next descriptor in the h/w chain. 2539 * This allows the HAL to look ahead to see if the 2540 * hardware is done with a descriptor by checking the 2541 * done bit in the following descriptor and the address 2542 * of the current descriptor the DMA engine is working 2543 * on. All this is necessary because of our use of 2544 * a self-linked list to avoid rx overruns. 2545 */ 2546 status = ath_hal_rxprocdesc(ah, ds, 2547 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2548#ifdef AR_DEBUG 2549 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2550 ath_printrxbuf(bf, status == HAL_OK); 2551#endif 2552 if (status == HAL_EINPROGRESS) 2553 break; 2554 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2555 if (ds->ds_rxstat.rs_more) { 2556 /* 2557 * Frame spans multiple descriptors; this 2558 * cannot happen yet as we don't support 2559 * jumbograms. If not in monitor mode, 2560 * discard the frame. 2561 */ 2562 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2563 sc->sc_stats.ast_rx_toobig++; 2564 goto rx_next; 2565 } 2566 /* fall thru for monitor mode handling... */ 2567 } else if (ds->ds_rxstat.rs_status != 0) { 2568 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2569 sc->sc_stats.ast_rx_crcerr++; 2570 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2571 sc->sc_stats.ast_rx_fifoerr++; 2572 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2573 sc->sc_stats.ast_rx_phyerr++; 2574 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2575 sc->sc_stats.ast_rx_phy[phyerr]++; 2576 goto rx_next; 2577 } 2578 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2579 /* 2580 * Decrypt error. If the error occurred 2581 * because there was no hardware key, then 2582 * let the frame through so the upper layers 2583 * can process it. This is necessary for 5210 2584 * parts which have no way to setup a ``clear'' 2585 * key cache entry. 2586 * 2587 * XXX do key cache faulting 2588 */ 2589 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2590 goto rx_accept; 2591 sc->sc_stats.ast_rx_badcrypt++; 2592 } 2593 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2594 sc->sc_stats.ast_rx_badmic++; 2595 /* 2596 * Do minimal work required to hand off 2597 * the 802.11 header for notifcation. 2598 */ 2599 /* XXX frag's and qos frames */ 2600 len = ds->ds_rxstat.rs_datalen; 2601 if (len >= sizeof (struct ieee80211_frame)) { 2602 bus_dmamap_sync(sc->sc_dmat, 2603 bf->bf_dmamap, 2604 BUS_DMASYNC_POSTREAD); 2605 ieee80211_notify_michael_failure(ic, 2606 mtod(m, struct ieee80211_frame *), 2607 sc->sc_splitmic ? 2608 ds->ds_rxstat.rs_keyix-32 : 2609 ds->ds_rxstat.rs_keyix 2610 ); 2611 } 2612 } 2613 ifp->if_ierrors++; 2614 /* 2615 * Reject error frames, we normally don't want 2616 * to see them in monitor mode (in monitor mode 2617 * allow through packets that have crypto problems). 2618 */ 2619 if ((ds->ds_rxstat.rs_status &~ 2620 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2621 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2622 goto rx_next; 2623 } 2624rx_accept: 2625 /* 2626 * Sync and unmap the frame. At this point we're 2627 * committed to passing the mbuf somewhere so clear 2628 * bf_m; this means a new sk_buff must be allocated 2629 * when the rx descriptor is setup again to receive 2630 * another frame. 2631 */ 2632 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2633 BUS_DMASYNC_POSTREAD); 2634 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2635 bf->bf_m = NULL; 2636 2637 m->m_pkthdr.rcvif = ifp; 2638 len = ds->ds_rxstat.rs_datalen; 2639 m->m_pkthdr.len = m->m_len = len; 2640 2641 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2642 2643 if (sc->sc_drvbpf) { 2644 const void *data; 2645 int hdrsize, hdrspace; 2646 u_int8_t rix; 2647 2648 /* 2649 * Discard anything shorter than an ack or cts. 2650 */ 2651 if (len < IEEE80211_ACK_LEN) { 2652 DPRINTF(sc, ATH_DEBUG_RECV, 2653 "%s: runt packet %d\n", 2654 __func__, len); 2655 sc->sc_stats.ast_rx_tooshort++; 2656 m_freem(m); 2657 goto rx_next; 2658 } 2659 rix = ds->ds_rxstat.rs_rate; 2660 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].flags; 2661 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2662 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2663 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2664 /* XXX TSF */ 2665 2666 /* 2667 * Gag, deal with hardware padding of headers. This 2668 * only happens for QoS frames. We copy the 802.11 2669 * header out-of-line and supply it separately, then 2670 * adjust the mbuf chain. It would be better if we 2671 * could just flag the packet in the radiotap header 2672 * and have applications DTRT. 2673 */ 2674 if (len > sizeof(struct ieee80211_qosframe)) { 2675 data = mtod(m, const void *); 2676 hdrsize = ieee80211_anyhdrsize(data); 2677 if (hdrsize & 3) { 2678 bcopy(data, &sc->sc_rx_wh, hdrsize); 2679 hdrspace = roundup(hdrsize, 2680 sizeof(u_int32_t)); 2681 m->m_data += hdrspace; 2682 m->m_len -= hdrspace; 2683 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx, 2684 sc->sc_rx_rt_len + hdrsize, m); 2685 m->m_data -= hdrspace; 2686 m->m_len += hdrspace; 2687 } else 2688 bpf_mtap2(sc->sc_drvbpf, 2689 &sc->sc_rx, sc->sc_rx_rt_len, m); 2690 } else 2691 bpf_mtap2(sc->sc_drvbpf, 2692 &sc->sc_rx, sc->sc_rx_rt_len, m); 2693 } 2694 2695 /* 2696 * From this point on we assume the frame is at least 2697 * as large as ieee80211_frame_min; verify that. 2698 */ 2699 if (len < IEEE80211_MIN_LEN) { 2700 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2701 __func__, len); 2702 sc->sc_stats.ast_rx_tooshort++; 2703 m_freem(m); 2704 goto rx_next; 2705 } 2706 2707 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2708 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2709 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2710 ds->ds_rxstat.rs_rssi); 2711 } 2712 2713 m_adj(m, -IEEE80211_CRC_LEN); 2714 2715 /* 2716 * Locate the node for sender, track state, and then 2717 * pass the (referenced) node up to the 802.11 layer 2718 * for its use. 2719 */ 2720 ni = ieee80211_find_rxnode(ic, 2721 mtod(m, const struct ieee80211_frame_min *)); 2722 2723 /* 2724 * Track rx rssi and do any rx antenna management. 2725 */ 2726 an = ATH_NODE(ni); 2727 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2728 if (sc->sc_diversity) { 2729 /* 2730 * When using fast diversity, change the default rx 2731 * antenna if diversity chooses the other antenna 3 2732 * times in a row. 2733 */ 2734 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2735 if (++sc->sc_rxotherant >= 3) 2736 ath_setdefantenna(sc, 2737 ds->ds_rxstat.rs_antenna); 2738 } else 2739 sc->sc_rxotherant = 0; 2740 } 2741 2742 /* 2743 * Send frame up for processing. 2744 */ 2745 ieee80211_input(ic, m, ni, 2746 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2747 2748 if (sc->sc_softled) { 2749 /* 2750 * Blink for any data frame. Otherwise do a 2751 * heartbeat-style blink when idle. The latter 2752 * is mainly for station mode where we depend on 2753 * periodic beacon frames to trigger the poll event. 2754 */ 2755 if (sc->sc_ipackets != ifp->if_ipackets) { 2756 sc->sc_ipackets = ifp->if_ipackets; 2757 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 2758 ath_led_event(sc, ATH_LED_RX); 2759 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 2760 ath_led_event(sc, ATH_LED_POLL); 2761 } 2762 2763 /* 2764 * Reclaim node reference. 2765 */ 2766 ieee80211_free_node(ni); 2767rx_next: 2768 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2769 } while (ath_rxbuf_init(sc, bf) == 0); 2770 2771 /* rx signal state monitoring */ 2772 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 2773 2774 NET_UNLOCK_GIANT(); /* XXX */ 2775#undef PA2DESC 2776} 2777 2778/* 2779 * Setup a h/w transmit queue. 2780 */ 2781static struct ath_txq * 2782ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 2783{ 2784#define N(a) (sizeof(a)/sizeof(a[0])) 2785 struct ath_hal *ah = sc->sc_ah; 2786 HAL_TXQ_INFO qi; 2787 int qnum; 2788 2789 memset(&qi, 0, sizeof(qi)); 2790 qi.tqi_subtype = subtype; 2791 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2792 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2793 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2794 /* 2795 * Enable interrupts only for EOL and DESC conditions. 2796 * We mark tx descriptors to receive a DESC interrupt 2797 * when a tx queue gets deep; otherwise waiting for the 2798 * EOL to reap descriptors. Note that this is done to 2799 * reduce interrupt load and this only defers reaping 2800 * descriptors, never transmitting frames. Aside from 2801 * reducing interrupts this also permits more concurrency. 2802 * The only potential downside is if the tx queue backs 2803 * up in which case the top half of the kernel may backup 2804 * due to a lack of tx descriptors. 2805 */ 2806 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 2807 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 2808 if (qnum == -1) { 2809 /* 2810 * NB: don't print a message, this happens 2811 * normally on parts with too few tx queues 2812 */ 2813 return NULL; 2814 } 2815 if (qnum >= N(sc->sc_txq)) { 2816 device_printf(sc->sc_dev, 2817 "hal qnum %u out of range, max %zu!\n", 2818 qnum, N(sc->sc_txq)); 2819 ath_hal_releasetxqueue(ah, qnum); 2820 return NULL; 2821 } 2822 if (!ATH_TXQ_SETUP(sc, qnum)) { 2823 struct ath_txq *txq = &sc->sc_txq[qnum]; 2824 2825 txq->axq_qnum = qnum; 2826 txq->axq_depth = 0; 2827 txq->axq_intrcnt = 0; 2828 txq->axq_link = NULL; 2829 STAILQ_INIT(&txq->axq_q); 2830 ATH_TXQ_LOCK_INIT(sc, txq); 2831 sc->sc_txqsetup |= 1<<qnum; 2832 } 2833 return &sc->sc_txq[qnum]; 2834#undef N 2835} 2836 2837/* 2838 * Setup a hardware data transmit queue for the specified 2839 * access control. The hal may not support all requested 2840 * queues in which case it will return a reference to a 2841 * previously setup queue. We record the mapping from ac's 2842 * to h/w queues for use by ath_tx_start and also track 2843 * the set of h/w queues being used to optimize work in the 2844 * transmit interrupt handler and related routines. 2845 */ 2846static int 2847ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 2848{ 2849#define N(a) (sizeof(a)/sizeof(a[0])) 2850 struct ath_txq *txq; 2851 2852 if (ac >= N(sc->sc_ac2q)) { 2853 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 2854 ac, N(sc->sc_ac2q)); 2855 return 0; 2856 } 2857 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 2858 if (txq != NULL) { 2859 sc->sc_ac2q[ac] = txq; 2860 return 1; 2861 } else 2862 return 0; 2863#undef N 2864} 2865 2866/* 2867 * Update WME parameters for a transmit queue. 2868 */ 2869static int 2870ath_txq_update(struct ath_softc *sc, int ac) 2871{ 2872#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 2873#define ATH_TXOP_TO_US(v) (v<<5) 2874 struct ieee80211com *ic = &sc->sc_ic; 2875 struct ath_txq *txq = sc->sc_ac2q[ac]; 2876 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2877 struct ath_hal *ah = sc->sc_ah; 2878 HAL_TXQ_INFO qi; 2879 2880 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 2881 qi.tqi_aifs = wmep->wmep_aifsn; 2882 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2883 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2884 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 2885 2886 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 2887 device_printf(sc->sc_dev, "unable to update hardware queue " 2888 "parameters for %s traffic!\n", 2889 ieee80211_wme_acnames[ac]); 2890 return 0; 2891 } else { 2892 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 2893 return 1; 2894 } 2895#undef ATH_TXOP_TO_US 2896#undef ATH_EXPONENT_TO_VALUE 2897} 2898 2899/* 2900 * Callback from the 802.11 layer to update WME parameters. 2901 */ 2902static int 2903ath_wme_update(struct ieee80211com *ic) 2904{ 2905 struct ath_softc *sc = ic->ic_ifp->if_softc; 2906 2907 return !ath_txq_update(sc, WME_AC_BE) || 2908 !ath_txq_update(sc, WME_AC_BK) || 2909 !ath_txq_update(sc, WME_AC_VI) || 2910 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 2911} 2912 2913/* 2914 * Reclaim resources for a setup queue. 2915 */ 2916static void 2917ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 2918{ 2919 2920 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 2921 ATH_TXQ_LOCK_DESTROY(txq); 2922 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 2923} 2924 2925/* 2926 * Reclaim all tx queue resources. 2927 */ 2928static void 2929ath_tx_cleanup(struct ath_softc *sc) 2930{ 2931 int i; 2932 2933 ATH_TXBUF_LOCK_DESTROY(sc); 2934 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 2935 if (ATH_TXQ_SETUP(sc, i)) 2936 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 2937} 2938 2939static int 2940ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 2941 struct mbuf *m0) 2942{ 2943 struct ieee80211com *ic = &sc->sc_ic; 2944 struct ath_hal *ah = sc->sc_ah; 2945 struct ifnet *ifp = &sc->sc_if; 2946 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 2947 u_int8_t rix, txrate, ctsrate; 2948 u_int8_t cix = 0xff; /* NB: silence compiler */ 2949 struct ath_desc *ds, *ds0; 2950 struct ath_txq *txq; 2951 struct mbuf *m; 2952 struct ieee80211_frame *wh; 2953 u_int subtype, flags, ctsduration; 2954 HAL_PKT_TYPE atype; 2955 const HAL_RATE_TABLE *rt; 2956 HAL_BOOL shortPreamble; 2957 struct ath_node *an; 2958 2959 wh = mtod(m0, struct ieee80211_frame *); 2960 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 2961 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2962 hdrlen = ieee80211_anyhdrsize(wh); 2963 /* 2964 * Packet length must not include any 2965 * pad bytes; deduct them here. 2966 */ 2967 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 2968 2969 if (iswep) { 2970 const struct ieee80211_cipher *cip; 2971 struct ieee80211_key *k; 2972 2973 /* 2974 * Construct the 802.11 header+trailer for an encrypted 2975 * frame. The only reason this can fail is because of an 2976 * unknown or unsupported cipher/key type. 2977 */ 2978 k = ieee80211_crypto_encap(ic, ni, m0); 2979 if (k == NULL) { 2980 /* 2981 * This can happen when the key is yanked after the 2982 * frame was queued. Just discard the frame; the 2983 * 802.11 layer counts failures and provides 2984 * debugging/diagnostics. 2985 */ 2986 return EIO; 2987 } 2988 /* 2989 * Adjust the packet + header lengths for the crypto 2990 * additions and calculate the h/w key index. When 2991 * a s/w mic is done the frame will have had any mic 2992 * added to it prior to entry so skb->len above will 2993 * account for it. Otherwise we need to add it to the 2994 * packet length. 2995 */ 2996 cip = k->wk_cipher; 2997 hdrlen += cip->ic_header; 2998 pktlen += cip->ic_header + cip->ic_trailer; 2999 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3000 pktlen += cip->ic_miclen; 3001 keyix = k->wk_keyix; 3002 3003 /* packet header may have moved, reset our local pointer */ 3004 wh = mtod(m0, struct ieee80211_frame *); 3005 } else 3006 keyix = HAL_TXKEYIX_INVALID; 3007 3008 pktlen += IEEE80211_CRC_LEN; 3009 3010 /* 3011 * Load the DMA map so any coalescing is done. This 3012 * also calculates the number of descriptors we need. 3013 */ 3014 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3015 ath_mbuf_load_cb, bf, 3016 BUS_DMA_NOWAIT); 3017 if (error == EFBIG) { 3018 /* XXX packet requires too many descriptors */ 3019 bf->bf_nseg = ATH_TXDESC+1; 3020 } else if (error != 0) { 3021 sc->sc_stats.ast_tx_busdma++; 3022 m_freem(m0); 3023 return error; 3024 } 3025 /* 3026 * Discard null packets and check for packets that 3027 * require too many TX descriptors. We try to convert 3028 * the latter to a cluster. 3029 */ 3030 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 3031 sc->sc_stats.ast_tx_linear++; 3032 MGETHDR(m, M_DONTWAIT, MT_DATA); 3033 if (m == NULL) { 3034 sc->sc_stats.ast_tx_nombuf++; 3035 m_freem(m0); 3036 return ENOMEM; 3037 } 3038 M_MOVE_PKTHDR(m, m0); 3039 MCLGET(m, M_DONTWAIT); 3040 if ((m->m_flags & M_EXT) == 0) { 3041 sc->sc_stats.ast_tx_nomcl++; 3042 m_freem(m0); 3043 m_free(m); 3044 return ENOMEM; 3045 } 3046 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3047 m_freem(m0); 3048 m->m_len = m->m_pkthdr.len; 3049 m0 = m; 3050 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3051 ath_mbuf_load_cb, bf, 3052 BUS_DMA_NOWAIT); 3053 if (error != 0) { 3054 sc->sc_stats.ast_tx_busdma++; 3055 m_freem(m0); 3056 return error; 3057 } 3058 KASSERT(bf->bf_nseg == 1, 3059 ("packet not one segment; nseg %u", bf->bf_nseg)); 3060 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3061 sc->sc_stats.ast_tx_nodata++; 3062 m_freem(m0); 3063 return EIO; 3064 } 3065 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3066 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3067 bf->bf_m = m0; 3068 bf->bf_node = ni; /* NB: held reference */ 3069 3070 /* setup descriptors */ 3071 ds = bf->bf_desc; 3072 rt = sc->sc_currates; 3073 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3074 3075 /* 3076 * NB: the 802.11 layer marks whether or not we should 3077 * use short preamble based on the current mode and 3078 * negotiated parameters. 3079 */ 3080 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3081 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3082 shortPreamble = AH_TRUE; 3083 sc->sc_stats.ast_tx_shortpre++; 3084 } else { 3085 shortPreamble = AH_FALSE; 3086 } 3087 3088 an = ATH_NODE(ni); 3089 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3090 /* 3091 * Calculate Atheros packet type from IEEE80211 packet header, 3092 * setup for rate calculations, and select h/w transmit queue. 3093 */ 3094 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3095 case IEEE80211_FC0_TYPE_MGT: 3096 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3097 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3098 atype = HAL_PKT_TYPE_BEACON; 3099 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3100 atype = HAL_PKT_TYPE_PROBE_RESP; 3101 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3102 atype = HAL_PKT_TYPE_ATIM; 3103 else 3104 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3105 rix = 0; /* XXX lowest rate */ 3106 try0 = ATH_TXMAXTRY; 3107 if (shortPreamble) 3108 txrate = an->an_tx_mgtratesp; 3109 else 3110 txrate = an->an_tx_mgtrate; 3111 /* NB: force all management frames to highest queue */ 3112 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3113 /* NB: force all management frames to highest queue */ 3114 txq = sc->sc_ac2q[WME_AC_VO]; 3115 } else 3116 txq = sc->sc_ac2q[WME_AC_BE]; 3117 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3118 break; 3119 case IEEE80211_FC0_TYPE_CTL: 3120 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3121 rix = 0; /* XXX lowest rate */ 3122 try0 = ATH_TXMAXTRY; 3123 if (shortPreamble) 3124 txrate = an->an_tx_mgtratesp; 3125 else 3126 txrate = an->an_tx_mgtrate; 3127 /* NB: force all ctl frames to highest queue */ 3128 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3129 /* NB: force all ctl frames to highest queue */ 3130 txq = sc->sc_ac2q[WME_AC_VO]; 3131 } else 3132 txq = sc->sc_ac2q[WME_AC_BE]; 3133 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3134 break; 3135 case IEEE80211_FC0_TYPE_DATA: 3136 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3137 /* 3138 * Data frames; consult the rate control module. 3139 */ 3140 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3141 &rix, &try0, &txrate); 3142 sc->sc_txrate = txrate; /* for LED blinking */ 3143 /* 3144 * Default all non-QoS traffic to the background queue. 3145 */ 3146 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3147 u_int pri = M_WME_GETAC(m0); 3148 txq = sc->sc_ac2q[pri]; 3149 if (ic->ic_wme.wme_wmeChanParams.cap_wmeParams[pri].wmep_noackPolicy) 3150 flags |= HAL_TXDESC_NOACK; 3151 } else 3152 txq = sc->sc_ac2q[WME_AC_BE]; 3153 break; 3154 default: 3155 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3156 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3157 /* XXX statistic */ 3158 m_freem(m0); 3159 return EIO; 3160 } 3161 3162 /* 3163 * When servicing one or more stations in power-save mode 3164 * multicast frames must be buffered until after the beacon. 3165 * We use the CAB queue for that. 3166 */ 3167 if (ismcast && ic->ic_ps_sta) { 3168 txq = sc->sc_cabq; 3169 /* XXX? more bit in 802.11 frame header */ 3170 } 3171 3172 /* 3173 * Calculate miscellaneous flags. 3174 */ 3175 if (ismcast) { 3176 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3177 sc->sc_stats.ast_tx_noack++; 3178 } else if (pktlen > ic->ic_rtsthreshold) { 3179 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3180 cix = rt->info[rix].controlRate; 3181 sc->sc_stats.ast_tx_rts++; 3182 } 3183 3184 /* 3185 * If 802.11g protection is enabled, determine whether 3186 * to use RTS/CTS or just CTS. Note that this is only 3187 * done for OFDM unicast frames. 3188 */ 3189 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3190 rt->info[rix].phy == IEEE80211_T_OFDM && 3191 (flags & HAL_TXDESC_NOACK) == 0) { 3192 /* XXX fragments must use CCK rates w/ protection */ 3193 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3194 flags |= HAL_TXDESC_RTSENA; 3195 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3196 flags |= HAL_TXDESC_CTSENA; 3197 cix = rt->info[sc->sc_protrix].controlRate; 3198 sc->sc_stats.ast_tx_protect++; 3199 } 3200 3201 /* 3202 * Calculate duration. This logically belongs in the 802.11 3203 * layer but it lacks sufficient information to calculate it. 3204 */ 3205 if ((flags & HAL_TXDESC_NOACK) == 0 && 3206 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3207 u_int16_t dur; 3208 /* 3209 * XXX not right with fragmentation. 3210 */ 3211 if (shortPreamble) 3212 dur = rt->info[rix].spAckDuration; 3213 else 3214 dur = rt->info[rix].lpAckDuration; 3215 *(u_int16_t *)wh->i_dur = htole16(dur); 3216 } 3217 3218 /* 3219 * Calculate RTS/CTS rate and duration if needed. 3220 */ 3221 ctsduration = 0; 3222 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3223 /* 3224 * CTS transmit rate is derived from the transmit rate 3225 * by looking in the h/w rate table. We must also factor 3226 * in whether or not a short preamble is to be used. 3227 */ 3228 /* NB: cix is set above where RTS/CTS is enabled */ 3229 KASSERT(cix != 0xff, ("cix not setup")); 3230 ctsrate = rt->info[cix].rateCode; 3231 /* 3232 * Compute the transmit duration based on the frame 3233 * size and the size of an ACK frame. We call into the 3234 * HAL to do the computation since it depends on the 3235 * characteristics of the actual PHY being used. 3236 * 3237 * NB: CTS is assumed the same size as an ACK so we can 3238 * use the precalculated ACK durations. 3239 */ 3240 if (shortPreamble) { 3241 ctsrate |= rt->info[cix].shortPreamble; 3242 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3243 ctsduration += rt->info[cix].spAckDuration; 3244 ctsduration += ath_hal_computetxtime(ah, 3245 rt, pktlen, rix, AH_TRUE); 3246 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3247 ctsduration += rt->info[cix].spAckDuration; 3248 } else { 3249 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3250 ctsduration += rt->info[cix].lpAckDuration; 3251 ctsduration += ath_hal_computetxtime(ah, 3252 rt, pktlen, rix, AH_FALSE); 3253 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3254 ctsduration += rt->info[cix].lpAckDuration; 3255 } 3256 /* 3257 * Must disable multi-rate retry when using RTS/CTS. 3258 */ 3259 try0 = ATH_TXMAXTRY; 3260 } else 3261 ctsrate = 0; 3262 3263 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3264 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3265 sc->sc_hwmap[txrate].ieeerate, -1); 3266 3267 if (ic->ic_rawbpf) 3268 bpf_mtap(ic->ic_rawbpf, m0); 3269 if (sc->sc_drvbpf) { 3270 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].flags; 3271 if (iswep) 3272 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3273 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3274 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3275 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3276 3277 bpf_mtap2(sc->sc_drvbpf, 3278 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3279 } 3280 3281 /* 3282 * Determine if a tx interrupt should be generated for 3283 * this descriptor. We take a tx interrupt to reap 3284 * descriptors when the h/w hits an EOL condition or 3285 * when the descriptor is specifically marked to generate 3286 * an interrupt. We periodically mark descriptors in this 3287 * way to insure timely replenishing of the supply needed 3288 * for sending frames. Defering interrupts reduces system 3289 * load and potentially allows more concurrent work to be 3290 * done but if done to aggressively can cause senders to 3291 * backup. 3292 * 3293 * NB: use >= to deal with sc_txintrperiod changing 3294 * dynamically through sysctl. 3295 */ 3296 if (flags & HAL_TXDESC_INTREQ) { 3297 txq->axq_intrcnt = 0; 3298 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3299 flags |= HAL_TXDESC_INTREQ; 3300 txq->axq_intrcnt = 0; 3301 } 3302 3303 /* 3304 * Formulate first tx descriptor with tx controls. 3305 */ 3306 /* XXX check return value? */ 3307 ath_hal_setuptxdesc(ah, ds 3308 , pktlen /* packet length */ 3309 , hdrlen /* header length */ 3310 , atype /* Atheros packet type */ 3311 , ni->ni_txpower /* txpower */ 3312 , txrate, try0 /* series 0 rate/tries */ 3313 , keyix /* key cache index */ 3314 , sc->sc_txantenna /* antenna mode */ 3315 , flags /* flags */ 3316 , ctsrate /* rts/cts rate */ 3317 , ctsduration /* rts/cts duration */ 3318 ); 3319 /* 3320 * Setup the multi-rate retry state only when we're 3321 * going to use it. This assumes ath_hal_setuptxdesc 3322 * initializes the descriptors (so we don't have to) 3323 * when the hardware supports multi-rate retry and 3324 * we don't use it. 3325 */ 3326 if (try0 != ATH_TXMAXTRY) 3327 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3328 3329 /* 3330 * Fillin the remainder of the descriptor info. 3331 */ 3332 ds0 = ds; 3333 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3334 ds->ds_data = bf->bf_segs[i].ds_addr; 3335 if (i == bf->bf_nseg - 1) 3336 ds->ds_link = 0; 3337 else 3338 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3339 ath_hal_filltxdesc(ah, ds 3340 , bf->bf_segs[i].ds_len /* segment length */ 3341 , i == 0 /* first segment */ 3342 , i == bf->bf_nseg - 1 /* last segment */ 3343 , ds0 /* first descriptor */ 3344 ); 3345 DPRINTF(sc, ATH_DEBUG_XMIT, 3346 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3347 __func__, i, ds->ds_link, ds->ds_data, 3348 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3349 } 3350#if 0 3351 if ((flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) && 3352 !ath_hal_updateCTSForBursting(ah, ds 3353 , txq->axq_linkbuf != NULL ? 3354 txq->axq_linkbuf->bf_desc : NULL 3355 , txq->axq_lastdsWithCTS 3356 , txq->axq_gatingds 3357 , IEEE80211_TXOP_TO_US(ic->ic_chanParams.cap_wmeParams[skb->priority].wmep_txopLimit) 3358 , ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE))) { 3359 ATH_TXQ_LOCK(txq); 3360 txq->axq_lastdsWithCTS = ds; 3361 /* set gating Desc to final desc */ 3362 txq->axq_gatingds = (struct ath_desc *)txq->axq_link; 3363 ATH_TXQ_UNLOCK(txq); 3364 } 3365#endif 3366 /* 3367 * Insert the frame on the outbound list and 3368 * pass it on to the hardware. 3369 */ 3370 ATH_TXQ_LOCK(txq); 3371 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3372 if (txq->axq_link == NULL) { 3373 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3374 DPRINTF(sc, ATH_DEBUG_XMIT, 3375 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3376 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3377 txq->axq_depth); 3378 } else { 3379 *txq->axq_link = bf->bf_daddr; 3380 DPRINTF(sc, ATH_DEBUG_XMIT, 3381 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3382 txq->axq_qnum, txq->axq_link, 3383 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3384 } 3385 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3386 ATH_TXQ_UNLOCK(txq); 3387 3388 /* 3389 * The CAB queue is started from the SWBA handler since 3390 * frames only go out on DTIM and to avoid possible races. 3391 */ 3392 if (txq != sc->sc_cabq) 3393 ath_hal_txstart(ah, txq->axq_qnum); 3394 return 0; 3395} 3396 3397/* 3398 * Process completed xmit descriptors from the specified queue. 3399 */ 3400static void 3401ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3402{ 3403 struct ath_hal *ah = sc->sc_ah; 3404 struct ieee80211com *ic = &sc->sc_ic; 3405 struct ath_buf *bf; 3406 struct ath_desc *ds; 3407 struct ieee80211_node *ni; 3408 struct ath_node *an; 3409 int sr, lr, pri; 3410 HAL_STATUS status; 3411 3412 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3413 __func__, txq->axq_qnum, 3414 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3415 txq->axq_link); 3416 for (;;) { 3417 ATH_TXQ_LOCK(txq); 3418 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3419 bf = STAILQ_FIRST(&txq->axq_q); 3420 if (bf == NULL) { 3421 txq->axq_link = NULL; 3422 ATH_TXQ_UNLOCK(txq); 3423 break; 3424 } 3425 /* only the last descriptor is needed */ 3426 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3427 status = ath_hal_txprocdesc(ah, ds); 3428#ifdef AR_DEBUG 3429 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3430 ath_printtxbuf(bf, status == HAL_OK); 3431#endif 3432 if (status == HAL_EINPROGRESS) { 3433 ATH_TXQ_UNLOCK(txq); 3434 break; 3435 } 3436#if 0 3437 if (bf->bf_desc == txq->axq_lastdsWithCTS) 3438 txq->axq_lastdsWithCTS = NULL; 3439 if (ds == txq->axq_gatingds) 3440 txq->axq_gatingds = NULL; 3441#endif 3442 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3443 ATH_TXQ_UNLOCK(txq); 3444 3445 ni = bf->bf_node; 3446 if (ni != NULL) { 3447 an = ATH_NODE(ni); 3448 if (ds->ds_txstat.ts_status == 0) { 3449 u_int8_t txant = ds->ds_txstat.ts_antenna; 3450 sc->sc_stats.ast_ant_tx[txant]++; 3451 sc->sc_ant_tx[txant]++; 3452 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3453 sc->sc_stats.ast_tx_altrate++; 3454 sc->sc_stats.ast_tx_rssi = 3455 ds->ds_txstat.ts_rssi; 3456 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3457 ds->ds_txstat.ts_rssi); 3458 pri = M_WME_GETAC(bf->bf_m); 3459 if (pri >= WME_AC_VO) 3460 ic->ic_wme.wme_hipri_traffic++; 3461 ni->ni_inact = ni->ni_inact_reload; 3462 } else { 3463 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3464 sc->sc_stats.ast_tx_xretries++; 3465 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3466 sc->sc_stats.ast_tx_fifoerr++; 3467 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3468 sc->sc_stats.ast_tx_filtered++; 3469 } 3470 sr = ds->ds_txstat.ts_shortretry; 3471 lr = ds->ds_txstat.ts_longretry; 3472 sc->sc_stats.ast_tx_shortretry += sr; 3473 sc->sc_stats.ast_tx_longretry += lr; 3474 /* 3475 * Hand the descriptor to the rate control algorithm. 3476 */ 3477 ath_rate_tx_complete(sc, an, ds); 3478 /* 3479 * Reclaim reference to node. 3480 * 3481 * NB: the node may be reclaimed here if, for example 3482 * this is a DEAUTH message that was sent and the 3483 * node was timed out due to inactivity. 3484 */ 3485 ieee80211_free_node(ni); 3486 } 3487 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3488 BUS_DMASYNC_POSTWRITE); 3489 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3490 m_freem(bf->bf_m); 3491 bf->bf_m = NULL; 3492 bf->bf_node = NULL; 3493 3494 ATH_TXBUF_LOCK(sc); 3495 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3496 ATH_TXBUF_UNLOCK(sc); 3497 } 3498} 3499 3500/* 3501 * Deferred processing of transmit interrupt; special-cased 3502 * for a single hardware transmit queue (e.g. 5210 and 5211). 3503 */ 3504static void 3505ath_tx_proc_q0(void *arg, int npending) 3506{ 3507 struct ath_softc *sc = arg; 3508 struct ifnet *ifp = &sc->sc_if; 3509 3510 ath_tx_processq(sc, &sc->sc_txq[0]); 3511 ath_tx_processq(sc, sc->sc_cabq); 3512 ifp->if_flags &= ~IFF_OACTIVE; 3513 sc->sc_tx_timer = 0; 3514 3515 if (sc->sc_softled) 3516 ath_led_event(sc, ATH_LED_TX); 3517 3518 ath_start(ifp); 3519} 3520 3521/* 3522 * Deferred processing of transmit interrupt; special-cased 3523 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3524 */ 3525static void 3526ath_tx_proc_q0123(void *arg, int npending) 3527{ 3528 struct ath_softc *sc = arg; 3529 struct ifnet *ifp = &sc->sc_if; 3530 3531 /* 3532 * Process each active queue. 3533 */ 3534 ath_tx_processq(sc, &sc->sc_txq[0]); 3535 ath_tx_processq(sc, &sc->sc_txq[1]); 3536 ath_tx_processq(sc, &sc->sc_txq[2]); 3537 ath_tx_processq(sc, &sc->sc_txq[3]); 3538 ath_tx_processq(sc, sc->sc_cabq); 3539 3540 ifp->if_flags &= ~IFF_OACTIVE; 3541 sc->sc_tx_timer = 0; 3542 3543 if (sc->sc_softled) 3544 ath_led_event(sc, ATH_LED_TX); 3545 3546 ath_start(ifp); 3547} 3548 3549/* 3550 * Deferred processing of transmit interrupt. 3551 */ 3552static void 3553ath_tx_proc(void *arg, int npending) 3554{ 3555 struct ath_softc *sc = arg; 3556 struct ifnet *ifp = &sc->sc_if; 3557 int i; 3558 3559 /* 3560 * Process each active queue. 3561 */ 3562 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3563 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3564 if (ATH_TXQ_SETUP(sc, i)) 3565 ath_tx_processq(sc, &sc->sc_txq[i]); 3566 3567 ifp->if_flags &= ~IFF_OACTIVE; 3568 sc->sc_tx_timer = 0; 3569 3570 if (sc->sc_softled) 3571 ath_led_event(sc, ATH_LED_TX); 3572 3573 ath_start(ifp); 3574} 3575 3576static void 3577ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3578{ 3579 struct ath_hal *ah = sc->sc_ah; 3580 struct ieee80211_node *ni; 3581 struct ath_buf *bf; 3582 3583 /* 3584 * NB: this assumes output has been stopped and 3585 * we do not need to block ath_tx_tasklet 3586 */ 3587 for (;;) { 3588 ATH_TXQ_LOCK(txq); 3589 bf = STAILQ_FIRST(&txq->axq_q); 3590 if (bf == NULL) { 3591 txq->axq_link = NULL; 3592 ATH_TXQ_UNLOCK(txq); 3593 break; 3594 } 3595 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3596 ATH_TXQ_UNLOCK(txq); 3597#ifdef AR_DEBUG 3598 if (sc->sc_debug & ATH_DEBUG_RESET) 3599 ath_printtxbuf(bf, 3600 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3601#endif /* AR_DEBUG */ 3602 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3603 m_freem(bf->bf_m); 3604 bf->bf_m = NULL; 3605 ni = bf->bf_node; 3606 bf->bf_node = NULL; 3607 if (ni != NULL) { 3608 /* 3609 * Reclaim node reference. 3610 */ 3611 ieee80211_free_node(ni); 3612 } 3613 ATH_TXBUF_LOCK(sc); 3614 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3615 ATH_TXBUF_UNLOCK(sc); 3616 } 3617} 3618 3619static void 3620ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3621{ 3622 struct ath_hal *ah = sc->sc_ah; 3623 3624 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 3625 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3626 __func__, txq->axq_qnum, 3627 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 3628 txq->axq_link); 3629} 3630 3631/* 3632 * Drain the transmit queues and reclaim resources. 3633 */ 3634static void 3635ath_draintxq(struct ath_softc *sc) 3636{ 3637 struct ath_hal *ah = sc->sc_ah; 3638 struct ifnet *ifp = &sc->sc_if; 3639 int i; 3640 3641 /* XXX return value */ 3642 if (!sc->sc_invalid) { 3643 /* don't touch the hardware if marked invalid */ 3644 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 3645 DPRINTF(sc, ATH_DEBUG_RESET, 3646 "%s: beacon queue %p\n", __func__, 3647 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 3648 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3649 if (ATH_TXQ_SETUP(sc, i)) 3650 ath_tx_stopdma(sc, &sc->sc_txq[i]); 3651 } 3652 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3653 if (ATH_TXQ_SETUP(sc, i)) 3654 ath_tx_draintxq(sc, &sc->sc_txq[i]); 3655 ifp->if_flags &= ~IFF_OACTIVE; 3656 sc->sc_tx_timer = 0; 3657} 3658 3659/* 3660 * Disable the receive h/w in preparation for a reset. 3661 */ 3662static void 3663ath_stoprecv(struct ath_softc *sc) 3664{ 3665#define PA2DESC(_sc, _pa) \ 3666 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3667 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3668 struct ath_hal *ah = sc->sc_ah; 3669 3670 ath_hal_stoppcurecv(ah); /* disable PCU */ 3671 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 3672 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 3673 DELAY(3000); /* 3ms is long enough for 1 frame */ 3674#ifdef AR_DEBUG 3675 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 3676 struct ath_buf *bf; 3677 3678 printf("%s: rx queue %p, link %p\n", __func__, 3679 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 3680 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3681 struct ath_desc *ds = bf->bf_desc; 3682 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 3683 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3684 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 3685 ath_printrxbuf(bf, status == HAL_OK); 3686 } 3687 } 3688#endif 3689 sc->sc_rxlink = NULL; /* just in case */ 3690#undef PA2DESC 3691} 3692 3693/* 3694 * Enable the receive h/w following a reset. 3695 */ 3696static int 3697ath_startrecv(struct ath_softc *sc) 3698{ 3699 struct ath_hal *ah = sc->sc_ah; 3700 struct ath_buf *bf; 3701 3702 sc->sc_rxlink = NULL; 3703 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3704 int error = ath_rxbuf_init(sc, bf); 3705 if (error != 0) { 3706 DPRINTF(sc, ATH_DEBUG_RECV, 3707 "%s: ath_rxbuf_init failed %d\n", 3708 __func__, error); 3709 return error; 3710 } 3711 } 3712 3713 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3714 ath_hal_putrxbuf(ah, bf->bf_daddr); 3715 ath_hal_rxena(ah); /* enable recv descriptors */ 3716 ath_mode_init(sc); /* set filters, etc. */ 3717 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 3718 return 0; 3719} 3720 3721/* 3722 * Update internal state after a channel change. 3723 */ 3724static void 3725ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 3726{ 3727 struct ieee80211com *ic = &sc->sc_ic; 3728 enum ieee80211_phymode mode; 3729 u_int16_t flags; 3730 3731 /* 3732 * Change channels and update the h/w rate map 3733 * if we're switching; e.g. 11a to 11b/g. 3734 */ 3735 mode = ieee80211_chan2mode(ic, chan); 3736 if (mode != sc->sc_curmode) 3737 ath_setcurmode(sc, mode); 3738 /* 3739 * Update BPF state. NB: ethereal et. al. don't handle 3740 * merged flags well so pick a unique mode for their use. 3741 */ 3742 if (IEEE80211_IS_CHAN_A(chan)) 3743 flags = IEEE80211_CHAN_A; 3744 /* XXX 11g schizophrenia */ 3745 else if (IEEE80211_IS_CHAN_G(chan) || 3746 IEEE80211_IS_CHAN_PUREG(chan)) 3747 flags = IEEE80211_CHAN_G; 3748 else 3749 flags = IEEE80211_CHAN_B; 3750 if (IEEE80211_IS_CHAN_T(chan)) 3751 flags |= IEEE80211_CHAN_TURBO; 3752 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 3753 htole16(chan->ic_freq); 3754 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 3755 htole16(flags); 3756} 3757 3758/* 3759 * Set/change channels. If the channel is really being changed, 3760 * it's done by reseting the chip. To accomplish this we must 3761 * first cleanup any pending DMA, then restart stuff after a la 3762 * ath_init. 3763 */ 3764static int 3765ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 3766{ 3767 struct ath_hal *ah = sc->sc_ah; 3768 struct ieee80211com *ic = &sc->sc_ic; 3769 HAL_CHANNEL hchan; 3770 3771 /* 3772 * Convert to a HAL channel description with 3773 * the flags constrained to reflect the current 3774 * operating mode. 3775 */ 3776 hchan.channel = chan->ic_freq; 3777 hchan.channelFlags = ath_chan2flags(ic, chan); 3778 3779 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 3780 __func__, 3781 ath_hal_mhz2ieee(sc->sc_curchan.channel, 3782 sc->sc_curchan.channelFlags), 3783 sc->sc_curchan.channel, 3784 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 3785 if (hchan.channel != sc->sc_curchan.channel || 3786 hchan.channelFlags != sc->sc_curchan.channelFlags) { 3787 HAL_STATUS status; 3788 3789 /* 3790 * To switch channels clear any pending DMA operations; 3791 * wait long enough for the RX fifo to drain, reset the 3792 * hardware at the new frequency, and then re-enable 3793 * the relevant bits of the h/w. 3794 */ 3795 ath_hal_intrset(ah, 0); /* disable interrupts */ 3796 ath_draintxq(sc); /* clear pending tx frames */ 3797 ath_stoprecv(sc); /* turn off frame recv */ 3798 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 3799 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset " 3800 "channel %u (%u Mhz)\n", 3801 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 3802 return EIO; 3803 } 3804 sc->sc_curchan = hchan; 3805 ath_update_txpow(sc); /* update tx power state */ 3806 3807 /* 3808 * Re-enable rx framework. 3809 */ 3810 if (ath_startrecv(sc) != 0) { 3811 if_printf(ic->ic_ifp, 3812 "ath_chan_set: unable to restart recv logic\n"); 3813 return EIO; 3814 } 3815 3816 /* 3817 * Change channels and update the h/w rate map 3818 * if we're switching; e.g. 11a to 11b/g. 3819 */ 3820 ic->ic_ibss_chan = chan; 3821 ath_chan_change(sc, chan); 3822 3823 /* 3824 * Re-enable interrupts. 3825 */ 3826 ath_hal_intrset(ah, sc->sc_imask); 3827 } 3828 return 0; 3829} 3830 3831static void 3832ath_next_scan(void *arg) 3833{ 3834 struct ath_softc *sc = arg; 3835 struct ieee80211com *ic = &sc->sc_ic; 3836 3837 if (ic->ic_state == IEEE80211_S_SCAN) 3838 ieee80211_next_scan(ic); 3839} 3840 3841/* 3842 * Periodically recalibrate the PHY to account 3843 * for temperature/environment changes. 3844 */ 3845static void 3846ath_calibrate(void *arg) 3847{ 3848 struct ath_softc *sc = arg; 3849 struct ath_hal *ah = sc->sc_ah; 3850 3851 sc->sc_stats.ast_per_cal++; 3852 3853 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 3854 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 3855 3856 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 3857 /* 3858 * Rfgain is out of bounds, reset the chip 3859 * to load new gain values. 3860 */ 3861 sc->sc_stats.ast_per_rfgain++; 3862 ath_reset(&sc->sc_if); 3863 } 3864 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 3865 DPRINTF(sc, ATH_DEBUG_ANY, 3866 "%s: calibration of channel %u failed\n", 3867 __func__, sc->sc_curchan.channel); 3868 sc->sc_stats.ast_per_calfail++; 3869 } 3870 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 3871} 3872 3873static int 3874ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3875{ 3876 struct ifnet *ifp = ic->ic_ifp; 3877 struct ath_softc *sc = ifp->if_softc; 3878 struct ath_hal *ah = sc->sc_ah; 3879 struct ieee80211_node *ni; 3880 int i, error; 3881 const u_int8_t *bssid; 3882 u_int32_t rfilt; 3883 static const HAL_LED_STATE leds[] = { 3884 HAL_LED_INIT, /* IEEE80211_S_INIT */ 3885 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 3886 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 3887 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 3888 HAL_LED_RUN, /* IEEE80211_S_RUN */ 3889 }; 3890 3891 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 3892 ieee80211_state_name[ic->ic_state], 3893 ieee80211_state_name[nstate]); 3894 3895 callout_stop(&sc->sc_scan_ch); 3896 callout_stop(&sc->sc_cal_ch); 3897 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 3898 3899 if (nstate == IEEE80211_S_INIT) { 3900 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 3901 ath_hal_intrset(ah, sc->sc_imask); 3902 /* 3903 * Notify the rate control algorithm. 3904 */ 3905 ath_rate_newstate(sc, nstate); 3906 goto done; 3907 } 3908 ni = ic->ic_bss; 3909 error = ath_chan_set(sc, ni->ni_chan); 3910 if (error != 0) 3911 goto bad; 3912 rfilt = ath_calcrxfilter(sc, nstate); 3913 if (nstate == IEEE80211_S_SCAN) 3914 bssid = ifp->if_broadcastaddr; 3915 else 3916 bssid = ni->ni_bssid; 3917 ath_hal_setrxfilter(ah, rfilt); 3918 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 3919 __func__, rfilt, ether_sprintf(bssid)); 3920 3921 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 3922 ath_hal_setassocid(ah, bssid, ni->ni_associd); 3923 else 3924 ath_hal_setassocid(ah, bssid, 0); 3925 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 3926 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3927 if (ath_hal_keyisvalid(ah, i)) 3928 ath_hal_keysetmac(ah, i, bssid); 3929 } 3930 3931 /* 3932 * Notify the rate control algorithm so rates 3933 * are setup should ath_beacon_alloc be called. 3934 */ 3935 ath_rate_newstate(sc, nstate); 3936 3937 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3938 /* nothing to do */; 3939 } else if (nstate == IEEE80211_S_RUN) { 3940 DPRINTF(sc, ATH_DEBUG_STATE, 3941 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 3942 "capinfo=0x%04x chan=%d\n" 3943 , __func__ 3944 , ic->ic_flags 3945 , ni->ni_intval 3946 , ether_sprintf(ni->ni_bssid) 3947 , ni->ni_capinfo 3948 , ieee80211_chan2ieee(ic, ni->ni_chan)); 3949 3950 /* 3951 * Allocate and setup the beacon frame for AP or adhoc mode. 3952 */ 3953 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3954 ic->ic_opmode == IEEE80211_M_IBSS) { 3955 error = ath_beacon_alloc(sc, ni); 3956 if (error != 0) 3957 goto bad; 3958 } 3959 3960 /* 3961 * Configure the beacon and sleep timers. 3962 */ 3963 ath_beacon_config(sc); 3964 } else { 3965 ath_hal_intrset(ah, 3966 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 3967 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 3968 } 3969done: 3970 /* 3971 * Invoke the parent method to complete the work. 3972 */ 3973 error = sc->sc_newstate(ic, nstate, arg); 3974 /* 3975 * Finally, start any timers. 3976 */ 3977 if (nstate == IEEE80211_S_RUN) { 3978 /* start periodic recalibration timer */ 3979 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 3980 ath_calibrate, sc); 3981 } else if (nstate == IEEE80211_S_SCAN) { 3982 /* start ap/neighbor scan timer */ 3983 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 3984 ath_next_scan, sc); 3985 } 3986bad: 3987 return error; 3988} 3989 3990/* 3991 * Setup driver-specific state for a newly associated node. 3992 * Note that we're called also on a re-associate, the isnew 3993 * param tells us if this is the first time or not. 3994 */ 3995static void 3996ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 3997{ 3998 struct ath_softc *sc = ic->ic_ifp->if_softc; 3999 4000 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4001} 4002 4003static int 4004ath_getchannels(struct ath_softc *sc, u_int cc, 4005 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4006{ 4007 struct ieee80211com *ic = &sc->sc_ic; 4008 struct ifnet *ifp = &sc->sc_if; 4009 struct ath_hal *ah = sc->sc_ah; 4010 HAL_CHANNEL *chans; 4011 int i, ix, nchan; 4012 4013 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4014 M_TEMP, M_NOWAIT); 4015 if (chans == NULL) { 4016 if_printf(ifp, "unable to allocate channel table\n"); 4017 return ENOMEM; 4018 } 4019 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4020 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4021 u_int32_t rd; 4022 4023 ath_hal_getregdomain(ah, &rd); 4024 if_printf(ifp, "unable to collect channel list from hal; " 4025 "regdomain likely %u country code %u\n", rd, cc); 4026 free(chans, M_TEMP); 4027 return EINVAL; 4028 } 4029 4030 /* 4031 * Convert HAL channels to ieee80211 ones and insert 4032 * them in the table according to their channel number. 4033 */ 4034 for (i = 0; i < nchan; i++) { 4035 HAL_CHANNEL *c = &chans[i]; 4036 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4037 if (ix > IEEE80211_CHAN_MAX) { 4038 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4039 ix, c->channel, c->channelFlags); 4040 continue; 4041 } 4042 /* NB: flags are known to be compatible */ 4043 if (ic->ic_channels[ix].ic_freq == 0) { 4044 ic->ic_channels[ix].ic_freq = c->channel; 4045 ic->ic_channels[ix].ic_flags = c->channelFlags; 4046 } else { 4047 /* channels overlap; e.g. 11g and 11b */ 4048 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4049 } 4050 } 4051 free(chans, M_TEMP); 4052 return 0; 4053} 4054 4055static void 4056ath_led_done(void *arg) 4057{ 4058 struct ath_softc *sc = arg; 4059 4060 sc->sc_blinking = 0; 4061} 4062 4063/* 4064 * Turn the LED off: flip the pin and then set a timer so no 4065 * update will happen for the specified duration. 4066 */ 4067static void 4068ath_led_off(void *arg) 4069{ 4070 struct ath_softc *sc = arg; 4071 4072 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4073 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4074} 4075 4076/* 4077 * Blink the LED according to the specified on/off times. 4078 */ 4079static void 4080ath_led_blink(struct ath_softc *sc, int on, int off) 4081{ 4082 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4083 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4084 sc->sc_blinking = 1; 4085 sc->sc_ledoff = off; 4086 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4087} 4088 4089static void 4090ath_led_event(struct ath_softc *sc, int event) 4091{ 4092 4093 sc->sc_ledevent = ticks; /* time of last event */ 4094 if (sc->sc_blinking) /* don't interrupt active blink */ 4095 return; 4096 switch (event) { 4097 case ATH_LED_POLL: 4098 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4099 sc->sc_hwmap[0].ledoff); 4100 break; 4101 case ATH_LED_TX: 4102 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4103 sc->sc_hwmap[sc->sc_txrate].ledoff); 4104 break; 4105 case ATH_LED_RX: 4106 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4107 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4108 break; 4109 } 4110} 4111 4112static void 4113ath_update_txpow(struct ath_softc *sc) 4114{ 4115 struct ieee80211com *ic = &sc->sc_ic; 4116 struct ath_hal *ah = sc->sc_ah; 4117 u_int32_t txpow; 4118 4119 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4120 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4121 /* read back in case value is clamped */ 4122 ath_hal_gettxpowlimit(ah, &txpow); 4123 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4124 } 4125 /* 4126 * Fetch max tx power level for status requests. 4127 */ 4128 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4129 ic->ic_bss->ni_txpower = txpow; 4130} 4131 4132static int 4133ath_rate_setup(struct ath_softc *sc, u_int mode) 4134{ 4135 struct ath_hal *ah = sc->sc_ah; 4136 struct ieee80211com *ic = &sc->sc_ic; 4137 const HAL_RATE_TABLE *rt; 4138 struct ieee80211_rateset *rs; 4139 int i, maxrates; 4140 4141 switch (mode) { 4142 case IEEE80211_MODE_11A: 4143 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4144 break; 4145 case IEEE80211_MODE_11B: 4146 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4147 break; 4148 case IEEE80211_MODE_11G: 4149 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4150 break; 4151 case IEEE80211_MODE_TURBO_A: 4152 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4153 break; 4154 case IEEE80211_MODE_TURBO_G: 4155 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4156 break; 4157 default: 4158 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4159 __func__, mode); 4160 return 0; 4161 } 4162 rt = sc->sc_rates[mode]; 4163 if (rt == NULL) 4164 return 0; 4165 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4166 DPRINTF(sc, ATH_DEBUG_ANY, 4167 "%s: rate table too small (%u > %u)\n", 4168 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4169 maxrates = IEEE80211_RATE_MAXSIZE; 4170 } else 4171 maxrates = rt->rateCount; 4172 rs = &ic->ic_sup_rates[mode]; 4173 for (i = 0; i < maxrates; i++) 4174 rs->rs_rates[i] = rt->info[i].dot11Rate; 4175 rs->rs_nrates = maxrates; 4176 return 1; 4177} 4178 4179static void 4180ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4181{ 4182#define N(a) (sizeof(a)/sizeof(a[0])) 4183 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4184 static const struct { 4185 u_int rate; /* tx/rx 802.11 rate */ 4186 u_int16_t timeOn; /* LED on time (ms) */ 4187 u_int16_t timeOff; /* LED off time (ms) */ 4188 } blinkrates[] = { 4189 { 108, 40, 10 }, 4190 { 96, 44, 11 }, 4191 { 72, 50, 13 }, 4192 { 48, 57, 14 }, 4193 { 36, 67, 16 }, 4194 { 24, 80, 20 }, 4195 { 22, 100, 25 }, 4196 { 18, 133, 34 }, 4197 { 12, 160, 40 }, 4198 { 10, 200, 50 }, 4199 { 6, 240, 58 }, 4200 { 4, 267, 66 }, 4201 { 2, 400, 100 }, 4202 { 0, 500, 130 }, 4203 }; 4204 const HAL_RATE_TABLE *rt; 4205 int i, j; 4206 4207 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4208 rt = sc->sc_rates[mode]; 4209 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4210 for (i = 0; i < rt->rateCount; i++) 4211 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4212 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4213 for (i = 0; i < 32; i++) { 4214 u_int8_t ix = rt->rateCodeToIndex[i]; 4215 if (ix == 0xff) { 4216 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4217 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4218 continue; 4219 } 4220 sc->sc_hwmap[i].ieeerate = 4221 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4222 if (rt->info[ix].shortPreamble || 4223 rt->info[ix].phy == IEEE80211_T_OFDM) 4224 sc->sc_hwmap[i].flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4225 /* setup blink rate table to avoid per-packet lookup */ 4226 for (j = 0; j < N(blinkrates)-1; j++) 4227 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4228 break; 4229 /* NB: this uses the last entry if the rate isn't found */ 4230 /* XXX beware of overlow */ 4231 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4232 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4233 } 4234 sc->sc_currates = rt; 4235 sc->sc_curmode = mode; 4236 /* 4237 * All protection frames are transmited at 2Mb/s for 4238 * 11g, otherwise at 1Mb/s. 4239 * XXX select protection rate index from rate table. 4240 */ 4241 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4242 /* NB: caller is responsible for reseting rate control state */ 4243#undef N 4244} 4245 4246#ifdef AR_DEBUG 4247static void 4248ath_printrxbuf(struct ath_buf *bf, int done) 4249{ 4250 struct ath_desc *ds; 4251 int i; 4252 4253 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4254 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4255 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4256 ds->ds_link, ds->ds_data, 4257 ds->ds_ctl0, ds->ds_ctl1, 4258 ds->ds_hw[0], ds->ds_hw[1], 4259 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4260 } 4261} 4262 4263static void 4264ath_printtxbuf(struct ath_buf *bf, int done) 4265{ 4266 struct ath_desc *ds; 4267 int i; 4268 4269 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4270 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4271 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4272 ds->ds_link, ds->ds_data, 4273 ds->ds_ctl0, ds->ds_ctl1, 4274 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4275 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4276 } 4277} 4278#endif /* AR_DEBUG */ 4279 4280static void 4281ath_watchdog(struct ifnet *ifp) 4282{ 4283 struct ath_softc *sc = ifp->if_softc; 4284 struct ieee80211com *ic = &sc->sc_ic; 4285 4286 ifp->if_timer = 0; 4287 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4288 return; 4289 if (sc->sc_tx_timer) { 4290 if (--sc->sc_tx_timer == 0) { 4291 if_printf(ifp, "device timeout\n"); 4292 ath_reset(ifp); 4293 ifp->if_oerrors++; 4294 sc->sc_stats.ast_watchdog++; 4295 } else 4296 ifp->if_timer = 1; 4297 } 4298 ieee80211_watchdog(ic); 4299} 4300 4301/* 4302 * Diagnostic interface to the HAL. This is used by various 4303 * tools to do things like retrieve register contents for 4304 * debugging. The mechanism is intentionally opaque so that 4305 * it can change frequently w/o concern for compatiblity. 4306 */ 4307static int 4308ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4309{ 4310 struct ath_hal *ah = sc->sc_ah; 4311 u_int id = ad->ad_id & ATH_DIAG_ID; 4312 void *indata = NULL; 4313 void *outdata = NULL; 4314 u_int32_t insize = ad->ad_in_size; 4315 u_int32_t outsize = ad->ad_out_size; 4316 int error = 0; 4317 4318 if (ad->ad_id & ATH_DIAG_IN) { 4319 /* 4320 * Copy in data. 4321 */ 4322 indata = malloc(insize, M_TEMP, M_NOWAIT); 4323 if (indata == NULL) { 4324 error = ENOMEM; 4325 goto bad; 4326 } 4327 error = copyin(ad->ad_in_data, indata, insize); 4328 if (error) 4329 goto bad; 4330 } 4331 if (ad->ad_id & ATH_DIAG_DYN) { 4332 /* 4333 * Allocate a buffer for the results (otherwise the HAL 4334 * returns a pointer to a buffer where we can read the 4335 * results). Note that we depend on the HAL leaving this 4336 * pointer for us to use below in reclaiming the buffer; 4337 * may want to be more defensive. 4338 */ 4339 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4340 if (outdata == NULL) { 4341 error = ENOMEM; 4342 goto bad; 4343 } 4344 } 4345 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4346 if (outsize < ad->ad_out_size) 4347 ad->ad_out_size = outsize; 4348 if (outdata != NULL) 4349 error = copyout(outdata, ad->ad_out_data, 4350 ad->ad_out_size); 4351 } else { 4352 error = EINVAL; 4353 } 4354bad: 4355 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4356 free(indata, M_TEMP); 4357 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4358 free(outdata, M_TEMP); 4359 return error; 4360} 4361 4362static int 4363ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4364{ 4365#define IS_RUNNING(ifp) \ 4366 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) 4367 struct ath_softc *sc = ifp->if_softc; 4368 struct ieee80211com *ic = &sc->sc_ic; 4369 struct ifreq *ifr = (struct ifreq *)data; 4370 int error = 0; 4371 4372 ATH_LOCK(sc); 4373 switch (cmd) { 4374 case SIOCSIFFLAGS: 4375 if (IS_RUNNING(ifp)) { 4376 /* 4377 * To avoid rescanning another access point, 4378 * do not call ath_init() here. Instead, 4379 * only reflect promisc mode settings. 4380 */ 4381 ath_mode_init(sc); 4382 } else if (ifp->if_flags & IFF_UP) { 4383 /* 4384 * Beware of being called during attach/detach 4385 * to reset promiscuous mode. In that case we 4386 * will still be marked UP but not RUNNING. 4387 * However trying to re-init the interface 4388 * is the wrong thing to do as we've already 4389 * torn down much of our state. There's 4390 * probably a better way to deal with this. 4391 */ 4392 if (!sc->sc_invalid && ic->ic_bss != NULL) 4393 ath_init(ifp); /* XXX lose error */ 4394 } else 4395 ath_stop_locked(ifp); 4396 break; 4397 case SIOCADDMULTI: 4398 case SIOCDELMULTI: 4399 /* 4400 * The upper layer has already installed/removed 4401 * the multicast address(es), just recalculate the 4402 * multicast filter for the card. 4403 */ 4404 if (ifp->if_flags & IFF_RUNNING) 4405 ath_mode_init(sc); 4406 break; 4407 case SIOCGATHSTATS: 4408 /* NB: embed these numbers to get a consistent view */ 4409 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4410 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4411 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4412 ATH_UNLOCK(sc); 4413 /* 4414 * NB: Drop the softc lock in case of a page fault; 4415 * we'll accept any potential inconsisentcy in the 4416 * statistics. The alternative is to copy the data 4417 * to a local structure. 4418 */ 4419 return copyout(&sc->sc_stats, 4420 ifr->ifr_data, sizeof (sc->sc_stats)); 4421 case SIOCGATHDIAG: 4422 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4423 break; 4424 default: 4425 error = ieee80211_ioctl(ic, cmd, data); 4426 if (error == ENETRESET) { 4427 if (IS_RUNNING(ifp) && 4428 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4429 ath_init(ifp); /* XXX lose error */ 4430 error = 0; 4431 } 4432 if (error == ERESTART) 4433 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4434 break; 4435 } 4436 ATH_UNLOCK(sc); 4437 return error; 4438#undef IS_RUNNING 4439} 4440 4441static int 4442ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 4443{ 4444 struct ath_softc *sc = arg1; 4445 u_int slottime = ath_hal_getslottime(sc->sc_ah); 4446 int error; 4447 4448 error = sysctl_handle_int(oidp, &slottime, 0, req); 4449 if (error || !req->newptr) 4450 return error; 4451 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 4452} 4453 4454static int 4455ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 4456{ 4457 struct ath_softc *sc = arg1; 4458 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 4459 int error; 4460 4461 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 4462 if (error || !req->newptr) 4463 return error; 4464 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 4465} 4466 4467static int 4468ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 4469{ 4470 struct ath_softc *sc = arg1; 4471 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 4472 int error; 4473 4474 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 4475 if (error || !req->newptr) 4476 return error; 4477 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 4478} 4479 4480static int 4481ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 4482{ 4483 struct ath_softc *sc = arg1; 4484 int softled = sc->sc_softled; 4485 int error; 4486 4487 error = sysctl_handle_int(oidp, &softled, 0, req); 4488 if (error || !req->newptr) 4489 return error; 4490 softled = (softled != 0); 4491 if (softled != sc->sc_softled) { 4492 if (softled) { 4493 /* NB: handle any sc_ledpin change */ 4494 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 4495 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 4496 !sc->sc_ledon); 4497 } 4498 sc->sc_softled = softled; 4499 } 4500 return 0; 4501} 4502 4503static int 4504ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 4505{ 4506 struct ath_softc *sc = arg1; 4507 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 4508 int error; 4509 4510 error = sysctl_handle_int(oidp, &defantenna, 0, req); 4511 if (!error && req->newptr) 4512 ath_hal_setdefantenna(sc->sc_ah, defantenna); 4513 return error; 4514} 4515 4516static int 4517ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 4518{ 4519 struct ath_softc *sc = arg1; 4520 u_int diversity = sc->sc_diversity; 4521 int error; 4522 4523 error = sysctl_handle_int(oidp, &diversity, 0, req); 4524 if (error || !req->newptr) 4525 return error; 4526 sc->sc_diversity = diversity; 4527 return !ath_hal_setdiversity(sc->sc_ah, diversity) ? EINVAL : 0; 4528} 4529 4530static int 4531ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 4532{ 4533 struct ath_softc *sc = arg1; 4534 u_int32_t diag; 4535 int error; 4536 4537 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 4538 return EINVAL; 4539 error = sysctl_handle_int(oidp, &diag, 0, req); 4540 if (error || !req->newptr) 4541 return error; 4542 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 4543} 4544 4545static int 4546ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 4547{ 4548 struct ath_softc *sc = arg1; 4549 struct ifnet *ifp = &sc->sc_if; 4550 u_int32_t scale; 4551 int error; 4552 4553 ath_hal_gettpscale(sc->sc_ah, &scale); 4554 error = sysctl_handle_int(oidp, &scale, 0, req); 4555 if (error || !req->newptr) 4556 return error; 4557 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp); 4558} 4559 4560static int 4561ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 4562{ 4563 struct ath_softc *sc = arg1; 4564 u_int tpc = ath_hal_gettpc(sc->sc_ah); 4565 int error; 4566 4567 error = sysctl_handle_int(oidp, &tpc, 0, req); 4568 if (error || !req->newptr) 4569 return error; 4570 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 4571} 4572 4573static void 4574ath_sysctlattach(struct ath_softc *sc) 4575{ 4576 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 4577 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 4578 4579 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode); 4580 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4581 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0, 4582 "EEPROM country code"); 4583 ath_hal_getregdomain(sc->sc_ah, &sc->sc_regdomain); 4584 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4585 "regdomain", CTLFLAG_RD, &sc->sc_regdomain, 0, 4586 "EEPROM regdomain code"); 4587 sc->sc_debug = ath_debug; 4588 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4589 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 4590 "control debugging printfs"); 4591 4592 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4593 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4594 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 4595 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4596 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4597 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 4598 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4599 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4600 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 4601 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4602 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4603 ath_sysctl_softled, "I", "enable/disable software LED support"); 4604 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4605 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0, 4606 "GPIO pin connected to LED"); 4607 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4608 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 4609 "setting to turn LED on"); 4610 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4611 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 4612 "idle time for inactivity LED (ticks)"); 4613 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4614 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0, 4615 "tx antenna (0=auto)"); 4616 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4617 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4618 ath_sysctl_rxantenna, "I", "default/rx antenna"); 4619 if (sc->sc_hasdiversity) 4620 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4621 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4622 ath_sysctl_diversity, "I", "antenna diversity"); 4623 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 4624 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4625 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 4626 "tx descriptor batching"); 4627 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4628 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4629 ath_sysctl_diag, "I", "h/w diagnostic control"); 4630 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4631 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4632 ath_sysctl_tpscale, "I", "tx power scaling"); 4633 if (sc->sc_hastpc) 4634 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4635 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4636 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 4637} 4638 4639static void 4640ath_bpfattach(struct ath_softc *sc) 4641{ 4642 struct ifnet *ifp = &sc->sc_if; 4643 4644 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4645 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4646 &sc->sc_drvbpf); 4647 /* 4648 * Initialize constant fields. 4649 * XXX make header lengths a multiple of 32-bits so subsequent 4650 * headers are properly aligned; this is a kludge to keep 4651 * certain applications happy. 4652 * 4653 * NB: the channel is setup each time we transition to the 4654 * RUN state to avoid filling it in for each frame. 4655 */ 4656 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4657 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4658 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4659 4660 sc->sc_rx_rt_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4661 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_rt_len); 4662 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4663} 4664 4665/* 4666 * Announce various information on device/driver attach. 4667 */ 4668static void 4669ath_announce(struct ath_softc *sc) 4670{ 4671#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4672 struct ifnet *ifp = &sc->sc_if; 4673 struct ath_hal *ah = sc->sc_ah; 4674 u_int modes, cc; 4675 4676 if_printf(ifp, "mac %d.%d phy %d.%d", 4677 ah->ah_macVersion, ah->ah_macRev, 4678 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4679 /* 4680 * Print radio revision(s). We check the wireless modes 4681 * to avoid falsely printing revs for inoperable parts. 4682 * Dual-band radio revs are returned in the 5Ghz rev number. 4683 */ 4684 ath_hal_getcountrycode(ah, &cc); 4685 modes = ath_hal_getwirelessmodes(ah, cc); 4686 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4687 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4688 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4689 ah->ah_analog5GhzRev >> 4, 4690 ah->ah_analog5GhzRev & 0xf, 4691 ah->ah_analog2GhzRev >> 4, 4692 ah->ah_analog2GhzRev & 0xf); 4693 else 4694 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4695 ah->ah_analog5GhzRev & 0xf); 4696 } else 4697 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4698 ah->ah_analog5GhzRev & 0xf); 4699 printf("\n"); 4700 if (bootverbose) { 4701 int i; 4702 for (i = 0; i <= WME_AC_VO; i++) { 4703 struct ath_txq *txq = sc->sc_ac2q[i]; 4704 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4705 txq->axq_qnum, ieee80211_wme_acnames[i]); 4706 } 4707 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4708 sc->sc_cabq->axq_qnum); 4709 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4710 } 4711#undef HAL_MODE_DUALBAND 4712} 4713