ar5416_misc.c revision 224244
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c 224244 2011-07-21 14:16:42Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24#ifdef AH_DEBUG 25#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 26#endif 27 28#include "ar5416/ar5416.h" 29#include "ar5416/ar5416reg.h" 30#include "ar5416/ar5416phy.h" 31 32/* 33 * Return the wireless modes (a,b,g,n,t) supported by hardware. 34 * 35 * This value is what is actually supported by the hardware 36 * and is unaffected by regulatory/country code settings. 37 * 38 */ 39u_int 40ar5416GetWirelessModes(struct ath_hal *ah) 41{ 42 u_int mode; 43 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 44 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 45 46 mode = ar5212GetWirelessModes(ah); 47 48 /* Only enable HT modes if the NIC supports HT */ 49 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 50 mode |= HAL_MODE_11NA_HT20 51 | HAL_MODE_11NA_HT40PLUS 52 | HAL_MODE_11NA_HT40MINUS 53 ; 54 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 55 mode |= HAL_MODE_11NG_HT20 56 | HAL_MODE_11NG_HT40PLUS 57 | HAL_MODE_11NG_HT40MINUS 58 ; 59 return mode; 60} 61 62/* 63 * Change the LED blinking pattern to correspond to the connectivity 64 */ 65void 66ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 67{ 68 static const uint32_t ledbits[8] = { 69 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 70 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 71 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 72 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 73 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 74 AR_MAC_LED_ASSOC_NONE, 75 AR_MAC_LED_ASSOC_NONE, 76 AR_MAC_LED_ASSOC_NONE, 77 }; 78 uint32_t bits; 79 80 if (AR_SREV_HOWL(ah)) 81 return; 82 83 bits = OS_REG_READ(ah, AR_MAC_LED); 84 bits = (bits &~ AR_MAC_LED_MODE) 85 | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE) 86#if 1 87 | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE) 88#endif 89 ; 90 bits = (bits &~ AR_MAC_LED_ASSOC) 91 | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC); 92 OS_REG_WRITE(ah, AR_MAC_LED, bits); 93} 94 95/* 96 * Reset the current hardware tsf for stamlme. 97 */ 98void 99ar5416ResetTsf(struct ath_hal *ah) 100{ 101 uint32_t v; 102 int i; 103 104 for (i = 0; i < 10; i++) { 105 v = OS_REG_READ(ah, AR_SLP32_MODE); 106 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 107 break; 108 OS_DELAY(10); 109 } 110 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 111} 112 113HAL_BOOL 114ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 115{ 116 return AH_TRUE; 117} 118 119/* Setup decompression for given key index */ 120HAL_BOOL 121ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 122{ 123 return HAL_OK; 124} 125 126/* Setup coverage class */ 127void 128ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 129{ 130 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 131} 132 133/* 134 * Return approximation of extension channel busy over an time interval 135 * 0% (clear) -> 100% (busy) 136 * 137 */ 138uint32_t 139ar5416Get11nExtBusy(struct ath_hal *ah) 140{ 141 struct ath_hal_5416 *ahp = AH5416(ah); 142 uint32_t busy; /* percentage */ 143 uint32_t cycleCount, ctlBusy, extBusy; 144 145 ctlBusy = OS_REG_READ(ah, AR_RCCNT); 146 extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 147 cycleCount = OS_REG_READ(ah, AR_CCCNT); 148 149 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 150 /* 151 * Cycle counter wrap (or initial call); it's not possible 152 * to accurately calculate a value because the registers 153 * right shift rather than wrap--so punt and return 0. 154 */ 155 busy = 0; 156 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 157 __func__); 158 159 } else { 160 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 161 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 162 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 163 uint32_t ctlClearDelta = 0; 164 165 /* Compute control channel rxclear. 166 * The cycle delta may be less than the control channel delta. 167 * This could be solved by freezing the timers (or an atomic read, 168 * if one was available). Checking for the condition should be 169 * sufficient. 170 */ 171 if (cycleDelta > ctlBusyDelta) { 172 ctlClearDelta = cycleDelta - ctlBusyDelta; 173 } 174 175 /* Compute ratio of extension channel busy to control channel clear 176 * as an approximation to extension channel cleanliness. 177 * 178 * According to the hardware folks, ext rxclear is undefined 179 * if the ctrl rxclear is de-asserted (i.e. busy) 180 */ 181 if (ctlClearDelta) { 182 busy = (extBusyDelta * 100) / ctlClearDelta; 183 } else { 184 busy = 100; 185 } 186 if (busy > 100) { 187 busy = 100; 188 } 189#if 0 190 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 191 "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 192 "busy %d\n", 193 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 194#endif 195 } 196 197 ahp->ah_cycleCount = cycleCount; 198 ahp->ah_ctlBusy = ctlBusy; 199 ahp->ah_extBusy = extBusy; 200 201 return busy; 202} 203 204/* 205 * Configure 20/40 operation 206 * 207 * 20/40 = joint rx clear (control and extension) 208 * 20 = rx clear (control) 209 * 210 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 211 * from 20/40 => 20 only 212 */ 213void 214ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 215{ 216 uint32_t macmode; 217 218 /* Configure MAC for 20/40 operation */ 219 if (mode == HAL_HT_MACMODE_2040) { 220 macmode = AR_2040_JOINED_RX_CLEAR; 221 } else { 222 macmode = 0; 223 } 224 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 225} 226 227/* 228 * Get Rx clear (control/extension channel) 229 * 230 * Returns active low (busy) for ctrl/ext channel 231 * Owl 2.0 232 */ 233HAL_HT_RXCLEAR 234ar5416Get11nRxClear(struct ath_hal *ah) 235{ 236 HAL_HT_RXCLEAR rxclear = 0; 237 uint32_t val; 238 239 val = OS_REG_READ(ah, AR_DIAG_SW); 240 241 /* control channel */ 242 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 243 rxclear |= HAL_RX_CLEAR_CTL_LOW; 244 } 245 /* extension channel */ 246 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 247 rxclear |= HAL_RX_CLEAR_EXT_LOW; 248 } 249 return rxclear; 250} 251 252/* 253 * Set Rx clear (control/extension channel) 254 * 255 * Useful for forcing the channel to appear busy for 256 * debugging/diagnostics 257 * Owl 2.0 258 */ 259void 260ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 261{ 262 /* control channel */ 263 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 264 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 265 } else { 266 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 267 } 268 /* extension channel */ 269 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 270 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 271 } else { 272 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 273 } 274} 275 276/* XXX shouldn't be here! */ 277#define TU_TO_USEC(_tu) ((_tu) << 10) 278 279HAL_STATUS 280ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 281 uint32_t nextStart, HAL_QUIET_FLAG flag) 282{ 283 uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */ 284 uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */ 285 if (flag & HAL_QUIET_ENABLE) { 286 if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 287 /* Add the nextStart offset to the current TSF */ 288 nextStart_us += OS_REG_READ(ah, AR_TSF_L32); 289 } 290 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 291 nextStart_us += ah->ah_config.ah_sw_beacon_response_time; 292 } 293 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 294 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 295 OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us); 296 OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us); 297 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 298 } else { 299 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 300 } 301 return HAL_OK; 302} 303#undef TU_TO_USEC 304 305HAL_STATUS 306ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 307 uint32_t capability, uint32_t *result) 308{ 309 switch (type) { 310 case HAL_CAP_BB_HANG: 311 switch (capability) { 312 case HAL_BB_HANG_RIFS: 313 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 314 case HAL_BB_HANG_DFS: 315 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 316 case HAL_BB_HANG_RX_CLEAR: 317 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 318 } 319 break; 320 case HAL_CAP_MAC_HANG: 321 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 322 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 323 AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 324 HAL_OK : HAL_ENOTSUPP; 325 case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 326 return HAL_ENXIO; 327 default: 328 break; 329 } 330 return ar5212GetCapability(ah, type, capability, result); 331} 332 333static int ar5416DetectMacHang(struct ath_hal *ah); 334static int ar5416DetectBBHang(struct ath_hal *ah); 335 336HAL_BOOL 337ar5416GetDiagState(struct ath_hal *ah, int request, 338 const void *args, uint32_t argsize, 339 void **result, uint32_t *resultsize) 340{ 341 struct ath_hal_5416 *ahp = AH5416(ah); 342 int hangs; 343 344 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 345 return AH_TRUE; 346 switch (request) { 347 case HAL_DIAG_EEPROM: 348 return ath_hal_eepromDiag(ah, request, 349 args, argsize, result, resultsize); 350 case HAL_DIAG_CHECK_HANGS: 351 if (argsize != sizeof(int)) 352 return AH_FALSE; 353 hangs = *(const int *) args; 354 ahp->ah_hangs = 0; 355 if (hangs & HAL_BB_HANGS) 356 ahp->ah_hangs |= ar5416DetectBBHang(ah); 357 /* NB: if BB is hung MAC will be hung too so skip check */ 358 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 359 ahp->ah_hangs |= ar5416DetectMacHang(ah); 360 *result = &ahp->ah_hangs; 361 *resultsize = sizeof(ahp->ah_hangs); 362 return AH_TRUE; 363 } 364 return ar5212GetDiagState(ah, request, 365 args, argsize, result, resultsize); 366} 367 368typedef struct { 369 uint32_t dma_dbg_3; 370 uint32_t dma_dbg_4; 371 uint32_t dma_dbg_5; 372 uint32_t dma_dbg_6; 373} mac_dbg_regs_t; 374 375typedef enum { 376 dcu_chain_state = 0x1, 377 dcu_complete_state = 0x2, 378 qcu_state = 0x4, 379 qcu_fsp_ok = 0x8, 380 qcu_fsp_state = 0x10, 381 qcu_stitch_state = 0x20, 382 qcu_fetch_state = 0x40, 383 qcu_complete_state = 0x80 384} hal_mac_hangs_t; 385 386typedef struct { 387 int states; 388 uint8_t dcu_chain_state; 389 uint8_t dcu_complete_state; 390 uint8_t qcu_state; 391 uint8_t qcu_fsp_ok; 392 uint8_t qcu_fsp_state; 393 uint8_t qcu_stitch_state; 394 uint8_t qcu_fetch_state; 395 uint8_t qcu_complete_state; 396} hal_mac_hang_check_t; 397 398HAL_BOOL 399ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, 400 HAL_BOOL enable) 401{ 402 uint32_t val; 403 HAL_BOOL is_chan_2g = AH_FALSE; 404 HAL_BOOL is_ht40 = AH_FALSE; 405 406 if (chan) 407 is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan); 408 409 if (chan) 410 is_ht40 = IEEE80211_IS_CHAN_HT40(chan); 411 412 /* Only support disabling RIFS delay for now */ 413 HALASSERT(enable == AH_FALSE); 414 415 if (enable == AH_TRUE) 416 return AH_FALSE; 417 418 /* Change RIFS init delay to 0 */ 419 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 420 val &= ~AR_PHY_RIFS_INIT_DELAY; 421 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 422 423 /* 424 * For Owl, RIFS RX parameters are controlled differently; 425 * it isn't enabled in the inivals by default. 426 * 427 * For Sowl/Howl, RIFS RX is enabled in the inivals by default; 428 * the following code sets them back to non-RIFS values. 429 * 430 * For > Sowl/Howl, RIFS RX can be left on by default and so 431 * this function shouldn't be called. 432 */ 433 if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah))) 434 return AH_TRUE; 435 436 /* Reset search delay to default values */ 437 if (is_chan_2g) 438 if (is_ht40) 439 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268); 440 else 441 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134); 442 else 443 if (is_ht40) 444 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370); 445 else 446 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8); 447 448 return AH_TRUE; 449} 450 451static HAL_BOOL 452ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 453 const hal_mac_hang_check_t *check) 454{ 455 int found_states; 456 457 found_states = 0; 458 if (check->states & dcu_chain_state) { 459 int i; 460 461 for (i = 0; i < 6; i++) { 462 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 463 check->dcu_chain_state) 464 found_states |= dcu_chain_state; 465 } 466 for (i = 0; i < 4; i++) { 467 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 468 check->dcu_chain_state) 469 found_states |= dcu_chain_state; 470 } 471 } 472 if (check->states & dcu_complete_state) { 473 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 474 found_states |= dcu_complete_state; 475 } 476 if (check->states & qcu_stitch_state) { 477 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 478 found_states |= qcu_stitch_state; 479 } 480 if (check->states & qcu_fetch_state) { 481 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 482 found_states |= qcu_fetch_state; 483 } 484 if (check->states & qcu_complete_state) { 485 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 486 found_states |= qcu_complete_state; 487 } 488 return (found_states == check->states); 489} 490 491#define NUM_STATUS_READS 50 492 493static int 494ar5416DetectMacHang(struct ath_hal *ah) 495{ 496 static const hal_mac_hang_check_t hang_sig1 = { 497 .dcu_chain_state = 0x6, 498 .dcu_complete_state = 0x1, 499 .states = dcu_chain_state 500 | dcu_complete_state, 501 }; 502 static const hal_mac_hang_check_t hang_sig2 = { 503 .qcu_stitch_state = 0x9, 504 .qcu_fetch_state = 0x8, 505 .qcu_complete_state = 0x4, 506 .states = qcu_stitch_state 507 | qcu_fetch_state 508 | qcu_complete_state, 509 }; 510 mac_dbg_regs_t mac_dbg; 511 int i; 512 513 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 514 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 515 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 516 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 517 for (i = 1; i <= NUM_STATUS_READS; i++) { 518 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 519 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 520 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 521 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 522 return 0; 523 } 524 525 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 526 return HAL_MAC_HANG_SIG1; 527 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 528 return HAL_MAC_HANG_SIG2; 529 530 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 531 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 532 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 533 mac_dbg.dma_dbg_6); 534 535 return 0; 536} 537 538/* 539 * Determine if the baseband using the Observation Bus Register 540 */ 541static int 542ar5416DetectBBHang(struct ath_hal *ah) 543{ 544#define N(a) (sizeof(a)/sizeof(a[0])) 545 /* 546 * Check the PCU Observation Bus 1 register (0x806c) 547 * NUM_STATUS_READS times 548 * 549 * 4 known BB hang signatures - 550 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 551 * [2] bits 8,9 are 1, bit 11 is 0. State machine state 552 * (bits 25-31) is 0x52 553 * [3] bits 8,9 are 1, bit 11 is 0. State machine state 554 * (bits 25-31) is 0x18 555 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 556 * Rx State (bits 20-24) is 0x7. 557 */ 558 static const struct { 559 uint32_t val; 560 uint32_t mask; 561 int code; 562 } hang_list[] = { 563 /* Reg Value Reg Mask Hang Code XXX */ 564 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 565 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 566 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 567 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 568 }; 569 uint32_t hang_sig; 570 int i; 571 572 hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 573 for (i = 1; i <= NUM_STATUS_READS; i++) { 574 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 575 return 0; 576 } 577 for (i = 0; i < N(hang_list); i++) 578 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 579 HALDEBUG(ah, HAL_DEBUG_HANG, 580 "%s BB hang, signature 0x%x, code 0x%x\n", 581 __func__, hang_sig, hang_list[i].code); 582 return hang_list[i].code; 583 } 584 585 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 586 "<0x806c>=0x%x\n", __func__, hang_sig); 587 588 return 0; 589#undef N 590} 591#undef NUM_STATUS_READS 592 593/* 594 * Get the radar parameter values and return them in the pe 595 * structure 596 */ 597void 598ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 599{ 600 uint32_t val, temp; 601 602 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 603 604 temp = MS(val,AR_PHY_RADAR_0_FIRPWR); 605 temp |= 0xFFFFFF80; 606 pe->pe_firpwr = temp; 607 pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI); 608 pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT); 609 pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI); 610 pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND); 611 612 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 613 temp = val & AR_PHY_RADAR_1_RELPWR_ENA; 614 pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH); 615 if (temp) 616 pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE; 617 temp = val & AR_PHY_RADAR_1_RELSTEP_CHECK; 618 pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH); 619 if (temp) 620 pe->pe_enabled = 1; 621 else 622 pe->pe_enabled = 0; 623 624 pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN); 625 pe->pe_extchannel = !! (OS_REG_READ(ah, AR_PHY_RADAR_EXT) & 626 AR_PHY_RADAR_EXT_ENA); 627 628 pe->pe_usefir128 = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 629 AR_PHY_RADAR_1_USE_FIR128); 630 pe->pe_blockradar = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 631 AR_PHY_RADAR_1_BLOCK_CHECK); 632 pe->pe_enmaxrssi = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 633 AR_PHY_RADAR_1_MAX_RRSSI); 634} 635 636/* 637 * Enable radar detection and set the radar parameters per the 638 * values in pe 639 */ 640void 641ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 642{ 643 uint32_t val; 644 645 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 646 647 if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) { 648 val &= ~AR_PHY_RADAR_0_FIRPWR; 649 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); 650 } 651 if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) { 652 val &= ~AR_PHY_RADAR_0_RRSSI; 653 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); 654 } 655 if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) { 656 val &= ~AR_PHY_RADAR_0_HEIGHT; 657 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); 658 } 659 if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) { 660 val &= ~AR_PHY_RADAR_0_PRSSI; 661 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); 662 } 663 if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) { 664 val &= ~AR_PHY_RADAR_0_INBAND; 665 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); 666 } 667 668 /*Enable FFT data*/ 669 val |= AR_PHY_RADAR_0_FFT_ENA; 670 671 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA); 672 673 if (pe->pe_usefir128 == 0) 674 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128); 675 else if (pe->pe_usefir128 == 1) 676 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128); 677 678 if (pe->pe_enmaxrssi == 0) 679 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI); 680 else if (pe->pe_enmaxrssi == 1) 681 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI); 682 683 if (pe->pe_blockradar == 0) 684 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK); 685 else if (pe->pe_blockradar == 1) 686 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK); 687 688 if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) { 689 val &= ~AR_PHY_RADAR_1_MAXLEN; 690 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN); 691 } 692 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 693 694 /* 695 * Enable HT/40 if the upper layer asks; 696 * it should check the channel is HT/40 and HAL_CAP_EXT_CHAN_DFS 697 * is available. 698 */ 699 if (pe->pe_extchannel == 1) 700 OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 701 else if (pe->pe_extchannel == 0) 702 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 703 704 if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) { 705 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 706 val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH; 707 val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH); 708 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 709 } 710 if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) { 711 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 712 val &= ~AR_PHY_RADAR_1_RELPWR_THRESH; 713 val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH); 714 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 715 } 716} 717 718/* 719 * Extract the radar event information from the given phy error. 720 * 721 * Returns AH_TRUE if the phy error was actually a phy error, 722 * AH_FALSE if the phy error wasn't a phy error. 723 */ 724HAL_BOOL 725ar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs, 726 uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event) 727{ 728 /* 729 * For now, this isn't implemented. 730 */ 731 return AH_FALSE; 732} 733