ar5416_misc.c revision 221580
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c 221580 2011-05-07 06:45:35Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24#ifdef AH_DEBUG 25#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 26#endif 27 28#include "ar5416/ar5416.h" 29#include "ar5416/ar5416reg.h" 30#include "ar5416/ar5416phy.h" 31 32/* 33 * Return the wireless modes (a,b,g,n,t) supported by hardware. 34 * 35 * This value is what is actually supported by the hardware 36 * and is unaffected by regulatory/country code settings. 37 * 38 */ 39u_int 40ar5416GetWirelessModes(struct ath_hal *ah) 41{ 42 u_int mode; 43 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 44 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 45 46 mode = ar5212GetWirelessModes(ah); 47 48 /* Only enable HT modes if the NIC supports HT */ 49 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 50 mode |= HAL_MODE_11NA_HT20 51 | HAL_MODE_11NA_HT40PLUS 52 | HAL_MODE_11NA_HT40MINUS 53 ; 54 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 55 mode |= HAL_MODE_11NG_HT20 56 | HAL_MODE_11NG_HT40PLUS 57 | HAL_MODE_11NG_HT40MINUS 58 ; 59 return mode; 60} 61 62/* 63 * Change the LED blinking pattern to correspond to the connectivity 64 */ 65void 66ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 67{ 68 static const uint32_t ledbits[8] = { 69 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 70 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 71 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 72 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 73 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 74 AR_MAC_LED_ASSOC_NONE, 75 AR_MAC_LED_ASSOC_NONE, 76 AR_MAC_LED_ASSOC_NONE, 77 }; 78 uint32_t bits; 79 80 if (AR_SREV_HOWL(ah)) 81 return; 82 83 bits = OS_REG_READ(ah, AR_MAC_LED); 84 bits = (bits &~ AR_MAC_LED_MODE) 85 | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE) 86#if 1 87 | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE) 88#endif 89 ; 90 bits = (bits &~ AR_MAC_LED_ASSOC) 91 | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC); 92 OS_REG_WRITE(ah, AR_MAC_LED, bits); 93} 94 95/* 96 * Reset the current hardware tsf for stamlme. 97 */ 98void 99ar5416ResetTsf(struct ath_hal *ah) 100{ 101 uint32_t v; 102 int i; 103 104 for (i = 0; i < 10; i++) { 105 v = OS_REG_READ(ah, AR_SLP32_MODE); 106 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 107 break; 108 OS_DELAY(10); 109 } 110 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 111} 112 113HAL_BOOL 114ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 115{ 116 return AH_TRUE; 117} 118 119/* Setup decompression for given key index */ 120HAL_BOOL 121ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 122{ 123 return HAL_OK; 124} 125 126/* Setup coverage class */ 127void 128ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 129{ 130 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 131} 132 133/* 134 * Return approximation of extension channel busy over an time interval 135 * 0% (clear) -> 100% (busy) 136 * 137 */ 138uint32_t 139ar5416Get11nExtBusy(struct ath_hal *ah) 140{ 141 struct ath_hal_5416 *ahp = AH5416(ah); 142 uint32_t busy; /* percentage */ 143 uint32_t cycleCount, ctlBusy, extBusy; 144 145 ctlBusy = OS_REG_READ(ah, AR_RCCNT); 146 extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 147 cycleCount = OS_REG_READ(ah, AR_CCCNT); 148 149 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 150 /* 151 * Cycle counter wrap (or initial call); it's not possible 152 * to accurately calculate a value because the registers 153 * right shift rather than wrap--so punt and return 0. 154 */ 155 busy = 0; 156 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 157 __func__); 158 159 } else { 160 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 161 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 162 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 163 uint32_t ctlClearDelta = 0; 164 165 /* Compute control channel rxclear. 166 * The cycle delta may be less than the control channel delta. 167 * This could be solved by freezing the timers (or an atomic read, 168 * if one was available). Checking for the condition should be 169 * sufficient. 170 */ 171 if (cycleDelta > ctlBusyDelta) { 172 ctlClearDelta = cycleDelta - ctlBusyDelta; 173 } 174 175 /* Compute ratio of extension channel busy to control channel clear 176 * as an approximation to extension channel cleanliness. 177 * 178 * According to the hardware folks, ext rxclear is undefined 179 * if the ctrl rxclear is de-asserted (i.e. busy) 180 */ 181 if (ctlClearDelta) { 182 busy = (extBusyDelta * 100) / ctlClearDelta; 183 } else { 184 busy = 100; 185 } 186 if (busy > 100) { 187 busy = 100; 188 } 189#if 0 190 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 191 "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 192 "busy %d\n", 193 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 194#endif 195 } 196 197 ahp->ah_cycleCount = cycleCount; 198 ahp->ah_ctlBusy = ctlBusy; 199 ahp->ah_extBusy = extBusy; 200 201 return busy; 202} 203 204/* 205 * Configure 20/40 operation 206 * 207 * 20/40 = joint rx clear (control and extension) 208 * 20 = rx clear (control) 209 * 210 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 211 * from 20/40 => 20 only 212 */ 213void 214ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 215{ 216 uint32_t macmode; 217 218 /* Configure MAC for 20/40 operation */ 219 if (mode == HAL_HT_MACMODE_2040) { 220 macmode = AR_2040_JOINED_RX_CLEAR; 221 } else { 222 macmode = 0; 223 } 224 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 225} 226 227/* 228 * Get Rx clear (control/extension channel) 229 * 230 * Returns active low (busy) for ctrl/ext channel 231 * Owl 2.0 232 */ 233HAL_HT_RXCLEAR 234ar5416Get11nRxClear(struct ath_hal *ah) 235{ 236 HAL_HT_RXCLEAR rxclear = 0; 237 uint32_t val; 238 239 val = OS_REG_READ(ah, AR_DIAG_SW); 240 241 /* control channel */ 242 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 243 rxclear |= HAL_RX_CLEAR_CTL_LOW; 244 } 245 /* extension channel */ 246 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 247 rxclear |= HAL_RX_CLEAR_EXT_LOW; 248 } 249 return rxclear; 250} 251 252/* 253 * Set Rx clear (control/extension channel) 254 * 255 * Useful for forcing the channel to appear busy for 256 * debugging/diagnostics 257 * Owl 2.0 258 */ 259void 260ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 261{ 262 /* control channel */ 263 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 264 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 265 } else { 266 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 267 } 268 /* extension channel */ 269 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 270 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 271 } else { 272 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 273 } 274} 275 276HAL_STATUS 277ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 278 uint32_t capability, uint32_t *result) 279{ 280 switch (type) { 281 case HAL_CAP_GTXTO: 282 return HAL_OK; /* All AR5416+ supports Global TX Timeout */ 283 case HAL_CAP_BB_HANG: 284 switch (capability) { 285 case HAL_BB_HANG_RIFS: 286 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 287 case HAL_BB_HANG_DFS: 288 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 289 case HAL_BB_HANG_RX_CLEAR: 290 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 291 } 292 break; 293 case HAL_CAP_MAC_HANG: 294 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 295 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 296 AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 297 HAL_OK : HAL_ENOTSUPP; 298 case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 299 return HAL_ENXIO; 300 default: 301 break; 302 } 303 return ar5212GetCapability(ah, type, capability, result); 304} 305 306static int ar5416DetectMacHang(struct ath_hal *ah); 307static int ar5416DetectBBHang(struct ath_hal *ah); 308 309HAL_BOOL 310ar5416GetDiagState(struct ath_hal *ah, int request, 311 const void *args, uint32_t argsize, 312 void **result, uint32_t *resultsize) 313{ 314 struct ath_hal_5416 *ahp = AH5416(ah); 315 int hangs; 316 317 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 318 return AH_TRUE; 319 switch (request) { 320 case HAL_DIAG_EEPROM: 321 return ath_hal_eepromDiag(ah, request, 322 args, argsize, result, resultsize); 323 case HAL_DIAG_CHECK_HANGS: 324 if (argsize != sizeof(int)) 325 return AH_FALSE; 326 hangs = *(const int *) args; 327 ahp->ah_hangs = 0; 328 if (hangs & HAL_BB_HANGS) 329 ahp->ah_hangs |= ar5416DetectBBHang(ah); 330 /* NB: if BB is hung MAC will be hung too so skip check */ 331 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 332 ahp->ah_hangs |= ar5416DetectMacHang(ah); 333 *result = &ahp->ah_hangs; 334 *resultsize = sizeof(ahp->ah_hangs); 335 return AH_TRUE; 336 } 337 return ar5212GetDiagState(ah, request, 338 args, argsize, result, resultsize); 339} 340 341typedef struct { 342 uint32_t dma_dbg_3; 343 uint32_t dma_dbg_4; 344 uint32_t dma_dbg_5; 345 uint32_t dma_dbg_6; 346} mac_dbg_regs_t; 347 348typedef enum { 349 dcu_chain_state = 0x1, 350 dcu_complete_state = 0x2, 351 qcu_state = 0x4, 352 qcu_fsp_ok = 0x8, 353 qcu_fsp_state = 0x10, 354 qcu_stitch_state = 0x20, 355 qcu_fetch_state = 0x40, 356 qcu_complete_state = 0x80 357} hal_mac_hangs_t; 358 359typedef struct { 360 int states; 361 uint8_t dcu_chain_state; 362 uint8_t dcu_complete_state; 363 uint8_t qcu_state; 364 uint8_t qcu_fsp_ok; 365 uint8_t qcu_fsp_state; 366 uint8_t qcu_stitch_state; 367 uint8_t qcu_fetch_state; 368 uint8_t qcu_complete_state; 369} hal_mac_hang_check_t; 370 371HAL_BOOL 372ar5416SetRifsDelay(struct ath_hal *ah, HAL_BOOL enable) 373{ 374 uint32_t val; 375 376 /* Only support disabling RIFS delay for now */ 377 HALASSERT(enable == AH_FALSE); 378 379 if (enable == AH_TRUE) 380 return AH_FALSE; 381 382 /* Change RIFS init delay to 0 */ 383 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 384 val &= ~AR_PHY_RIFS_INIT_DELAY; 385 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 386 387 return AH_TRUE; 388} 389 390static HAL_BOOL 391ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 392 const hal_mac_hang_check_t *check) 393{ 394 int found_states; 395 396 found_states = 0; 397 if (check->states & dcu_chain_state) { 398 int i; 399 400 for (i = 0; i < 6; i++) { 401 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 402 check->dcu_chain_state) 403 found_states |= dcu_chain_state; 404 } 405 for (i = 0; i < 4; i++) { 406 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 407 check->dcu_chain_state) 408 found_states |= dcu_chain_state; 409 } 410 } 411 if (check->states & dcu_complete_state) { 412 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 413 found_states |= dcu_complete_state; 414 } 415 if (check->states & qcu_stitch_state) { 416 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 417 found_states |= qcu_stitch_state; 418 } 419 if (check->states & qcu_fetch_state) { 420 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 421 found_states |= qcu_fetch_state; 422 } 423 if (check->states & qcu_complete_state) { 424 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 425 found_states |= qcu_complete_state; 426 } 427 return (found_states == check->states); 428} 429 430#define NUM_STATUS_READS 50 431 432static int 433ar5416DetectMacHang(struct ath_hal *ah) 434{ 435 static const hal_mac_hang_check_t hang_sig1 = { 436 .dcu_chain_state = 0x6, 437 .dcu_complete_state = 0x1, 438 .states = dcu_chain_state 439 | dcu_complete_state, 440 }; 441 static const hal_mac_hang_check_t hang_sig2 = { 442 .qcu_stitch_state = 0x9, 443 .qcu_fetch_state = 0x8, 444 .qcu_complete_state = 0x4, 445 .states = qcu_stitch_state 446 | qcu_fetch_state 447 | qcu_complete_state, 448 }; 449 mac_dbg_regs_t mac_dbg; 450 int i; 451 452 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 453 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 454 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 455 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 456 for (i = 1; i <= NUM_STATUS_READS; i++) { 457 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 458 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 459 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 460 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 461 return 0; 462 } 463 464 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 465 return HAL_MAC_HANG_SIG1; 466 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 467 return HAL_MAC_HANG_SIG2; 468 469 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 470 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 471 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 472 mac_dbg.dma_dbg_6); 473 474 return HAL_MAC_HANG_UNKNOWN; 475} 476 477/* 478 * Determine if the baseband using the Observation Bus Register 479 */ 480static int 481ar5416DetectBBHang(struct ath_hal *ah) 482{ 483#define N(a) (sizeof(a)/sizeof(a[0])) 484 /* 485 * Check the PCU Observation Bus 1 register (0x806c) 486 * NUM_STATUS_READS times 487 * 488 * 4 known BB hang signatures - 489 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 490 * [2] bits 8,9 are 1, bit 11 is 0. State machine state 491 * (bits 25-31) is 0x52 492 * [3] bits 8,9 are 1, bit 11 is 0. State machine state 493 * (bits 25-31) is 0x18 494 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 495 * Rx State (bits 20-24) is 0x7. 496 */ 497 static const struct { 498 uint32_t val; 499 uint32_t mask; 500 int code; 501 } hang_list[] = { 502 /* Reg Value Reg Mask Hang Code XXX */ 503 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 504 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 505 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 506 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 507 }; 508 uint32_t hang_sig; 509 int i; 510 511 hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 512 for (i = 1; i <= NUM_STATUS_READS; i++) { 513 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 514 return 0; 515 } 516 for (i = 0; i < N(hang_list); i++) 517 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 518 HALDEBUG(ah, HAL_DEBUG_HANG, 519 "%s BB hang, signature 0x%x, code 0x%x\n", 520 __func__, hang_sig, hang_list[i].code); 521 return hang_list[i].code; 522 } 523 524 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 525 "<0x806c>=0x%x\n", __func__, hang_sig); 526 527 return HAL_BB_HANG_UNKNOWN; 528#undef N 529} 530#undef NUM_STATUS_READS 531