ar5212_misc.c revision 222815
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c 222815 2011-06-07 09:03:28Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24#ifdef AH_DEBUG 25#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 26#endif 27 28#include "ar5212/ar5212.h" 29#include "ar5212/ar5212reg.h" 30#include "ar5212/ar5212phy.h" 31 32#include "ah_eeprom_v3.h" 33 34#define AR_NUM_GPIO 6 /* 6 GPIO pins */ 35#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 36 37void 38ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac) 39{ 40 struct ath_hal_5212 *ahp = AH5212(ah); 41 42 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 43} 44 45HAL_BOOL 46ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac) 47{ 48 struct ath_hal_5212 *ahp = AH5212(ah); 49 50 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 51 return AH_TRUE; 52} 53 54void 55ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask) 56{ 57 struct ath_hal_5212 *ahp = AH5212(ah); 58 59 OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN); 60} 61 62HAL_BOOL 63ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask) 64{ 65 struct ath_hal_5212 *ahp = AH5212(ah); 66 67 /* save it since it must be rewritten on reset */ 68 OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN); 69 70 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 71 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 72 return AH_TRUE; 73} 74 75/* 76 * Attempt to change the cards operating regulatory domain to the given value 77 */ 78HAL_BOOL 79ar5212SetRegulatoryDomain(struct ath_hal *ah, 80 uint16_t regDomain, HAL_STATUS *status) 81{ 82 HAL_STATUS ecode; 83 84 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) { 85 ecode = HAL_EINVAL; 86 goto bad; 87 } 88 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) { 89 ecode = HAL_EEWRITE; 90 goto bad; 91 } 92#ifdef AH_SUPPORT_WRITE_REGDOMAIN 93 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) { 94 HALDEBUG(ah, HAL_DEBUG_ANY, 95 "%s: set regulatory domain to %u (0x%x)\n", 96 __func__, regDomain, regDomain); 97 AH_PRIVATE(ah)->ah_currentRD = regDomain; 98 return AH_TRUE; 99 } 100#endif 101 ecode = HAL_EIO; 102bad: 103 if (status) 104 *status = ecode; 105 return AH_FALSE; 106} 107 108/* 109 * Return the wireless modes (a,b,g,t) supported by hardware. 110 * 111 * This value is what is actually supported by the hardware 112 * and is unaffected by regulatory/country code settings. 113 */ 114u_int 115ar5212GetWirelessModes(struct ath_hal *ah) 116{ 117 u_int mode = 0; 118 119 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 120 mode = HAL_MODE_11A; 121 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 122 mode |= HAL_MODE_TURBO | HAL_MODE_108A; 123 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate) 124 mode |= HAL_MODE_11A_HALF_RATE; 125 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate) 126 mode |= HAL_MODE_11A_QUARTER_RATE; 127 } 128 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 129 mode |= HAL_MODE_11B; 130 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 131 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 132 mode |= HAL_MODE_11G; 133 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 134 mode |= HAL_MODE_108G; 135 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate) 136 mode |= HAL_MODE_11G_HALF_RATE; 137 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate) 138 mode |= HAL_MODE_11G_QUARTER_RATE; 139 } 140 return mode; 141} 142 143/* 144 * Set the interrupt and GPIO values so the ISR can disable RF 145 * on a switch signal. Assumes GPIO port and interrupt polarity 146 * are set prior to call. 147 */ 148void 149ar5212EnableRfKill(struct ath_hal *ah) 150{ 151 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent; 152 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL); 153 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY); 154 155 /* 156 * Configure the desired GPIO port for input 157 * and enable baseband rf silence. 158 */ 159 ath_hal_gpioCfgInput(ah, select); 160 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000); 161 /* 162 * If radio disable switch connection to GPIO bit x is enabled 163 * program GPIO interrupt. 164 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 165 * verified that it is a later version of eeprom, it has a place for 166 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 167 * connection is present. 168 */ 169 ath_hal_gpioSetIntr(ah, select, 170 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity)); 171} 172 173/* 174 * Change the LED blinking pattern to correspond to the connectivity 175 */ 176void 177ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 178{ 179 static const uint32_t ledbits[8] = { 180 AR_PCICFG_LEDCTL_NONE, /* HAL_LED_INIT */ 181 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_SCAN */ 182 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_AUTH */ 183 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_ASSOC*/ 184 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_RUN */ 185 AR_PCICFG_LEDCTL_NONE, 186 AR_PCICFG_LEDCTL_NONE, 187 AR_PCICFG_LEDCTL_NONE, 188 }; 189 uint32_t bits; 190 191 bits = OS_REG_READ(ah, AR_PCICFG); 192 if (IS_2417(ah)) { 193 /* 194 * Enable LED for Nala. There is a bit marked reserved 195 * that must be set and we also turn on the power led. 196 * Because we mark s/w LED control setting the control 197 * status bits below is meangless (the driver must flash 198 * the LED(s) using the GPIO lines). 199 */ 200 bits = (bits &~ AR_PCICFG_LEDMODE) 201 | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE) 202#if 0 203 | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE) 204#endif 205 | 0x08000000; 206 } 207 bits = (bits &~ AR_PCICFG_LEDCTL) 208 | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL); 209 OS_REG_WRITE(ah, AR_PCICFG, bits); 210} 211 212/* 213 * Change association related fields programmed into the hardware. 214 * Writing a valid BSSID to the hardware effectively enables the hardware 215 * to synchronize its TSF to the correct beacons and receive frames coming 216 * from that BSSID. It is called by the SME JOIN operation. 217 */ 218void 219ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId) 220{ 221 struct ath_hal_5212 *ahp = AH5212(ah); 222 223 /* XXX save bssid for possible re-use on reset */ 224 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 225 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 226 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | 227 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S)); 228} 229 230/* 231 * Get the current hardware tsf for stamlme 232 */ 233uint64_t 234ar5212GetTsf64(struct ath_hal *ah) 235{ 236 uint32_t low1, low2, u32; 237 238 /* sync multi-word read */ 239 low1 = OS_REG_READ(ah, AR_TSF_L32); 240 u32 = OS_REG_READ(ah, AR_TSF_U32); 241 low2 = OS_REG_READ(ah, AR_TSF_L32); 242 if (low2 < low1) { /* roll over */ 243 /* 244 * If we are not preempted this will work. If we are 245 * then we re-reading AR_TSF_U32 does no good as the 246 * low bits will be meaningless. Likewise reading 247 * L32, U32, U32, then comparing the last two reads 248 * to check for rollover doesn't help if preempted--so 249 * we take this approach as it costs one less PCI read 250 * which can be noticeable when doing things like 251 * timestamping packets in monitor mode. 252 */ 253 u32++; 254 } 255 return (((uint64_t) u32) << 32) | ((uint64_t) low2); 256} 257 258/* 259 * Get the current hardware tsf for stamlme 260 */ 261uint32_t 262ar5212GetTsf32(struct ath_hal *ah) 263{ 264 return OS_REG_READ(ah, AR_TSF_L32); 265} 266 267void 268ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64) 269{ 270 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 271 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 272} 273 274/* 275 * Reset the current hardware tsf for stamlme. 276 */ 277void 278ar5212ResetTsf(struct ath_hal *ah) 279{ 280 281 uint32_t val = OS_REG_READ(ah, AR_BEACON); 282 283 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); 284 /* 285 * When resetting the TSF, write twice to the 286 * corresponding register; each write to the RESET_TSF bit toggles 287 * the internal signal to cause a reset of the TSF - but if the signal 288 * is left high, it will reset the TSF on the next chip reset also! 289 * writing the bit an even number of times fixes this issue 290 */ 291 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); 292} 293 294/* 295 * Set or clear hardware basic rate bit 296 * Set hardware basic rate set if basic rate is found 297 * and basic rate is equal or less than 2Mbps 298 */ 299void 300ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs) 301{ 302 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 303 uint32_t reg; 304 uint8_t xset; 305 int i; 306 307 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) 308 return; 309 xset = 0; 310 for (i = 0; i < rs->rs_count; i++) { 311 uint8_t rset = rs->rs_rates[i]; 312 /* Basic rate defined? */ 313 if ((rset & 0x80) && (rset &= 0x7f) >= xset) 314 xset = rset; 315 } 316 /* 317 * Set the h/w bit to reflect whether or not the basic 318 * rate is found to be equal or less than 2Mbps. 319 */ 320 reg = OS_REG_READ(ah, AR_STA_ID1); 321 if (xset && xset/2 <= 2) 322 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 323 else 324 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 325} 326 327/* 328 * Grab a semi-random value from hardware registers - may not 329 * change often 330 */ 331uint32_t 332ar5212GetRandomSeed(struct ath_hal *ah) 333{ 334 uint32_t nf; 335 336 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 337 if (nf & 0x100) 338 nf = 0 - ((nf ^ 0x1ff) + 1); 339 return (OS_REG_READ(ah, AR_TSF_U32) ^ 340 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 341} 342 343/* 344 * Detect if our card is present 345 */ 346HAL_BOOL 347ar5212DetectCardPresent(struct ath_hal *ah) 348{ 349 uint16_t macVersion, macRev; 350 uint32_t v; 351 352 /* 353 * Read the Silicon Revision register and compare that 354 * to what we read at attach time. If the same, we say 355 * a card/device is present. 356 */ 357 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 358 macVersion = v >> AR_SREV_ID_S; 359 macRev = v & AR_SREV_REVISION; 360 return (AH_PRIVATE(ah)->ah_macVersion == macVersion && 361 AH_PRIVATE(ah)->ah_macRev == macRev); 362} 363 364void 365ar5212EnableMibCounters(struct ath_hal *ah) 366{ 367 /* NB: this just resets the mib counter machinery */ 368 OS_REG_WRITE(ah, AR_MIBC, 369 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f); 370} 371 372void 373ar5212DisableMibCounters(struct ath_hal *ah) 374{ 375 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC); 376} 377 378/* 379 * Update MIB Counters 380 */ 381void 382ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats) 383{ 384 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 385 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 386 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 387 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 388 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 389} 390 391/* 392 * Detect if the HW supports spreading a CCK signal on channel 14 393 */ 394HAL_BOOL 395ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah) 396{ 397 return AH_TRUE; 398} 399 400/* 401 * Get the rssi of frame curently being received. 402 */ 403uint32_t 404ar5212GetCurRssi(struct ath_hal *ah) 405{ 406 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); 407} 408 409u_int 410ar5212GetDefAntenna(struct ath_hal *ah) 411{ 412 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 413} 414 415void 416ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna) 417{ 418 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 419} 420 421HAL_ANT_SETTING 422ar5212GetAntennaSwitch(struct ath_hal *ah) 423{ 424 return AH5212(ah)->ah_antControl; 425} 426 427HAL_BOOL 428ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting) 429{ 430 struct ath_hal_5212 *ahp = AH5212(ah); 431 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 432 433 if (!ahp->ah_phyPowerOn || chan == AH_NULL) { 434 /* PHY powered off, just stash settings */ 435 ahp->ah_antControl = setting; 436 ahp->ah_diversity = (setting == HAL_ANT_VARIABLE); 437 return AH_TRUE; 438 } 439 return ar5212SetAntennaSwitchInternal(ah, setting, chan); 440} 441 442HAL_BOOL 443ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah) 444{ 445 return AH_TRUE; 446} 447 448HAL_BOOL 449ar5212SetSifsTime(struct ath_hal *ah, u_int us) 450{ 451 struct ath_hal_5212 *ahp = AH5212(ah); 452 453 if (us > ath_hal_mac_usec(ah, 0xffff)) { 454 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n", 455 __func__, us); 456 ahp->ah_sifstime = (u_int) -1; /* restore default handling */ 457 return AH_FALSE; 458 } else { 459 /* convert to system clocks */ 460 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2)); 461 ahp->ah_sifstime = us; 462 return AH_TRUE; 463 } 464} 465 466u_int 467ar5212GetSifsTime(struct ath_hal *ah) 468{ 469 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; 470 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */ 471} 472 473HAL_BOOL 474ar5212SetSlotTime(struct ath_hal *ah, u_int us) 475{ 476 struct ath_hal_5212 *ahp = AH5212(ah); 477 478 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) { 479 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n", 480 __func__, us); 481 ahp->ah_slottime = (u_int) -1; /* restore default handling */ 482 return AH_FALSE; 483 } else { 484 /* convert to system clocks */ 485 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us)); 486 ahp->ah_slottime = us; 487 return AH_TRUE; 488 } 489} 490 491u_int 492ar5212GetSlotTime(struct ath_hal *ah) 493{ 494 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; 495 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 496} 497 498HAL_BOOL 499ar5212SetAckTimeout(struct ath_hal *ah, u_int us) 500{ 501 struct ath_hal_5212 *ahp = AH5212(ah); 502 503 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 504 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n", 505 __func__, us); 506 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */ 507 return AH_FALSE; 508 } else { 509 /* convert to system clocks */ 510 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, 511 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us)); 512 ahp->ah_acktimeout = us; 513 return AH_TRUE; 514 } 515} 516 517u_int 518ar5212GetAckTimeout(struct ath_hal *ah) 519{ 520 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 521 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 522} 523 524u_int 525ar5212GetAckCTSRate(struct ath_hal *ah) 526{ 527 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0); 528} 529 530HAL_BOOL 531ar5212SetAckCTSRate(struct ath_hal *ah, u_int high) 532{ 533 struct ath_hal_5212 *ahp = AH5212(ah); 534 535 if (high) { 536 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); 537 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB; 538 } else { 539 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); 540 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB; 541 } 542 return AH_TRUE; 543} 544 545HAL_BOOL 546ar5212SetCTSTimeout(struct ath_hal *ah, u_int us) 547{ 548 struct ath_hal_5212 *ahp = AH5212(ah); 549 550 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 551 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n", 552 __func__, us); 553 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */ 554 return AH_FALSE; 555 } else { 556 /* convert to system clocks */ 557 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, 558 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us)); 559 ahp->ah_ctstimeout = us; 560 return AH_TRUE; 561 } 562} 563 564u_int 565ar5212GetCTSTimeout(struct ath_hal *ah) 566{ 567 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); 568 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 569} 570 571/* Setup decompression for given key index */ 572HAL_BOOL 573ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 574{ 575 struct ath_hal_5212 *ahp = AH5212(ah); 576 577 if (keyidx >= HAL_DECOMP_MASK_SIZE) 578 return HAL_EINVAL; 579 OS_REG_WRITE(ah, AR_DCM_A, keyidx); 580 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0); 581 ahp->ah_decompMask[keyidx] = en; 582 583 return AH_TRUE; 584} 585 586/* Setup coverage class */ 587void 588ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 589{ 590 uint32_t slot, timeout, eifs; 591 u_int clkRate; 592 593 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 594 595 if (now) { 596 if (AH_PRIVATE(ah)->ah_coverageClass == 0) 597 return; 598 599 /* Don't apply coverage class to non A channels */ 600 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan)) 601 return; 602 603 /* Get core clock rate */ 604 clkRate = ath_hal_mac_clks(ah, 1); 605 606 /* Compute EIFS */ 607 slot = coverageclass * 3 * clkRate; 608 eifs = coverageclass * 6 * clkRate; 609 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) { 610 slot += IFS_SLOT_HALF_RATE; 611 eifs += IFS_EIFS_HALF_RATE; 612 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) { 613 slot += IFS_SLOT_QUARTER_RATE; 614 eifs += IFS_EIFS_QUARTER_RATE; 615 } else { /* full rate */ 616 slot += IFS_SLOT_FULL_RATE; 617 eifs += IFS_EIFS_FULL_RATE; 618 } 619 620 /* 621 * Add additional time for air propagation for ACK and CTS 622 * timeouts. This value is in core clocks. 623 */ 624 timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate); 625 626 /* 627 * Write the values: slot, eifs, ack/cts timeouts. 628 */ 629 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 630 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 631 OS_REG_WRITE(ah, AR_TIME_OUT, 632 SM(timeout, AR_TIME_OUT_CTS) 633 | SM(timeout, AR_TIME_OUT_ACK)); 634 } 635} 636 637HAL_STATUS 638ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 639 uint32_t nextStart, HAL_QUIET_FLAG flag) 640{ 641 OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S)); 642 if (flag & HAL_QUIET_ENABLE) { 643 OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16)); 644 } 645 else { 646 OS_REG_WRITE(ah, AR_QUIET1, nextStart); 647 } 648 return HAL_OK; 649} 650 651void 652ar5212SetPCUConfig(struct ath_hal *ah) 653{ 654 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); 655} 656 657/* 658 * Return whether an external 32KHz crystal should be used 659 * to reduce power consumption when sleeping. We do so if 660 * the crystal is present (obtained from EEPROM) and if we 661 * are not running as an AP and are configured to use it. 662 */ 663HAL_BOOL 664ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode) 665{ 666 if (opmode != HAL_M_HOSTAP) { 667 struct ath_hal_5212 *ahp = AH5212(ah); 668 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) && 669 (ahp->ah_enable32kHzClock == USE_32KHZ || 670 ahp->ah_enable32kHzClock == AUTO_32KHZ); 671 } else 672 return AH_FALSE; 673} 674 675/* 676 * If 32KHz clock exists, use it to lower power consumption during sleep 677 * 678 * Note: If clock is set to 32 KHz, delays on accessing certain 679 * baseband registers (27-31, 124-127) are required. 680 */ 681void 682ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode) 683{ 684 if (ar5212Use32KHzclock(ah, opmode)) { 685 /* 686 * Enable clocks to be turned OFF in BB during sleep 687 * and also enable turning OFF 32MHz/40MHz Refclk 688 * from A2. 689 */ 690 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 691 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 692 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18); 693 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1); 694 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ 695 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1); 696 697 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) { 698 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26); 699 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d); 700 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07); 701 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f); 702 /* # Set sleep clock rate to 32 KHz. */ 703 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2); 704 } else { 705 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a); 706 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c); 707 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03); 708 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20); 709 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3); 710 } 711 } else { 712 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0); 713 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0); 714 715 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */ 716 717 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 718 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); 719 720 if (IS_2417(ah)) 721 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a); 722 else if (IS_HB63(ah)) 723 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32); 724 else 725 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 726 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); 727 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); 728 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 729 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18); 730 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 731 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31); 732 } 733} 734 735/* 736 * If 32KHz clock exists, turn it off and turn back on the 32Mhz 737 */ 738void 739ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode) 740{ 741 if (ar5212Use32KHzclock(ah, opmode)) { 742 /* # Set sleep clock rate back to 32 MHz. */ 743 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0); 744 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0); 745 746 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ 747 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 748 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31); 749 750 /* 751 * Restore BB registers to power-on defaults 752 */ 753 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 754 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); 755 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 756 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); 757 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); 758 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 759 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18); 760 } 761} 762 763/* 764 * Adjust NF based on statistical values for 5GHz frequencies. 765 * Default method: this may be overridden by the rf backend. 766 */ 767int16_t 768ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 769{ 770 static const struct { 771 uint16_t freqLow; 772 int16_t adjust; 773 } adjustDef[] = { 774 { 5790, 11 }, /* NB: ordered high -> low */ 775 { 5730, 10 }, 776 { 5690, 9 }, 777 { 5660, 8 }, 778 { 5610, 7 }, 779 { 5530, 5 }, 780 { 5450, 4 }, 781 { 5379, 2 }, 782 { 5209, 0 }, 783 { 3000, 1 }, 784 { 0, 0 }, 785 }; 786 int i; 787 788 for (i = 0; c->channel <= adjustDef[i].freqLow; i++) 789 ; 790 return adjustDef[i].adjust; 791} 792 793HAL_STATUS 794ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 795 uint32_t capability, uint32_t *result) 796{ 797#define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion 798 struct ath_hal_5212 *ahp = AH5212(ah); 799 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 800 const struct ar5212AniState *ani; 801 802 switch (type) { 803 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 804 switch (capability) { 805 case HAL_CIPHER_AES_CCM: 806 return pCap->halCipherAesCcmSupport ? 807 HAL_OK : HAL_ENOTSUPP; 808 case HAL_CIPHER_AES_OCB: 809 case HAL_CIPHER_TKIP: 810 case HAL_CIPHER_WEP: 811 case HAL_CIPHER_MIC: 812 case HAL_CIPHER_CLR: 813 return HAL_OK; 814 default: 815 return HAL_ENOTSUPP; 816 } 817 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 818 switch (capability) { 819 case 0: /* hardware capability */ 820 return HAL_OK; 821 case 1: 822 return (ahp->ah_staId1Defaults & 823 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 824 } 825 return HAL_EINVAL; 826 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 827 switch (capability) { 828 case 0: /* hardware capability */ 829 return pCap->halTkipMicTxRxKeySupport ? 830 HAL_ENXIO : HAL_OK; 831 case 1: /* current setting */ 832 return (ahp->ah_miscMode & 833 AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK; 834 } 835 return HAL_EINVAL; 836 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC w/ WMM */ 837 /* XXX move to capability bit */ 838 return MACVERSION(ah) > AR_SREV_VERSION_VENICE || 839 (MACVERSION(ah) == AR_SREV_VERSION_VENICE && 840 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP; 841 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 842 switch (capability) { 843 case 0: /* hardware capability */ 844 return HAL_OK; 845 case 1: /* current setting */ 846 return ahp->ah_diversity ? HAL_OK : HAL_ENXIO; 847 } 848 return HAL_EINVAL; 849 case HAL_CAP_DIAG: 850 *result = AH_PRIVATE(ah)->ah_diagreg; 851 return HAL_OK; 852 case HAL_CAP_TPC: 853 switch (capability) { 854 case 0: /* hardware capability */ 855 return HAL_OK; 856 case 1: 857 return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO; 858 } 859 return HAL_OK; 860 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 861 switch (capability) { 862 case HAL_CAP_RADAR: 863 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ? 864 HAL_OK: HAL_ENXIO; 865 case HAL_CAP_AR: 866 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) || 867 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ? 868 HAL_OK: HAL_ENXIO; 869 } 870 return HAL_ENXIO; 871 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 872 switch (capability) { 873 case 0: /* hardware capability */ 874 return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENXIO; 875 case 1: 876 return (ahp->ah_staId1Defaults & 877 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 878 } 879 return HAL_EINVAL; 880 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 881 switch (capability) { 882 case 0: /* hardware capability */ 883 return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 884 case 1: 885 return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ? 886 HAL_OK : HAL_ENXIO; 887 } 888 return HAL_EINVAL; 889 case HAL_CAP_TPC_ACK: 890 *result = MS(ahp->ah_macTPC, AR_TPC_ACK); 891 return HAL_OK; 892 case HAL_CAP_TPC_CTS: 893 *result = MS(ahp->ah_macTPC, AR_TPC_CTS); 894 return HAL_OK; 895 case HAL_CAP_INTMIT: /* interference mitigation */ 896 switch (capability) { 897 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 898 return HAL_OK; 899 case HAL_CAP_INTMIT_ENABLE: 900 return (ahp->ah_procPhyErr & HAL_ANI_ENA) ? 901 HAL_OK : HAL_ENXIO; 902 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 903 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 904 case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 905 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 906 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 907 ani = ar5212AniGetCurrentState(ah); 908 if (ani == AH_NULL) 909 return HAL_ENXIO; 910 switch (capability) { 911 case 2: *result = ani->noiseImmunityLevel; break; 912 case 3: *result = !ani->ofdmWeakSigDetectOff; break; 913 case 4: *result = ani->cckWeakSigThreshold; break; 914 case 5: *result = ani->firstepLevel; break; 915 case 6: *result = ani->spurImmunityLevel; break; 916 } 917 return HAL_OK; 918 } 919 return HAL_EINVAL; 920 default: 921 return ath_hal_getcapability(ah, type, capability, result); 922 } 923#undef MACVERSION 924} 925 926HAL_BOOL 927ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 928 uint32_t capability, uint32_t setting, HAL_STATUS *status) 929{ 930#define N(a) (sizeof(a)/sizeof(a[0])) 931 struct ath_hal_5212 *ahp = AH5212(ah); 932 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 933 uint32_t v; 934 935 switch (type) { 936 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 937 if (setting) 938 ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 939 else 940 ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 941 return AH_TRUE; 942 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 943 if (!pCap->halTkipMicTxRxKeySupport) 944 return AH_FALSE; 945 /* NB: true =>'s use split key cache layout */ 946 if (setting) 947 ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE; 948 else 949 ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE; 950 /* NB: write here so keys can be setup w/o a reset */ 951 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 952 return AH_TRUE; 953 case HAL_CAP_DIVERSITY: 954 if (ahp->ah_phyPowerOn) { 955 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 956 if (setting) 957 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 958 else 959 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 960 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 961 } 962 ahp->ah_diversity = (setting != 0); 963 return AH_TRUE; 964 case HAL_CAP_DIAG: /* hardware diagnostic support */ 965 /* 966 * NB: could split this up into virtual capabilities, 967 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 968 * seems worth the additional complexity. 969 */ 970 AH_PRIVATE(ah)->ah_diagreg = setting; 971 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 972 return AH_TRUE; 973 case HAL_CAP_TPC: 974 ahp->ah_tpcEnabled = (setting != 0); 975 return AH_TRUE; 976 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 977 if (setting) 978 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 979 else 980 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 981 return AH_TRUE; 982 case HAL_CAP_TPC_ACK: 983 case HAL_CAP_TPC_CTS: 984 setting += ahp->ah_txPowerIndexOffset; 985 if (setting > 63) 986 setting = 63; 987 if (type == HAL_CAP_TPC_ACK) { 988 ahp->ah_macTPC &= AR_TPC_ACK; 989 ahp->ah_macTPC |= MS(setting, AR_TPC_ACK); 990 } else { 991 ahp->ah_macTPC &= AR_TPC_CTS; 992 ahp->ah_macTPC |= MS(setting, AR_TPC_CTS); 993 } 994 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC); 995 return AH_TRUE; 996 case HAL_CAP_INTMIT: { /* interference mitigation */ 997 /* This maps the public ANI commands to the internal ANI commands */ 998 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 999 static const HAL_ANI_CMD cmds[] = { 1000 HAL_ANI_PRESENT, 1001 HAL_ANI_MODE, 1002 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1003 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1004 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1005 HAL_ANI_FIRSTEP_LEVEL, 1006 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1007 }; 1008 return capability < N(cmds) ? 1009 AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) : 1010 AH_FALSE; 1011 } 1012 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1013 if (pCap->halTsfAddSupport) { 1014 if (setting) 1015 ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF; 1016 else 1017 ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF; 1018 return AH_TRUE; 1019 } 1020 /* fall thru... */ 1021 default: 1022 return ath_hal_setcapability(ah, type, capability, 1023 setting, status); 1024 } 1025#undef N 1026} 1027 1028HAL_BOOL 1029ar5212GetDiagState(struct ath_hal *ah, int request, 1030 const void *args, uint32_t argsize, 1031 void **result, uint32_t *resultsize) 1032{ 1033 struct ath_hal_5212 *ahp = AH5212(ah); 1034 1035 (void) ahp; 1036 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 1037 return AH_TRUE; 1038 switch (request) { 1039 case HAL_DIAG_EEPROM: 1040 case HAL_DIAG_EEPROM_EXP_11A: 1041 case HAL_DIAG_EEPROM_EXP_11B: 1042 case HAL_DIAG_EEPROM_EXP_11G: 1043 case HAL_DIAG_RFGAIN: 1044 return ath_hal_eepromDiag(ah, request, 1045 args, argsize, result, resultsize); 1046 case HAL_DIAG_RFGAIN_CURSTEP: 1047 *result = __DECONST(void *, ahp->ah_gainValues.currStep); 1048 *resultsize = (*result == AH_NULL) ? 1049 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1050 return AH_TRUE; 1051 case HAL_DIAG_PCDAC: 1052 *result = ahp->ah_pcdacTable; 1053 *resultsize = ahp->ah_pcdacTableSize; 1054 return AH_TRUE; 1055 case HAL_DIAG_TXRATES: 1056 *result = &ahp->ah_ratesArray[0]; 1057 *resultsize = sizeof(ahp->ah_ratesArray); 1058 return AH_TRUE; 1059 case HAL_DIAG_ANI_CURRENT: 1060 *result = ar5212AniGetCurrentState(ah); 1061 *resultsize = (*result == AH_NULL) ? 1062 0 : sizeof(struct ar5212AniState); 1063 return AH_TRUE; 1064 case HAL_DIAG_ANI_STATS: 1065 *result = ar5212AniGetCurrentStats(ah); 1066 *resultsize = (*result == AH_NULL) ? 1067 0 : sizeof(struct ar5212Stats); 1068 return AH_TRUE; 1069 case HAL_DIAG_ANI_CMD: 1070 if (argsize != 2*sizeof(uint32_t)) 1071 return AH_FALSE; 1072 AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0], 1073 ((const uint32_t *)args)[1]); 1074 return AH_TRUE; 1075 case HAL_DIAG_ANI_PARAMS: 1076 /* 1077 * NB: We assume struct ar5212AniParams is identical 1078 * to HAL_ANI_PARAMS; if they diverge then we'll need 1079 * to handle it here 1080 */ 1081 if (argsize == 0 && args == AH_NULL) { 1082 struct ar5212AniState *aniState = 1083 ar5212AniGetCurrentState(ah); 1084 if (aniState == AH_NULL) 1085 return AH_FALSE; 1086 *result = __DECONST(void *, aniState->params); 1087 *resultsize = sizeof(struct ar5212AniParams); 1088 return AH_TRUE; 1089 } else { 1090 if (argsize != sizeof(struct ar5212AniParams)) 1091 return AH_FALSE; 1092 return ar5212AniSetParams(ah, args, args); 1093 } 1094 } 1095 return AH_FALSE; 1096} 1097 1098/* 1099 * Check whether there's an in-progress NF completion. 1100 * 1101 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE 1102 * otherwise. 1103 */ 1104HAL_BOOL 1105ar5212IsNFCalInProgress(struct ath_hal *ah) 1106{ 1107 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) 1108 return AH_TRUE; 1109 return AH_FALSE; 1110} 1111 1112/* 1113 * Wait for an in-progress NF calibration to complete. 1114 * 1115 * The completion function waits "i" times 10uS. 1116 * It returns AH_TRUE if the NF calibration completed (or was never 1117 * in progress); AH_FALSE if it was still in progress after "i" checks. 1118 */ 1119HAL_BOOL 1120ar5212WaitNFCalComplete(struct ath_hal *ah, int i) 1121{ 1122 int j; 1123 if (i <= 0) 1124 i = 1; /* it should run at least once */ 1125 for (j = 0; j < i; j++) { 1126 if (! ar5212IsNFCalInProgress(ah)) 1127 return AH_TRUE; 1128 OS_DELAY(10); 1129 } 1130 return AH_FALSE; 1131} 1132 1133void 1134ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 1135{ 1136 uint32_t val; 1137 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 1138 1139 if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) { 1140 val &= ~AR_PHY_RADAR_0_FIRPWR; 1141 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); 1142 } 1143 if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) { 1144 val &= ~AR_PHY_RADAR_0_RRSSI; 1145 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); 1146 } 1147 if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) { 1148 val &= ~AR_PHY_RADAR_0_HEIGHT; 1149 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); 1150 } 1151 if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) { 1152 val &= ~AR_PHY_RADAR_0_PRSSI; 1153 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); 1154 } 1155 if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) { 1156 val &= ~AR_PHY_RADAR_0_INBAND; 1157 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); 1158 } 1159 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA); 1160} 1161 1162void 1163ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 1164{ 1165 uint32_t val,temp; 1166 1167 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 1168 1169 temp = MS(val,AR_PHY_RADAR_0_FIRPWR); 1170 temp |= 0xFFFFFF80; 1171 pe->pe_firpwr = temp; 1172 pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI); 1173 pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT); 1174 pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI); 1175 pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND); 1176 1177 pe->pe_relpwr = 0; 1178 pe->pe_relstep = 0; 1179 pe->pe_maxlen = 0; 1180 pe->pe_extchannel = AH_FALSE; 1181} 1182 1183/* 1184 * Process the radar phy error and extract the pulse duration. 1185 */ 1186HAL_BOOL 1187ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs, 1188 uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event) 1189{ 1190 uint8_t dur; 1191 uint8_t rssi; 1192 1193 /* Check whether the given phy error is a radar event */ 1194 if ((rxs->rs_phyerr != HAL_PHYERR_RADAR) && 1195 (rxs->rs_phyerr != HAL_PHYERR_FALSE_RADAR_EXT)) 1196 return AH_FALSE; 1197 1198 /* 1199 * The first byte is the pulse width - if there's 1200 * no data, simply set the duration to 0 1201 */ 1202 if (rxs->rs_datalen >= 1) 1203 /* The pulse width is byte 0 of the data */ 1204 dur = ((uint8_t) buf[0]) & 0xff; 1205 else 1206 dur = 0; 1207 1208 /* Pulse RSSI is the normal reported RSSI */ 1209 rssi = (uint8_t) rxs->rs_rssi; 1210 1211 /* 0 duration/rssi is not a valid radar event */ 1212 if (dur == 0 && rssi == 0) 1213 return AH_FALSE; 1214 1215 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n", 1216 __func__, rssi, dur); 1217 1218 /* Record the event */ 1219 event->re_full_ts = fulltsf; 1220 event->re_ts = rxs->rs_tstamp; 1221 event->re_rssi = rssi; 1222 event->re_dur = dur; 1223 event->re_flags = HAL_DFS_EVENT_PRICH; 1224 1225 return AH_TRUE; 1226} 1227