ar5212.h revision 234774
1214478Srpaulo/* 217680Spst * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3214478Srpaulo * Copyright (c) 2002-2008 Atheros Communications, Inc. 475115Sfenner * 575115Sfenner * Permission to use, copy, modify, and/or distribute this software for any 617680Spst * purpose with or without fee is hereby granted, provided that the above 7190207Srpaulo * copyright notice and this permission notice appear in all copies. 8190207Srpaulo * 975115Sfenner * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10214478Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11214478Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1275115Sfenner * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13214478Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14214478Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1575115Sfenner * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16251158Sdelphij * 1775115Sfenner * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212.h 234774 2012-04-28 22:03:19Z adrian $ 18251158Sdelphij */ 19251158Sdelphij#ifndef _ATH_AR5212_H_ 20251158Sdelphij#define _ATH_AR5212_H_ 21251158Sdelphij 2275115Sfenner#include "ah_eeprom.h" 2375115Sfenner 2475115Sfenner#define AR5212_MAGIC 0x19541014 2575115Sfenner 2617680Spst/* DCU Transmit Filter macros */ 2775115Sfenner#define CALC_MMR(dcu, idx) \ 2875115Sfenner ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 2975115Sfenner#define TXBLK_FROM_MMR(mmr) \ 3075115Sfenner (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 3175115Sfenner#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 3217680Spst#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 3375115Sfenner 3417680Spst/* MAC register values */ 3575115Sfenner 3675115Sfenner#define INIT_INTERRUPT_MASK \ 3717680Spst ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 3817680Spst AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 3917680Spst AR_IMR_HIUERR ) 4017680Spst#define INIT_BEACON_CONTROL \ 4117680Spst ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 4239297Sfenner (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 4339297Sfenner 4439297Sfenner#define INIT_CONFIG_STATUS 0x00000000 4539297Sfenner#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 4639297Sfenner#define INIT_IQCAL_LOG_COUNT_MAX 0xF 4739297Sfenner#define INIT_BCON_CNTRL_REG 0x00000000 4839297Sfenner 4939297Sfenner#define INIT_USEC 40 5017680Spst#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 5139297Sfenner#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 5239297Sfenner 5339297Sfenner#define RX_NON_FULL_RATE_LATENCY 63 5417680Spst#define TX_HALF_RATE_LATENCY 108 5539297Sfenner#define TX_QUARTER_RATE_LATENCY 216 5639297Sfenner 5739297Sfenner#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 5817680Spst#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 5917680Spst#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 6017680Spst#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 6117680Spst#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 6239297Sfenner#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 6317680Spst 6439297Sfenner#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 6539297Sfenner 6639297Sfenner/* Tx frame start to tx data start delay */ 6739297Sfenner#define TX_FRAME_D_START_HALF_RATE 0xc 6839297Sfenner#define TX_FRAME_D_START_QUARTER_RATE 0xd 6939297Sfenner 7039297Sfenner/* 7139297Sfenner * Various fifo fill before Tx start, in 64-byte units 72111726Sfenner * i.e. put the frame in the air while still DMAing 73190207Srpaulo */ 74251158Sdelphij#define MIN_TX_FIFO_THRESHOLD 0x1 75251158Sdelphij#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 7617680Spst#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77251158Sdelphij 7875115Sfenner#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79111726Sfenner 80251158Sdelphij/* 8175115Sfenner * Gain support. 82251158Sdelphij */ 83111726Sfenner#define NUM_CORNER_FIX_BITS 4 84251158Sdelphij#define NUM_CORNER_FIX_BITS_5112 7 85251158Sdelphij#define DYN_ADJ_UP_MARGIN 15 86251158Sdelphij#define DYN_ADJ_LO_MARGIN 20 87251158Sdelphij#define PHY_PROBE_CCK_CORRECTION 5 8875115Sfenner#define CCK_OFDM_GAIN_DELTA 15 8975115Sfenner 9075115Sfennerenum GAIN_PARAMS { 9175115Sfenner GP_TXCLIP, 9217680Spst GP_PD90, 9317680Spst GP_PD84, 9417680Spst GP_GSEL, 9517680Spst}; 9617680Spst 9717680Spstenum GAIN_PARAMS_5112 { 9817680Spst GP_MIXGAIN_OVR, 9917680Spst GP_PWD_138, 10017680Spst GP_PWD_137, 10117680Spst GP_PWD_136, 10217680Spst GP_PWD_132, 10317680Spst GP_PWD_131, 10417680Spst GP_PWD_130, 10517680Spst}; 10617680Spst 10717680Spsttypedef struct _gainOptStep { 10817680Spst int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 10917680Spst int32_t stepGain; 11017680Spst int8_t stepName[16]; 11117680Spst} GAIN_OPTIMIZATION_STEP; 11217680Spst 11317680Spsttypedef struct { 11417680Spst uint32_t numStepsInLadder; 11517680Spst uint32_t defaultStepNum; 11617680Spst GAIN_OPTIMIZATION_STEP optStep[10]; 11717680Spst} GAIN_OPTIMIZATION_LADDER; 11817680Spst 11917680Spsttypedef struct { 12017680Spst uint32_t currStepNum; 12117680Spst uint32_t currGain; 12217680Spst uint32_t targetGain; 12317680Spst uint32_t loTrig; 12417680Spst uint32_t hiTrig; 12517680Spst uint32_t active; 12617680Spst const GAIN_OPTIMIZATION_STEP *currStep; 12717680Spst} GAIN_VALUES; 12817680Spst 12917680Spst/* RF HAL structures */ 13017680Spsttypedef struct RfHalFuncs { 13117680Spst void *priv; /* private state */ 13217680Spst 13317680Spst void (*rfDetach)(struct ath_hal *ah); 13417680Spst void (*writeRegs)(struct ath_hal *, 13517680Spst u_int modeIndex, u_int freqIndex, int regWrites); 13617680Spst uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 13717680Spst HAL_BOOL (*setChannel)(struct ath_hal *, 13817680Spst const struct ieee80211_channel *); 13917680Spst HAL_BOOL (*setRfRegs)(struct ath_hal *, 14017680Spst const struct ieee80211_channel *, uint16_t modesIndex, 14117680Spst uint16_t *rfXpdGain); 14217680Spst HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 14317680Spst int16_t *minPower, int16_t *maxPower, 14417680Spst const struct ieee80211_channel *, uint16_t *rfXpdGain); 14517680Spst HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 14617680Spst const const struct ieee80211_channel *, 14717680Spst int16_t *maxPow, int16_t *minPow); 14817680Spst int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 14917680Spst} RF_HAL_FUNCS; 15017680Spst 15117680Spststruct ar5212AniParams { 15217680Spst int maxNoiseImmunityLevel; /* [0..4] */ 15317680Spst int totalSizeDesired[5]; 15417680Spst int coarseHigh[5]; 15517680Spst int coarseLow[5]; 15617680Spst int firpwr[5]; 15717680Spst 15817680Spst int maxSpurImmunityLevel; /* [0..7] */ 15917680Spst int cycPwrThr1[8]; 16017680Spst 16117680Spst int maxFirstepLevel; /* [0..2] */ 16217680Spst int firstep[3]; 16317680Spst 16417680Spst uint32_t ofdmTrigHigh; 16517680Spst uint32_t ofdmTrigLow; 16617680Spst uint32_t cckTrigHigh; 16717680Spst uint32_t cckTrigLow; 16817680Spst int32_t rssiThrLow; 16917680Spst uint32_t rssiThrHigh; 17017680Spst 17117680Spst int period; /* update listen period */ 17217680Spst 17317680Spst /* NB: intentionally ordered so data exported to user space is first */ 17417680Spst uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 17517680Spst uint32_t cckPhyErrBase; /* Base value for cck err counters */ 17617680Spst}; 17717680Spst 17817680Spst/* 17917680Spst * Per-channel ANI state private to the driver. 18017680Spst */ 18117680Spststruct ar5212AniState { 18217680Spst uint8_t noiseImmunityLevel; 18317680Spst uint8_t spurImmunityLevel; 18417680Spst uint8_t firstepLevel; 18517680Spst uint8_t ofdmWeakSigDetectOff; 18617680Spst uint8_t cckWeakSigThreshold; 18717680Spst uint32_t listenTime; 18817680Spst 18917680Spst /* NB: intentionally ordered so data exported to user space is first */ 19017680Spst uint32_t txFrameCount; /* Last txFrameCount */ 19117680Spst uint32_t rxFrameCount; /* Last rx Frame count */ 19217680Spst uint32_t cycleCount; /* Last cycleCount 19317680Spst (to detect wrap-around) */ 19417680Spst uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 19517680Spst uint32_t cckPhyErrCount; /* CCK err count since last reset */ 19617680Spst 19717680Spst const struct ar5212AniParams *params; 19817680Spst}; 19917680Spst 20017680Spst#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 20117680Spst#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 20217680Spst 20317680Spststruct ar5212Stats { 20417680Spst uint32_t ast_ani_niup; /* ANI increased noise immunity */ 20517680Spst uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 20617680Spst uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 20717680Spst uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 20817680Spst uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 20917680Spst uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 21017680Spst uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 21117680Spst uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 21217680Spst uint32_t ast_ani_stepup; /* ANI increased first step level */ 21317680Spst uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 21417680Spst uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 21517680Spst uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 21617680Spst uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 21717680Spst uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 21817680Spst uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 21917680Spst HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 22017680Spst HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 22117680Spst}; 22217680Spst 22317680Spst/* 22417680Spst * NF Cal history buffer 22517680Spst */ 22617680Spst#define AR5212_CCA_MAX_GOOD_VALUE -95 22717680Spst#define AR5212_CCA_MAX_HIGH_VALUE -62 22817680Spst#define AR5212_CCA_MIN_BAD_VALUE -125 22917680Spst 23017680Spst#define AR512_NF_CAL_HIST_MAX 5 23117680Spst 23217680Spststruct ar5212NfCalHist { 23317680Spst int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 23417680Spst int16_t privNF; 23517680Spst uint8_t currIndex; 23617680Spst uint8_t first_run; 23717680Spst uint8_t invalidNFcount; 23817680Spst}; 23917680Spst 240struct ath_hal_5212 { 241 struct ath_hal_private ah_priv; /* base class */ 242 243 /* 244 * Per-chip common Initialization data. 245 * NB: RF backends have their own ini data. 246 */ 247 HAL_INI_ARRAY ah_ini_modes; 248 HAL_INI_ARRAY ah_ini_common; 249 250 GAIN_VALUES ah_gainValues; 251 252 uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 253 uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 254 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 255 uint16_t ah_assocId; 256 257 /* 258 * Runtime state. 259 */ 260 uint32_t ah_maskReg; /* copy of AR_IMR */ 261 struct ar5212Stats ah_stats; /* various statistics */ 262 RF_HAL_FUNCS *ah_rfHal; 263 uint32_t ah_txDescMask; /* mask for TXDESC */ 264 uint32_t ah_txOkInterruptMask; 265 uint32_t ah_txErrInterruptMask; 266 uint32_t ah_txDescInterruptMask; 267 uint32_t ah_txEolInterruptMask; 268 uint32_t ah_txUrnInterruptMask; 269 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 270 uint32_t ah_intrTxqs; /* tx q interrupt state */ 271 /* decomp mask array */ 272 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 273 HAL_POWER_MODE ah_powerMode; 274 HAL_ANT_SETTING ah_antControl; /* antenna setting */ 275 HAL_BOOL ah_diversity; /* fast diversity setting */ 276 enum { 277 IQ_CAL_INACTIVE, 278 IQ_CAL_RUNNING, 279 IQ_CAL_DONE 280 } ah_bIQCalibration; /* IQ calibrate state */ 281 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 282 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 283 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 284 uint32_t ah_miscMode; /* MISC_MODE settings */ 285 uint32_t ah_rssiThr; /* RSSI_THR settings */ 286 HAL_BOOL ah_cwCalRequire; /* for ap51 */ 287 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 288 HAL_BOOL ah_phyPowerOn; /* PHY power state */ 289 HAL_BOOL ah_isHb63; /* cached HB63 check */ 290 uint32_t ah_macTPC; /* tpc register */ 291 uint32_t ah_beaconInterval; /* XXX */ 292 enum { 293 AUTO_32KHZ, /* use it if 32kHz crystal present */ 294 USE_32KHZ, /* do it regardless */ 295 DONT_USE_32KHZ, /* don't use it regardless */ 296 } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 297 uint32_t ah_ofdmTxPower; 298 int16_t ah_txPowerIndexOffset; 299 /* 300 * Noise floor cal histogram support. 301 */ 302 struct ar5212NfCalHist ah_nfCalHist; 303 304 u_int ah_slottime; /* user-specified slot time */ 305 u_int ah_acktimeout; /* user-specified ack timeout */ 306 u_int ah_ctstimeout; /* user-specified cts timeout */ 307 u_int ah_sifstime; /* user-specified sifs time */ 308 /* 309 * RF Silent handling; setup according to the EEPROM. 310 */ 311 uint32_t ah_gpioSelect; /* GPIO pin to use */ 312 uint32_t ah_polarity; /* polarity to disable RF */ 313 uint32_t ah_gpioBit; /* after init, prev value */ 314 /* 315 * ANI support. 316 */ 317 uint32_t ah_procPhyErr; /* Process Phy errs */ 318 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 319 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 320 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 321 struct ar5212AniState *ah_curani; /* cached last reference */ 322 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 323 HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */ 324 325 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 326 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 327 328 /* 329 * Transmit power state. Note these are maintained 330 * here so they can be retrieved by diagnostic tools. 331 */ 332 uint16_t *ah_pcdacTable; 333 u_int ah_pcdacTableSize; 334 uint16_t ah_ratesArray[37]; 335 336 uint8_t ah_txTrigLev; /* current Tx trigger level */ 337 uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 338}; 339#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 340 341/* 342 * IS_XXXX macros test the MAC version 343 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 344 * 345 * Some single chip radios have equivalent radio/RF (e.g. 5112) 346 * for those use IS_RADXXX_ANY macros. 347 */ 348#define IS_2317(ah) \ 349 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 350 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 351#define IS_2316(ah) \ 352 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 353#define IS_2413(ah) \ 354 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 355#define IS_5424(ah) \ 356 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 357 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 358 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 359#define IS_5413(ah) \ 360 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 361#define IS_2425(ah) \ 362 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 363#define IS_2417(ah) \ 364 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 365#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 366 367#define AH_RADIO_MAJOR(ah) \ 368 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 369#define AH_RADIO_MINOR(ah) \ 370 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 371#define IS_RAD5111(ah) \ 372 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 373 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 374#define IS_RAD5112(ah) \ 375 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 376 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 377/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 378#define IS_RAD5112_ANY(ah) \ 379 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 380 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 381#define IS_RAD5112_REV1(ah) \ 382 (IS_RAD5112(ah) && \ 383 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 384#define IS_RADX112_REV2(ah) \ 385 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 386 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 387 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 388 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 389 390#define ar5212RfDetach(ah) do { \ 391 if (AH5212(ah)->ah_rfHal != AH_NULL) \ 392 AH5212(ah)->ah_rfHal->rfDetach(ah); \ 393} while (0) 394#define ar5212GetRfBank(ah, b) \ 395 AH5212(ah)->ah_rfHal->getRfBank(ah, b) 396 397/* 398 * Hack macros for Nala/San: 11b is handled 399 * using 11g; flip the channel flags to accomplish this. 400 */ 401#define SAVE_CCK(_ah, _chan, _flag) do { \ 402 if ((IS_2425(_ah) || IS_2417(_ah)) && \ 403 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 404 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 405 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 406 (_flag) = AH_TRUE; \ 407 } else \ 408 (_flag) = AH_FALSE; \ 409} while (0) 410#define RESTORE_CCK(_ah, _chan, _flag) do { \ 411 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 412 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 413 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 414 } \ 415} while (0) 416 417struct ath_hal; 418 419extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 420extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 421 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 422extern void ar5212Detach(struct ath_hal *ah); 423extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 424extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 425 uint16_t flags, uint16_t *low, uint16_t *high); 426extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 427 428extern void ar5212SetBeaconTimers(struct ath_hal *ah, 429 const HAL_BEACON_TIMERS *); 430extern void ar5212BeaconInit(struct ath_hal *ah, 431 uint32_t next_beacon, uint32_t beacon_period); 432extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 433extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 434 const HAL_BEACON_STATE *); 435extern uint64_t ar5212GetNextTBTT(struct ath_hal *); 436 437extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 438extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 439extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 440extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 441 442extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 443extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 444extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 445extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 446 uint16_t entry, const uint8_t *mac); 447extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 448 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 449 450extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 451extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 452extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 453extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 454extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 455extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 456extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 457 uint16_t regDomain, HAL_STATUS *stats); 458extern u_int ar5212GetWirelessModes(struct ath_hal *ah); 459extern void ar5212EnableRfKill(struct ath_hal *); 460extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 461 HAL_GPIO_MUX_TYPE); 462extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 463extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 464extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 465extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 466extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 467extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 468 uint16_t assocId); 469extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 470extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 471extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 472extern void ar5212ResetTsf(struct ath_hal *ah); 473extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 474extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 475extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 476extern void ar5212EnableMibCounters(struct ath_hal *); 477extern void ar5212DisableMibCounters(struct ath_hal *); 478extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 479extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 480extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 481extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 482extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 483extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 484extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 485extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 486extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 487extern u_int ar5212GetSifsTime(struct ath_hal *); 488extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 489extern u_int ar5212GetSlotTime(struct ath_hal *); 490extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 491extern u_int ar5212GetAckTimeout(struct ath_hal *); 492extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 493extern u_int ar5212GetAckCTSRate(struct ath_hal *); 494extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 495extern u_int ar5212GetCTSTimeout(struct ath_hal *); 496extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 497void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 498extern void ar5212SetPCUConfig(struct ath_hal *); 499extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 500extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 501extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 502extern int16_t ar5212GetNfAdjust(struct ath_hal *, 503 const HAL_CHANNEL_INTERNAL *); 504extern void ar5212SetCompRegs(struct ath_hal *ah); 505extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 506 uint32_t, uint32_t *); 507extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 508 uint32_t, uint32_t, HAL_STATUS *); 509extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 510 const void *args, uint32_t argsize, 511 void **result, uint32_t *resultsize); 512extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 513 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 514 515extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 516 int setChip); 517extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 518extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 519 520extern uint32_t ar5212GetRxDP(struct ath_hal *ath); 521extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp); 522extern void ar5212EnableReceive(struct ath_hal *ah); 523extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 524extern void ar5212StartPcuReceive(struct ath_hal *ah); 525extern void ar5212StopPcuReceive(struct ath_hal *ah); 526extern void ar5212SetMulticastFilter(struct ath_hal *ah, 527 uint32_t filter0, uint32_t filter1); 528extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 529extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 530extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 531extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 532extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 533 struct ath_desc *, uint32_t size, u_int flags); 534extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 535 uint32_t, struct ath_desc *, uint64_t, 536 struct ath_rx_status *); 537 538extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 539 struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 540 HAL_STATUS *status); 541extern HAL_BOOL ar5212SetChannel(struct ath_hal *, 542 const struct ieee80211_channel *); 543extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 544extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 545extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 546extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 547 const struct ieee80211_channel *); 548extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 549 struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 550extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 551 struct ieee80211_channel *chan, u_int chainMask, 552 HAL_BOOL longCal, HAL_BOOL *isCalDone); 553extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 554 const struct ieee80211_channel *); 555extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 556extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 557extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 558extern void ar5212SetSpurMitigation(struct ath_hal *, 559 const struct ieee80211_channel *); 560extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 561 HAL_ANT_SETTING settings, const struct ieee80211_channel *); 562extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 563extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 564 struct ieee80211_channel *chan); 565extern void ar5212InitializeGainValues(struct ath_hal *); 566extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 567extern void ar5212RequestRfgain(struct ath_hal *); 568 569extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 570 HAL_BOOL IncTrigLevel); 571extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 572 const HAL_TXQ_INFO *qInfo); 573extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 574 HAL_TXQ_INFO *qInfo); 575extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 576 const HAL_TXQ_INFO *qInfo); 577extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 578extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 579extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 580extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 581extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 582extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 583extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 584extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 585 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 586 u_int txRate0, u_int txTries0, 587 u_int keyIx, u_int antMode, u_int flags, 588 u_int rtsctsRate, u_int rtsctsDuration, 589 u_int compicvLen, u_int compivLen, u_int comp); 590extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 591 u_int txRate1, u_int txRetries1, 592 u_int txRate2, u_int txRetries2, 593 u_int txRate3, u_int txRetries3); 594extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 595 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 596 const struct ath_desc *ds0); 597extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 598 struct ath_desc *, struct ath_tx_status *); 599extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 600extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 601extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 602 const struct ath_desc *ds0, int *rates, int *tries); 603 604extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 605 606extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 607 const struct ar5212AniParams *, HAL_BOOL ena); 608extern void ar5212AniDetach(struct ath_hal *); 609extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 610extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); 611extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 612extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 613 const struct ar5212AniParams *, const struct ar5212AniParams *); 614struct ath_rx_status; 615extern void ar5212AniPhyErrReport(struct ath_hal *ah, 616 const struct ath_rx_status *rs); 617extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 618extern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 619 const struct ieee80211_channel *); 620extern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 621extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 622 HAL_OPMODE, int); 623 624extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 625extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 626extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 627extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 628extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 629 struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 630 HAL_DFS_EVENT *event); 631extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 632extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 633 634#endif /* _ATH_AR5212_H_ */ 635