1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19#ifndef _ATH_AR5212_H_ 20#define _ATH_AR5212_H_ 21 22#include "ah_eeprom.h" 23 24#define AR5212_MAGIC 0x19541014 25 26/* DCU Transmit Filter macros */ 27#define CALC_MMR(dcu, idx) \ 28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29#define TXBLK_FROM_MMR(mmr) \ 30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33 34/* MAC register values */ 35 36#define INIT_INTERRUPT_MASK \ 37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39 AR_IMR_HIUERR ) 40#define INIT_BEACON_CONTROL \ 41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43 44#define INIT_CONFIG_STATUS 0x00000000 45#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46#define INIT_IQCAL_LOG_COUNT_MAX 0xF 47#define INIT_BCON_CNTRL_REG 0x00000000 48 49#define INIT_USEC 40 50#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52 53#define RX_NON_FULL_RATE_LATENCY 63 54#define TX_HALF_RATE_LATENCY 108 55#define TX_QUARTER_RATE_LATENCY 216 56 57#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63 64#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65 66/* Tx frame start to tx data start delay */ 67#define TX_FRAME_D_START_HALF_RATE 0xc 68#define TX_FRAME_D_START_QUARTER_RATE 0xd 69 70/* 71 * Various fifo fill before Tx start, in 64-byte units 72 * i.e. put the frame in the air while still DMAing 73 */ 74#define MIN_TX_FIFO_THRESHOLD 0x1 75#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77 78#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79 80/* 81 * Gain support. 82 */ 83#define NUM_CORNER_FIX_BITS 4 84#define NUM_CORNER_FIX_BITS_5112 7 85#define DYN_ADJ_UP_MARGIN 15 86#define DYN_ADJ_LO_MARGIN 20 87#define PHY_PROBE_CCK_CORRECTION 5 88#define CCK_OFDM_GAIN_DELTA 15 89 90enum GAIN_PARAMS { 91 GP_TXCLIP, 92 GP_PD90, 93 GP_PD84, 94 GP_GSEL, 95}; 96 97enum GAIN_PARAMS_5112 { 98 GP_MIXGAIN_OVR, 99 GP_PWD_138, 100 GP_PWD_137, 101 GP_PWD_136, 102 GP_PWD_132, 103 GP_PWD_131, 104 GP_PWD_130, 105}; 106 107typedef struct _gainOptStep { 108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109 int32_t stepGain; 110 int8_t stepName[16]; 111} GAIN_OPTIMIZATION_STEP; 112 113typedef struct { 114 uint32_t numStepsInLadder; 115 uint32_t defaultStepNum; 116 GAIN_OPTIMIZATION_STEP optStep[10]; 117} GAIN_OPTIMIZATION_LADDER; 118 119typedef struct { 120 uint32_t currStepNum; 121 uint32_t currGain; 122 uint32_t targetGain; 123 uint32_t loTrig; 124 uint32_t hiTrig; 125 uint32_t active; 126 const GAIN_OPTIMIZATION_STEP *currStep; 127} GAIN_VALUES; 128 129/* RF HAL structures */ 130typedef struct RfHalFuncs { 131 void *priv; /* private state */ 132 133 void (*rfDetach)(struct ath_hal *ah); 134 void (*writeRegs)(struct ath_hal *, 135 u_int modeIndex, u_int freqIndex, int regWrites); 136 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 137 HAL_BOOL (*setChannel)(struct ath_hal *, 138 const struct ieee80211_channel *); 139 HAL_BOOL (*setRfRegs)(struct ath_hal *, 140 const struct ieee80211_channel *, uint16_t modesIndex, 141 uint16_t *rfXpdGain); 142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143 int16_t *minPower, int16_t *maxPower, 144 const struct ieee80211_channel *, uint16_t *rfXpdGain); 145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 146 const struct ieee80211_channel *, 147 int16_t *maxPow, int16_t *minPow); 148 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 149} RF_HAL_FUNCS; 150 151struct ar5212AniParams { 152 int maxNoiseImmunityLevel; /* [0..4] */ 153 int totalSizeDesired[5]; 154 int coarseHigh[5]; 155 int coarseLow[5]; 156 int firpwr[5]; 157 158 int maxSpurImmunityLevel; /* [0..7] */ 159 int cycPwrThr1[8]; 160 161 int maxFirstepLevel; /* [0..2] */ 162 int firstep[3]; 163 164 uint32_t ofdmTrigHigh; 165 uint32_t ofdmTrigLow; 166 uint32_t cckTrigHigh; 167 uint32_t cckTrigLow; 168 int32_t rssiThrLow; 169 uint32_t rssiThrHigh; 170 171 int period; /* update listen period */ 172 173 /* NB: intentionally ordered so data exported to user space is first */ 174 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 175 uint32_t cckPhyErrBase; /* Base value for cck err counters */ 176}; 177 178/* 179 * Per-channel ANI state private to the driver. 180 */ 181struct ar5212AniState { 182 uint8_t noiseImmunityLevel; 183 uint8_t spurImmunityLevel; 184 uint8_t firstepLevel; 185 uint8_t ofdmWeakSigDetectOff; 186 uint8_t cckWeakSigThreshold; 187 uint32_t listenTime; 188 189 /* NB: intentionally ordered so data exported to user space is first */ 190 uint32_t txFrameCount; /* Last txFrameCount */ 191 uint32_t rxFrameCount; /* Last rx Frame count */ 192 uint32_t cycleCount; /* Last cycleCount 193 (to detect wrap-around) */ 194 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 195 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 196 197 const struct ar5212AniParams *params; 198}; 199 200#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 201#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 202 203#if 0 204struct ar5212Stats { 205 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 206 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 207 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 208 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 209 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 210 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 211 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 212 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 213 uint32_t ast_ani_stepup; /* ANI increased first step level */ 214 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 215 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 216 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 217 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 218 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 219 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 220 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 221 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 222}; 223#endif 224 225/* 226 * NF Cal history buffer 227 */ 228#define AR5212_CCA_MAX_GOOD_VALUE -95 229#define AR5212_CCA_MAX_HIGH_VALUE -62 230#define AR5212_CCA_MIN_BAD_VALUE -125 231 232#define AR512_NF_CAL_HIST_MAX 5 233 234struct ar5212NfCalHist { 235 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 236 int16_t privNF; 237 uint8_t currIndex; 238 uint8_t first_run; 239 uint8_t invalidNFcount; 240}; 241 242struct ath_hal_5212 { 243 struct ath_hal_private ah_priv; /* base class */ 244 245 /* 246 * Per-chip common Initialization data. 247 * NB: RF backends have their own ini data. 248 */ 249 HAL_INI_ARRAY ah_ini_modes; 250 HAL_INI_ARRAY ah_ini_common; 251 252 GAIN_VALUES ah_gainValues; 253 254 uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 255 uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 256 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 257 uint16_t ah_assocId; 258 259 /* 260 * Runtime state. 261 */ 262 uint32_t ah_maskReg; /* copy of AR_IMR */ 263 HAL_ANI_STATS ah_stats; /* various statistics */ 264 RF_HAL_FUNCS *ah_rfHal; 265 uint32_t ah_txDescMask; /* mask for TXDESC */ 266 uint32_t ah_txOkInterruptMask; 267 uint32_t ah_txErrInterruptMask; 268 uint32_t ah_txDescInterruptMask; 269 uint32_t ah_txEolInterruptMask; 270 uint32_t ah_txUrnInterruptMask; 271 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 272 uint32_t ah_intrTxqs; /* tx q interrupt state */ 273 /* decomp mask array */ 274 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 275 HAL_ANT_SETTING ah_antControl; /* antenna setting */ 276 HAL_BOOL ah_diversity; /* fast diversity setting */ 277 enum { 278 IQ_CAL_INACTIVE, 279 IQ_CAL_RUNNING, 280 IQ_CAL_DONE 281 } ah_bIQCalibration; /* IQ calibrate state */ 282 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 283 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 284 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 285 uint32_t ah_miscMode; /* MISC_MODE settings */ 286 uint32_t ah_rssiThr; /* RSSI_THR settings */ 287 HAL_BOOL ah_cwCalRequire; /* for ap51 */ 288 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 289 HAL_BOOL ah_phyPowerOn; /* PHY power state */ 290 HAL_BOOL ah_isHb63; /* cached HB63 check */ 291 uint32_t ah_macTPC; /* tpc register */ 292 uint32_t ah_beaconInterval; /* XXX */ 293 enum { 294 AUTO_32KHZ, /* use it if 32kHz crystal present */ 295 USE_32KHZ, /* do it regardless */ 296 DONT_USE_32KHZ, /* don't use it regardless */ 297 } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 298 uint32_t ah_ofdmTxPower; 299 int16_t ah_txPowerIndexOffset; 300 /* 301 * Noise floor cal histogram support. 302 */ 303 struct ar5212NfCalHist ah_nfCalHist; 304 305 u_int ah_slottime; /* user-specified slot time */ 306 u_int ah_acktimeout; /* user-specified ack timeout */ 307 u_int ah_ctstimeout; /* user-specified cts timeout */ 308 u_int ah_sifstime; /* user-specified sifs time */ 309 /* 310 * RF Silent handling; setup according to the EEPROM. 311 */ 312 uint32_t ah_gpioSelect; /* GPIO pin to use */ 313 uint32_t ah_polarity; /* polarity to disable RF */ 314 uint32_t ah_gpioBit; /* after init, prev value */ 315 /* 316 * ANI support. 317 */ 318 uint32_t ah_procPhyErr; /* Process Phy errs */ 319 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 320 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 321 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 322 struct ar5212AniState *ah_curani; /* cached last reference */ 323 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 324 325 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 326 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 327 328 /* 329 * Transmit power state. Note these are maintained 330 * here so they can be retrieved by diagnostic tools. 331 */ 332 uint16_t *ah_pcdacTable; 333 u_int ah_pcdacTableSize; 334 uint16_t ah_ratesArray[37]; 335 336 uint8_t ah_txTrigLev; /* current Tx trigger level */ 337 uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 338 339 /* 340 * Channel Tx, Rx, Rx Clear State 341 */ 342 uint32_t ah_cycleCount; 343 uint32_t ah_ctlBusy; 344 uint32_t ah_rxBusy; 345 uint32_t ah_txBusy; 346 uint32_t ah_rx_chainmask; 347 uint32_t ah_tx_chainmask; 348 349 /* Used to return ANI statistics to the diagnostic API */ 350 HAL_ANI_STATS ext_ani_stats; 351}; 352#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 353 354/* 355 * IS_XXXX macros test the MAC version 356 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 357 * 358 * Some single chip radios have equivalent radio/RF (e.g. 5112) 359 * for those use IS_RADXXX_ANY macros. 360 */ 361#define IS_2317(ah) \ 362 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 363 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 364#define IS_2316(ah) \ 365 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 366#define IS_2413(ah) \ 367 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 368#define IS_5424(ah) \ 369 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 370 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 371 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 372#define IS_5413(ah) \ 373 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 374#define IS_2425(ah) \ 375 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 376#define IS_2417(ah) \ 377 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 378#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 379 380#define AH_RADIO_MAJOR(ah) \ 381 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 382#define AH_RADIO_MINOR(ah) \ 383 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 384#define IS_RAD5111(ah) \ 385 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 386 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 387#define IS_RAD5112(ah) \ 388 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 389 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 390/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 391#define IS_RAD5112_ANY(ah) \ 392 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 393 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 394#define IS_RAD5112_REV1(ah) \ 395 (IS_RAD5112(ah) && \ 396 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 397#define IS_RADX112_REV2(ah) \ 398 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 399 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 400 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 401 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 402 403#define ar5212RfDetach(ah) do { \ 404 if (AH5212(ah)->ah_rfHal != AH_NULL) \ 405 AH5212(ah)->ah_rfHal->rfDetach(ah); \ 406} while (0) 407#define ar5212GetRfBank(ah, b) \ 408 AH5212(ah)->ah_rfHal->getRfBank(ah, b) 409 410/* 411 * Hack macros for Nala/San: 11b is handled 412 * using 11g; flip the channel flags to accomplish this. 413 */ 414#define SAVE_CCK(_ah, _chan, _flag) do { \ 415 if ((IS_2425(_ah) || IS_2417(_ah)) && \ 416 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 417 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 418 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 419 (_flag) = AH_TRUE; \ 420 } else \ 421 (_flag) = AH_FALSE; \ 422} while (0) 423#define RESTORE_CCK(_ah, _chan, _flag) do { \ 424 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 425 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 426 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 427 } \ 428} while (0) 429 430struct ath_hal; 431 432extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 433extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 434 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 435extern void ar5212Detach(struct ath_hal *ah); 436extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 437extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 438 uint16_t flags, uint16_t *low, uint16_t *high); 439extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 440 441extern void ar5212SetBeaconTimers(struct ath_hal *ah, 442 const HAL_BEACON_TIMERS *); 443extern void ar5212BeaconInit(struct ath_hal *ah, 444 uint32_t next_beacon, uint32_t beacon_period); 445extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 446extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 447 const HAL_BEACON_STATE *); 448extern uint64_t ar5212GetNextTBTT(struct ath_hal *); 449 450extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 451extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 452extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 453extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 454 455extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 456extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 457extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 458extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 459 uint16_t entry, const uint8_t *mac); 460extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 461 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 462 463extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 464extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 465extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 466extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 467extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 468extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 469extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 470 uint16_t regDomain, HAL_STATUS *stats); 471extern u_int ar5212GetWirelessModes(struct ath_hal *ah); 472extern void ar5212EnableRfKill(struct ath_hal *); 473extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 474 HAL_GPIO_MUX_TYPE); 475extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 476extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 477extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 478extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 479extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 480extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 481 uint16_t assocId); 482extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 483extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 484extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 485extern void ar5212ResetTsf(struct ath_hal *ah); 486extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 487extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 488extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 489extern void ar5212EnableMibCounters(struct ath_hal *); 490extern void ar5212DisableMibCounters(struct ath_hal *); 491extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 492extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 493extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 494extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 495extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 496extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 497extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 498extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 499extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 500extern u_int ar5212GetSifsTime(struct ath_hal *); 501extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 502extern u_int ar5212GetSlotTime(struct ath_hal *); 503extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 504extern u_int ar5212GetAckTimeout(struct ath_hal *); 505extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 506extern u_int ar5212GetAckCTSRate(struct ath_hal *); 507extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 508extern u_int ar5212GetCTSTimeout(struct ath_hal *); 509extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 510void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 511extern void ar5212SetPCUConfig(struct ath_hal *); 512extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 513extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 514extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 515extern int16_t ar5212GetNfAdjust(struct ath_hal *, 516 const HAL_CHANNEL_INTERNAL *); 517extern void ar5212SetCompRegs(struct ath_hal *ah); 518extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 519 uint32_t, uint32_t *); 520extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 521 uint32_t, uint32_t, HAL_STATUS *); 522extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 523 const void *args, uint32_t argsize, 524 void **result, uint32_t *resultsize); 525extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 526 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 527extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *, 528 HAL_SURVEY_SAMPLE *); 529extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 530 531extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 532 int setChip); 533extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 534extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 535 536extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE); 537extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE); 538extern void ar5212EnableReceive(struct ath_hal *ah); 539extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 540extern void ar5212StartPcuReceive(struct ath_hal *ah); 541extern void ar5212StopPcuReceive(struct ath_hal *ah); 542extern void ar5212SetMulticastFilter(struct ath_hal *ah, 543 uint32_t filter0, uint32_t filter1); 544extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 545extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 546extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 547extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 548extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 549 struct ath_desc *, uint32_t size, u_int flags); 550extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 551 uint32_t, struct ath_desc *, uint64_t, 552 struct ath_rx_status *); 553 554extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 555 struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 556 HAL_RESET_TYPE, HAL_STATUS *status); 557extern HAL_BOOL ar5212SetChannel(struct ath_hal *, 558 const struct ieee80211_channel *); 559extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 560extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 561extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 562extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 563 const struct ieee80211_channel *); 564extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 565 struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 566extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 567 struct ieee80211_channel *chan, u_int chainMask, 568 HAL_BOOL longCal, HAL_BOOL *isCalDone); 569extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 570 const struct ieee80211_channel *); 571extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 572extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 573extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 574extern void ar5212SetSpurMitigation(struct ath_hal *, 575 const struct ieee80211_channel *); 576extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 577 HAL_ANT_SETTING settings, const struct ieee80211_channel *); 578extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 579extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 580 struct ieee80211_channel *chan); 581extern void ar5212InitializeGainValues(struct ath_hal *); 582extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 583extern void ar5212RequestRfgain(struct ath_hal *); 584 585extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 586 HAL_BOOL IncTrigLevel); 587extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 588 const HAL_TXQ_INFO *qInfo); 589extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 590 HAL_TXQ_INFO *qInfo); 591extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 592 const HAL_TXQ_INFO *qInfo); 593extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 594extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 595extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 596extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 597extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 598extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 599extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 600extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 601 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 602 u_int txRate0, u_int txTries0, 603 u_int keyIx, u_int antMode, u_int flags, 604 u_int rtsctsRate, u_int rtsctsDuration, 605 u_int compicvLen, u_int compivLen, u_int comp); 606extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 607 u_int txRate1, u_int txRetries1, 608 u_int txRate2, u_int txRetries2, 609 u_int txRate3, u_int txRetries3); 610extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 611 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 612 u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 613 const struct ath_desc *ds0); 614extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 615 struct ath_desc *, struct ath_tx_status *); 616extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 617extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 618extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 619 const struct ath_desc *ds0, int *rates, int *tries); 620extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, 621 uint32_t link); 622extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, 623 uint32_t *link); 624extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 625 uint32_t **linkptr); 626 627extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 628 629extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 630 const struct ar5212AniParams *, HAL_BOOL ena); 631extern void ar5212AniDetach(struct ath_hal *); 632extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 633extern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *); 634extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 635extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 636 const struct ar5212AniParams *, const struct ar5212AniParams *); 637struct ath_rx_status; 638extern void ar5212AniPhyErrReport(struct ath_hal *ah, 639 const struct ath_rx_status *rs); 640extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 641extern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 642 const struct ieee80211_channel *); 643extern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 644extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 645 HAL_OPMODE, int); 646 647extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 648extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 649extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 650extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah, 651 HAL_PHYERR_PARAM *pe); 652extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 653extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 654 struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 655 HAL_DFS_EVENT *event); 656extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 657extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 658 659#endif /* _ATH_AR5212_H_ */ 660