ar5212.h revision 225444
1263646Sbapt/* 2263646Sbapt * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3263646Sbapt * Copyright (c) 2002-2008 Atheros Communications, Inc. 4263646Sbapt * 5263646Sbapt * Permission to use, copy, modify, and/or distribute this software for any 6263646Sbapt * purpose with or without fee is hereby granted, provided that the above 7263646Sbapt * copyright notice and this permission notice appear in all copies. 8263646Sbapt * 9263646Sbapt * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10263646Sbapt * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11263646Sbapt * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12263646Sbapt * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13263646Sbapt * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14263646Sbapt * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15263646Sbapt * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16263646Sbapt * 17263646Sbapt * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212.h 225444 2011-09-08 01:23:05Z adrian $ 18263646Sbapt */ 19263646Sbapt#ifndef _ATH_AR5212_H_ 20263646Sbapt#define _ATH_AR5212_H_ 21263646Sbapt 22263646Sbapt#include "ah_eeprom.h" 23263646Sbapt 24263646Sbapt#define AR5212_MAGIC 0x19541014 25263646Sbapt 26263646Sbapt/* DCU Transmit Filter macros */ 27263646Sbapt#define CALC_MMR(dcu, idx) \ 28263646Sbapt ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29263646Sbapt#define TXBLK_FROM_MMR(mmr) \ 30263646Sbapt (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31263646Sbapt#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32263646Sbapt#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33263646Sbapt 34263646Sbapt/* MAC register values */ 35263646Sbapt 36263646Sbapt#define INIT_INTERRUPT_MASK \ 37263646Sbapt ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38263646Sbapt AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39263646Sbapt AR_IMR_HIUERR ) 40263646Sbapt#define INIT_BEACON_CONTROL \ 41263646Sbapt ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42263646Sbapt (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43264789Sbapt 44264789Sbapt#define INIT_CONFIG_STATUS 0x00000000 45263646Sbapt#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46298166Sbapt#define INIT_IQCAL_LOG_COUNT_MAX 0xF 47298166Sbapt#define INIT_BCON_CNTRL_REG 0x00000000 48263646Sbapt 49263646Sbapt#define INIT_USEC 40 50263646Sbapt#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51263646Sbapt#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52263646Sbapt 53263646Sbapt#define RX_NON_FULL_RATE_LATENCY 63 54264789Sbapt#define TX_HALF_RATE_LATENCY 108 55263646Sbapt#define TX_QUARTER_RATE_LATENCY 216 56263646Sbapt 57263646Sbapt#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58263646Sbapt#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59263646Sbapt#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60263646Sbapt#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61263646Sbapt#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62263646Sbapt#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63263646Sbapt 64263646Sbapt#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65263646Sbapt 66263646Sbapt/* Tx frame start to tx data start delay */ 67263646Sbapt#define TX_FRAME_D_START_HALF_RATE 0xc 68263646Sbapt#define TX_FRAME_D_START_QUARTER_RATE 0xd 69263646Sbapt 70263646Sbapt/* 71264789Sbapt * Various fifo fill before Tx start, in 64-byte units 72307790Sbapt * i.e. put the frame in the air while still DMAing 73263646Sbapt */ 74264789Sbapt#define MIN_TX_FIFO_THRESHOLD 0x1 75264789Sbapt#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76263646Sbapt#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77264789Sbapt 78263646Sbapt#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79263646Sbapt 80263646Sbapt/* 81307790Sbapt * Gain support. 82307790Sbapt */ 83307790Sbapt#define NUM_CORNER_FIX_BITS 4 84307790Sbapt#define NUM_CORNER_FIX_BITS_5112 7 85307790Sbapt#define DYN_ADJ_UP_MARGIN 15 86307790Sbapt#define DYN_ADJ_LO_MARGIN 20 87263646Sbapt#define PHY_PROBE_CCK_CORRECTION 5 88307790Sbapt#define CCK_OFDM_GAIN_DELTA 15 89307790Sbapt 90307790Sbaptenum GAIN_PARAMS { 91263646Sbapt GP_TXCLIP, 92263646Sbapt GP_PD90, 93263646Sbapt GP_PD84, 94264789Sbapt GP_GSEL, 95263646Sbapt}; 96263646Sbapt 97263646Sbaptenum GAIN_PARAMS_5112 { 98263646Sbapt GP_MIXGAIN_OVR, 99263646Sbapt GP_PWD_138, 100263646Sbapt GP_PWD_137, 101263646Sbapt GP_PWD_136, 102264789Sbapt GP_PWD_132, 103264789Sbapt GP_PWD_131, 104298166Sbapt GP_PWD_130, 105298166Sbapt}; 106263646Sbapt 107264789Sbapttypedef struct _gainOptStep { 108263646Sbapt int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109263646Sbapt int32_t stepGain; 110263646Sbapt int8_t stepName[16]; 111298166Sbapt} GAIN_OPTIMIZATION_STEP; 112298166Sbapt 113263646Sbapttypedef struct { 114263646Sbapt uint32_t numStepsInLadder; 115263646Sbapt uint32_t defaultStepNum; 116263646Sbapt GAIN_OPTIMIZATION_STEP optStep[10]; 117298166Sbapt} GAIN_OPTIMIZATION_LADDER; 118298166Sbapt 119263646Sbapttypedef struct { 120263646Sbapt uint32_t currStepNum; 121263646Sbapt uint32_t currGain; 122263646Sbapt uint32_t targetGain; 123263646Sbapt uint32_t loTrig; 124263646Sbapt uint32_t hiTrig; 125263646Sbapt uint32_t active; 126263646Sbapt const GAIN_OPTIMIZATION_STEP *currStep; 127263646Sbapt} GAIN_VALUES; 128298166Sbapt 129263646Sbapt/* RF HAL structures */ 130263646Sbapttypedef struct RfHalFuncs { 131263646Sbapt void *priv; /* private state */ 132263646Sbapt 133263646Sbapt void (*rfDetach)(struct ath_hal *ah); 134263646Sbapt void (*writeRegs)(struct ath_hal *, 135263646Sbapt u_int modeIndex, u_int freqIndex, int regWrites); 136263646Sbapt uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 137263646Sbapt HAL_BOOL (*setChannel)(struct ath_hal *, 138263646Sbapt const struct ieee80211_channel *); 139263646Sbapt HAL_BOOL (*setRfRegs)(struct ath_hal *, 140264789Sbapt const struct ieee80211_channel *, uint16_t modesIndex, 141264789Sbapt uint16_t *rfXpdGain); 142298166Sbapt HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143298166Sbapt int16_t *minPower, int16_t *maxPower, 144263646Sbapt const struct ieee80211_channel *, uint16_t *rfXpdGain); 145264789Sbapt HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 146263646Sbapt const const struct ieee80211_channel *, 147263646Sbapt int16_t *maxPow, int16_t *minPow); 148263646Sbapt int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 149263646Sbapt} RF_HAL_FUNCS; 150263646Sbapt 151298166Sbaptstruct ar5212AniParams { 152263646Sbapt int maxNoiseImmunityLevel; /* [0..4] */ 153263646Sbapt int totalSizeDesired[5]; 154263646Sbapt int coarseHigh[5]; 155298166Sbapt int coarseLow[5]; 156298166Sbapt int firpwr[5]; 157263646Sbapt 158298166Sbapt int maxSpurImmunityLevel; /* [0..7] */ 159298166Sbapt int cycPwrThr1[8]; 160263646Sbapt 161263646Sbapt int maxFirstepLevel; /* [0..2] */ 162263646Sbapt int firstep[3]; 163263646Sbapt 164263646Sbapt uint32_t ofdmTrigHigh; 165263646Sbapt uint32_t ofdmTrigLow; 166263646Sbapt uint32_t cckTrigHigh; 167263646Sbapt uint32_t cckTrigLow; 168263646Sbapt int32_t rssiThrLow; 169263646Sbapt uint32_t rssiThrHigh; 170263646Sbapt 171263646Sbapt int period; /* update listen period */ 172263646Sbapt 173263646Sbapt /* NB: intentionally ordered so data exported to user space is first */ 174263646Sbapt uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 175263646Sbapt uint32_t cckPhyErrBase; /* Base value for cck err counters */ 176263646Sbapt}; 177263646Sbapt 178263646Sbapt/* 179263646Sbapt * Per-channel ANI state private to the driver. 180263646Sbapt */ 181263646Sbaptstruct ar5212AniState { 182263646Sbapt uint8_t noiseImmunityLevel; 183263646Sbapt uint8_t spurImmunityLevel; 184263646Sbapt uint8_t firstepLevel; 185263646Sbapt uint8_t ofdmWeakSigDetectOff; 186263646Sbapt uint8_t cckWeakSigThreshold; 187263646Sbapt uint32_t listenTime; 188263646Sbapt 189263646Sbapt /* NB: intentionally ordered so data exported to user space is first */ 190263646Sbapt uint32_t txFrameCount; /* Last txFrameCount */ 191263646Sbapt uint32_t rxFrameCount; /* Last rx Frame count */ 192263646Sbapt uint32_t cycleCount; /* Last cycleCount 193263646Sbapt (to detect wrap-around) */ 194263646Sbapt uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 195263646Sbapt uint32_t cckPhyErrCount; /* CCK err count since last reset */ 196263646Sbapt 197263646Sbapt const struct ar5212AniParams *params; 198263646Sbapt}; 199263646Sbapt 200263646Sbapt#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 201263646Sbapt#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 202263646Sbapt 203263646Sbaptstruct ar5212Stats { 204263646Sbapt uint32_t ast_ani_niup; /* ANI increased noise immunity */ 205263646Sbapt uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 206263646Sbapt uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 207263646Sbapt uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 208263646Sbapt uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 209263646Sbapt uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 210263646Sbapt uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 211263646Sbapt uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 212263646Sbapt uint32_t ast_ani_stepup; /* ANI increased first step level */ 213307790Sbapt uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 214307790Sbapt uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 215263646Sbapt uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 216298166Sbapt uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 217307790Sbapt uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 218307790Sbapt uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 219307790Sbapt HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 220307790Sbapt HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 221307790Sbapt}; 222307790Sbapt 223307790Sbapt/* 224263646Sbapt * NF Cal history buffer 225263646Sbapt */ 226263646Sbapt#define AR5212_CCA_MAX_GOOD_VALUE -95 227263646Sbapt#define AR5212_CCA_MAX_HIGH_VALUE -62 228263646Sbapt#define AR5212_CCA_MIN_BAD_VALUE -125 229298166Sbapt 230298166Sbapt#define AR512_NF_CAL_HIST_MAX 5 231263646Sbapt 232263646Sbaptstruct ar5212NfCalHist { 233263646Sbapt int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 234263646Sbapt int16_t privNF; 235263646Sbapt uint8_t currIndex; 236263646Sbapt uint8_t first_run; 237263646Sbapt uint8_t invalidNFcount; 238263646Sbapt}; 239298166Sbapt 240298166Sbaptstruct ath_hal_5212 { 241298166Sbapt struct ath_hal_private ah_priv; /* base class */ 242263646Sbapt 243263646Sbapt /* 244263646Sbapt * Per-chip common Initialization data. 245298166Sbapt * NB: RF backends have their own ini data. 246298166Sbapt */ 247307790Sbapt HAL_INI_ARRAY ah_ini_modes; 248263646Sbapt HAL_INI_ARRAY ah_ini_common; 249263646Sbapt 250263646Sbapt GAIN_VALUES ah_gainValues; 251263646Sbapt 252263646Sbapt uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 253263646Sbapt uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 254263646Sbapt uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 255263646Sbapt 256263646Sbapt /* 257263646Sbapt * Runtime state. 258263646Sbapt */ 259263646Sbapt uint32_t ah_maskReg; /* copy of AR_IMR */ 260263646Sbapt struct ar5212Stats ah_stats; /* various statistics */ 261263646Sbapt RF_HAL_FUNCS *ah_rfHal; 262298166Sbapt uint32_t ah_txDescMask; /* mask for TXDESC */ 263298166Sbapt uint32_t ah_txOkInterruptMask; 264263646Sbapt uint32_t ah_txErrInterruptMask; 265263646Sbapt uint32_t ah_txDescInterruptMask; 266263646Sbapt uint32_t ah_txEolInterruptMask; 267263646Sbapt uint32_t ah_txUrnInterruptMask; 268263646Sbapt HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 269263646Sbapt uint32_t ah_intrTxqs; /* tx q interrupt state */ 270263646Sbapt /* decomp mask array */ 271263646Sbapt uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 272263646Sbapt HAL_POWER_MODE ah_powerMode; 273263646Sbapt HAL_ANT_SETTING ah_antControl; /* antenna setting */ 274298166Sbapt HAL_BOOL ah_diversity; /* fast diversity setting */ 275298166Sbapt enum { 276263646Sbapt IQ_CAL_INACTIVE, 277263646Sbapt IQ_CAL_RUNNING, 278263646Sbapt IQ_CAL_DONE 279263646Sbapt } ah_bIQCalibration; /* IQ calibrate state */ 280263646Sbapt HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 281263646Sbapt uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 282263646Sbapt uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 283263646Sbapt uint32_t ah_miscMode; /* MISC_MODE settings */ 284263646Sbapt uint32_t ah_rssiThr; /* RSSI_THR settings */ 285263646Sbapt HAL_BOOL ah_cwCalRequire; /* for ap51 */ 286263646Sbapt HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 287263646Sbapt HAL_BOOL ah_phyPowerOn; /* PHY power state */ 288263646Sbapt HAL_BOOL ah_isHb63; /* cached HB63 check */ 289263646Sbapt uint32_t ah_macTPC; /* tpc register */ 290263646Sbapt uint32_t ah_beaconInterval; /* XXX */ 291264789Sbapt enum { 292264789Sbapt AUTO_32KHZ, /* use it if 32kHz crystal present */ 293263646Sbapt USE_32KHZ, /* do it regardless */ 294264789Sbapt DONT_USE_32KHZ, /* don't use it regardless */ 295263646Sbapt } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 296263646Sbapt uint32_t ah_ofdmTxPower; 297263646Sbapt int16_t ah_txPowerIndexOffset; 298263646Sbapt /* 299263646Sbapt * Noise floor cal histogram support. 300298166Sbapt */ 301263646Sbapt struct ar5212NfCalHist ah_nfCalHist; 302263646Sbapt 303263646Sbapt u_int ah_slottime; /* user-specified slot time */ 304263646Sbapt u_int ah_acktimeout; /* user-specified ack timeout */ 305263646Sbapt u_int ah_ctstimeout; /* user-specified cts timeout */ 306263646Sbapt u_int ah_sifstime; /* user-specified sifs time */ 307263646Sbapt /* 308263646Sbapt * RF Silent handling; setup according to the EEPROM. 309263646Sbapt */ 310263646Sbapt uint32_t ah_gpioSelect; /* GPIO pin to use */ 311263646Sbapt uint32_t ah_polarity; /* polarity to disable RF */ 312263646Sbapt uint32_t ah_gpioBit; /* after init, prev value */ 313263646Sbapt /* 314263646Sbapt * ANI support. 315263646Sbapt */ 316263646Sbapt uint32_t ah_procPhyErr; /* Process Phy errs */ 317263646Sbapt HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 318263646Sbapt struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 319263646Sbapt struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 320263646Sbapt struct ar5212AniState *ah_curani; /* cached last reference */ 321263646Sbapt struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 322298166Sbapt 323263646Sbapt /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 324263646Sbapt HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 325263646Sbapt 326263646Sbapt /* 327263646Sbapt * Transmit power state. Note these are maintained 328263646Sbapt * here so they can be retrieved by diagnostic tools. 329263646Sbapt */ 330263646Sbapt uint16_t *ah_pcdacTable; 331263646Sbapt u_int ah_pcdacTableSize; 332263646Sbapt uint16_t ah_ratesArray[37]; 333263646Sbapt 334263646Sbapt uint8_t ah_txTrigLev; /* current Tx trigger level */ 335263646Sbapt uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 336263646Sbapt}; 337263646Sbapt#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 338298166Sbapt 339263646Sbapt/* 340263646Sbapt * IS_XXXX macros test the MAC version 341263646Sbapt * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 342263646Sbapt * 343263646Sbapt * Some single chip radios have equivalent radio/RF (e.g. 5112) 344263646Sbapt * for those use IS_RADXXX_ANY macros. 345263646Sbapt */ 346263646Sbapt#define IS_2317(ah) \ 347263646Sbapt ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 348263646Sbapt (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 349263646Sbapt#define IS_2316(ah) \ 350263646Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 351263646Sbapt#define IS_2413(ah) \ 352263646Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 353263646Sbapt#define IS_5424(ah) \ 354263646Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 355263646Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 356263646Sbapt AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 357264789Sbapt#define IS_5413(ah) \ 358264789Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 359263646Sbapt#define IS_2425(ah) \ 360264789Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 361263646Sbapt#define IS_2417(ah) \ 362263646Sbapt ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 363263646Sbapt#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 364264789Sbapt 365263646Sbapt#define AH_RADIO_MAJOR(ah) \ 366264789Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 367263646Sbapt#define AH_RADIO_MINOR(ah) \ 368298166Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 369263646Sbapt#define IS_RAD5111(ah) \ 370263646Sbapt (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 371263646Sbapt AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 372263646Sbapt#define IS_RAD5112(ah) \ 373263646Sbapt (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 374263646Sbapt AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 375263646Sbapt/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 376263646Sbapt#define IS_RAD5112_ANY(ah) \ 377263646Sbapt (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 378263646Sbapt AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 379263646Sbapt#define IS_RAD5112_REV1(ah) \ 380263646Sbapt (IS_RAD5112(ah) && \ 381263646Sbapt AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 382263646Sbapt#define IS_RADX112_REV2(ah) \ 383263646Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 384263646Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 385263646Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 386263646Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 387263646Sbapt 388263646Sbapt#define ar5212RfDetach(ah) do { \ 389263646Sbapt if (AH5212(ah)->ah_rfHal != AH_NULL) \ 390263646Sbapt AH5212(ah)->ah_rfHal->rfDetach(ah); \ 391264789Sbapt} while (0) 392263646Sbapt#define ar5212GetRfBank(ah, b) \ 393263646Sbapt AH5212(ah)->ah_rfHal->getRfBank(ah, b) 394263646Sbapt 395263646Sbapt/* 396263646Sbapt * Hack macros for Nala/San: 11b is handled 397263646Sbapt * using 11g; flip the channel flags to accomplish this. 398263646Sbapt */ 399263646Sbapt#define SAVE_CCK(_ah, _chan, _flag) do { \ 400263646Sbapt if ((IS_2425(_ah) || IS_2417(_ah)) && \ 401263646Sbapt (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 402263646Sbapt (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 403263646Sbapt (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 404263646Sbapt (_flag) = AH_TRUE; \ 405263646Sbapt } else \ 406263646Sbapt (_flag) = AH_FALSE; \ 407263646Sbapt} while (0) 408263646Sbapt#define RESTORE_CCK(_ah, _chan, _flag) do { \ 409264789Sbapt if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 410263646Sbapt (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 411263646Sbapt (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 412263646Sbapt } \ 413263646Sbapt} while (0) 414263646Sbapt 415263646Sbaptstruct ath_hal; 416264789Sbapt 417263646Sbaptextern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 418263646Sbaptextern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 419263646Sbapt HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 420263646Sbaptextern void ar5212Detach(struct ath_hal *ah); 421263646Sbaptextern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 422263646Sbaptextern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 423263646Sbapt uint16_t flags, uint16_t *low, uint16_t *high); 424263646Sbaptextern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 425263646Sbapt 426263646Sbaptextern void ar5212SetBeaconTimers(struct ath_hal *ah, 427263646Sbapt const HAL_BEACON_TIMERS *); 428264789Sbaptextern void ar5212BeaconInit(struct ath_hal *ah, 429263646Sbapt uint32_t next_beacon, uint32_t beacon_period); 430263646Sbaptextern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 431263646Sbaptextern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 432263646Sbapt const HAL_BEACON_STATE *); 433263646Sbaptextern uint64_t ar5212GetNextTBTT(struct ath_hal *); 434264789Sbapt 435263646Sbaptextern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 436263646Sbaptextern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 437263646Sbaptextern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 438264789Sbaptextern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 439263646Sbapt 440263646Sbaptextern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 441263646Sbaptextern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 442298166Sbaptextern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 443263646Sbaptextern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 444263646Sbapt uint16_t entry, const uint8_t *mac); 445263646Sbaptextern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 446263646Sbapt const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 447263646Sbapt 448263646Sbaptextern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 449263646Sbaptextern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 450263646Sbaptextern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 451263646Sbaptextern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 452263646Sbaptextern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 453263646Sbaptextern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 454263646Sbaptextern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 455263646Sbapt uint16_t regDomain, HAL_STATUS *stats); 456263646Sbaptextern u_int ar5212GetWirelessModes(struct ath_hal *ah); 457263646Sbaptextern void ar5212EnableRfKill(struct ath_hal *); 458263646Sbaptextern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 459263646Sbapt HAL_GPIO_MUX_TYPE); 460263646Sbaptextern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 461263646Sbaptextern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 462263646Sbaptextern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 463263646Sbaptextern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 464263646Sbaptextern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 465263646Sbaptextern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 466263646Sbapt uint16_t assocId); 467263646Sbaptextern uint32_t ar5212GetTsf32(struct ath_hal *ah); 468263646Sbaptextern uint64_t ar5212GetTsf64(struct ath_hal *ah); 469263646Sbaptextern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 470263646Sbaptextern void ar5212ResetTsf(struct ath_hal *ah); 471264789Sbaptextern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 472264789Sbaptextern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 473298166Sbaptextern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 474298166Sbaptextern void ar5212EnableMibCounters(struct ath_hal *); 475263646Sbaptextern void ar5212DisableMibCounters(struct ath_hal *); 476264789Sbaptextern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 477263646Sbaptextern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 478263646Sbaptextern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 479263646Sbaptextern u_int ar5212GetDefAntenna(struct ath_hal *ah); 480263646Sbaptextern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 481279549Sbaptextern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 482263646Sbaptextern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 483298166Sbaptextern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 484263646Sbaptextern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 485263646Sbaptextern u_int ar5212GetSifsTime(struct ath_hal *); 486279549Sbaptextern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 487298166Sbaptextern u_int ar5212GetSlotTime(struct ath_hal *); 488263646Sbaptextern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 489298166Sbaptextern u_int ar5212GetAckTimeout(struct ath_hal *); 490298166Sbaptextern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 491279549Sbaptextern u_int ar5212GetAckCTSRate(struct ath_hal *); 492263646Sbaptextern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 493263646Sbaptextern u_int ar5212GetCTSTimeout(struct ath_hal *); 494263646Sbaptextern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 495263646Sbaptvoid ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 496263646Sbaptextern void ar5212SetPCUConfig(struct ath_hal *); 497263646Sbaptextern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 498263646Sbaptextern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 499263646Sbaptextern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 500263646Sbaptextern int16_t ar5212GetNfAdjust(struct ath_hal *, 501298166Sbapt const HAL_CHANNEL_INTERNAL *); 502298166Sbaptextern void ar5212SetCompRegs(struct ath_hal *ah); 503298166Sbaptextern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 504263646Sbapt uint32_t, uint32_t *); 505263646Sbaptextern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 506263646Sbapt uint32_t, uint32_t, HAL_STATUS *); 507263646Sbaptextern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 508263646Sbapt const void *args, uint32_t argsize, 509263646Sbapt void **result, uint32_t *resultsize); 510263646Sbaptextern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 511263646Sbapt uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 512263646Sbapt 513263646Sbaptextern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 514263646Sbapt int setChip); 515263646Sbaptextern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 516263646Sbaptextern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 517263646Sbapt 518263646Sbaptextern uint32_t ar5212GetRxDP(struct ath_hal *ath); 519263646Sbaptextern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp); 520263646Sbaptextern void ar5212EnableReceive(struct ath_hal *ah); 521263646Sbaptextern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 522263646Sbaptextern void ar5212StartPcuReceive(struct ath_hal *ah); 523263646Sbaptextern void ar5212StopPcuReceive(struct ath_hal *ah); 524263646Sbaptextern void ar5212SetMulticastFilter(struct ath_hal *ah, 525263646Sbapt uint32_t filter0, uint32_t filter1); 526263646Sbaptextern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 527263646Sbaptextern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 528263646Sbaptextern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 529263646Sbaptextern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 530263646Sbaptextern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 531263646Sbapt struct ath_desc *, uint32_t size, u_int flags); 532263646Sbaptextern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 533263646Sbapt uint32_t, struct ath_desc *, uint64_t, 534263646Sbapt struct ath_rx_status *); 535263646Sbapt 536263646Sbaptextern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 537263646Sbapt struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 538263646Sbapt HAL_STATUS *status); 539263646Sbaptextern HAL_BOOL ar5212SetChannel(struct ath_hal *, 540263646Sbapt const struct ieee80211_channel *); 541263646Sbaptextern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 542263646Sbaptextern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 543263646Sbaptextern HAL_BOOL ar5212Disable(struct ath_hal *ah); 544263646Sbaptextern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 545263646Sbapt const struct ieee80211_channel *); 546263646Sbaptextern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 547263646Sbapt struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 548263646Sbaptextern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 549263646Sbapt struct ieee80211_channel *chan, u_int chainMask, 550263646Sbapt HAL_BOOL longCal, HAL_BOOL *isCalDone); 551263646Sbaptextern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 552263646Sbapt const struct ieee80211_channel *); 553263646Sbaptextern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 554263646Sbaptextern void ar5212InitNfCalHistBuffer(struct ath_hal *); 555263646Sbaptextern int16_t ar5212GetNfHistMid(const int16_t calData[]); 556263646Sbaptextern void ar5212SetSpurMitigation(struct ath_hal *, 557263646Sbapt const struct ieee80211_channel *); 558263646Sbaptextern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 559263646Sbapt HAL_ANT_SETTING settings, const struct ieee80211_channel *); 560263646Sbaptextern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 561263646Sbaptextern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 562263646Sbapt struct ieee80211_channel *chan); 563263646Sbaptextern void ar5212InitializeGainValues(struct ath_hal *); 564263646Sbaptextern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 565263646Sbaptextern void ar5212RequestRfgain(struct ath_hal *); 566263646Sbapt 567279549Sbaptextern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 568263646Sbapt HAL_BOOL IncTrigLevel); 569263646Sbaptextern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 570298166Sbapt const HAL_TXQ_INFO *qInfo); 571263646Sbaptextern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 572263646Sbapt HAL_TXQ_INFO *qInfo); 573263646Sbaptextern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 574279549Sbapt const HAL_TXQ_INFO *qInfo); 575263646Sbaptextern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 576263646Sbaptextern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 577263646Sbaptextern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 578263646Sbaptextern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 579263646Sbaptextern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 580263646Sbaptextern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 581263646Sbaptextern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 582263646Sbaptextern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 583263646Sbapt u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 584263646Sbapt u_int txRate0, u_int txTries0, 585263646Sbapt u_int keyIx, u_int antMode, u_int flags, 586263646Sbapt u_int rtsctsRate, u_int rtsctsDuration, 587263646Sbapt u_int compicvLen, u_int compivLen, u_int comp); 588263646Sbaptextern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 589263646Sbapt u_int txRate1, u_int txRetries1, 590263646Sbapt u_int txRate2, u_int txRetries2, 591263646Sbapt u_int txRate3, u_int txRetries3); 592264789Sbaptextern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 593263646Sbapt u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 594263646Sbapt const struct ath_desc *ds0); 595263646Sbaptextern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 596264789Sbapt struct ath_desc *, struct ath_tx_status *); 597263646Sbaptextern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 598263646Sbaptextern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 599263646Sbaptextern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 600263646Sbapt const struct ath_desc *ds0, int *rates, int *tries); 601263646Sbapt 602263646Sbaptextern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 603263646Sbapt 604263646Sbaptextern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 605263646Sbapt const struct ar5212AniParams *, HAL_BOOL ena); 606263646Sbaptextern void ar5212AniDetach(struct ath_hal *); 607298166Sbaptextern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 608263646Sbaptextern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); 609263646Sbaptextern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 610263646Sbaptextern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 611263646Sbapt const struct ar5212AniParams *, const struct ar5212AniParams *); 612263646Sbaptstruct ath_rx_status; 613263646Sbaptextern void ar5212AniPhyErrReport(struct ath_hal *ah, 614263646Sbapt const struct ath_rx_status *rs); 615298166Sbaptextern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 616263646Sbaptextern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 617263646Sbapt const struct ieee80211_channel *); 618263646Sbaptextern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 619263646Sbaptextern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 620263646Sbapt HAL_OPMODE, int); 621263646Sbapt 622263646Sbaptextern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 623263646Sbaptextern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 624263646Sbaptextern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 625263646Sbaptextern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 626263646Sbaptextern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 627263646Sbapt struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 628263646Sbapt HAL_DFS_EVENT *event); 629263646Sbaptextern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 630263646Sbapt 631263646Sbapt#endif /* _ATH_AR5212_H_ */ 632263646Sbapt