1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _ATH_AR5212_H_ 20185377Ssam#define _ATH_AR5212_H_ 21185377Ssam 22185377Ssam#include "ah_eeprom.h" 23185377Ssam 24185377Ssam#define AR5212_MAGIC 0x19541014 25185377Ssam 26185377Ssam/* DCU Transmit Filter macros */ 27185377Ssam#define CALC_MMR(dcu, idx) \ 28185377Ssam ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29185377Ssam#define TXBLK_FROM_MMR(mmr) \ 30185377Ssam (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31185377Ssam#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32185377Ssam#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33185377Ssam 34185377Ssam/* MAC register values */ 35185377Ssam 36185377Ssam#define INIT_INTERRUPT_MASK \ 37185377Ssam ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38185377Ssam AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39185377Ssam AR_IMR_HIUERR ) 40185377Ssam#define INIT_BEACON_CONTROL \ 41185377Ssam ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42185377Ssam (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43185377Ssam 44185377Ssam#define INIT_CONFIG_STATUS 0x00000000 45185377Ssam#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46185377Ssam#define INIT_IQCAL_LOG_COUNT_MAX 0xF 47185377Ssam#define INIT_BCON_CNTRL_REG 0x00000000 48185377Ssam 49185377Ssam#define INIT_USEC 40 50185377Ssam#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51185377Ssam#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52185377Ssam 53185377Ssam#define RX_NON_FULL_RATE_LATENCY 63 54185377Ssam#define TX_HALF_RATE_LATENCY 108 55185377Ssam#define TX_QUARTER_RATE_LATENCY 216 56185377Ssam 57185377Ssam#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58185377Ssam#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59185377Ssam#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60185377Ssam#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61185377Ssam#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62185377Ssam#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63185377Ssam 64185377Ssam#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65185377Ssam 66185377Ssam/* Tx frame start to tx data start delay */ 67185377Ssam#define TX_FRAME_D_START_HALF_RATE 0xc 68185377Ssam#define TX_FRAME_D_START_QUARTER_RATE 0xd 69185377Ssam 70185377Ssam/* 71185377Ssam * Various fifo fill before Tx start, in 64-byte units 72185377Ssam * i.e. put the frame in the air while still DMAing 73185377Ssam */ 74185377Ssam#define MIN_TX_FIFO_THRESHOLD 0x1 75185377Ssam#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76185377Ssam#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77185377Ssam 78185377Ssam#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79185377Ssam 80185377Ssam/* 81185377Ssam * Gain support. 82185377Ssam */ 83185377Ssam#define NUM_CORNER_FIX_BITS 4 84185377Ssam#define NUM_CORNER_FIX_BITS_5112 7 85185377Ssam#define DYN_ADJ_UP_MARGIN 15 86185377Ssam#define DYN_ADJ_LO_MARGIN 20 87185377Ssam#define PHY_PROBE_CCK_CORRECTION 5 88185377Ssam#define CCK_OFDM_GAIN_DELTA 15 89185377Ssam 90185377Ssamenum GAIN_PARAMS { 91185377Ssam GP_TXCLIP, 92185377Ssam GP_PD90, 93185377Ssam GP_PD84, 94185377Ssam GP_GSEL, 95185377Ssam}; 96185377Ssam 97185377Ssamenum GAIN_PARAMS_5112 { 98185377Ssam GP_MIXGAIN_OVR, 99185377Ssam GP_PWD_138, 100185377Ssam GP_PWD_137, 101185377Ssam GP_PWD_136, 102185377Ssam GP_PWD_132, 103185377Ssam GP_PWD_131, 104185377Ssam GP_PWD_130, 105185377Ssam}; 106185377Ssam 107185377Ssamtypedef struct _gainOptStep { 108185377Ssam int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109185377Ssam int32_t stepGain; 110185377Ssam int8_t stepName[16]; 111185377Ssam} GAIN_OPTIMIZATION_STEP; 112185377Ssam 113185377Ssamtypedef struct { 114185377Ssam uint32_t numStepsInLadder; 115185377Ssam uint32_t defaultStepNum; 116185377Ssam GAIN_OPTIMIZATION_STEP optStep[10]; 117185377Ssam} GAIN_OPTIMIZATION_LADDER; 118185377Ssam 119185377Ssamtypedef struct { 120185377Ssam uint32_t currStepNum; 121185377Ssam uint32_t currGain; 122185377Ssam uint32_t targetGain; 123185377Ssam uint32_t loTrig; 124185377Ssam uint32_t hiTrig; 125185377Ssam uint32_t active; 126185377Ssam const GAIN_OPTIMIZATION_STEP *currStep; 127185377Ssam} GAIN_VALUES; 128185377Ssam 129185377Ssam/* RF HAL structures */ 130185377Ssamtypedef struct RfHalFuncs { 131185377Ssam void *priv; /* private state */ 132185377Ssam 133185377Ssam void (*rfDetach)(struct ath_hal *ah); 134185377Ssam void (*writeRegs)(struct ath_hal *, 135187831Ssam u_int modeIndex, u_int freqIndex, int regWrites); 136185377Ssam uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 137187831Ssam HAL_BOOL (*setChannel)(struct ath_hal *, 138187831Ssam const struct ieee80211_channel *); 139185377Ssam HAL_BOOL (*setRfRegs)(struct ath_hal *, 140187831Ssam const struct ieee80211_channel *, uint16_t modesIndex, 141185377Ssam uint16_t *rfXpdGain); 142185377Ssam HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143185377Ssam int16_t *minPower, int16_t *maxPower, 144187831Ssam const struct ieee80211_channel *, uint16_t *rfXpdGain); 145187831Ssam HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 146242625Sdim const struct ieee80211_channel *, 147185377Ssam int16_t *maxPow, int16_t *minPow); 148185377Ssam int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 149185377Ssam} RF_HAL_FUNCS; 150185377Ssam 151185377Ssamstruct ar5212AniParams { 152185377Ssam int maxNoiseImmunityLevel; /* [0..4] */ 153185377Ssam int totalSizeDesired[5]; 154185377Ssam int coarseHigh[5]; 155185377Ssam int coarseLow[5]; 156185377Ssam int firpwr[5]; 157185377Ssam 158185377Ssam int maxSpurImmunityLevel; /* [0..7] */ 159185377Ssam int cycPwrThr1[8]; 160185377Ssam 161185377Ssam int maxFirstepLevel; /* [0..2] */ 162185377Ssam int firstep[3]; 163185377Ssam 164185377Ssam uint32_t ofdmTrigHigh; 165185377Ssam uint32_t ofdmTrigLow; 166185377Ssam uint32_t cckTrigHigh; 167185377Ssam uint32_t cckTrigLow; 168185377Ssam int32_t rssiThrLow; 169185377Ssam uint32_t rssiThrHigh; 170185377Ssam 171185377Ssam int period; /* update listen period */ 172185377Ssam 173185377Ssam /* NB: intentionally ordered so data exported to user space is first */ 174185377Ssam uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 175185377Ssam uint32_t cckPhyErrBase; /* Base value for cck err counters */ 176185377Ssam}; 177185377Ssam 178185377Ssam/* 179185377Ssam * Per-channel ANI state private to the driver. 180185377Ssam */ 181185377Ssamstruct ar5212AniState { 182185377Ssam uint8_t noiseImmunityLevel; 183185377Ssam uint8_t spurImmunityLevel; 184185377Ssam uint8_t firstepLevel; 185185377Ssam uint8_t ofdmWeakSigDetectOff; 186185377Ssam uint8_t cckWeakSigThreshold; 187185377Ssam uint32_t listenTime; 188185377Ssam 189185377Ssam /* NB: intentionally ordered so data exported to user space is first */ 190185377Ssam uint32_t txFrameCount; /* Last txFrameCount */ 191185377Ssam uint32_t rxFrameCount; /* Last rx Frame count */ 192185377Ssam uint32_t cycleCount; /* Last cycleCount 193185377Ssam (to detect wrap-around) */ 194185377Ssam uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 195185377Ssam uint32_t cckPhyErrCount; /* CCK err count since last reset */ 196185377Ssam 197185377Ssam const struct ar5212AniParams *params; 198185377Ssam}; 199185377Ssam 200185377Ssam#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 201185377Ssam#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 202185377Ssam 203280940Sadrian#if 0 204185377Ssamstruct ar5212Stats { 205185377Ssam uint32_t ast_ani_niup; /* ANI increased noise immunity */ 206185377Ssam uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 207185377Ssam uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 208185377Ssam uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 209185377Ssam uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 210185377Ssam uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 211185377Ssam uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 212185377Ssam uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 213185377Ssam uint32_t ast_ani_stepup; /* ANI increased first step level */ 214185377Ssam uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 215185377Ssam uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 216185377Ssam uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 217185377Ssam uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 218185377Ssam uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 219185377Ssam uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 220185377Ssam HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 221185377Ssam HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 222185377Ssam}; 223280940Sadrian#endif 224185377Ssam 225185377Ssam/* 226185377Ssam * NF Cal history buffer 227185377Ssam */ 228185377Ssam#define AR5212_CCA_MAX_GOOD_VALUE -95 229185377Ssam#define AR5212_CCA_MAX_HIGH_VALUE -62 230185377Ssam#define AR5212_CCA_MIN_BAD_VALUE -125 231185377Ssam 232185377Ssam#define AR512_NF_CAL_HIST_MAX 5 233185377Ssam 234185377Ssamstruct ar5212NfCalHist { 235185377Ssam int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 236185377Ssam int16_t privNF; 237185377Ssam uint8_t currIndex; 238185377Ssam uint8_t first_run; 239185377Ssam uint8_t invalidNFcount; 240185377Ssam}; 241185377Ssam 242185377Ssamstruct ath_hal_5212 { 243185377Ssam struct ath_hal_private ah_priv; /* base class */ 244185377Ssam 245185377Ssam /* 246185377Ssam * Per-chip common Initialization data. 247185377Ssam * NB: RF backends have their own ini data. 248185377Ssam */ 249185377Ssam HAL_INI_ARRAY ah_ini_modes; 250185377Ssam HAL_INI_ARRAY ah_ini_common; 251185377Ssam 252185377Ssam GAIN_VALUES ah_gainValues; 253185377Ssam 254185377Ssam uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 255185377Ssam uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 256185377Ssam uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 257226760Sadrian uint16_t ah_assocId; 258185377Ssam 259185377Ssam /* 260185377Ssam * Runtime state. 261185377Ssam */ 262185377Ssam uint32_t ah_maskReg; /* copy of AR_IMR */ 263280940Sadrian HAL_ANI_STATS ah_stats; /* various statistics */ 264185377Ssam RF_HAL_FUNCS *ah_rfHal; 265185377Ssam uint32_t ah_txDescMask; /* mask for TXDESC */ 266185377Ssam uint32_t ah_txOkInterruptMask; 267185377Ssam uint32_t ah_txErrInterruptMask; 268185377Ssam uint32_t ah_txDescInterruptMask; 269185377Ssam uint32_t ah_txEolInterruptMask; 270185377Ssam uint32_t ah_txUrnInterruptMask; 271185377Ssam HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 272185380Ssam uint32_t ah_intrTxqs; /* tx q interrupt state */ 273185377Ssam /* decomp mask array */ 274185380Ssam uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 275185380Ssam HAL_ANT_SETTING ah_antControl; /* antenna setting */ 276185380Ssam HAL_BOOL ah_diversity; /* fast diversity setting */ 277185377Ssam enum { 278185377Ssam IQ_CAL_INACTIVE, 279185377Ssam IQ_CAL_RUNNING, 280185377Ssam IQ_CAL_DONE 281185377Ssam } ah_bIQCalibration; /* IQ calibrate state */ 282185377Ssam HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 283185377Ssam uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 284185377Ssam uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 285185377Ssam uint32_t ah_miscMode; /* MISC_MODE settings */ 286185377Ssam uint32_t ah_rssiThr; /* RSSI_THR settings */ 287185377Ssam HAL_BOOL ah_cwCalRequire; /* for ap51 */ 288185377Ssam HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 289185380Ssam HAL_BOOL ah_phyPowerOn; /* PHY power state */ 290185380Ssam HAL_BOOL ah_isHb63; /* cached HB63 check */ 291185377Ssam uint32_t ah_macTPC; /* tpc register */ 292185377Ssam uint32_t ah_beaconInterval; /* XXX */ 293185377Ssam enum { 294185377Ssam AUTO_32KHZ, /* use it if 32kHz crystal present */ 295185377Ssam USE_32KHZ, /* do it regardless */ 296185377Ssam DONT_USE_32KHZ, /* don't use it regardless */ 297185377Ssam } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 298185377Ssam uint32_t ah_ofdmTxPower; 299185377Ssam int16_t ah_txPowerIndexOffset; 300185377Ssam /* 301185377Ssam * Noise floor cal histogram support. 302185377Ssam */ 303185377Ssam struct ar5212NfCalHist ah_nfCalHist; 304185377Ssam 305185377Ssam u_int ah_slottime; /* user-specified slot time */ 306185377Ssam u_int ah_acktimeout; /* user-specified ack timeout */ 307185377Ssam u_int ah_ctstimeout; /* user-specified cts timeout */ 308185377Ssam u_int ah_sifstime; /* user-specified sifs time */ 309185377Ssam /* 310185377Ssam * RF Silent handling; setup according to the EEPROM. 311185377Ssam */ 312185377Ssam uint32_t ah_gpioSelect; /* GPIO pin to use */ 313185377Ssam uint32_t ah_polarity; /* polarity to disable RF */ 314185377Ssam uint32_t ah_gpioBit; /* after init, prev value */ 315185377Ssam /* 316185377Ssam * ANI support. 317185377Ssam */ 318185377Ssam uint32_t ah_procPhyErr; /* Process Phy errs */ 319185377Ssam HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 320185377Ssam struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 321185377Ssam struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 322185377Ssam struct ar5212AniState *ah_curani; /* cached last reference */ 323187831Ssam struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 324185377Ssam 325222265Sadrian /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 326222265Sadrian HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 327222265Sadrian 328185377Ssam /* 329185377Ssam * Transmit power state. Note these are maintained 330185377Ssam * here so they can be retrieved by diagnostic tools. 331185377Ssam */ 332185377Ssam uint16_t *ah_pcdacTable; 333185377Ssam u_int ah_pcdacTableSize; 334218012Sadrian uint16_t ah_ratesArray[37]; 335204579Srpaulo 336204579Srpaulo uint8_t ah_txTrigLev; /* current Tx trigger level */ 337204579Srpaulo uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 338256139Sadrian 339256139Sadrian /* 340256139Sadrian * Channel Tx, Rx, Rx Clear State 341256139Sadrian */ 342256139Sadrian uint32_t ah_cycleCount; 343256139Sadrian uint32_t ah_ctlBusy; 344256139Sadrian uint32_t ah_rxBusy; 345256139Sadrian uint32_t ah_txBusy; 346256139Sadrian uint32_t ah_rx_chainmask; 347256139Sadrian uint32_t ah_tx_chainmask; 348281128Sadrian 349281128Sadrian /* Used to return ANI statistics to the diagnostic API */ 350281128Sadrian HAL_ANI_STATS ext_ani_stats; 351185377Ssam}; 352185377Ssam#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 353185377Ssam 354185380Ssam/* 355185380Ssam * IS_XXXX macros test the MAC version 356185380Ssam * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 357185380Ssam * 358185380Ssam * Some single chip radios have equivalent radio/RF (e.g. 5112) 359185380Ssam * for those use IS_RADXXX_ANY macros. 360185380Ssam */ 361185377Ssam#define IS_2317(ah) \ 362185377Ssam ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 363185377Ssam (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 364185377Ssam#define IS_2316(ah) \ 365185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 366185377Ssam#define IS_2413(ah) \ 367185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 368185377Ssam#define IS_5424(ah) \ 369185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 370185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 371185377Ssam AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 372185377Ssam#define IS_5413(ah) \ 373185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 374185377Ssam#define IS_2425(ah) \ 375185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 376185377Ssam#define IS_2417(ah) \ 377185377Ssam ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 378185377Ssam#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 379185377Ssam 380185380Ssam#define AH_RADIO_MAJOR(ah) \ 381185380Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 382185380Ssam#define AH_RADIO_MINOR(ah) \ 383185380Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 384185380Ssam#define IS_RAD5111(ah) \ 385185380Ssam (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 386185380Ssam AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 387185380Ssam#define IS_RAD5112(ah) \ 388185380Ssam (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 389185380Ssam AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 390185380Ssam/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 391185380Ssam#define IS_RAD5112_ANY(ah) \ 392185380Ssam (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 393185380Ssam AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 394185380Ssam#define IS_RAD5112_REV1(ah) \ 395185380Ssam (IS_RAD5112(ah) && \ 396185380Ssam AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 397185380Ssam#define IS_RADX112_REV2(ah) \ 398185380Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 399185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 400185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 401185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 402185380Ssam 403185377Ssam#define ar5212RfDetach(ah) do { \ 404185377Ssam if (AH5212(ah)->ah_rfHal != AH_NULL) \ 405185377Ssam AH5212(ah)->ah_rfHal->rfDetach(ah); \ 406185377Ssam} while (0) 407185377Ssam#define ar5212GetRfBank(ah, b) \ 408185377Ssam AH5212(ah)->ah_rfHal->getRfBank(ah, b) 409185377Ssam 410185377Ssam/* 411185377Ssam * Hack macros for Nala/San: 11b is handled 412185377Ssam * using 11g; flip the channel flags to accomplish this. 413185377Ssam */ 414185377Ssam#define SAVE_CCK(_ah, _chan, _flag) do { \ 415185377Ssam if ((IS_2425(_ah) || IS_2417(_ah)) && \ 416187831Ssam (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 417187831Ssam (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 418187831Ssam (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 419185377Ssam (_flag) = AH_TRUE; \ 420188012Ssam } else \ 421188012Ssam (_flag) = AH_FALSE; \ 422185377Ssam} while (0) 423185377Ssam#define RESTORE_CCK(_ah, _chan, _flag) do { \ 424188012Ssam if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 425187831Ssam (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 426187831Ssam (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 427185377Ssam } \ 428185377Ssam} while (0) 429185377Ssam 430185377Ssamstruct ath_hal; 431185377Ssam 432185377Ssamextern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 433185377Ssamextern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 434185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 435185377Ssamextern void ar5212Detach(struct ath_hal *ah); 436185377Ssamextern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 437185377Ssamextern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 438185377Ssam uint16_t flags, uint16_t *low, uint16_t *high); 439185377Ssamextern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 440185377Ssam 441185377Ssamextern void ar5212SetBeaconTimers(struct ath_hal *ah, 442185377Ssam const HAL_BEACON_TIMERS *); 443185377Ssamextern void ar5212BeaconInit(struct ath_hal *ah, 444185377Ssam uint32_t next_beacon, uint32_t beacon_period); 445185377Ssamextern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 446185377Ssamextern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 447185377Ssam const HAL_BEACON_STATE *); 448225444Sadrianextern uint64_t ar5212GetNextTBTT(struct ath_hal *); 449185377Ssam 450185377Ssamextern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 451185377Ssamextern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 452185377Ssamextern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 453185377Ssamextern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 454185377Ssam 455185377Ssamextern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 456185377Ssamextern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 457185377Ssamextern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 458185377Ssamextern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 459185377Ssam uint16_t entry, const uint8_t *mac); 460185377Ssamextern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 461185377Ssam const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 462185377Ssam 463185377Ssamextern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 464185377Ssamextern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 465185377Ssamextern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 466185377Ssamextern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 467185377Ssamextern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 468185377Ssamextern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 469185377Ssamextern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 470185377Ssam uint16_t regDomain, HAL_STATUS *stats); 471185377Ssamextern u_int ar5212GetWirelessModes(struct ath_hal *ah); 472185377Ssamextern void ar5212EnableRfKill(struct ath_hal *); 473188974Ssamextern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 474188974Ssam HAL_GPIO_MUX_TYPE); 475185377Ssamextern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 476185377Ssamextern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 477185377Ssamextern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 478185377Ssamextern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 479185377Ssamextern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 480185377Ssamextern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 481185377Ssam uint16_t assocId); 482185377Ssamextern uint32_t ar5212GetTsf32(struct ath_hal *ah); 483185377Ssamextern uint64_t ar5212GetTsf64(struct ath_hal *ah); 484219419Sadrianextern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 485185377Ssamextern void ar5212ResetTsf(struct ath_hal *ah); 486185377Ssamextern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 487185377Ssamextern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 488185377Ssamextern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 489185377Ssamextern void ar5212EnableMibCounters(struct ath_hal *); 490185377Ssamextern void ar5212DisableMibCounters(struct ath_hal *); 491185377Ssamextern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 492185377Ssamextern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 493185377Ssamextern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 494185377Ssamextern u_int ar5212GetDefAntenna(struct ath_hal *ah); 495185377Ssamextern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 496185377Ssamextern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 497185377Ssamextern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 498185377Ssamextern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 499185377Ssamextern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 500185377Ssamextern u_int ar5212GetSifsTime(struct ath_hal *); 501185377Ssamextern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 502185377Ssamextern u_int ar5212GetSlotTime(struct ath_hal *); 503185377Ssamextern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 504185377Ssamextern u_int ar5212GetAckTimeout(struct ath_hal *); 505185377Ssamextern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 506185377Ssamextern u_int ar5212GetAckCTSRate(struct ath_hal *); 507185377Ssamextern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 508185377Ssamextern u_int ar5212GetCTSTimeout(struct ath_hal *); 509185377Ssamextern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 510185377Ssamvoid ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 511185377Ssamextern void ar5212SetPCUConfig(struct ath_hal *); 512185377Ssamextern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 513185377Ssamextern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 514185377Ssamextern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 515185377Ssamextern int16_t ar5212GetNfAdjust(struct ath_hal *, 516185377Ssam const HAL_CHANNEL_INTERNAL *); 517185377Ssamextern void ar5212SetCompRegs(struct ath_hal *ah); 518185377Ssamextern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 519185377Ssam uint32_t, uint32_t *); 520185377Ssamextern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 521185377Ssam uint32_t, uint32_t, HAL_STATUS *); 522185377Ssamextern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 523185377Ssam const void *args, uint32_t argsize, 524185377Ssam void **result, uint32_t *resultsize); 525222644Sadrianextern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 526222644Sadrian uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 527234873Sadrianextern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *, 528234873Sadrian HAL_SURVEY_SAMPLE *); 529247286Sadrianextern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 530185377Ssam 531185377Ssamextern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 532185377Ssam int setChip); 533185377Ssamextern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 534185377Ssamextern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 535185377Ssam 536238278Sadrianextern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE); 537238278Sadrianextern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE); 538185377Ssamextern void ar5212EnableReceive(struct ath_hal *ah); 539185377Ssamextern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 540185377Ssamextern void ar5212StartPcuReceive(struct ath_hal *ah); 541185377Ssamextern void ar5212StopPcuReceive(struct ath_hal *ah); 542185377Ssamextern void ar5212SetMulticastFilter(struct ath_hal *ah, 543185377Ssam uint32_t filter0, uint32_t filter1); 544185377Ssamextern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 545185377Ssamextern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 546185377Ssamextern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 547185377Ssamextern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 548185377Ssamextern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 549185377Ssam struct ath_desc *, uint32_t size, u_int flags); 550185377Ssamextern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 551185377Ssam uint32_t, struct ath_desc *, uint64_t, 552185377Ssam struct ath_rx_status *); 553185377Ssam 554185377Ssamextern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 555187831Ssam struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 556290612Sadrian HAL_RESET_TYPE, HAL_STATUS *status); 557187831Ssamextern HAL_BOOL ar5212SetChannel(struct ath_hal *, 558187831Ssam const struct ieee80211_channel *); 559185377Ssamextern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 560185377Ssamextern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 561185377Ssamextern HAL_BOOL ar5212Disable(struct ath_hal *ah); 562187831Ssamextern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 563187831Ssam const struct ieee80211_channel *); 564187831Ssamextern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 565187831Ssam struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 566187831Ssamextern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 567187831Ssam struct ieee80211_channel *chan, u_int chainMask, 568187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 569187831Ssamextern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 570187831Ssam const struct ieee80211_channel *); 571185377Ssamextern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 572185377Ssamextern void ar5212InitNfCalHistBuffer(struct ath_hal *); 573185377Ssamextern int16_t ar5212GetNfHistMid(const int16_t calData[]); 574187831Ssamextern void ar5212SetSpurMitigation(struct ath_hal *, 575187831Ssam const struct ieee80211_channel *); 576185377Ssamextern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 577187831Ssam HAL_ANT_SETTING settings, const struct ieee80211_channel *); 578185377Ssamextern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 579185377Ssamextern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 580187831Ssam struct ieee80211_channel *chan); 581185377Ssamextern void ar5212InitializeGainValues(struct ath_hal *); 582185377Ssamextern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 583185380Ssamextern void ar5212RequestRfgain(struct ath_hal *); 584185377Ssam 585185377Ssamextern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 586185377Ssam HAL_BOOL IncTrigLevel); 587185377Ssamextern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 588185377Ssam const HAL_TXQ_INFO *qInfo); 589185377Ssamextern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 590185377Ssam HAL_TXQ_INFO *qInfo); 591185377Ssamextern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 592185377Ssam const HAL_TXQ_INFO *qInfo); 593185377Ssamextern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 594185377Ssamextern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 595185377Ssamextern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 596185377Ssamextern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 597185377Ssamextern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 598185377Ssamextern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 599185377Ssamextern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 600185377Ssamextern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 601185377Ssam u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 602185377Ssam u_int txRate0, u_int txTries0, 603185377Ssam u_int keyIx, u_int antMode, u_int flags, 604185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 605185377Ssam u_int compicvLen, u_int compivLen, u_int comp); 606185377Ssamextern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 607185377Ssam u_int txRate1, u_int txRetries1, 608185377Ssam u_int txRate2, u_int txRetries2, 609185377Ssam u_int txRate3, u_int txRetries3); 610185377Ssamextern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 611239051Sadrian HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 612239051Sadrian u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 613185377Ssam const struct ath_desc *ds0); 614185377Ssamextern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 615185377Ssam struct ath_desc *, struct ath_tx_status *); 616185377Ssamextern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 617185377Ssamextern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 618217621Sadrianextern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 619217621Sadrian const struct ath_desc *ds0, int *rates, int *tries); 620238607Sadrianextern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, 621238607Sadrian uint32_t link); 622238607Sadrianextern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, 623238607Sadrian uint32_t *link); 624238607Sadrianextern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 625238607Sadrian uint32_t **linkptr); 626185377Ssam 627185377Ssamextern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 628185377Ssam 629185377Ssamextern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 630185377Ssam const struct ar5212AniParams *, HAL_BOOL ena); 631185377Ssamextern void ar5212AniDetach(struct ath_hal *); 632185377Ssamextern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 633280940Sadrianextern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *); 634185377Ssamextern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 635185377Ssamextern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 636185377Ssam const struct ar5212AniParams *, const struct ar5212AniParams *); 637185377Ssamstruct ath_rx_status; 638185377Ssamextern void ar5212AniPhyErrReport(struct ath_hal *ah, 639185377Ssam const struct ath_rx_status *rs); 640185377Ssamextern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 641217684Sadrianextern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 642187831Ssam const struct ieee80211_channel *); 643217684Sadrianextern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 644187831Ssamextern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 645185377Ssam HAL_OPMODE, int); 646211206Sadrian 647211206Sadrianextern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 648211206Sadrianextern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 649222584Sadrianextern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 650239642Sadrianextern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah, 651239642Sadrian HAL_PHYERR_PARAM *pe); 652222584Sadrianextern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 653222815Sadrianextern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 654222815Sadrian struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 655222815Sadrian HAL_DFS_EVENT *event); 656224709Sadrianextern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 657230791Sadrianextern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 658211206Sadrian 659185377Ssam#endif /* _ATH_AR5212_H_ */ 660