ah.h revision 247286
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 247286 2013-02-25 22:42:43Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77} HAL_STATUS; 78 79typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 141 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 142 143 HAL_CAP_DS = 67, /* 2 stream */ 144 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 145 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 146 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 147 148 HAL_CAP_TS = 72, /* 3 stream */ 149 150 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 151 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 152 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 153 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 154 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 155 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 156 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 157 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 158 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 159 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 160 161 HAL_CAP_BB_PANIC_WATCHDOG = 92, 162 163 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 164 165 HAL_CAP_LDPC = 99, 166 167 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 168 169 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 170 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 171 HAL_CAP_LDPCWAR = 108, 172 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 173 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 174 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 175 HAL_CAP_PCIE_LCR_OFFSET = 112, 176 177 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 178 HAL_CAP_MCI = 118, 179 HAL_CAP_SMARTANTENNA = 119, 180 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 181 HAL_CAP_TX_DIVERSITY = 121, 182 HAL_CAP_CRDC = 122, 183 184 /* The following are private to the FreeBSD HAL (224 onward) */ 185 186 HAL_CAP_INTMIT = 229, /* interference mitigation */ 187 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 188 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 189 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 190 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 191 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 192 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 193 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 194 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 195 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 196 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 197} HAL_CAPABILITY_TYPE; 198 199/* 200 * "States" for setting the LED. These correspond to 201 * the possible 802.11 operational states and there may 202 * be a many-to-one mapping between these states and the 203 * actual hardware state for the LED's (i.e. the hardware 204 * may have fewer states). 205 */ 206typedef enum { 207 HAL_LED_INIT = 0, 208 HAL_LED_SCAN = 1, 209 HAL_LED_AUTH = 2, 210 HAL_LED_ASSOC = 3, 211 HAL_LED_RUN = 4 212} HAL_LED_STATE; 213 214/* 215 * Transmit queue types/numbers. These are used to tag 216 * each transmit queue in the hardware and to identify a set 217 * of transmit queues for operations such as start/stop dma. 218 */ 219typedef enum { 220 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 221 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 222 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 223 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 224 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 225 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 226 HAL_TX_QUEUE_CFEND = 6, 227 HAL_TX_QUEUE_PAPRD = 7, 228} HAL_TX_QUEUE; 229 230#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 231 232/* 233 * Receive queue types. These are used to tag 234 * each transmit queue in the hardware and to identify a set 235 * of transmit queues for operations such as start/stop dma. 236 */ 237typedef enum { 238 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 239 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 240} HAL_RX_QUEUE; 241 242#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 243 244#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 245 246/* 247 * Transmit queue subtype. These map directly to 248 * WME Access Categories (except for UPSD). Refer 249 * to Table 5 of the WME spec. 250 */ 251typedef enum { 252 HAL_WME_AC_BK = 0, /* background access category */ 253 HAL_WME_AC_BE = 1, /* best effort access category*/ 254 HAL_WME_AC_VI = 2, /* video access category */ 255 HAL_WME_AC_VO = 3, /* voice access category */ 256 HAL_WME_UPSD = 4, /* uplink power save */ 257} HAL_TX_QUEUE_SUBTYPE; 258 259/* 260 * Transmit queue flags that control various 261 * operational parameters. 262 */ 263typedef enum { 264 /* 265 * Per queue interrupt enables. When set the associated 266 * interrupt may be delivered for packets sent through 267 * the queue. Without these enabled no interrupts will 268 * be delivered for transmits through the queue. 269 */ 270 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 271 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 272 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 273 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 274 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 275 /* 276 * Enable hardware compression for packets sent through 277 * the queue. The compression buffer must be setup and 278 * packets must have a key entry marked in the tx descriptor. 279 */ 280 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 281 /* 282 * Disable queue when veol is hit or ready time expires. 283 * By default the queue is disabled only on reaching the 284 * physical end of queue (i.e. a null link ptr in the 285 * descriptor chain). 286 */ 287 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 288 /* 289 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 290 * event. Frames will be transmitted only when this timer 291 * fires, e.g to transmit a beacon in ap or adhoc modes. 292 */ 293 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 294 /* 295 * Each transmit queue has a counter that is incremented 296 * each time the queue is enabled and decremented when 297 * the list of frames to transmit is traversed (or when 298 * the ready time for the queue expires). This counter 299 * must be non-zero for frames to be scheduled for 300 * transmission. The following controls disable bumping 301 * this counter under certain conditions. Typically this 302 * is used to gate frames based on the contents of another 303 * queue (e.g. CAB traffic may only follow a beacon frame). 304 * These are meaningful only when frames are scheduled 305 * with a non-ASAP policy (e.g. DBA-gated). 306 */ 307 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 308 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 309 310 /* 311 * Fragment burst backoff policy. Normally the no backoff 312 * is done after a successful transmission, the next fragment 313 * is sent at SIFS. If this flag is set backoff is done 314 * after each fragment, regardless whether it was ack'd or 315 * not, after the backoff count reaches zero a normal channel 316 * access procedure is done before the next transmit (i.e. 317 * wait AIFS instead of SIFS). 318 */ 319 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 320 /* 321 * Disable post-tx backoff following each frame. 322 */ 323 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 324 /* 325 * DCU arbiter lockout control. This controls how 326 * lower priority tx queues are handled with respect to 327 * to a specific queue when multiple queues have frames 328 * to send. No lockout means lower priority queues arbitrate 329 * concurrently with this queue. Intra-frame lockout 330 * means lower priority queues are locked out until the 331 * current frame transmits (e.g. including backoffs and bursting). 332 * Global lockout means nothing lower can arbitrary so 333 * long as there is traffic activity on this queue (frames, 334 * backoff, etc). 335 */ 336 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 337 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 338 339 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 340 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 341} HAL_TX_QUEUE_FLAGS; 342 343typedef struct { 344 uint32_t tqi_ver; /* hal TXQ version */ 345 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 346 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 347 uint32_t tqi_priority; /* (not used) */ 348 uint32_t tqi_aifs; /* aifs */ 349 uint32_t tqi_cwmin; /* cwMin */ 350 uint32_t tqi_cwmax; /* cwMax */ 351 uint16_t tqi_shretry; /* rts retry limit */ 352 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 353 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 354 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 355 uint32_t tqi_burstTime; /* max burst duration (us) */ 356 uint32_t tqi_readyTime; /* frame schedule time (us) */ 357 uint32_t tqi_compBuf; /* comp buffer phys addr */ 358} HAL_TXQ_INFO; 359 360#define HAL_TQI_NONVAL 0xffff 361 362/* token to use for aifs, cwmin, cwmax */ 363#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 364 365/* compression definitions */ 366#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 367#define HAL_COMP_BUF_ALIGN_SIZE 512 368 369/* 370 * Transmit packet types. This belongs in ah_desc.h, but 371 * is here so we can give a proper type to various parameters 372 * (and not require everyone include the file). 373 * 374 * NB: These values are intentionally assigned for 375 * direct use when setting up h/w descriptors. 376 */ 377typedef enum { 378 HAL_PKT_TYPE_NORMAL = 0, 379 HAL_PKT_TYPE_ATIM = 1, 380 HAL_PKT_TYPE_PSPOLL = 2, 381 HAL_PKT_TYPE_BEACON = 3, 382 HAL_PKT_TYPE_PROBE_RESP = 4, 383 HAL_PKT_TYPE_CHIRP = 5, 384 HAL_PKT_TYPE_GRP_POLL = 6, 385 HAL_PKT_TYPE_AMPDU = 7, 386} HAL_PKT_TYPE; 387 388/* Rx Filter Frame Types */ 389typedef enum { 390 /* 391 * These bits correspond to AR_RX_FILTER for all chips. 392 * Not all bits are supported by all chips. 393 */ 394 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 395 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 396 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 397 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 398 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 399 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 400 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 401 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 402 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 403 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 404 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 405 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 406 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 407 /* Allow all mcast/bcast frames */ 408 409 /* 410 * Magic RX filter flags that aren't targetting hardware bits 411 * but instead the HAL sets individual bits - eg PHYERR will result 412 * in OFDM/CCK timing error frames being received. 413 */ 414 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 415} HAL_RX_FILTER; 416 417typedef enum { 418 HAL_PM_AWAKE = 0, 419 HAL_PM_FULL_SLEEP = 1, 420 HAL_PM_NETWORK_SLEEP = 2, 421 HAL_PM_UNDEFINED = 3 422} HAL_POWER_MODE; 423 424/* 425 * Enterprise mode flags 426 */ 427#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 428#define AH_ENT_CHAIN2_DISABLE 0x00000002 429#define AH_ENT_5MHZ_DISABLE 0x00000004 430#define AH_ENT_10MHZ_DISABLE 0x00000008 431#define AH_ENT_49GHZ_DISABLE 0x00000010 432#define AH_ENT_LOOPBACK_DISABLE 0x00000020 433#define AH_ENT_TPC_PERF_DISABLE 0x00000040 434#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 435#define AH_ENT_SPECTRAL_PRECISION 0x00000300 436#define AH_ENT_SPECTRAL_PRECISION_S 8 437#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 438 439#define AH_FIRST_DESC_NDELIMS 60 440 441/* 442 * NOTE WELL: 443 * These are mapped to take advantage of the common locations for many of 444 * the bits on all of the currently supported MAC chips. This is to make 445 * the ISR as efficient as possible, while still abstracting HW differences. 446 * When new hardware breaks this commonality this enumerated type, as well 447 * as the HAL functions using it, must be modified. All values are directly 448 * mapped unless commented otherwise. 449 */ 450typedef enum { 451 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 452 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 453 HAL_INT_RXERR = 0x00000004, 454 HAL_INT_RXHP = 0x00000001, /* EDMA */ 455 HAL_INT_RXLP = 0x00000002, /* EDMA */ 456 HAL_INT_RXNOFRM = 0x00000008, 457 HAL_INT_RXEOL = 0x00000010, 458 HAL_INT_RXORN = 0x00000020, 459 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 460 HAL_INT_TXDESC = 0x00000080, 461 HAL_INT_TIM_TIMER= 0x00000100, 462 HAL_INT_MCI = 0x00000200, 463 HAL_INT_BBPANIC = 0x00000400, 464 HAL_INT_TXURN = 0x00000800, 465 HAL_INT_MIB = 0x00001000, 466 HAL_INT_RXPHY = 0x00004000, 467 HAL_INT_RXKCM = 0x00008000, 468 HAL_INT_SWBA = 0x00010000, 469 HAL_INT_BRSSI = 0x00020000, 470 HAL_INT_BMISS = 0x00040000, 471 HAL_INT_BNR = 0x00100000, 472 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 473 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 474 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 475 HAL_INT_GPIO = 0x01000000, 476 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 477 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 478 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 479 /* Atheros ref driver has a generic timer interrupt now..*/ 480 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 481 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 482 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 483 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 484#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 485 HAL_INT_BMISC = HAL_INT_TIM 486 | HAL_INT_DTIM 487 | HAL_INT_DTIMSYNC 488 | HAL_INT_CABEND 489 | HAL_INT_TBTT, 490 491 /* Interrupt bits that map directly to ISR/IMR bits */ 492 HAL_INT_COMMON = HAL_INT_RXNOFRM 493 | HAL_INT_RXDESC 494 | HAL_INT_RXEOL 495 | HAL_INT_RXORN 496 | HAL_INT_TXDESC 497 | HAL_INT_TXURN 498 | HAL_INT_MIB 499 | HAL_INT_RXPHY 500 | HAL_INT_RXKCM 501 | HAL_INT_SWBA 502 | HAL_INT_BMISS 503 | HAL_INT_BRSSI 504 | HAL_INT_BNR 505 | HAL_INT_GPIO, 506} HAL_INT; 507 508/* 509 * MSI vector assignments 510 */ 511typedef enum { 512 HAL_MSIVEC_MISC = 0, 513 HAL_MSIVEC_TX = 1, 514 HAL_MSIVEC_RXLP = 2, 515 HAL_MSIVEC_RXHP = 3, 516} HAL_MSIVEC; 517 518typedef enum { 519 HAL_INT_LINE = 0, 520 HAL_INT_MSI = 1, 521} HAL_INT_TYPE; 522 523/* For interrupt mitigation registers */ 524typedef enum { 525 HAL_INT_RX_FIRSTPKT=0, 526 HAL_INT_RX_LASTPKT, 527 HAL_INT_TX_FIRSTPKT, 528 HAL_INT_TX_LASTPKT, 529 HAL_INT_THRESHOLD 530} HAL_INT_MITIGATION; 531 532/* XXX this is duplicate information! */ 533typedef struct { 534 u_int32_t cyclecnt_diff; /* delta cycle count */ 535 u_int32_t rxclr_cnt; /* rx clear count */ 536 u_int32_t txframecnt_diff; /* delta tx frame count */ 537 u_int32_t rxframecnt_diff; /* delta rx frame count */ 538 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 539 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 540 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 541 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 542 HAL_BOOL valid; /* if the stats are valid*/ 543} HAL_ANISTATS; 544 545typedef struct { 546 u_int8_t txctl_offset; 547 u_int8_t txctl_numwords; 548 u_int8_t txstatus_offset; 549 u_int8_t txstatus_numwords; 550 551 u_int8_t rxctl_offset; 552 u_int8_t rxctl_numwords; 553 u_int8_t rxstatus_offset; 554 u_int8_t rxstatus_numwords; 555 556 u_int8_t macRevision; 557} HAL_DESC_INFO; 558 559typedef enum { 560 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 561 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 562 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 563 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 564 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 565 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 566 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 567} HAL_GPIO_MUX_TYPE; 568 569typedef enum { 570 HAL_GPIO_INTR_LOW = 0, 571 HAL_GPIO_INTR_HIGH = 1, 572 HAL_GPIO_INTR_DISABLE = 2 573} HAL_GPIO_INTR_TYPE; 574 575typedef struct halCounters { 576 u_int32_t tx_frame_count; 577 u_int32_t rx_frame_count; 578 u_int32_t rx_clear_count; 579 u_int32_t cycle_count; 580 u_int8_t is_rx_active; // true (1) or false (0) 581 u_int8_t is_tx_active; // true (1) or false (0) 582} HAL_COUNTERS; 583 584typedef enum { 585 HAL_RFGAIN_INACTIVE = 0, 586 HAL_RFGAIN_READ_REQUESTED = 1, 587 HAL_RFGAIN_NEED_CHANGE = 2 588} HAL_RFGAIN; 589 590typedef uint16_t HAL_CTRY_CODE; /* country code */ 591typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 592 593#define HAL_ANTENNA_MIN_MODE 0 594#define HAL_ANTENNA_FIXED_A 1 595#define HAL_ANTENNA_FIXED_B 2 596#define HAL_ANTENNA_MAX_MODE 3 597 598typedef struct { 599 uint32_t ackrcv_bad; 600 uint32_t rts_bad; 601 uint32_t rts_good; 602 uint32_t fcs_bad; 603 uint32_t beacons; 604} HAL_MIB_STATS; 605 606/* 607 * These bits represent what's in ah_currentRDext. 608 */ 609typedef enum { 610 REG_EXT_FCC_MIDBAND = 0, 611 REG_EXT_JAPAN_MIDBAND = 1, 612 REG_EXT_FCC_DFS_HT40 = 2, 613 REG_EXT_JAPAN_NONDFS_HT40 = 3, 614 REG_EXT_JAPAN_DFS_HT40 = 4 615} REG_EXT_BITMAP; 616 617enum { 618 HAL_MODE_11A = 0x001, /* 11a channels */ 619 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 620 HAL_MODE_11B = 0x004, /* 11b channels */ 621 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 622#ifdef notdef 623 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 624#else 625 HAL_MODE_11G = 0x008, /* XXX historical */ 626#endif 627 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 628 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 629 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 630 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 631 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 632 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 633 HAL_MODE_11NG_HT20 = 0x008000, 634 HAL_MODE_11NA_HT20 = 0x010000, 635 HAL_MODE_11NG_HT40PLUS = 0x020000, 636 HAL_MODE_11NG_HT40MINUS = 0x040000, 637 HAL_MODE_11NA_HT40PLUS = 0x080000, 638 HAL_MODE_11NA_HT40MINUS = 0x100000, 639 HAL_MODE_ALL = 0xffffff 640}; 641 642typedef struct { 643 int rateCount; /* NB: for proper padding */ 644 uint8_t rateCodeToIndex[256]; /* back mapping */ 645 struct { 646 uint8_t valid; /* valid for rate control use */ 647 uint8_t phy; /* CCK/OFDM/XR */ 648 uint32_t rateKbps; /* transfer rate in kbs */ 649 uint8_t rateCode; /* rate for h/w descriptors */ 650 uint8_t shortPreamble; /* mask for enabling short 651 * preamble in CCK rate code */ 652 uint8_t dot11Rate; /* value for supported rates 653 * info element of MLME */ 654 uint8_t controlRate; /* index of next lower basic 655 * rate; used for dur. calcs */ 656 uint16_t lpAckDuration; /* long preamble ACK duration */ 657 uint16_t spAckDuration; /* short preamble ACK duration*/ 658 } info[64]; 659} HAL_RATE_TABLE; 660 661typedef struct { 662 u_int rs_count; /* number of valid entries */ 663 uint8_t rs_rates[64]; /* rates */ 664} HAL_RATE_SET; 665 666/* 667 * 802.11n specific structures and enums 668 */ 669typedef enum { 670 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 671 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 672} HAL_CHAIN_TYPE; 673 674typedef struct { 675 u_int Tries; 676 u_int Rate; /* hardware rate code */ 677 u_int RateIndex; /* rate series table index */ 678 u_int PktDuration; 679 u_int ChSel; 680 u_int RateFlags; 681#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 682#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 683#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 684#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 685 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 686} HAL_11N_RATE_SERIES; 687 688typedef enum { 689 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 690 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 691} HAL_HT_MACMODE; 692 693typedef enum { 694 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 695 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 696} HAL_HT_PHYMODE; 697 698typedef enum { 699 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 700 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 701} HAL_HT_EXTPROTSPACING; 702 703 704typedef enum { 705 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 706 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 707} HAL_HT_RXCLEAR; 708 709typedef enum { 710 HAL_FREQ_BAND_5GHZ = 0, 711 HAL_FREQ_BAND_2GHZ = 1, 712} HAL_FREQ_BAND; 713 714/* 715 * Antenna switch control. By default antenna selection 716 * enables multiple (2) antenna use. To force use of the 717 * A or B antenna only specify a fixed setting. Fixing 718 * the antenna will also disable any diversity support. 719 */ 720typedef enum { 721 HAL_ANT_VARIABLE = 0, /* variable by programming */ 722 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 723 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 724} HAL_ANT_SETTING; 725 726typedef enum { 727 HAL_M_STA = 1, /* infrastructure station */ 728 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 729 HAL_M_HOSTAP = 6, /* Software Access Point */ 730 HAL_M_MONITOR = 8 /* Monitor mode */ 731} HAL_OPMODE; 732 733typedef struct { 734 uint8_t kv_type; /* one of HAL_CIPHER */ 735 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 736 uint16_t kv_len; /* length in bits */ 737 uint8_t kv_val[16]; /* enough for 128-bit keys */ 738 uint8_t kv_mic[8]; /* TKIP MIC key */ 739 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 740} HAL_KEYVAL; 741 742/* 743 * This is the TX descriptor field which marks the key padding requirement. 744 * The naming is unfortunately unclear. 745 */ 746#define AH_KEYTYPE_MASK 0x0F 747typedef enum { 748 HAL_KEY_TYPE_CLEAR, 749 HAL_KEY_TYPE_WEP, 750 HAL_KEY_TYPE_AES, 751 HAL_KEY_TYPE_TKIP, 752} HAL_KEY_TYPE; 753 754typedef enum { 755 HAL_CIPHER_WEP = 0, 756 HAL_CIPHER_AES_OCB = 1, 757 HAL_CIPHER_AES_CCM = 2, 758 HAL_CIPHER_CKIP = 3, 759 HAL_CIPHER_TKIP = 4, 760 HAL_CIPHER_CLR = 5, /* no encryption */ 761 762 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 763} HAL_CIPHER; 764 765enum { 766 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 767 HAL_SLOT_TIME_9 = 9, 768 HAL_SLOT_TIME_20 = 20, 769}; 770 771/* 772 * Per-station beacon timer state. Note that the specified 773 * beacon interval (given in TU's) can also include flags 774 * to force a TSF reset and to enable the beacon xmit logic. 775 * If bs_cfpmaxduration is non-zero the hardware is setup to 776 * coexist with a PCF-capable AP. 777 */ 778typedef struct { 779 uint32_t bs_nexttbtt; /* next beacon in TU */ 780 uint32_t bs_nextdtim; /* next DTIM in TU */ 781 uint32_t bs_intval; /* beacon interval+flags */ 782/* 783 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 784 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 785 * register. 786 */ 787#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 788#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 789#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 790#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 791#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 792 uint32_t bs_dtimperiod; 793 uint16_t bs_cfpperiod; /* CFP period in TU */ 794 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 795 uint32_t bs_cfpnext; /* next CFP in TU */ 796 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 797 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 798 uint32_t bs_sleepduration; /* max sleep duration */ 799 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 800} HAL_BEACON_STATE; 801 802/* 803 * Like HAL_BEACON_STATE but for non-station mode setup. 804 * NB: see above flag definitions for bt_intval. 805 */ 806typedef struct { 807 uint32_t bt_intval; /* beacon interval+flags */ 808 uint32_t bt_nexttbtt; /* next beacon in TU */ 809 uint32_t bt_nextatim; /* next ATIM in TU */ 810 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 811 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 812 uint32_t bt_flags; /* timer enables */ 813#define HAL_BEACON_TBTT_EN 0x00000001 814#define HAL_BEACON_DBA_EN 0x00000002 815#define HAL_BEACON_SWBA_EN 0x00000004 816} HAL_BEACON_TIMERS; 817 818/* 819 * Per-node statistics maintained by the driver for use in 820 * optimizing signal quality and other operational aspects. 821 */ 822typedef struct { 823 uint32_t ns_avgbrssi; /* average beacon rssi */ 824 uint32_t ns_avgrssi; /* average data rssi */ 825 uint32_t ns_avgtxrssi; /* average tx rssi */ 826} HAL_NODE_STATS; 827 828#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 829 830 831struct ath_desc; 832struct ath_tx_status; 833struct ath_rx_status; 834struct ieee80211_channel; 835 836/* 837 * This is a channel survey sample entry. 838 * 839 * The AR5212 ANI routines fill these samples. The ANI code then uses it 840 * when calculating listen time; it is also exported via a diagnostic 841 * API. 842 */ 843typedef struct { 844 uint32_t seq_num; 845 uint32_t tx_busy; 846 uint32_t rx_busy; 847 uint32_t chan_busy; 848 uint32_t ext_chan_busy; 849 uint32_t cycle_count; 850 /* XXX TODO */ 851 uint32_t ofdm_phyerr_count; 852 uint32_t cck_phyerr_count; 853} HAL_SURVEY_SAMPLE; 854 855/* 856 * This provides 3.2 seconds of sample space given an 857 * ANI time of 1/10th of a second. This may not be enough! 858 */ 859#define CHANNEL_SURVEY_SAMPLE_COUNT 32 860 861typedef struct { 862 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 863 uint32_t cur_sample; /* current sample in sequence */ 864 uint32_t cur_seq; /* current sequence number */ 865} HAL_CHANNEL_SURVEY; 866 867/* 868 * ANI commands. 869 * 870 * These are used both internally and externally via the diagnostic 871 * API. 872 * 873 * Note that this is NOT the ANI commands being used via the INTMIT 874 * capability - that has a different mapping for some reason. 875 */ 876typedef enum { 877 HAL_ANI_PRESENT = 0, /* is ANI support present */ 878 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 879 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 880 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 881 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 882 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 883 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 884 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 885 HAL_ANI_MRC_CCK = 8, 886} HAL_ANI_CMD; 887 888#define HAL_ANI_ALL 0xffffffff 889 890/* 891 * This is the layout of the ANI INTMIT capability. 892 * 893 * Notice that the command values differ to HAL_ANI_CMD. 894 */ 895typedef enum { 896 HAL_CAP_INTMIT_PRESENT = 0, 897 HAL_CAP_INTMIT_ENABLE = 1, 898 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 899 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 900 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 901 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 902 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 903} HAL_CAP_INTMIT_CMD; 904 905typedef struct { 906 int32_t pe_firpwr; /* FIR pwr out threshold */ 907 int32_t pe_rrssi; /* Radar rssi thresh */ 908 int32_t pe_height; /* Pulse height thresh */ 909 int32_t pe_prssi; /* Pulse rssi thresh */ 910 int32_t pe_inband; /* Inband thresh */ 911 912 /* The following params are only for AR5413 and later */ 913 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 914 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 915 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 916 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 917 int32_t pe_blockradar; /* 918 * Enable to block radar check if pkt detect is done via OFDM 919 * weak signal detect or pkt is detected immediately after tx 920 * to rx transition 921 */ 922 int32_t pe_enmaxrssi; /* 923 * Enable to use the max rssi instead of the last rssi during 924 * fine gain changes for radar detection 925 */ 926 int32_t pe_extchannel; /* Enable DFS on ext channel */ 927 int32_t pe_enabled; /* Whether radar detection is enabled */ 928 int32_t pe_enrelpwr; 929 int32_t pe_en_relstep_check; 930} HAL_PHYERR_PARAM; 931 932#define HAL_PHYERR_PARAM_NOVAL 65535 933 934typedef struct { 935 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 936 u_int16_t ss_period; /* Spectral scan period */ 937 u_int16_t ss_count; /* # of reports to return from ss_active */ 938 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 939 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 940 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 941 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 942 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 943 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 944 int ss_enabled; 945 int ss_active; 946} HAL_SPECTRAL_PARAM; 947#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 948#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 949 950/* 951 * DFS operating mode flags. 952 */ 953typedef enum { 954 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 955 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 956 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 957 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 958} HAL_DFS_DOMAIN; 959 960 961/* 962 * MFP decryption options for initializing the MAC. 963 */ 964typedef enum { 965 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 966 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 967 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 968} HAL_MFP_OPT_T; 969 970/* LNA config supported */ 971typedef enum { 972 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 973 HAL_ANT_DIV_COMB_LNA2 = 1, 974 HAL_ANT_DIV_COMB_LNA1 = 2, 975 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 976} HAL_ANT_DIV_COMB_LNA_CONF; 977 978typedef struct { 979 u_int8_t main_lna_conf; 980 u_int8_t alt_lna_conf; 981 u_int8_t fast_div_bias; 982 u_int8_t main_gaintb; 983 u_int8_t alt_gaintb; 984 u_int8_t antdiv_configgroup; 985 int8_t lna1_lna2_delta; 986} HAL_ANT_COMB_CONFIG; 987 988#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 989#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 990#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 991#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 992 993/* 994 * Flag for setting QUIET period 995 */ 996typedef enum { 997 HAL_QUIET_DISABLE = 0x0, 998 HAL_QUIET_ENABLE = 0x1, 999 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1000 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1001} HAL_QUIET_FLAG; 1002 1003#define HAL_DFS_EVENT_PRICH 0x0000001 1004#define HAL_DFS_EVENT_EXTCH 0x0000002 1005#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1006#define HAL_DFS_EVENT_ISDC 0x0000008 1007 1008struct hal_dfs_event { 1009 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1010 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1011 uint8_t re_rssi; /* rssi of radar event */ 1012 uint8_t re_dur; /* duration of radar pulse */ 1013 uint32_t re_flags; /* Flags (see above) */ 1014}; 1015typedef struct hal_dfs_event HAL_DFS_EVENT; 1016 1017/* 1018 * Generic Timer domain 1019 */ 1020typedef enum { 1021 HAL_GEN_TIMER_TSF = 0, 1022 HAL_GEN_TIMER_TSF2, 1023 HAL_GEN_TIMER_TSF_ANY 1024} HAL_GEN_TIMER_DOMAIN; 1025 1026typedef enum { 1027 HAL_RESET_NONE = 0x0, 1028 HAL_RESET_BBPANIC = 0x1, 1029} HAL_RESET_TYPE; 1030 1031/* 1032 * BT Co-existence definitions 1033 */ 1034typedef enum { 1035 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1036 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1037 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1038 HAL_MAX_BT_MODULES 1039} HAL_BT_MODULE; 1040 1041typedef struct { 1042 HAL_BT_MODULE bt_module; 1043 u_int8_t bt_coex_config; 1044 u_int8_t bt_gpio_bt_active; 1045 u_int8_t bt_gpio_bt_priority; 1046 u_int8_t bt_gpio_wlan_active; 1047 u_int8_t bt_active_polarity; 1048 HAL_BOOL bt_single_ant; 1049 u_int8_t bt_dutyCycle; 1050 u_int8_t bt_isolation; 1051 u_int8_t bt_period; 1052} HAL_BT_COEX_INFO; 1053 1054typedef enum { 1055 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1056 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1057 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1058 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1059} HAL_BT_COEX_MODE; 1060 1061typedef enum { 1062 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1063 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1064 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1065 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1066 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1067 HAL_BT_COEX_CFG_MCI /* MCI */ 1068} HAL_BT_COEX_CFG; 1069 1070typedef enum { 1071 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1072 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1073 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1074} HAL_BT_COEX_SET_PARAMETER; 1075 1076#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1077#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1078/* Check Rx Diversity is allowed */ 1079#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1080/* Check Diversity is on or off */ 1081#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1082 1083#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1084/* main: LNA1, alt: LNA2 */ 1085#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1086#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1087#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1088#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1089#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1090 1091#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1092 1093#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1094 1095#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1096 1097#define HAL_BT_COEX_LOW_ACK_POWER 0x0 1098#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1099 1100typedef enum { 1101 HAL_BT_COEX_NO_STOMP = 0, 1102 HAL_BT_COEX_STOMP_ALL, 1103 HAL_BT_COEX_STOMP_LOW, 1104 HAL_BT_COEX_STOMP_NONE, 1105 HAL_BT_COEX_STOMP_ALL_FORCE, 1106 HAL_BT_COEX_STOMP_LOW_FORCE, 1107} HAL_BT_COEX_STOMP_TYPE; 1108 1109typedef struct { 1110 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1111 u_int8_t bt_time_extend; 1112 1113 /* 1114 * extend rx_clear as long as txsm is 1115 * transmitting or waiting for ack. 1116 */ 1117 HAL_BOOL bt_txstate_extend; 1118 1119 /* 1120 * extend rx_clear so that when tx_frame 1121 * is asserted, rx_clear will drop. 1122 */ 1123 HAL_BOOL bt_txframe_extend; 1124 1125 /* 1126 * coexistence mode 1127 */ 1128 HAL_BT_COEX_MODE bt_mode; 1129 1130 /* 1131 * treat BT high priority traffic as 1132 * a quiet collision 1133 */ 1134 HAL_BOOL bt_quiet_collision; 1135 1136 /* 1137 * invert rx_clear as WLAN_ACTIVE 1138 */ 1139 HAL_BOOL bt_rxclear_polarity; 1140 1141 /* 1142 * slotted mode only. indicate the time in usec 1143 * from the rising edge of BT_ACTIVE to the time 1144 * BT_PRIORITY can be sampled to indicate priority. 1145 */ 1146 u_int8_t bt_priority_time; 1147 1148 /* 1149 * slotted mode only. indicate the time in usec 1150 * from the rising edge of BT_ACTIVE to the time 1151 * BT_PRIORITY can be sampled to indicate tx/rx and 1152 * BT_FREQ is sampled. 1153 */ 1154 u_int8_t bt_first_slot_time; 1155 1156 /* 1157 * slotted mode only. rx_clear and bt_ant decision 1158 * will be held the entire time that BT_ACTIVE is asserted, 1159 * otherwise the decision is made before every slot boundry. 1160 */ 1161 HAL_BOOL bt_hold_rxclear; 1162} HAL_BT_COEX_CONFIG; 1163 1164struct hal_bb_panic_info { 1165 u_int32_t status; 1166 u_int32_t tsf; 1167 u_int32_t phy_panic_wd_ctl1; 1168 u_int32_t phy_panic_wd_ctl2; 1169 u_int32_t phy_gen_ctrl; 1170 u_int32_t rxc_pcnt; 1171 u_int32_t rxf_pcnt; 1172 u_int32_t txf_pcnt; 1173 u_int32_t cycles; 1174 u_int32_t wd; 1175 u_int32_t det; 1176 u_int32_t rdar; 1177 u_int32_t r_odfm; 1178 u_int32_t r_cck; 1179 u_int32_t t_odfm; 1180 u_int32_t t_cck; 1181 u_int32_t agc; 1182 u_int32_t src; 1183}; 1184 1185/* Serialize Register Access Mode */ 1186typedef enum { 1187 SER_REG_MODE_OFF = 0, 1188 SER_REG_MODE_ON = 1, 1189 SER_REG_MODE_AUTO = 2, 1190} SER_REG_MODE; 1191 1192typedef struct 1193{ 1194 int ah_debug; /* only used if AH_DEBUG is defined */ 1195 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1196 1197 /* NB: these are deprecated; they exist for now for compatibility */ 1198 int ah_dma_beacon_response_time;/* in TU's */ 1199 int ah_sw_beacon_response_time; /* in TU's */ 1200 int ah_additional_swba_backoff; /* in TU's */ 1201 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1202 int ah_serialise_reg_war; /* force serialisation of register IO */ 1203 1204 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1205 int ath_hal_desc_tpc; /* Per-packet TPC */ 1206 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1207 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1208 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1209 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1210 1211 /* I'm not sure what the default values for these should be */ 1212 int ath_hal_pll_pwr_save; 1213 int ath_hal_pcie_power_save_enable; 1214 int ath_hal_intr_mitigation_rx; 1215 int ath_hal_intr_mitigation_tx; 1216 1217 int ath_hal_pcie_clock_req; 1218#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1219#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1220#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1221 1222 int ath_hal_pcie_waen; 1223 int ath_hal_pcie_ser_des_write; 1224 1225 /* these are important for correct AR9300 behaviour */ 1226 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1227 int ath_hal_diversity_control; 1228 int ath_hal_antenna_switch_swap; 1229 int ath_hal_ext_lna_ctl_gpio; 1230 int ath_hal_spur_mode; 1231 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1232 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1233 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1234 1235 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1236 int ath_hal_mfp_support; 1237 1238 int ath_hal_enable_ani; /* should set this.. */ 1239 int ath_hal_cwm_ignore_ext_cca; 1240 int ath_hal_show_bb_panic; 1241 int ath_hal_ant_ctrl_comm2g_switch_enable; 1242 int ath_hal_ext_atten_margin_cfg; 1243 int ath_hal_war70c; 1244} HAL_OPS_CONFIG; 1245 1246/* 1247 * Hardware Access Layer (HAL) API. 1248 * 1249 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1250 * ath_hal structure for use with the device. Hardware-related operations 1251 * that follow must call back into the HAL through interface, supplying 1252 * the reference as the first parameter. Note that before using the 1253 * reference returned by ath_hal_attach the caller should verify the 1254 * ABI version number. 1255 */ 1256struct ath_hal { 1257 uint32_t ah_magic; /* consistency check magic number */ 1258 uint16_t ah_devid; /* PCI device ID */ 1259 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1260 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1261 HAL_BUS_TAG ah_st; /* params for register r+w */ 1262 HAL_BUS_HANDLE ah_sh; 1263 HAL_CTRY_CODE ah_countryCode; 1264 1265 uint32_t ah_macVersion; /* MAC version id */ 1266 uint16_t ah_macRev; /* MAC revision */ 1267 uint16_t ah_phyRev; /* PHY revision */ 1268 /* NB: when only one radio is present the rev is in 5Ghz */ 1269 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1270 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1271 1272 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1273 1274 uint32_t ah_intrstate[8]; /* last int state */ 1275 uint32_t ah_syncstate; /* last sync intr state */ 1276 1277 HAL_OPS_CONFIG ah_config; 1278 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1279 u_int mode); 1280 void __ahdecl(*ah_detach)(struct ath_hal*); 1281 1282 /* Reset functions */ 1283 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1284 struct ieee80211_channel *, 1285 HAL_BOOL bChannelChange, HAL_STATUS *status); 1286 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1287 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1288 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1289 HAL_BOOL power_off); 1290 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1291 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1292 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1293 struct ieee80211_channel *, HAL_BOOL *); 1294 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1295 struct ieee80211_channel *, u_int chainMask, 1296 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1297 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1298 const struct ieee80211_channel *); 1299 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1300 const struct ieee80211_channel *, uint16_t *); 1301 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1302 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1303 const struct ieee80211_channel *); 1304 1305 /* Transmit functions */ 1306 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1307 HAL_BOOL incTrigLevel); 1308 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1309 const HAL_TXQ_INFO *qInfo); 1310 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1311 const HAL_TXQ_INFO *qInfo); 1312 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1313 HAL_TXQ_INFO *qInfo); 1314 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1315 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1316 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1317 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1318 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1319 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1320 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1321 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1322 u_int pktLen, u_int hdrLen, 1323 HAL_PKT_TYPE type, u_int txPower, 1324 u_int txRate0, u_int txTries0, 1325 u_int keyIx, u_int antMode, u_int flags, 1326 u_int rtsctsRate, u_int rtsctsDuration, 1327 u_int compicvLen, u_int compivLen, 1328 u_int comp); 1329 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1330 u_int txRate1, u_int txTries1, 1331 u_int txRate2, u_int txTries2, 1332 u_int txRate3, u_int txTries3); 1333 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1334 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1335 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1336 HAL_BOOL lastSeg, const struct ath_desc *); 1337 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1338 struct ath_desc *, struct ath_tx_status *); 1339 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1340 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1341 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1342 const struct ath_desc *ds, int *rates, int *tries); 1343 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1344 uint32_t link); 1345 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1346 uint32_t *link); 1347 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1348 uint32_t **linkptr); 1349 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1350 void *ts_start, uint32_t ts_paddr_start, 1351 uint16_t size); 1352 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1353 1354 /* Receive Functions */ 1355 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1356 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1357 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1358 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1359 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1360 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1361 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1362 uint32_t filter0, uint32_t filter1); 1363 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1364 uint32_t index); 1365 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1366 uint32_t index); 1367 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1368 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1369 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1370 uint32_t size, u_int flags); 1371 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1372 struct ath_desc *, uint32_t phyAddr, 1373 struct ath_desc *next, uint64_t tsf, 1374 struct ath_rx_status *); 1375 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1376 const HAL_NODE_STATS *, 1377 const struct ieee80211_channel *); 1378 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1379 const struct ieee80211_channel *); 1380 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1381 const HAL_NODE_STATS *); 1382 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1383 struct ath_rx_status *, 1384 unsigned long, int); 1385 1386 /* Misc Functions */ 1387 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1388 HAL_CAPABILITY_TYPE, uint32_t capability, 1389 uint32_t *result); 1390 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1391 HAL_CAPABILITY_TYPE, uint32_t capability, 1392 uint32_t setting, HAL_STATUS *); 1393 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1394 const void *args, uint32_t argsize, 1395 void **result, uint32_t *resultsize); 1396 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1397 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1398 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1399 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1400 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1401 uint16_t, HAL_STATUS *); 1402 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1403 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1404 const uint8_t *bssid, uint16_t assocId); 1405 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1406 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1407 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1408 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1409 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1410 uint32_t gpio, uint32_t val); 1411 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1412 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1413 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1414 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1415 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1416 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1417 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1418 HAL_MIB_STATS*); 1419 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1420 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1421 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1422 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1423 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1424 HAL_ANT_SETTING); 1425 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1426 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1427 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1428 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1429 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1430 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1431 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1432 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1433 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1434 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1435 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1436 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1437 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1438 uint32_t duration, uint32_t nextStart, 1439 HAL_QUIET_FLAG flag); 1440 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1441 uint32_t, uint32_t); 1442 1443 /* DFS functions */ 1444 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1445 HAL_PHYERR_PARAM *pe); 1446 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1447 HAL_PHYERR_PARAM *pe); 1448 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1449 HAL_PHYERR_PARAM *pe); 1450 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1451 struct ath_rx_status *rxs, uint64_t fulltsf, 1452 const char *buf, HAL_DFS_EVENT *event); 1453 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1454 1455 /* Spectral Scan functions */ 1456 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1457 HAL_SPECTRAL_PARAM *sp); 1458 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1459 HAL_SPECTRAL_PARAM *sp); 1460 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1461 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1462 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1463 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1464 /* XXX getNfPri() and getNfExt() */ 1465 1466 /* Key Cache Functions */ 1467 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1468 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1469 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1470 uint16_t); 1471 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1472 uint16_t, const HAL_KEYVAL *, 1473 const uint8_t *, int); 1474 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1475 uint16_t, const uint8_t *); 1476 1477 /* Power Management Functions */ 1478 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1479 HAL_POWER_MODE mode, int setChip); 1480 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1481 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1482 const struct ieee80211_channel *); 1483 1484 /* Beacon Management Functions */ 1485 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1486 const HAL_BEACON_TIMERS *); 1487 /* NB: deprecated, use ah_setBeaconTimers instead */ 1488 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1489 uint32_t nexttbtt, uint32_t intval); 1490 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1491 const HAL_BEACON_STATE *); 1492 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1493 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1494 1495 /* 802.11n Functions */ 1496 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1497 struct ath_desc *, 1498 HAL_DMA_ADDR *bufAddrList, 1499 uint32_t *segLenList, 1500 u_int, u_int, HAL_PKT_TYPE, 1501 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1502 HAL_BOOL, HAL_BOOL); 1503 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1504 struct ath_desc *, u_int, u_int, u_int, 1505 u_int, u_int, u_int, u_int, u_int); 1506 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1507 struct ath_desc *, const struct ath_desc *); 1508 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1509 struct ath_desc *, u_int, u_int, 1510 HAL_11N_RATE_SERIES [], u_int, u_int); 1511 1512 /* 1513 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1514 * to the EDMA HAL. Descriptors are chained together by 1515 * using filltxdesc (not ChainTxDesc) and then setting the 1516 * aggregate flags appropriately using first/middle/last. 1517 */ 1518 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1519 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1520 u_int); 1521 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1522 struct ath_desc *, u_int, u_int); 1523 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1524 struct ath_desc *, u_int); 1525 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1526 struct ath_desc *); 1527 1528 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1529 struct ath_desc *); 1530 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1531 struct ath_desc *, u_int); 1532 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1533 HAL_SURVEY_SAMPLE *); 1534 1535 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1536 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1537 HAL_HT_MACMODE); 1538 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1539 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1540 HAL_HT_RXCLEAR); 1541 1542 /* Interrupt functions */ 1543 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1544 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1545 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1546 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1547 1548 /* Bluetooth Coexistence functions */ 1549 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1550 HAL_BT_COEX_INFO *); 1551 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1552 HAL_BT_COEX_CONFIG *); 1553 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1554 int); 1555 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1556 uint32_t); 1557 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1558 uint32_t); 1559 void __ahdecl(*ah_btcoexSetParameter)(struct ath_hal *, 1560 uint32_t, uint32_t); 1561 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1562 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1563}; 1564 1565/* 1566 * Check the PCI vendor ID and device ID against Atheros' values 1567 * and return a printable description for any Atheros hardware. 1568 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1569 */ 1570extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1571 1572/* 1573 * Attach the HAL for use with the specified device. The device is 1574 * defined by the PCI device ID. The caller provides an opaque pointer 1575 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1576 * HAL state block for later use. Hardware register accesses are done 1577 * using the specified bus tag and handle. On successful return a 1578 * reference to a state block is returned that must be supplied in all 1579 * subsequent HAL calls. Storage associated with this reference is 1580 * dynamically allocated and must be freed by calling the ah_detach 1581 * method when the client is done. If the attach operation fails a 1582 * null (AH_NULL) reference will be returned and a status code will 1583 * be returned if the status parameter is non-zero. 1584 */ 1585extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1586 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1587 1588extern const char *ath_hal_mac_name(struct ath_hal *); 1589extern const char *ath_hal_rf_name(struct ath_hal *); 1590 1591/* 1592 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1593 * request a set of channels for a particular country code and/or 1594 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1595 * this list is constructed according to the contents of the EEPROM. 1596 * ath_hal_getchannels acts similarly but does not alter the operating 1597 * state; this can be used to collect information for a particular 1598 * regulatory configuration. Finally ath_hal_set_channels installs a 1599 * channel list constructed outside the driver. The HAL will adopt the 1600 * channel list and setup internal state according to the specified 1601 * regulatory configuration (e.g. conformance test limits). 1602 * 1603 * For all interfaces the channel list is returned in the supplied array. 1604 * maxchans defines the maximum size of this array. nchans contains the 1605 * actual number of channels returned. If a problem occurred then a 1606 * status code != HAL_OK is returned. 1607 */ 1608struct ieee80211_channel; 1609 1610/* 1611 * Return a list of channels according to the specified regulatory. 1612 */ 1613extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1614 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1615 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1616 HAL_BOOL enableExtendedChannels); 1617 1618/* 1619 * Return a list of channels and install it as the current operating 1620 * regulatory list. 1621 */ 1622extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1623 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1624 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1625 HAL_BOOL enableExtendedChannels); 1626 1627/* 1628 * Install the list of channels as the current operating regulatory 1629 * and setup related state according to the country code and sku. 1630 */ 1631extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1632 struct ieee80211_channel *chans, int nchans, 1633 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1634 1635/* 1636 * Fetch the ctl/ext noise floor values reported by a MIMO 1637 * radio. Returns 1 for valid results, 0 for invalid channel. 1638 */ 1639extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1640 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1641 int16_t *nf_ext); 1642 1643/* 1644 * Calibrate noise floor data following a channel scan or similar. 1645 * This must be called prior retrieving noise floor data. 1646 */ 1647extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1648 1649/* 1650 * Return bit mask of wireless modes supported by the hardware. 1651 */ 1652extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1653 1654/* 1655 * Get the HAL wireless mode for the given channel. 1656 */ 1657extern int ath_hal_get_curmode(struct ath_hal *ah, 1658 const struct ieee80211_channel *chan); 1659 1660/* 1661 * Calculate the packet TX time for a legacy or 11n frame 1662 */ 1663extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1664 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1665 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1666 1667/* 1668 * Calculate the duration of an 11n frame. 1669 */ 1670extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1671 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1672 1673/* 1674 * Calculate the transmit duration of a legacy frame. 1675 */ 1676extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1677 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1678 uint16_t rateix, HAL_BOOL shortPreamble); 1679 1680/* 1681 * Adjust the TSF. 1682 */ 1683extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1684 1685/* 1686 * Enable or disable CCA. 1687 */ 1688void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1689 1690/* 1691 * Get CCA setting. 1692 */ 1693int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1694 1695/* 1696 * Read EEPROM data from ah_eepromdata 1697 */ 1698HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1699 u_int off, uint16_t *data); 1700 1701/* 1702 * For now, simply pass through MFP frames. 1703 */ 1704static inline u_int32_t 1705ath_hal_get_mfp_qos(struct ath_hal *ah) 1706{ 1707 //return AH_PRIVATE(ah)->ah_mfp_qos; 1708 return HAL_MFP_QOSDATA; 1709} 1710 1711#endif /* _ATH_AH_H_ */ 1712