1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77} HAL_STATUS; 78 79typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_RX_STBC = 58, 141 HAL_CAP_TX_STBC = 59, 142 143 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145 146 HAL_CAP_DS = 67, /* 2 stream */ 147 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150 151 HAL_CAP_TS = 72, /* 3 stream */ 152 153 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163 164 HAL_CAP_BB_PANIC_WATCHDOG = 92, 165 166 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167 168 HAL_CAP_LDPC = 99, 169 170 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171 172 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 173 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 174 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 175 HAL_CAP_LDPCWAR = 108, 176 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 177 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 178 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 179 HAL_CAP_PCIE_LCR_OFFSET = 112, 180 181 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 182 HAL_CAP_MCI = 118, 183 HAL_CAP_SMARTANTENNA = 119, 184 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 185 HAL_CAP_TX_DIVERSITY = 121, 186 HAL_CAP_CRDC = 122, 187 188 /* The following are private to the FreeBSD HAL (224 onward) */ 189 190 HAL_CAP_INTMIT = 229, /* interference mitigation */ 191 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 192 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 193 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 194 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 195 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 196 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 197 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 198 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 199 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 200 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 201 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 202 HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 203} HAL_CAPABILITY_TYPE; 204 205/* 206 * "States" for setting the LED. These correspond to 207 * the possible 802.11 operational states and there may 208 * be a many-to-one mapping between these states and the 209 * actual hardware state for the LED's (i.e. the hardware 210 * may have fewer states). 211 */ 212typedef enum { 213 HAL_LED_INIT = 0, 214 HAL_LED_SCAN = 1, 215 HAL_LED_AUTH = 2, 216 HAL_LED_ASSOC = 3, 217 HAL_LED_RUN = 4 218} HAL_LED_STATE; 219 220/* 221 * Transmit queue types/numbers. These are used to tag 222 * each transmit queue in the hardware and to identify a set 223 * of transmit queues for operations such as start/stop dma. 224 */ 225typedef enum { 226 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 227 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 228 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 229 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 230 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 231 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 232 HAL_TX_QUEUE_CFEND = 6, 233 HAL_TX_QUEUE_PAPRD = 7, 234} HAL_TX_QUEUE; 235 236#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 237 238/* 239 * Receive queue types. These are used to tag 240 * each transmit queue in the hardware and to identify a set 241 * of transmit queues for operations such as start/stop dma. 242 */ 243typedef enum { 244 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 245 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 246} HAL_RX_QUEUE; 247 248#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 249 250#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 251 252/* 253 * Transmit queue subtype. These map directly to 254 * WME Access Categories (except for UPSD). Refer 255 * to Table 5 of the WME spec. 256 */ 257typedef enum { 258 HAL_WME_AC_BK = 0, /* background access category */ 259 HAL_WME_AC_BE = 1, /* best effort access category*/ 260 HAL_WME_AC_VI = 2, /* video access category */ 261 HAL_WME_AC_VO = 3, /* voice access category */ 262 HAL_WME_UPSD = 4, /* uplink power save */ 263} HAL_TX_QUEUE_SUBTYPE; 264 265/* 266 * Transmit queue flags that control various 267 * operational parameters. 268 */ 269typedef enum { 270 /* 271 * Per queue interrupt enables. When set the associated 272 * interrupt may be delivered for packets sent through 273 * the queue. Without these enabled no interrupts will 274 * be delivered for transmits through the queue. 275 */ 276 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 277 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 278 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 279 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 280 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 281 /* 282 * Enable hardware compression for packets sent through 283 * the queue. The compression buffer must be setup and 284 * packets must have a key entry marked in the tx descriptor. 285 */ 286 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 287 /* 288 * Disable queue when veol is hit or ready time expires. 289 * By default the queue is disabled only on reaching the 290 * physical end of queue (i.e. a null link ptr in the 291 * descriptor chain). 292 */ 293 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 294 /* 295 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 296 * event. Frames will be transmitted only when this timer 297 * fires, e.g to transmit a beacon in ap or adhoc modes. 298 */ 299 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 300 /* 301 * Each transmit queue has a counter that is incremented 302 * each time the queue is enabled and decremented when 303 * the list of frames to transmit is traversed (or when 304 * the ready time for the queue expires). This counter 305 * must be non-zero for frames to be scheduled for 306 * transmission. The following controls disable bumping 307 * this counter under certain conditions. Typically this 308 * is used to gate frames based on the contents of another 309 * queue (e.g. CAB traffic may only follow a beacon frame). 310 * These are meaningful only when frames are scheduled 311 * with a non-ASAP policy (e.g. DBA-gated). 312 */ 313 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 314 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 315 316 /* 317 * Fragment burst backoff policy. Normally the no backoff 318 * is done after a successful transmission, the next fragment 319 * is sent at SIFS. If this flag is set backoff is done 320 * after each fragment, regardless whether it was ack'd or 321 * not, after the backoff count reaches zero a normal channel 322 * access procedure is done before the next transmit (i.e. 323 * wait AIFS instead of SIFS). 324 */ 325 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 326 /* 327 * Disable post-tx backoff following each frame. 328 */ 329 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 330 /* 331 * DCU arbiter lockout control. This controls how 332 * lower priority tx queues are handled with respect to 333 * to a specific queue when multiple queues have frames 334 * to send. No lockout means lower priority queues arbitrate 335 * concurrently with this queue. Intra-frame lockout 336 * means lower priority queues are locked out until the 337 * current frame transmits (e.g. including backoffs and bursting). 338 * Global lockout means nothing lower can arbitrary so 339 * long as there is traffic activity on this queue (frames, 340 * backoff, etc). 341 */ 342 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 343 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 344 345 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 346 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 347} HAL_TX_QUEUE_FLAGS; 348 349typedef struct { 350 uint32_t tqi_ver; /* hal TXQ version */ 351 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 352 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 353 uint32_t tqi_priority; /* (not used) */ 354 uint32_t tqi_aifs; /* aifs */ 355 uint32_t tqi_cwmin; /* cwMin */ 356 uint32_t tqi_cwmax; /* cwMax */ 357 uint16_t tqi_shretry; /* rts retry limit */ 358 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 359 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 360 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 361 uint32_t tqi_burstTime; /* max burst duration (us) */ 362 uint32_t tqi_readyTime; /* frame schedule time (us) */ 363 uint32_t tqi_compBuf; /* comp buffer phys addr */ 364} HAL_TXQ_INFO; 365 366#define HAL_TQI_NONVAL 0xffff 367 368/* token to use for aifs, cwmin, cwmax */ 369#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 370 371/* compression definitions */ 372#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 373#define HAL_COMP_BUF_ALIGN_SIZE 512 374 375/* 376 * Transmit packet types. This belongs in ah_desc.h, but 377 * is here so we can give a proper type to various parameters 378 * (and not require everyone include the file). 379 * 380 * NB: These values are intentionally assigned for 381 * direct use when setting up h/w descriptors. 382 */ 383typedef enum { 384 HAL_PKT_TYPE_NORMAL = 0, 385 HAL_PKT_TYPE_ATIM = 1, 386 HAL_PKT_TYPE_PSPOLL = 2, 387 HAL_PKT_TYPE_BEACON = 3, 388 HAL_PKT_TYPE_PROBE_RESP = 4, 389 HAL_PKT_TYPE_CHIRP = 5, 390 HAL_PKT_TYPE_GRP_POLL = 6, 391 HAL_PKT_TYPE_AMPDU = 7, 392} HAL_PKT_TYPE; 393 394/* Rx Filter Frame Types */ 395typedef enum { 396 /* 397 * These bits correspond to AR_RX_FILTER for all chips. 398 * Not all bits are supported by all chips. 399 */ 400 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 401 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 402 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 403 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 404 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 405 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 406 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 407 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 408 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 409 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 410 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 411 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 412 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 413 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 414 /* Allow all mcast/bcast frames */ 415 416 /* 417 * Magic RX filter flags that aren't targeting hardware bits 418 * but instead the HAL sets individual bits - eg PHYERR will result 419 * in OFDM/CCK timing error frames being received. 420 */ 421 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 422} HAL_RX_FILTER; 423 424typedef enum { 425 HAL_PM_AWAKE = 0, 426 HAL_PM_FULL_SLEEP = 1, 427 HAL_PM_NETWORK_SLEEP = 2, 428 HAL_PM_UNDEFINED = 3 429} HAL_POWER_MODE; 430 431/* 432 * Enterprise mode flags 433 */ 434#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 435#define AH_ENT_CHAIN2_DISABLE 0x00000002 436#define AH_ENT_5MHZ_DISABLE 0x00000004 437#define AH_ENT_10MHZ_DISABLE 0x00000008 438#define AH_ENT_49GHZ_DISABLE 0x00000010 439#define AH_ENT_LOOPBACK_DISABLE 0x00000020 440#define AH_ENT_TPC_PERF_DISABLE 0x00000040 441#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 442#define AH_ENT_SPECTRAL_PRECISION 0x00000300 443#define AH_ENT_SPECTRAL_PRECISION_S 8 444#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 445 446#define AH_FIRST_DESC_NDELIMS 60 447 448/* 449 * NOTE WELL: 450 * These are mapped to take advantage of the common locations for many of 451 * the bits on all of the currently supported MAC chips. This is to make 452 * the ISR as efficient as possible, while still abstracting HW differences. 453 * When new hardware breaks this commonality this enumerated type, as well 454 * as the HAL functions using it, must be modified. All values are directly 455 * mapped unless commented otherwise. 456 */ 457typedef enum { 458 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 459 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 460 HAL_INT_RXERR = 0x00000004, 461 HAL_INT_RXHP = 0x00000001, /* EDMA */ 462 HAL_INT_RXLP = 0x00000002, /* EDMA */ 463 HAL_INT_RXNOFRM = 0x00000008, 464 HAL_INT_RXEOL = 0x00000010, 465 HAL_INT_RXORN = 0x00000020, 466 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 467 HAL_INT_TXDESC = 0x00000080, 468 HAL_INT_TIM_TIMER= 0x00000100, 469 HAL_INT_MCI = 0x00000200, 470 HAL_INT_BBPANIC = 0x00000400, 471 HAL_INT_TXURN = 0x00000800, 472 HAL_INT_MIB = 0x00001000, 473 HAL_INT_RXPHY = 0x00004000, 474 HAL_INT_RXKCM = 0x00008000, 475 HAL_INT_SWBA = 0x00010000, 476 HAL_INT_BRSSI = 0x00020000, 477 HAL_INT_BMISS = 0x00040000, 478 HAL_INT_BNR = 0x00100000, 479 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 480 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 481 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 482 HAL_INT_GPIO = 0x01000000, 483 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 484 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 485 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 486 /* Atheros ref driver has a generic timer interrupt now..*/ 487 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 488 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 489 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 490 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 491#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 492 HAL_INT_BMISC = HAL_INT_TIM 493 | HAL_INT_DTIM 494 | HAL_INT_DTIMSYNC 495 | HAL_INT_CABEND 496 | HAL_INT_TBTT, 497 498 /* Interrupt bits that map directly to ISR/IMR bits */ 499 HAL_INT_COMMON = HAL_INT_RXNOFRM 500 | HAL_INT_RXDESC 501 | HAL_INT_RXEOL 502 | HAL_INT_RXORN 503 | HAL_INT_TXDESC 504 | HAL_INT_TXURN 505 | HAL_INT_MIB 506 | HAL_INT_RXPHY 507 | HAL_INT_RXKCM 508 | HAL_INT_SWBA 509 | HAL_INT_BMISS 510 | HAL_INT_BRSSI 511 | HAL_INT_BNR 512 | HAL_INT_GPIO, 513} HAL_INT; 514 515/* 516 * MSI vector assignments 517 */ 518typedef enum { 519 HAL_MSIVEC_MISC = 0, 520 HAL_MSIVEC_TX = 1, 521 HAL_MSIVEC_RXLP = 2, 522 HAL_MSIVEC_RXHP = 3, 523} HAL_MSIVEC; 524 525typedef enum { 526 HAL_INT_LINE = 0, 527 HAL_INT_MSI = 1, 528} HAL_INT_TYPE; 529 530/* For interrupt mitigation registers */ 531typedef enum { 532 HAL_INT_RX_FIRSTPKT=0, 533 HAL_INT_RX_LASTPKT, 534 HAL_INT_TX_FIRSTPKT, 535 HAL_INT_TX_LASTPKT, 536 HAL_INT_THRESHOLD 537} HAL_INT_MITIGATION; 538 539/* XXX this is duplicate information! */ 540typedef struct { 541 u_int32_t cyclecnt_diff; /* delta cycle count */ 542 u_int32_t rxclr_cnt; /* rx clear count */ 543 u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 544 u_int32_t txframecnt_diff; /* delta tx frame count */ 545 u_int32_t rxframecnt_diff; /* delta rx frame count */ 546 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 547 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 548 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 549 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 550 HAL_BOOL valid; /* if the stats are valid*/ 551} HAL_ANISTATS; 552 553typedef struct { 554 u_int8_t txctl_offset; 555 u_int8_t txctl_numwords; 556 u_int8_t txstatus_offset; 557 u_int8_t txstatus_numwords; 558 559 u_int8_t rxctl_offset; 560 u_int8_t rxctl_numwords; 561 u_int8_t rxstatus_offset; 562 u_int8_t rxstatus_numwords; 563 564 u_int8_t macRevision; 565} HAL_DESC_INFO; 566 567typedef enum { 568 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 569 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 570 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 571 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 572 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 573 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 574 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 575 576 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 577 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 578 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 579 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 580 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 581 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 582 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 583 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 584 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 585 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 586 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 587 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 588 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 589 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 590} HAL_GPIO_MUX_TYPE; 591 592typedef enum { 593 HAL_GPIO_INTR_LOW = 0, 594 HAL_GPIO_INTR_HIGH = 1, 595 HAL_GPIO_INTR_DISABLE = 2 596} HAL_GPIO_INTR_TYPE; 597 598typedef struct halCounters { 599 u_int32_t tx_frame_count; 600 u_int32_t rx_frame_count; 601 u_int32_t rx_clear_count; 602 u_int32_t cycle_count; 603 u_int8_t is_rx_active; // true (1) or false (0) 604 u_int8_t is_tx_active; // true (1) or false (0) 605} HAL_COUNTERS; 606 607typedef enum { 608 HAL_RFGAIN_INACTIVE = 0, 609 HAL_RFGAIN_READ_REQUESTED = 1, 610 HAL_RFGAIN_NEED_CHANGE = 2 611} HAL_RFGAIN; 612 613typedef uint16_t HAL_CTRY_CODE; /* country code */ 614typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 615 616#define HAL_ANTENNA_MIN_MODE 0 617#define HAL_ANTENNA_FIXED_A 1 618#define HAL_ANTENNA_FIXED_B 2 619#define HAL_ANTENNA_MAX_MODE 3 620 621typedef struct { 622 uint32_t ackrcv_bad; 623 uint32_t rts_bad; 624 uint32_t rts_good; 625 uint32_t fcs_bad; 626 uint32_t beacons; 627} HAL_MIB_STATS; 628 629/* 630 * These bits represent what's in ah_currentRDext. 631 */ 632typedef enum { 633 REG_EXT_FCC_MIDBAND = 0, 634 REG_EXT_JAPAN_MIDBAND = 1, 635 REG_EXT_FCC_DFS_HT40 = 2, 636 REG_EXT_JAPAN_NONDFS_HT40 = 3, 637 REG_EXT_JAPAN_DFS_HT40 = 4 638} REG_EXT_BITMAP; 639 640enum { 641 HAL_MODE_11A = 0x001, /* 11a channels */ 642 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 643 HAL_MODE_11B = 0x004, /* 11b channels */ 644 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 645#ifdef notdef 646 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 647#else 648 HAL_MODE_11G = 0x008, /* XXX historical */ 649#endif 650 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 651 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 652 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 653 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 654 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 655 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 656 HAL_MODE_11NG_HT20 = 0x008000, 657 HAL_MODE_11NA_HT20 = 0x010000, 658 HAL_MODE_11NG_HT40PLUS = 0x020000, 659 HAL_MODE_11NG_HT40MINUS = 0x040000, 660 HAL_MODE_11NA_HT40PLUS = 0x080000, 661 HAL_MODE_11NA_HT40MINUS = 0x100000, 662 HAL_MODE_ALL = 0xffffff 663}; 664 665typedef struct { 666 int rateCount; /* NB: for proper padding */ 667 uint8_t rateCodeToIndex[256]; /* back mapping */ 668 struct { 669 uint8_t valid; /* valid for rate control use */ 670 uint8_t phy; /* CCK/OFDM/XR */ 671 uint32_t rateKbps; /* transfer rate in kbs */ 672 uint8_t rateCode; /* rate for h/w descriptors */ 673 uint8_t shortPreamble; /* mask for enabling short 674 * preamble in CCK rate code */ 675 uint8_t dot11Rate; /* value for supported rates 676 * info element of MLME */ 677 uint8_t controlRate; /* index of next lower basic 678 * rate; used for dur. calcs */ 679 uint16_t lpAckDuration; /* long preamble ACK duration */ 680 uint16_t spAckDuration; /* short preamble ACK duration*/ 681 } info[64]; 682} HAL_RATE_TABLE; 683 684typedef struct { 685 u_int rs_count; /* number of valid entries */ 686 uint8_t rs_rates[64]; /* rates */ 687} HAL_RATE_SET; 688 689/* 690 * 802.11n specific structures and enums 691 */ 692typedef enum { 693 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 694 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 695} HAL_CHAIN_TYPE; 696 697typedef struct { 698 u_int Tries; 699 u_int Rate; /* hardware rate code */ 700 u_int RateIndex; /* rate series table index */ 701 u_int PktDuration; 702 u_int ChSel; 703 u_int RateFlags; 704#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 705#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 706#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 707#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 708 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 709} HAL_11N_RATE_SERIES; 710 711typedef enum { 712 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 713 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 714} HAL_HT_MACMODE; 715 716typedef enum { 717 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 718 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 719} HAL_HT_PHYMODE; 720 721typedef enum { 722 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 723 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 724} HAL_HT_EXTPROTSPACING; 725 726 727typedef enum { 728 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 729 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 730} HAL_HT_RXCLEAR; 731 732typedef enum { 733 HAL_FREQ_BAND_5GHZ = 0, 734 HAL_FREQ_BAND_2GHZ = 1, 735} HAL_FREQ_BAND; 736 737/* 738 * Antenna switch control. By default antenna selection 739 * enables multiple (2) antenna use. To force use of the 740 * A or B antenna only specify a fixed setting. Fixing 741 * the antenna will also disable any diversity support. 742 */ 743typedef enum { 744 HAL_ANT_VARIABLE = 0, /* variable by programming */ 745 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 746 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 747} HAL_ANT_SETTING; 748 749typedef enum { 750 HAL_M_STA = 1, /* infrastructure station */ 751 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 752 HAL_M_HOSTAP = 6, /* Software Access Point */ 753 HAL_M_MONITOR = 8 /* Monitor mode */ 754} HAL_OPMODE; 755 756typedef enum { 757 HAL_RESET_NORMAL = 0, /* Do normal reset */ 758 HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 759 HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 760} HAL_RESET_TYPE; 761 762typedef struct { 763 uint8_t kv_type; /* one of HAL_CIPHER */ 764 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 765 uint16_t kv_len; /* length in bits */ 766 uint8_t kv_val[16]; /* enough for 128-bit keys */ 767 uint8_t kv_mic[8]; /* TKIP MIC key */ 768 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 769} HAL_KEYVAL; 770 771/* 772 * This is the TX descriptor field which marks the key padding requirement. 773 * The naming is unfortunately unclear. 774 */ 775#define AH_KEYTYPE_MASK 0x0F 776typedef enum { 777 HAL_KEY_TYPE_CLEAR, 778 HAL_KEY_TYPE_WEP, 779 HAL_KEY_TYPE_AES, 780 HAL_KEY_TYPE_TKIP, 781} HAL_KEY_TYPE; 782 783typedef enum { 784 HAL_CIPHER_WEP = 0, 785 HAL_CIPHER_AES_OCB = 1, 786 HAL_CIPHER_AES_CCM = 2, 787 HAL_CIPHER_CKIP = 3, 788 HAL_CIPHER_TKIP = 4, 789 HAL_CIPHER_CLR = 5, /* no encryption */ 790 791 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 792} HAL_CIPHER; 793 794enum { 795 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 796 HAL_SLOT_TIME_9 = 9, 797 HAL_SLOT_TIME_20 = 20, 798}; 799 800/* 801 * Per-station beacon timer state. Note that the specified 802 * beacon interval (given in TU's) can also include flags 803 * to force a TSF reset and to enable the beacon xmit logic. 804 * If bs_cfpmaxduration is non-zero the hardware is setup to 805 * coexist with a PCF-capable AP. 806 */ 807typedef struct { 808 uint32_t bs_nexttbtt; /* next beacon in TU */ 809 uint32_t bs_nextdtim; /* next DTIM in TU */ 810 uint32_t bs_intval; /* beacon interval+flags */ 811/* 812 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 813 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 814 * register. 815 */ 816#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 817#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 818#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 819#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 820#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 821 uint32_t bs_dtimperiod; 822 uint16_t bs_cfpperiod; /* CFP period in TU */ 823 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 824 uint32_t bs_cfpnext; /* next CFP in TU */ 825 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 826 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 827 uint32_t bs_sleepduration; /* max sleep duration */ 828 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 829} HAL_BEACON_STATE; 830 831/* 832 * Like HAL_BEACON_STATE but for non-station mode setup. 833 * NB: see above flag definitions for bt_intval. 834 */ 835typedef struct { 836 uint32_t bt_intval; /* beacon interval+flags */ 837 uint32_t bt_nexttbtt; /* next beacon in TU */ 838 uint32_t bt_nextatim; /* next ATIM in TU */ 839 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 840 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 841 uint32_t bt_flags; /* timer enables */ 842#define HAL_BEACON_TBTT_EN 0x00000001 843#define HAL_BEACON_DBA_EN 0x00000002 844#define HAL_BEACON_SWBA_EN 0x00000004 845} HAL_BEACON_TIMERS; 846 847/* 848 * Per-node statistics maintained by the driver for use in 849 * optimizing signal quality and other operational aspects. 850 */ 851typedef struct { 852 uint32_t ns_avgbrssi; /* average beacon rssi */ 853 uint32_t ns_avgrssi; /* average data rssi */ 854 uint32_t ns_avgtxrssi; /* average tx rssi */ 855} HAL_NODE_STATS; 856 857#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 858 859/* 860 * This is the ANI state and MIB stats. 861 * 862 * It's used by the HAL modules to keep state /and/ by the debug ioctl 863 * to fetch ANI information. 864 */ 865typedef struct { 866 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 867 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 868 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 869 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 870 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 871 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 872 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 873 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 874 uint32_t ast_ani_stepup; /* ANI increased first step level */ 875 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 876 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 877 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 878 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 879 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 880 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 881 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 882 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 883} HAL_ANI_STATS; 884 885typedef struct { 886 uint8_t noiseImmunityLevel; 887 uint8_t spurImmunityLevel; 888 uint8_t firstepLevel; 889 uint8_t ofdmWeakSigDetectOff; 890 uint8_t cckWeakSigThreshold; 891 uint32_t listenTime; 892 893 /* NB: intentionally ordered so data exported to user space is first */ 894 uint32_t txFrameCount; /* Last txFrameCount */ 895 uint32_t rxFrameCount; /* Last rx Frame count */ 896 uint32_t cycleCount; /* Last cycleCount 897 (to detect wrap-around) */ 898 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 899 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 900} HAL_ANI_STATE; 901 902struct ath_desc; 903struct ath_tx_status; 904struct ath_rx_status; 905struct ieee80211_channel; 906 907/* 908 * This is a channel survey sample entry. 909 * 910 * The AR5212 ANI routines fill these samples. The ANI code then uses it 911 * when calculating listen time; it is also exported via a diagnostic 912 * API. 913 */ 914typedef struct { 915 uint32_t seq_num; 916 uint32_t tx_busy; 917 uint32_t rx_busy; 918 uint32_t chan_busy; 919 uint32_t ext_chan_busy; 920 uint32_t cycle_count; 921 /* XXX TODO */ 922 uint32_t ofdm_phyerr_count; 923 uint32_t cck_phyerr_count; 924} HAL_SURVEY_SAMPLE; 925 926/* 927 * This provides 3.2 seconds of sample space given an 928 * ANI time of 1/10th of a second. This may not be enough! 929 */ 930#define CHANNEL_SURVEY_SAMPLE_COUNT 32 931 932typedef struct { 933 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 934 uint32_t cur_sample; /* current sample in sequence */ 935 uint32_t cur_seq; /* current sequence number */ 936} HAL_CHANNEL_SURVEY; 937 938/* 939 * ANI commands. 940 * 941 * These are used both internally and externally via the diagnostic 942 * API. 943 * 944 * Note that this is NOT the ANI commands being used via the INTMIT 945 * capability - that has a different mapping for some reason. 946 */ 947typedef enum { 948 HAL_ANI_PRESENT = 0, /* is ANI support present */ 949 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 950 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 951 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 952 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 953 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 954 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 955 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 956 HAL_ANI_MRC_CCK = 8, 957} HAL_ANI_CMD; 958 959#define HAL_ANI_ALL 0xffffffff 960 961/* 962 * This is the layout of the ANI INTMIT capability. 963 * 964 * Notice that the command values differ to HAL_ANI_CMD. 965 */ 966typedef enum { 967 HAL_CAP_INTMIT_PRESENT = 0, 968 HAL_CAP_INTMIT_ENABLE = 1, 969 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 970 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 971 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 972 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 973 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 974} HAL_CAP_INTMIT_CMD; 975 976typedef struct { 977 int32_t pe_firpwr; /* FIR pwr out threshold */ 978 int32_t pe_rrssi; /* Radar rssi thresh */ 979 int32_t pe_height; /* Pulse height thresh */ 980 int32_t pe_prssi; /* Pulse rssi thresh */ 981 int32_t pe_inband; /* Inband thresh */ 982 983 /* The following params are only for AR5413 and later */ 984 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 985 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 986 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 987 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 988 int32_t pe_blockradar; /* 989 * Enable to block radar check if pkt detect is done via OFDM 990 * weak signal detect or pkt is detected immediately after tx 991 * to rx transition 992 */ 993 int32_t pe_enmaxrssi; /* 994 * Enable to use the max rssi instead of the last rssi during 995 * fine gain changes for radar detection 996 */ 997 int32_t pe_extchannel; /* Enable DFS on ext channel */ 998 int32_t pe_enabled; /* Whether radar detection is enabled */ 999 int32_t pe_enrelpwr; 1000 int32_t pe_en_relstep_check; 1001} HAL_PHYERR_PARAM; 1002 1003#define HAL_PHYERR_PARAM_NOVAL 65535 1004 1005typedef struct { 1006 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1007 u_int16_t ss_period; /* Spectral scan period */ 1008 u_int16_t ss_count; /* # of reports to return from ss_active */ 1009 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 1010 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1011 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1012 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1013 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1014 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1015 int ss_enabled; 1016 int ss_active; 1017} HAL_SPECTRAL_PARAM; 1018#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1019#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1020 1021/* 1022 * DFS operating mode flags. 1023 */ 1024typedef enum { 1025 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1026 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1027 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1028 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1029} HAL_DFS_DOMAIN; 1030 1031 1032/* 1033 * MFP decryption options for initializing the MAC. 1034 */ 1035typedef enum { 1036 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1037 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1038 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1039} HAL_MFP_OPT_T; 1040 1041/* LNA config supported */ 1042typedef enum { 1043 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1044 HAL_ANT_DIV_COMB_LNA2 = 1, 1045 HAL_ANT_DIV_COMB_LNA1 = 2, 1046 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1047} HAL_ANT_DIV_COMB_LNA_CONF; 1048 1049typedef struct { 1050 u_int8_t main_lna_conf; 1051 u_int8_t alt_lna_conf; 1052 u_int8_t fast_div_bias; 1053 u_int8_t main_gaintb; 1054 u_int8_t alt_gaintb; 1055 u_int8_t antdiv_configgroup; 1056 int8_t lna1_lna2_delta; 1057} HAL_ANT_COMB_CONFIG; 1058 1059#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1060#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1061#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1062#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1063 1064/* 1065 * Flag for setting QUIET period 1066 */ 1067typedef enum { 1068 HAL_QUIET_DISABLE = 0x0, 1069 HAL_QUIET_ENABLE = 0x1, 1070 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1071 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1072} HAL_QUIET_FLAG; 1073 1074#define HAL_DFS_EVENT_PRICH 0x0000001 1075#define HAL_DFS_EVENT_EXTCH 0x0000002 1076#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1077#define HAL_DFS_EVENT_ISDC 0x0000008 1078 1079struct hal_dfs_event { 1080 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1081 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1082 uint8_t re_rssi; /* rssi of radar event */ 1083 uint8_t re_dur; /* duration of radar pulse */ 1084 uint32_t re_flags; /* Flags (see above) */ 1085}; 1086typedef struct hal_dfs_event HAL_DFS_EVENT; 1087 1088/* 1089 * Generic Timer domain 1090 */ 1091typedef enum { 1092 HAL_GEN_TIMER_TSF = 0, 1093 HAL_GEN_TIMER_TSF2, 1094 HAL_GEN_TIMER_TSF_ANY 1095} HAL_GEN_TIMER_DOMAIN; 1096 1097/* 1098 * BT Co-existence definitions 1099 */ 1100#include "ath_hal/ah_btcoex.h" 1101 1102struct hal_bb_panic_info { 1103 u_int32_t status; 1104 u_int32_t tsf; 1105 u_int32_t phy_panic_wd_ctl1; 1106 u_int32_t phy_panic_wd_ctl2; 1107 u_int32_t phy_gen_ctrl; 1108 u_int32_t rxc_pcnt; 1109 u_int32_t rxf_pcnt; 1110 u_int32_t txf_pcnt; 1111 u_int32_t cycles; 1112 u_int32_t wd; 1113 u_int32_t det; 1114 u_int32_t rdar; 1115 u_int32_t r_odfm; 1116 u_int32_t r_cck; 1117 u_int32_t t_odfm; 1118 u_int32_t t_cck; 1119 u_int32_t agc; 1120 u_int32_t src; 1121}; 1122 1123/* Serialize Register Access Mode */ 1124typedef enum { 1125 SER_REG_MODE_OFF = 0, 1126 SER_REG_MODE_ON = 1, 1127 SER_REG_MODE_AUTO = 2, 1128} SER_REG_MODE; 1129 1130typedef struct 1131{ 1132 int ah_debug; /* only used if AH_DEBUG is defined */ 1133 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1134 1135 /* NB: these are deprecated; they exist for now for compatibility */ 1136 int ah_dma_beacon_response_time;/* in TU's */ 1137 int ah_sw_beacon_response_time; /* in TU's */ 1138 int ah_additional_swba_backoff; /* in TU's */ 1139 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1140 int ah_serialise_reg_war; /* force serialisation of register IO */ 1141 1142 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1143 int ath_hal_desc_tpc; /* Per-packet TPC */ 1144 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1145 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1146 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1147 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1148 1149 /* I'm not sure what the default values for these should be */ 1150 int ath_hal_pll_pwr_save; 1151 int ath_hal_pcie_power_save_enable; 1152 int ath_hal_intr_mitigation_rx; 1153 int ath_hal_intr_mitigation_tx; 1154 1155 int ath_hal_pcie_clock_req; 1156#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1157#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1158#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1159 1160 int ath_hal_pcie_waen; 1161 int ath_hal_pcie_ser_des_write; 1162 1163 /* these are important for correct AR9300 behaviour */ 1164 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1165 int ath_hal_diversity_control; 1166 int ath_hal_antenna_switch_swap; 1167 int ath_hal_ext_lna_ctl_gpio; 1168 int ath_hal_spur_mode; 1169 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1170 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1171 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1172 1173 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1174 int ath_hal_mfp_support; 1175 1176 int ath_hal_enable_ani; /* should set this.. */ 1177 int ath_hal_cwm_ignore_ext_cca; 1178 int ath_hal_show_bb_panic; 1179 int ath_hal_ant_ctrl_comm2g_switch_enable; 1180 int ath_hal_ext_atten_margin_cfg; 1181 int ath_hal_min_gainidx; 1182 int ath_hal_war70c; 1183 uint32_t ath_hal_mci_config; 1184} HAL_OPS_CONFIG; 1185 1186/* 1187 * Hardware Access Layer (HAL) API. 1188 * 1189 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1190 * ath_hal structure for use with the device. Hardware-related operations 1191 * that follow must call back into the HAL through interface, supplying 1192 * the reference as the first parameter. Note that before using the 1193 * reference returned by ath_hal_attach the caller should verify the 1194 * ABI version number. 1195 */ 1196struct ath_hal { 1197 uint32_t ah_magic; /* consistency check magic number */ 1198 uint16_t ah_devid; /* PCI device ID */ 1199 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1200 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1201 HAL_BUS_TAG ah_st; /* params for register r+w */ 1202 HAL_BUS_HANDLE ah_sh; 1203 HAL_CTRY_CODE ah_countryCode; 1204 1205 uint32_t ah_macVersion; /* MAC version id */ 1206 uint16_t ah_macRev; /* MAC revision */ 1207 uint16_t ah_phyRev; /* PHY revision */ 1208 /* NB: when only one radio is present the rev is in 5Ghz */ 1209 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1210 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1211 1212 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1213 1214 uint32_t ah_intrstate[8]; /* last int state */ 1215 uint32_t ah_syncstate; /* last sync intr state */ 1216 1217 /* Current powerstate from HAL calls */ 1218 HAL_POWER_MODE ah_powerMode; 1219 1220 HAL_OPS_CONFIG ah_config; 1221 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1222 u_int mode); 1223 void __ahdecl(*ah_detach)(struct ath_hal*); 1224 1225 /* Reset functions */ 1226 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1227 struct ieee80211_channel *, 1228 HAL_BOOL bChannelChange, 1229 HAL_RESET_TYPE resetType, 1230 HAL_STATUS *status); 1231 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1232 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1233 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1234 HAL_BOOL power_off); 1235 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1236 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1237 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1238 struct ieee80211_channel *, HAL_BOOL *); 1239 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1240 struct ieee80211_channel *, u_int chainMask, 1241 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1242 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1243 const struct ieee80211_channel *); 1244 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1245 const struct ieee80211_channel *, uint16_t *); 1246 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1247 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1248 const struct ieee80211_channel *); 1249 1250 /* Transmit functions */ 1251 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1252 HAL_BOOL incTrigLevel); 1253 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1254 const HAL_TXQ_INFO *qInfo); 1255 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1256 const HAL_TXQ_INFO *qInfo); 1257 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1258 HAL_TXQ_INFO *qInfo); 1259 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1260 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1261 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1262 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1263 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1264 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1265 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1266 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1267 u_int pktLen, u_int hdrLen, 1268 HAL_PKT_TYPE type, u_int txPower, 1269 u_int txRate0, u_int txTries0, 1270 u_int keyIx, u_int antMode, u_int flags, 1271 u_int rtsctsRate, u_int rtsctsDuration, 1272 u_int compicvLen, u_int compivLen, 1273 u_int comp); 1274 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1275 u_int txRate1, u_int txTries1, 1276 u_int txRate2, u_int txTries2, 1277 u_int txRate3, u_int txTries3); 1278 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1279 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1280 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1281 HAL_BOOL lastSeg, const struct ath_desc *); 1282 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1283 struct ath_desc *, struct ath_tx_status *); 1284 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1285 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1286 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1287 const struct ath_desc *ds, int *rates, int *tries); 1288 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1289 uint32_t link); 1290 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1291 uint32_t *link); 1292 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1293 uint32_t **linkptr); 1294 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1295 void *ts_start, uint32_t ts_paddr_start, 1296 uint16_t size); 1297 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1298 1299 /* Receive Functions */ 1300 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1301 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1302 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1303 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1304 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1305 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1306 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1307 uint32_t filter0, uint32_t filter1); 1308 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1309 uint32_t index); 1310 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1311 uint32_t index); 1312 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1313 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1314 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1315 uint32_t size, u_int flags); 1316 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1317 struct ath_desc *, uint32_t phyAddr, 1318 struct ath_desc *next, uint64_t tsf, 1319 struct ath_rx_status *); 1320 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1321 const HAL_NODE_STATS *, 1322 const struct ieee80211_channel *); 1323 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1324 const struct ieee80211_channel *); 1325 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1326 const HAL_NODE_STATS *); 1327 1328 /* Misc Functions */ 1329 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1330 HAL_CAPABILITY_TYPE, uint32_t capability, 1331 uint32_t *result); 1332 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1333 HAL_CAPABILITY_TYPE, uint32_t capability, 1334 uint32_t setting, HAL_STATUS *); 1335 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1336 const void *args, uint32_t argsize, 1337 void **result, uint32_t *resultsize); 1338 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1339 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1340 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1341 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1342 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1343 uint16_t, HAL_STATUS *); 1344 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1345 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1346 const uint8_t *bssid, uint16_t assocId); 1347 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1348 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1349 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1350 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1351 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1352 uint32_t gpio, uint32_t val); 1353 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1354 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1355 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1356 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1357 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1358 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1359 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1360 HAL_MIB_STATS*); 1361 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1362 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1363 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1364 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1365 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1366 HAL_ANT_SETTING); 1367 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1368 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1369 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1370 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1371 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1372 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1373 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1374 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1375 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1376 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1377 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1378 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1379 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1380 uint32_t duration, uint32_t nextStart, 1381 HAL_QUIET_FLAG flag); 1382 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1383 uint32_t, uint32_t); 1384 1385 /* DFS functions */ 1386 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1387 HAL_PHYERR_PARAM *pe); 1388 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1389 HAL_PHYERR_PARAM *pe); 1390 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1391 HAL_PHYERR_PARAM *pe); 1392 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1393 struct ath_rx_status *rxs, uint64_t fulltsf, 1394 const char *buf, HAL_DFS_EVENT *event); 1395 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1396 1397 /* Spectral Scan functions */ 1398 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1399 HAL_SPECTRAL_PARAM *sp); 1400 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1401 HAL_SPECTRAL_PARAM *sp); 1402 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1403 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1404 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1405 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1406 /* XXX getNfPri() and getNfExt() */ 1407 1408 /* Key Cache Functions */ 1409 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1410 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1411 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1412 uint16_t); 1413 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1414 uint16_t, const HAL_KEYVAL *, 1415 const uint8_t *, int); 1416 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1417 uint16_t, const uint8_t *); 1418 1419 /* Power Management Functions */ 1420 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1421 HAL_POWER_MODE mode, int setChip); 1422 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1423 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1424 const struct ieee80211_channel *); 1425 1426 /* Beacon Management Functions */ 1427 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1428 const HAL_BEACON_TIMERS *); 1429 /* NB: deprecated, use ah_setBeaconTimers instead */ 1430 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1431 uint32_t nexttbtt, uint32_t intval); 1432 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1433 const HAL_BEACON_STATE *); 1434 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1435 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1436 1437 /* 802.11n Functions */ 1438 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1439 struct ath_desc *, 1440 HAL_DMA_ADDR *bufAddrList, 1441 uint32_t *segLenList, 1442 u_int, u_int, HAL_PKT_TYPE, 1443 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1444 HAL_BOOL, HAL_BOOL); 1445 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1446 struct ath_desc *, u_int, u_int, u_int, 1447 u_int, u_int, u_int, u_int, u_int); 1448 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1449 struct ath_desc *, const struct ath_desc *); 1450 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1451 struct ath_desc *, u_int, u_int, 1452 HAL_11N_RATE_SERIES [], u_int, u_int); 1453 1454 /* 1455 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1456 * to the EDMA HAL. Descriptors are chained together by 1457 * using filltxdesc (not ChainTxDesc) and then setting the 1458 * aggregate flags appropriately using first/middle/last. 1459 */ 1460 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1461 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1462 u_int); 1463 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1464 struct ath_desc *, u_int, u_int); 1465 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1466 struct ath_desc *, u_int); 1467 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1468 struct ath_desc *); 1469 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1470 struct ath_desc *); 1471 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1472 struct ath_desc *, u_int); 1473 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1474 struct ath_desc *, u_int); 1475 1476 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1477 HAL_SURVEY_SAMPLE *); 1478 1479 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1480 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1481 HAL_HT_MACMODE); 1482 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1483 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1484 HAL_HT_RXCLEAR); 1485 1486 /* Interrupt functions */ 1487 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1488 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1489 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1490 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1491 1492 /* Bluetooth Coexistence functions */ 1493 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1494 HAL_BT_COEX_INFO *); 1495 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1496 HAL_BT_COEX_CONFIG *); 1497 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1498 int); 1499 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1500 uint32_t); 1501 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1502 uint32_t); 1503 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1504 uint32_t, uint32_t); 1505 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1506 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1507 1508 /* Bluetooth MCI methods */ 1509 void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1510 uint32_t, void *, uint16_t, uint32_t); 1511 HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1512 uint8_t, uint32_t, uint32_t *, uint8_t, 1513 HAL_BOOL, HAL_BOOL); 1514 uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1515 uint32_t *, uint32_t *); 1516 uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1517 uint32_t, uint32_t *); 1518 void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1519 1520 /* LNA diversity configuration */ 1521 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1522 HAL_ANT_COMB_CONFIG *); 1523 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1524 HAL_ANT_COMB_CONFIG *); 1525}; 1526 1527/* 1528 * Check the PCI vendor ID and device ID against Atheros' values 1529 * and return a printable description for any Atheros hardware. 1530 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1531 */ 1532extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1533 1534/* 1535 * Attach the HAL for use with the specified device. The device is 1536 * defined by the PCI device ID. The caller provides an opaque pointer 1537 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1538 * HAL state block for later use. Hardware register accesses are done 1539 * using the specified bus tag and handle. On successful return a 1540 * reference to a state block is returned that must be supplied in all 1541 * subsequent HAL calls. Storage associated with this reference is 1542 * dynamically allocated and must be freed by calling the ah_detach 1543 * method when the client is done. If the attach operation fails a 1544 * null (AH_NULL) reference will be returned and a status code will 1545 * be returned if the status parameter is non-zero. 1546 */ 1547extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1548 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1549 HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1550 1551extern const char *ath_hal_mac_name(struct ath_hal *); 1552extern const char *ath_hal_rf_name(struct ath_hal *); 1553 1554/* 1555 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1556 * request a set of channels for a particular country code and/or 1557 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1558 * this list is constructed according to the contents of the EEPROM. 1559 * ath_hal_getchannels acts similarly but does not alter the operating 1560 * state; this can be used to collect information for a particular 1561 * regulatory configuration. Finally ath_hal_set_channels installs a 1562 * channel list constructed outside the driver. The HAL will adopt the 1563 * channel list and setup internal state according to the specified 1564 * regulatory configuration (e.g. conformance test limits). 1565 * 1566 * For all interfaces the channel list is returned in the supplied array. 1567 * maxchans defines the maximum size of this array. nchans contains the 1568 * actual number of channels returned. If a problem occurred then a 1569 * status code != HAL_OK is returned. 1570 */ 1571struct ieee80211_channel; 1572 1573/* 1574 * Return a list of channels according to the specified regulatory. 1575 */ 1576extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1577 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1578 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1579 HAL_BOOL enableExtendedChannels); 1580 1581/* 1582 * Return a list of channels and install it as the current operating 1583 * regulatory list. 1584 */ 1585extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1586 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1587 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1588 HAL_BOOL enableExtendedChannels); 1589 1590/* 1591 * Install the list of channels as the current operating regulatory 1592 * and setup related state according to the country code and sku. 1593 */ 1594extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1595 struct ieee80211_channel *chans, int nchans, 1596 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1597 1598/* 1599 * Fetch the ctl/ext noise floor values reported by a MIMO 1600 * radio. Returns 1 for valid results, 0 for invalid channel. 1601 */ 1602extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1603 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1604 int16_t *nf_ext); 1605 1606/* 1607 * Calibrate noise floor data following a channel scan or similar. 1608 * This must be called prior retrieving noise floor data. 1609 */ 1610extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1611 1612/* 1613 * Return bit mask of wireless modes supported by the hardware. 1614 */ 1615extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1616 1617/* 1618 * Get the HAL wireless mode for the given channel. 1619 */ 1620extern int ath_hal_get_curmode(struct ath_hal *ah, 1621 const struct ieee80211_channel *chan); 1622 1623/* 1624 * Calculate the packet TX time for a legacy or 11n frame 1625 */ 1626extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1627 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1628 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1629 1630/* 1631 * Calculate the duration of an 11n frame. 1632 */ 1633extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1634 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1635 1636/* 1637 * Calculate the transmit duration of a legacy frame. 1638 */ 1639extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1640 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1641 uint16_t rateix, HAL_BOOL shortPreamble); 1642 1643/* 1644 * Adjust the TSF. 1645 */ 1646extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1647 1648/* 1649 * Enable or disable CCA. 1650 */ 1651void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1652 1653/* 1654 * Get CCA setting. 1655 */ 1656int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1657 1658/* 1659 * Read EEPROM data from ah_eepromdata 1660 */ 1661HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1662 u_int off, uint16_t *data); 1663 1664/* 1665 * For now, simply pass through MFP frames. 1666 */ 1667static inline u_int32_t 1668ath_hal_get_mfp_qos(struct ath_hal *ah) 1669{ 1670 //return AH_PRIVATE(ah)->ah_mfp_qos; 1671 return HAL_MFP_QOSDATA; 1672} 1673 1674#endif /* _ATH_AH_H_ */ 1675