ah.h revision 238280
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 238280 2012-07-09 07:31:26Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MIMO_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77} HAL_STATUS; 78 79typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 123 HAL_CAP_RIFS_RX = 39, 124 HAL_CAP_RIFS_TX = 40, 125 HAL_CAP_FORCE_PPM = 41, 126 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 127 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 128 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 129 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 130 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 131 132 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 133 automatically after waking up to receive TIM */ 134 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 135 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 136 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 137 HAL_CAP_BB_RIFS_HANG = 52, 138 HAL_CAP_RIFS_RX_ENABLED = 53, 139 HAL_CAP_BB_DFS_HANG = 54, 140 141 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 142 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 143 144 HAL_CAP_DS = 67, /* 2 stream */ 145 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 146 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 147 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 148 149 HAL_CAP_TS = 72, /* 3 stream */ 150 151 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 152 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 153 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 154 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 155 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 156 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 157 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 158 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 159 160 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 161 162 HAL_CAP_BB_PANIC_WATCHDOG = 92, 163 164 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 165 166 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 167 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 168 169 /* The following are private to the FreeBSD HAL (224 onward) */ 170 171 HAL_CAP_INTMIT = 229, /* interference mitigation */ 172 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 173 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 174 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 175 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 176 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 177 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 178 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 179 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 180 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 181} HAL_CAPABILITY_TYPE; 182 183/* 184 * "States" for setting the LED. These correspond to 185 * the possible 802.11 operational states and there may 186 * be a many-to-one mapping between these states and the 187 * actual hardware state for the LED's (i.e. the hardware 188 * may have fewer states). 189 */ 190typedef enum { 191 HAL_LED_INIT = 0, 192 HAL_LED_SCAN = 1, 193 HAL_LED_AUTH = 2, 194 HAL_LED_ASSOC = 3, 195 HAL_LED_RUN = 4 196} HAL_LED_STATE; 197 198/* 199 * Transmit queue types/numbers. These are used to tag 200 * each transmit queue in the hardware and to identify a set 201 * of transmit queues for operations such as start/stop dma. 202 */ 203typedef enum { 204 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 205 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 206 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 207 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 208 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 209 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 210 HAL_TX_QUEUE_CFEND = 6, 211 HAL_TX_QUEUE_PAPRD = 7, 212} HAL_TX_QUEUE; 213 214#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 215 216typedef enum { 217 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 218 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 219} HAL_RX_QUEUE; 220 221#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 222 223/* 224 * Transmit queue subtype. These map directly to 225 * WME Access Categories (except for UPSD). Refer 226 * to Table 5 of the WME spec. 227 */ 228typedef enum { 229 HAL_WME_AC_BK = 0, /* background access category */ 230 HAL_WME_AC_BE = 1, /* best effort access category*/ 231 HAL_WME_AC_VI = 2, /* video access category */ 232 HAL_WME_AC_VO = 3, /* voice access category */ 233 HAL_WME_UPSD = 4, /* uplink power save */ 234} HAL_TX_QUEUE_SUBTYPE; 235 236/* 237 * Transmit queue flags that control various 238 * operational parameters. 239 */ 240typedef enum { 241 /* 242 * Per queue interrupt enables. When set the associated 243 * interrupt may be delivered for packets sent through 244 * the queue. Without these enabled no interrupts will 245 * be delivered for transmits through the queue. 246 */ 247 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 248 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 249 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 250 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 251 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 252 /* 253 * Enable hardware compression for packets sent through 254 * the queue. The compression buffer must be setup and 255 * packets must have a key entry marked in the tx descriptor. 256 */ 257 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 258 /* 259 * Disable queue when veol is hit or ready time expires. 260 * By default the queue is disabled only on reaching the 261 * physical end of queue (i.e. a null link ptr in the 262 * descriptor chain). 263 */ 264 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 265 /* 266 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 267 * event. Frames will be transmitted only when this timer 268 * fires, e.g to transmit a beacon in ap or adhoc modes. 269 */ 270 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 271 /* 272 * Each transmit queue has a counter that is incremented 273 * each time the queue is enabled and decremented when 274 * the list of frames to transmit is traversed (or when 275 * the ready time for the queue expires). This counter 276 * must be non-zero for frames to be scheduled for 277 * transmission. The following controls disable bumping 278 * this counter under certain conditions. Typically this 279 * is used to gate frames based on the contents of another 280 * queue (e.g. CAB traffic may only follow a beacon frame). 281 * These are meaningful only when frames are scheduled 282 * with a non-ASAP policy (e.g. DBA-gated). 283 */ 284 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 285 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 286 287 /* 288 * Fragment burst backoff policy. Normally the no backoff 289 * is done after a successful transmission, the next fragment 290 * is sent at SIFS. If this flag is set backoff is done 291 * after each fragment, regardless whether it was ack'd or 292 * not, after the backoff count reaches zero a normal channel 293 * access procedure is done before the next transmit (i.e. 294 * wait AIFS instead of SIFS). 295 */ 296 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 297 /* 298 * Disable post-tx backoff following each frame. 299 */ 300 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 301 /* 302 * DCU arbiter lockout control. This controls how 303 * lower priority tx queues are handled with respect to 304 * to a specific queue when multiple queues have frames 305 * to send. No lockout means lower priority queues arbitrate 306 * concurrently with this queue. Intra-frame lockout 307 * means lower priority queues are locked out until the 308 * current frame transmits (e.g. including backoffs and bursting). 309 * Global lockout means nothing lower can arbitrary so 310 * long as there is traffic activity on this queue (frames, 311 * backoff, etc). 312 */ 313 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 314 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 315 316 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 317 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 318} HAL_TX_QUEUE_FLAGS; 319 320typedef struct { 321 uint32_t tqi_ver; /* hal TXQ version */ 322 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 323 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 324 uint32_t tqi_priority; /* (not used) */ 325 uint32_t tqi_aifs; /* aifs */ 326 uint32_t tqi_cwmin; /* cwMin */ 327 uint32_t tqi_cwmax; /* cwMax */ 328 uint16_t tqi_shretry; /* rts retry limit */ 329 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 330 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 331 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 332 uint32_t tqi_burstTime; /* max burst duration (us) */ 333 uint32_t tqi_readyTime; /* frame schedule time (us) */ 334 uint32_t tqi_compBuf; /* comp buffer phys addr */ 335} HAL_TXQ_INFO; 336 337#define HAL_TQI_NONVAL 0xffff 338 339/* token to use for aifs, cwmin, cwmax */ 340#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 341 342/* compression definitions */ 343#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 344#define HAL_COMP_BUF_ALIGN_SIZE 512 345 346/* 347 * Transmit packet types. This belongs in ah_desc.h, but 348 * is here so we can give a proper type to various parameters 349 * (and not require everyone include the file). 350 * 351 * NB: These values are intentionally assigned for 352 * direct use when setting up h/w descriptors. 353 */ 354typedef enum { 355 HAL_PKT_TYPE_NORMAL = 0, 356 HAL_PKT_TYPE_ATIM = 1, 357 HAL_PKT_TYPE_PSPOLL = 2, 358 HAL_PKT_TYPE_BEACON = 3, 359 HAL_PKT_TYPE_PROBE_RESP = 4, 360 HAL_PKT_TYPE_CHIRP = 5, 361 HAL_PKT_TYPE_GRP_POLL = 6, 362 HAL_PKT_TYPE_AMPDU = 7, 363} HAL_PKT_TYPE; 364 365/* Rx Filter Frame Types */ 366typedef enum { 367 /* 368 * These bits correspond to AR_RX_FILTER for all chips. 369 * Not all bits are supported by all chips. 370 */ 371 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 372 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 373 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 374 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 375 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 376 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 377 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 378 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 379 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 380 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 381 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 382 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 383 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 384 /* Allow all mcast/bcast frames */ 385 386 /* 387 * Magic RX filter flags that aren't targetting hardware bits 388 * but instead the HAL sets individual bits - eg PHYERR will result 389 * in OFDM/CCK timing error frames being received. 390 */ 391 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 392} HAL_RX_FILTER; 393 394typedef enum { 395 HAL_PM_AWAKE = 0, 396 HAL_PM_FULL_SLEEP = 1, 397 HAL_PM_NETWORK_SLEEP = 2, 398 HAL_PM_UNDEFINED = 3 399} HAL_POWER_MODE; 400 401/* 402 * NOTE WELL: 403 * These are mapped to take advantage of the common locations for many of 404 * the bits on all of the currently supported MAC chips. This is to make 405 * the ISR as efficient as possible, while still abstracting HW differences. 406 * When new hardware breaks this commonality this enumerated type, as well 407 * as the HAL functions using it, must be modified. All values are directly 408 * mapped unless commented otherwise. 409 */ 410typedef enum { 411 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 412 HAL_INT_RXDESC = 0x00000002, 413 HAL_INT_RXNOFRM = 0x00000008, 414 HAL_INT_RXEOL = 0x00000010, 415 HAL_INT_RXORN = 0x00000020, 416 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 417 HAL_INT_TXDESC = 0x00000080, 418 HAL_INT_TIM_TIMER= 0x00000100, 419 HAL_INT_TXURN = 0x00000800, 420 HAL_INT_MIB = 0x00001000, 421 HAL_INT_RXPHY = 0x00004000, 422 HAL_INT_RXKCM = 0x00008000, 423 HAL_INT_SWBA = 0x00010000, 424 HAL_INT_BMISS = 0x00040000, 425 HAL_INT_BNR = 0x00100000, 426 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 427 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 428 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 429 HAL_INT_GPIO = 0x01000000, 430 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 431 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 432 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 433 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 434 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 435 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 436#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 437 HAL_INT_BMISC = HAL_INT_TIM 438 | HAL_INT_DTIM 439 | HAL_INT_DTIMSYNC 440 | HAL_INT_CABEND 441 | HAL_INT_TBTT, 442 443 /* Interrupt bits that map directly to ISR/IMR bits */ 444 HAL_INT_COMMON = HAL_INT_RXNOFRM 445 | HAL_INT_RXDESC 446 | HAL_INT_RXEOL 447 | HAL_INT_RXORN 448 | HAL_INT_TXDESC 449 | HAL_INT_TXURN 450 | HAL_INT_MIB 451 | HAL_INT_RXPHY 452 | HAL_INT_RXKCM 453 | HAL_INT_SWBA 454 | HAL_INT_BMISS 455 | HAL_INT_BNR 456 | HAL_INT_GPIO, 457} HAL_INT; 458 459/* 460 * MSI vector assignments 461 */ 462typedef enum { 463 HAL_MSIVEC_MISC = 0, 464 HAL_MSIVEC_TX = 1, 465 HAL_MSIVEC_RXLP = 2, 466 HAL_MSIVEC_RXHP = 3, 467} HAL_MSIVEC; 468 469typedef enum { 470 HAL_INT_LINE = 0, 471 HAL_INT_MSI = 1, 472} HAL_INT_TYPE; 473 474/* For interrupt mitigation registers */ 475typedef enum { 476 HAL_INT_RX_FIRSTPKT=0, 477 HAL_INT_RX_LASTPKT, 478 HAL_INT_TX_FIRSTPKT, 479 HAL_INT_TX_LASTPKT, 480 HAL_INT_THRESHOLD 481} HAL_INT_MITIGATION; 482 483typedef enum { 484 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 485 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 486 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 487 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 488 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 489 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 490 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 491} HAL_GPIO_MUX_TYPE; 492 493typedef enum { 494 HAL_GPIO_INTR_LOW = 0, 495 HAL_GPIO_INTR_HIGH = 1, 496 HAL_GPIO_INTR_DISABLE = 2 497} HAL_GPIO_INTR_TYPE; 498 499typedef enum { 500 HAL_RFGAIN_INACTIVE = 0, 501 HAL_RFGAIN_READ_REQUESTED = 1, 502 HAL_RFGAIN_NEED_CHANGE = 2 503} HAL_RFGAIN; 504 505typedef uint16_t HAL_CTRY_CODE; /* country code */ 506typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 507 508#define HAL_ANTENNA_MIN_MODE 0 509#define HAL_ANTENNA_FIXED_A 1 510#define HAL_ANTENNA_FIXED_B 2 511#define HAL_ANTENNA_MAX_MODE 3 512 513typedef struct { 514 uint32_t ackrcv_bad; 515 uint32_t rts_bad; 516 uint32_t rts_good; 517 uint32_t fcs_bad; 518 uint32_t beacons; 519} HAL_MIB_STATS; 520 521enum { 522 HAL_MODE_11A = 0x001, /* 11a channels */ 523 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 524 HAL_MODE_11B = 0x004, /* 11b channels */ 525 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 526#ifdef notdef 527 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 528#else 529 HAL_MODE_11G = 0x008, /* XXX historical */ 530#endif 531 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 532 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 533 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 534 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 535 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 536 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 537 HAL_MODE_11NG_HT20 = 0x008000, 538 HAL_MODE_11NA_HT20 = 0x010000, 539 HAL_MODE_11NG_HT40PLUS = 0x020000, 540 HAL_MODE_11NG_HT40MINUS = 0x040000, 541 HAL_MODE_11NA_HT40PLUS = 0x080000, 542 HAL_MODE_11NA_HT40MINUS = 0x100000, 543 HAL_MODE_ALL = 0xffffff 544}; 545 546typedef struct { 547 int rateCount; /* NB: for proper padding */ 548 uint8_t rateCodeToIndex[144]; /* back mapping */ 549 struct { 550 uint8_t valid; /* valid for rate control use */ 551 uint8_t phy; /* CCK/OFDM/XR */ 552 uint32_t rateKbps; /* transfer rate in kbs */ 553 uint8_t rateCode; /* rate for h/w descriptors */ 554 uint8_t shortPreamble; /* mask for enabling short 555 * preamble in CCK rate code */ 556 uint8_t dot11Rate; /* value for supported rates 557 * info element of MLME */ 558 uint8_t controlRate; /* index of next lower basic 559 * rate; used for dur. calcs */ 560 uint16_t lpAckDuration; /* long preamble ACK duration */ 561 uint16_t spAckDuration; /* short preamble ACK duration*/ 562 } info[32]; 563} HAL_RATE_TABLE; 564 565typedef struct { 566 u_int rs_count; /* number of valid entries */ 567 uint8_t rs_rates[32]; /* rates */ 568} HAL_RATE_SET; 569 570/* 571 * 802.11n specific structures and enums 572 */ 573typedef enum { 574 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 575 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 576} HAL_CHAIN_TYPE; 577 578typedef struct { 579 u_int Tries; 580 u_int Rate; 581 u_int PktDuration; 582 u_int ChSel; 583 u_int RateFlags; 584#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 585#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 586#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 587} HAL_11N_RATE_SERIES; 588 589typedef enum { 590 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 591 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 592} HAL_HT_MACMODE; 593 594typedef enum { 595 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 596 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 597} HAL_HT_PHYMODE; 598 599typedef enum { 600 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 601 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 602} HAL_HT_EXTPROTSPACING; 603 604 605typedef enum { 606 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 607 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 608} HAL_HT_RXCLEAR; 609 610/* 611 * Antenna switch control. By default antenna selection 612 * enables multiple (2) antenna use. To force use of the 613 * A or B antenna only specify a fixed setting. Fixing 614 * the antenna will also disable any diversity support. 615 */ 616typedef enum { 617 HAL_ANT_VARIABLE = 0, /* variable by programming */ 618 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 619 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 620} HAL_ANT_SETTING; 621 622typedef enum { 623 HAL_M_STA = 1, /* infrastructure station */ 624 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 625 HAL_M_HOSTAP = 6, /* Software Access Point */ 626 HAL_M_MONITOR = 8 /* Monitor mode */ 627} HAL_OPMODE; 628 629typedef struct { 630 uint8_t kv_type; /* one of HAL_CIPHER */ 631 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 632 uint16_t kv_len; /* length in bits */ 633 uint8_t kv_val[16]; /* enough for 128-bit keys */ 634 uint8_t kv_mic[8]; /* TKIP MIC key */ 635 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 636} HAL_KEYVAL; 637 638typedef enum { 639 HAL_CIPHER_WEP = 0, 640 HAL_CIPHER_AES_OCB = 1, 641 HAL_CIPHER_AES_CCM = 2, 642 HAL_CIPHER_CKIP = 3, 643 HAL_CIPHER_TKIP = 4, 644 HAL_CIPHER_CLR = 5, /* no encryption */ 645 646 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 647} HAL_CIPHER; 648 649enum { 650 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 651 HAL_SLOT_TIME_9 = 9, 652 HAL_SLOT_TIME_20 = 20, 653}; 654 655/* 656 * Per-station beacon timer state. Note that the specified 657 * beacon interval (given in TU's) can also include flags 658 * to force a TSF reset and to enable the beacon xmit logic. 659 * If bs_cfpmaxduration is non-zero the hardware is setup to 660 * coexist with a PCF-capable AP. 661 */ 662typedef struct { 663 uint32_t bs_nexttbtt; /* next beacon in TU */ 664 uint32_t bs_nextdtim; /* next DTIM in TU */ 665 uint32_t bs_intval; /* beacon interval+flags */ 666#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 667#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 668#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 669 uint32_t bs_dtimperiod; 670 uint16_t bs_cfpperiod; /* CFP period in TU */ 671 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 672 uint32_t bs_cfpnext; /* next CFP in TU */ 673 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 674 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 675 uint32_t bs_sleepduration; /* max sleep duration */ 676} HAL_BEACON_STATE; 677 678/* 679 * Like HAL_BEACON_STATE but for non-station mode setup. 680 * NB: see above flag definitions for bt_intval. 681 */ 682typedef struct { 683 uint32_t bt_intval; /* beacon interval+flags */ 684 uint32_t bt_nexttbtt; /* next beacon in TU */ 685 uint32_t bt_nextatim; /* next ATIM in TU */ 686 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 687 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 688 uint32_t bt_flags; /* timer enables */ 689#define HAL_BEACON_TBTT_EN 0x00000001 690#define HAL_BEACON_DBA_EN 0x00000002 691#define HAL_BEACON_SWBA_EN 0x00000004 692} HAL_BEACON_TIMERS; 693 694/* 695 * Per-node statistics maintained by the driver for use in 696 * optimizing signal quality and other operational aspects. 697 */ 698typedef struct { 699 uint32_t ns_avgbrssi; /* average beacon rssi */ 700 uint32_t ns_avgrssi; /* average data rssi */ 701 uint32_t ns_avgtxrssi; /* average tx rssi */ 702} HAL_NODE_STATS; 703 704#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 705 706struct ath_desc; 707struct ath_tx_status; 708struct ath_rx_status; 709struct ieee80211_channel; 710 711/* 712 * This is a channel survey sample entry. 713 * 714 * The AR5212 ANI routines fill these samples. The ANI code then uses it 715 * when calculating listen time; it is also exported via a diagnostic 716 * API. 717 */ 718typedef struct { 719 uint32_t seq_num; 720 uint32_t tx_busy; 721 uint32_t rx_busy; 722 uint32_t chan_busy; 723 uint32_t ext_chan_busy; 724 uint32_t cycle_count; 725 /* XXX TODO */ 726 uint32_t ofdm_phyerr_count; 727 uint32_t cck_phyerr_count; 728} HAL_SURVEY_SAMPLE; 729 730/* 731 * This provides 3.2 seconds of sample space given an 732 * ANI time of 1/10th of a second. This may not be enough! 733 */ 734#define CHANNEL_SURVEY_SAMPLE_COUNT 32 735 736typedef struct { 737 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 738 uint32_t cur_sample; /* current sample in sequence */ 739 uint32_t cur_seq; /* current sequence number */ 740} HAL_CHANNEL_SURVEY; 741 742/* 743 * ANI commands. 744 * 745 * These are used both internally and externally via the diagnostic 746 * API. 747 * 748 * Note that this is NOT the ANI commands being used via the INTMIT 749 * capability - that has a different mapping for some reason. 750 */ 751typedef enum { 752 HAL_ANI_PRESENT = 0, /* is ANI support present */ 753 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 754 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 755 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 756 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 757 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 758 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 759 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 760 HAL_ANI_MRC_CCK = 8, 761} HAL_ANI_CMD; 762 763/* 764 * This is the layout of the ANI INTMIT capability. 765 * 766 * Notice that the command values differ to HAL_ANI_CMD. 767 */ 768typedef enum { 769 HAL_CAP_INTMIT_PRESENT = 0, 770 HAL_CAP_INTMIT_ENABLE = 1, 771 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 772 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 773 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 774 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 775 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 776} HAL_CAP_INTMIT_CMD; 777 778/* DFS defines */ 779typedef struct { 780 int32_t pe_firpwr; /* FIR pwr out threshold */ 781 int32_t pe_rrssi; /* Radar rssi thresh */ 782 int32_t pe_height; /* Pulse height thresh */ 783 int32_t pe_prssi; /* Pulse rssi thresh */ 784 int32_t pe_inband; /* Inband thresh */ 785 786 /* The following params are only for AR5413 and later */ 787 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 788 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 789 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 790 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 791 int32_t pe_blockradar; /* 792 * Enable to block radar check if pkt detect is done via OFDM 793 * weak signal detect or pkt is detected immediately after tx 794 * to rx transition 795 */ 796 int32_t pe_enmaxrssi; /* 797 * Enable to use the max rssi instead of the last rssi during 798 * fine gain changes for radar detection 799 */ 800 int32_t pe_extchannel; /* Enable DFS on ext channel */ 801 int32_t pe_enabled; /* Whether radar detection is enabled */ 802 int32_t pe_enrelpwr; 803 int32_t pe_en_relstep_check; 804} HAL_PHYERR_PARAM; 805 806#define HAL_PHYERR_PARAM_NOVAL 65535 807 808/* 809 * DFS operating mode flags. 810 */ 811typedef enum { 812 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 813 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 814 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 815 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 816} HAL_DFS_DOMAIN; 817 818/* 819 * Flag for setting QUIET period 820 */ 821typedef enum { 822 HAL_QUIET_DISABLE = 0x0, 823 HAL_QUIET_ENABLE = 0x1, 824 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 825 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 826} HAL_QUIET_FLAG; 827 828#define HAL_DFS_EVENT_PRICH 0x0000001 829#define HAL_DFS_EVENT_EXTCH 0x0000002 830#define HAL_DFS_EVENT_EXTEARLY 0x0000004 831#define HAL_DFS_EVENT_ISDC 0x0000008 832 833struct hal_dfs_event { 834 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 835 uint32_t re_ts; /* Original 15 bit recv timestamp */ 836 uint8_t re_rssi; /* rssi of radar event */ 837 uint8_t re_dur; /* duration of radar pulse */ 838 uint32_t re_flags; /* Flags (see above) */ 839}; 840typedef struct hal_dfs_event HAL_DFS_EVENT; 841 842/* 843 * BT Co-existence definitions 844 */ 845typedef enum { 846 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 847 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 848 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 849 HAL_MAX_BT_MODULES 850} HAL_BT_MODULE; 851 852typedef struct { 853 HAL_BT_MODULE bt_module; 854 u_int8_t bt_coex_config; 855 u_int8_t bt_gpio_bt_active; 856 u_int8_t bt_gpio_bt_priority; 857 u_int8_t bt_gpio_wlan_active; 858 u_int8_t bt_active_polarity; 859 HAL_BOOL bt_single_ant; 860 u_int8_t bt_dutyCycle; 861 u_int8_t bt_isolation; 862 u_int8_t bt_period; 863} HAL_BT_COEX_INFO; 864 865typedef enum { 866 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 867 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 868 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 869 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 870} HAL_BT_COEX_MODE; 871 872typedef enum { 873 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 874 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 875 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 876 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 877 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 878 HAL_BT_COEX_CFG_MCI /* MCI */ 879} HAL_BT_COEX_CFG; 880 881typedef enum { 882 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 883 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 884 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 885} HAL_BT_COEX_SET_PARAMETER; 886 887#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 888#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 889/* Check Rx Diversity is allowed */ 890#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 891/* Check Diversity is on or off */ 892#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 893 894#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 895/* main: LNA1, alt: LNA2 */ 896#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 897#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 898#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 899#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 900#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 901 902#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 903 904#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 905 906#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 907 908#define HAL_BT_COEX_LOW_ACK_POWER 0x0 909#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 910 911typedef enum { 912 HAL_BT_COEX_NO_STOMP = 0, 913 HAL_BT_COEX_STOMP_ALL, 914 HAL_BT_COEX_STOMP_LOW, 915 HAL_BT_COEX_STOMP_NONE, 916 HAL_BT_COEX_STOMP_ALL_FORCE, 917 HAL_BT_COEX_STOMP_LOW_FORCE, 918} HAL_BT_COEX_STOMP_TYPE; 919 920typedef struct { 921 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 922 u_int8_t bt_time_extend; 923 924 /* 925 * extend rx_clear as long as txsm is 926 * transmitting or waiting for ack. 927 */ 928 HAL_BOOL bt_txstate_extend; 929 930 /* 931 * extend rx_clear so that when tx_frame 932 * is asserted, rx_clear will drop. 933 */ 934 HAL_BOOL bt_txframe_extend; 935 936 /* 937 * coexistence mode 938 */ 939 HAL_BT_COEX_MODE bt_mode; 940 941 /* 942 * treat BT high priority traffic as 943 * a quiet collision 944 */ 945 HAL_BOOL bt_quiet_collision; 946 947 /* 948 * invert rx_clear as WLAN_ACTIVE 949 */ 950 HAL_BOOL bt_rxclear_polarity; 951 952 /* 953 * slotted mode only. indicate the time in usec 954 * from the rising edge of BT_ACTIVE to the time 955 * BT_PRIORITY can be sampled to indicate priority. 956 */ 957 u_int8_t bt_priority_time; 958 959 /* 960 * slotted mode only. indicate the time in usec 961 * from the rising edge of BT_ACTIVE to the time 962 * BT_PRIORITY can be sampled to indicate tx/rx and 963 * BT_FREQ is sampled. 964 */ 965 u_int8_t bt_first_slot_time; 966 967 /* 968 * slotted mode only. rx_clear and bt_ant decision 969 * will be held the entire time that BT_ACTIVE is asserted, 970 * otherwise the decision is made before every slot boundry. 971 */ 972 HAL_BOOL bt_hold_rxclear; 973} HAL_BT_COEX_CONFIG; 974 975typedef struct 976{ 977 int ah_debug; /* only used if AH_DEBUG is defined */ 978 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 979 980 /* NB: these are deprecated; they exist for now for compatibility */ 981 int ah_dma_beacon_response_time;/* in TU's */ 982 int ah_sw_beacon_response_time; /* in TU's */ 983 int ah_additional_swba_backoff; /* in TU's */ 984 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 985 int ah_serialise_reg_war; /* force serialisation of register IO */ 986} HAL_OPS_CONFIG; 987 988/* 989 * Hardware Access Layer (HAL) API. 990 * 991 * Clients of the HAL call ath_hal_attach to obtain a reference to an 992 * ath_hal structure for use with the device. Hardware-related operations 993 * that follow must call back into the HAL through interface, supplying 994 * the reference as the first parameter. Note that before using the 995 * reference returned by ath_hal_attach the caller should verify the 996 * ABI version number. 997 */ 998struct ath_hal { 999 uint32_t ah_magic; /* consistency check magic number */ 1000 uint16_t ah_devid; /* PCI device ID */ 1001 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1002 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1003 HAL_BUS_TAG ah_st; /* params for register r+w */ 1004 HAL_BUS_HANDLE ah_sh; 1005 HAL_CTRY_CODE ah_countryCode; 1006 1007 uint32_t ah_macVersion; /* MAC version id */ 1008 uint16_t ah_macRev; /* MAC revision */ 1009 uint16_t ah_phyRev; /* PHY revision */ 1010 /* NB: when only one radio is present the rev is in 5Ghz */ 1011 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1012 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1013 1014 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1015 1016 uint32_t ah_intrstate[8]; /* last int state */ 1017 uint32_t ah_syncstate; /* last sync intr state */ 1018 1019 HAL_OPS_CONFIG ah_config; 1020 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1021 u_int mode); 1022 void __ahdecl(*ah_detach)(struct ath_hal*); 1023 1024 /* Reset functions */ 1025 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1026 struct ieee80211_channel *, 1027 HAL_BOOL bChannelChange, HAL_STATUS *status); 1028 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1029 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1030 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1031 HAL_BOOL power_off); 1032 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1033 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1034 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1035 struct ieee80211_channel *, HAL_BOOL *); 1036 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1037 struct ieee80211_channel *, u_int chainMask, 1038 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1039 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1040 const struct ieee80211_channel *); 1041 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1042 const struct ieee80211_channel *, uint16_t *); 1043 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1044 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1045 const struct ieee80211_channel *); 1046 1047 /* Transmit functions */ 1048 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1049 HAL_BOOL incTrigLevel); 1050 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1051 const HAL_TXQ_INFO *qInfo); 1052 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1053 const HAL_TXQ_INFO *qInfo); 1054 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1055 HAL_TXQ_INFO *qInfo); 1056 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1057 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1058 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1059 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1060 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1061 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1062 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1063 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1064 u_int pktLen, u_int hdrLen, 1065 HAL_PKT_TYPE type, u_int txPower, 1066 u_int txRate0, u_int txTries0, 1067 u_int keyIx, u_int antMode, u_int flags, 1068 u_int rtsctsRate, u_int rtsctsDuration, 1069 u_int compicvLen, u_int compivLen, 1070 u_int comp); 1071 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1072 u_int txRate1, u_int txTries1, 1073 u_int txRate2, u_int txTries2, 1074 u_int txRate3, u_int txTries3); 1075 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1076 u_int segLen, HAL_BOOL firstSeg, 1077 HAL_BOOL lastSeg, const struct ath_desc *); 1078 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1079 struct ath_desc *, struct ath_tx_status *); 1080 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1081 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1082 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1083 const struct ath_desc *ds, int *rates, int *tries); 1084 1085 /* Receive Functions */ 1086 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1087 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1088 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1089 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1090 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1091 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1092 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1093 uint32_t filter0, uint32_t filter1); 1094 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1095 uint32_t index); 1096 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1097 uint32_t index); 1098 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1099 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1100 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1101 uint32_t size, u_int flags); 1102 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1103 struct ath_desc *, uint32_t phyAddr, 1104 struct ath_desc *next, uint64_t tsf, 1105 struct ath_rx_status *); 1106 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1107 const HAL_NODE_STATS *, 1108 const struct ieee80211_channel *); 1109 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1110 const struct ieee80211_channel *); 1111 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1112 const HAL_NODE_STATS *); 1113 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1114 struct ath_rx_status *, 1115 unsigned long, int); 1116 1117 /* Misc Functions */ 1118 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1119 HAL_CAPABILITY_TYPE, uint32_t capability, 1120 uint32_t *result); 1121 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1122 HAL_CAPABILITY_TYPE, uint32_t capability, 1123 uint32_t setting, HAL_STATUS *); 1124 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1125 const void *args, uint32_t argsize, 1126 void **result, uint32_t *resultsize); 1127 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1128 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1129 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1130 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1131 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1132 uint16_t, HAL_STATUS *); 1133 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1134 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1135 const uint8_t *bssid, uint16_t assocId); 1136 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1137 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1138 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1139 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1140 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1141 uint32_t gpio, uint32_t val); 1142 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1143 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1144 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1145 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1146 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1147 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1148 HAL_MIB_STATS*); 1149 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1150 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1151 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1152 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1153 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1154 HAL_ANT_SETTING); 1155 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1156 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1157 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1158 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1159 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1160 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1161 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1162 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1163 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1164 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1165 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1166 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1167 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1168 uint32_t duration, uint32_t nextStart, 1169 HAL_QUIET_FLAG flag); 1170 1171 /* DFS functions */ 1172 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1173 HAL_PHYERR_PARAM *pe); 1174 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1175 HAL_PHYERR_PARAM *pe); 1176 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1177 struct ath_rx_status *rxs, uint64_t fulltsf, 1178 const char *buf, HAL_DFS_EVENT *event); 1179 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1180 1181 /* Key Cache Functions */ 1182 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1183 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1184 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1185 uint16_t); 1186 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1187 uint16_t, const HAL_KEYVAL *, 1188 const uint8_t *, int); 1189 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1190 uint16_t, const uint8_t *); 1191 1192 /* Power Management Functions */ 1193 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1194 HAL_POWER_MODE mode, int setChip); 1195 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1196 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1197 const struct ieee80211_channel *); 1198 1199 /* Beacon Management Functions */ 1200 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1201 const HAL_BEACON_TIMERS *); 1202 /* NB: deprecated, use ah_setBeaconTimers instead */ 1203 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1204 uint32_t nexttbtt, uint32_t intval); 1205 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1206 const HAL_BEACON_STATE *); 1207 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1208 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1209 1210 /* 802.11n Functions */ 1211 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1212 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1213 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1214 HAL_BOOL, HAL_BOOL); 1215 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1216 struct ath_desc *, u_int, u_int, u_int, 1217 u_int, u_int, u_int, u_int, u_int); 1218 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1219 struct ath_desc *, const struct ath_desc *); 1220 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1221 struct ath_desc *, u_int, u_int, 1222 HAL_11N_RATE_SERIES [], u_int, u_int); 1223 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1224 struct ath_desc *, u_int, u_int); 1225 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1226 struct ath_desc *, u_int); 1227 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1228 struct ath_desc *); 1229 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1230 struct ath_desc *); 1231 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1232 struct ath_desc *, u_int); 1233 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1234 HAL_SURVEY_SAMPLE *); 1235 1236 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1237 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1238 HAL_HT_MACMODE); 1239 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1240 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1241 HAL_HT_RXCLEAR); 1242 1243 /* Interrupt functions */ 1244 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1245 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1246 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1247 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1248}; 1249 1250/* 1251 * Check the PCI vendor ID and device ID against Atheros' values 1252 * and return a printable description for any Atheros hardware. 1253 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1254 */ 1255extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1256 1257/* 1258 * Attach the HAL for use with the specified device. The device is 1259 * defined by the PCI device ID. The caller provides an opaque pointer 1260 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1261 * HAL state block for later use. Hardware register accesses are done 1262 * using the specified bus tag and handle. On successful return a 1263 * reference to a state block is returned that must be supplied in all 1264 * subsequent HAL calls. Storage associated with this reference is 1265 * dynamically allocated and must be freed by calling the ah_detach 1266 * method when the client is done. If the attach operation fails a 1267 * null (AH_NULL) reference will be returned and a status code will 1268 * be returned if the status parameter is non-zero. 1269 */ 1270extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1271 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1272 1273extern const char *ath_hal_mac_name(struct ath_hal *); 1274extern const char *ath_hal_rf_name(struct ath_hal *); 1275 1276/* 1277 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1278 * request a set of channels for a particular country code and/or 1279 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1280 * this list is constructed according to the contents of the EEPROM. 1281 * ath_hal_getchannels acts similarly but does not alter the operating 1282 * state; this can be used to collect information for a particular 1283 * regulatory configuration. Finally ath_hal_set_channels installs a 1284 * channel list constructed outside the driver. The HAL will adopt the 1285 * channel list and setup internal state according to the specified 1286 * regulatory configuration (e.g. conformance test limits). 1287 * 1288 * For all interfaces the channel list is returned in the supplied array. 1289 * maxchans defines the maximum size of this array. nchans contains the 1290 * actual number of channels returned. If a problem occurred then a 1291 * status code != HAL_OK is returned. 1292 */ 1293struct ieee80211_channel; 1294 1295/* 1296 * Return a list of channels according to the specified regulatory. 1297 */ 1298extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1299 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1300 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1301 HAL_BOOL enableExtendedChannels); 1302 1303/* 1304 * Return a list of channels and install it as the current operating 1305 * regulatory list. 1306 */ 1307extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1308 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1309 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1310 HAL_BOOL enableExtendedChannels); 1311 1312/* 1313 * Install the list of channels as the current operating regulatory 1314 * and setup related state according to the country code and sku. 1315 */ 1316extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1317 struct ieee80211_channel *chans, int nchans, 1318 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1319 1320/* 1321 * Fetch the ctl/ext noise floor values reported by a MIMO 1322 * radio. Returns 1 for valid results, 0 for invalid channel. 1323 */ 1324extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1325 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1326 int16_t *nf_ext); 1327 1328/* 1329 * Calibrate noise floor data following a channel scan or similar. 1330 * This must be called prior retrieving noise floor data. 1331 */ 1332extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1333 1334/* 1335 * Return bit mask of wireless modes supported by the hardware. 1336 */ 1337extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1338 1339/* 1340 * Calculate the packet TX time for a legacy or 11n frame 1341 */ 1342extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1343 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1344 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1345 1346/* 1347 * Calculate the duration of an 11n frame. 1348 */ 1349extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1350 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1351 1352/* 1353 * Calculate the transmit duration of a legacy frame. 1354 */ 1355extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1356 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1357 uint16_t rateix, HAL_BOOL shortPreamble); 1358 1359/* 1360 * Adjust the TSF. 1361 */ 1362extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1363 1364/* 1365 * Enable or disable CCA. 1366 */ 1367void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1368 1369/* 1370 * Get CCA setting. 1371 */ 1372int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1373 1374/* 1375 * Read EEPROM data from ah_eepromdata 1376 */ 1377HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1378 u_int off, uint16_t *data); 1379 1380#endif /* _ATH_AH_H_ */ 1381