ah.h revision 227365
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 227365 2011-11-08 22:50:28Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MIMO_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76} HAL_STATUS; 77 78typedef enum { 79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 80 AH_TRUE = 1, 81} HAL_BOOL; 82 83typedef enum { 84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 98 HAL_CAP_TXPOW = 15, /* global tx power limit */ 99 HAL_CAP_TPC = 16, /* per-packet tx power control */ 100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 104 /* 21 was HAL_CAP_XR */ 105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 106 /* 23 was HAL_CAP_CHAN_HALFRATE */ 107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 112 113 HAL_CAP_HT = 30, /* hardware can support HT */ 114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 119 120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 121 122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 124 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 125 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 126 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 127 128 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 129 automatically after waking up to receive TIM */ 130 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 131 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 132 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 133 134 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 135 136 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 137 138 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 139 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 140 141 /* The following are private to the FreeBSD HAL (224 onward) */ 142 143 HAL_CAP_INTMIT = 229, /* interference mitigation */ 144 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 145 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 146 HAL_CAP_MAC_HANG = 236, /* can MAC hang */ 147 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 148 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 149 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 150 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 151 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 152 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 153} HAL_CAPABILITY_TYPE; 154 155/* 156 * "States" for setting the LED. These correspond to 157 * the possible 802.11 operational states and there may 158 * be a many-to-one mapping between these states and the 159 * actual hardware state for the LED's (i.e. the hardware 160 * may have fewer states). 161 */ 162typedef enum { 163 HAL_LED_INIT = 0, 164 HAL_LED_SCAN = 1, 165 HAL_LED_AUTH = 2, 166 HAL_LED_ASSOC = 3, 167 HAL_LED_RUN = 4 168} HAL_LED_STATE; 169 170/* 171 * Transmit queue types/numbers. These are used to tag 172 * each transmit queue in the hardware and to identify a set 173 * of transmit queues for operations such as start/stop dma. 174 */ 175typedef enum { 176 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 177 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 178 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 179 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 180 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 181 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 182} HAL_TX_QUEUE; 183 184#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 185 186/* 187 * Transmit queue subtype. These map directly to 188 * WME Access Categories (except for UPSD). Refer 189 * to Table 5 of the WME spec. 190 */ 191typedef enum { 192 HAL_WME_AC_BK = 0, /* background access category */ 193 HAL_WME_AC_BE = 1, /* best effort access category*/ 194 HAL_WME_AC_VI = 2, /* video access category */ 195 HAL_WME_AC_VO = 3, /* voice access category */ 196 HAL_WME_UPSD = 4, /* uplink power save */ 197} HAL_TX_QUEUE_SUBTYPE; 198 199/* 200 * Transmit queue flags that control various 201 * operational parameters. 202 */ 203typedef enum { 204 /* 205 * Per queue interrupt enables. When set the associated 206 * interrupt may be delivered for packets sent through 207 * the queue. Without these enabled no interrupts will 208 * be delivered for transmits through the queue. 209 */ 210 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 211 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 212 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 213 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 214 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 215 /* 216 * Enable hardware compression for packets sent through 217 * the queue. The compression buffer must be setup and 218 * packets must have a key entry marked in the tx descriptor. 219 */ 220 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 221 /* 222 * Disable queue when veol is hit or ready time expires. 223 * By default the queue is disabled only on reaching the 224 * physical end of queue (i.e. a null link ptr in the 225 * descriptor chain). 226 */ 227 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 228 /* 229 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 230 * event. Frames will be transmitted only when this timer 231 * fires, e.g to transmit a beacon in ap or adhoc modes. 232 */ 233 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 234 /* 235 * Each transmit queue has a counter that is incremented 236 * each time the queue is enabled and decremented when 237 * the list of frames to transmit is traversed (or when 238 * the ready time for the queue expires). This counter 239 * must be non-zero for frames to be scheduled for 240 * transmission. The following controls disable bumping 241 * this counter under certain conditions. Typically this 242 * is used to gate frames based on the contents of another 243 * queue (e.g. CAB traffic may only follow a beacon frame). 244 * These are meaningful only when frames are scheduled 245 * with a non-ASAP policy (e.g. DBA-gated). 246 */ 247 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 248 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 249 250 /* 251 * Fragment burst backoff policy. Normally the no backoff 252 * is done after a successful transmission, the next fragment 253 * is sent at SIFS. If this flag is set backoff is done 254 * after each fragment, regardless whether it was ack'd or 255 * not, after the backoff count reaches zero a normal channel 256 * access procedure is done before the next transmit (i.e. 257 * wait AIFS instead of SIFS). 258 */ 259 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 260 /* 261 * Disable post-tx backoff following each frame. 262 */ 263 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 264 /* 265 * DCU arbiter lockout control. This controls how 266 * lower priority tx queues are handled with respect to 267 * to a specific queue when multiple queues have frames 268 * to send. No lockout means lower priority queues arbitrate 269 * concurrently with this queue. Intra-frame lockout 270 * means lower priority queues are locked out until the 271 * current frame transmits (e.g. including backoffs and bursting). 272 * Global lockout means nothing lower can arbitrary so 273 * long as there is traffic activity on this queue (frames, 274 * backoff, etc). 275 */ 276 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 277 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 278 279 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 280 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 281} HAL_TX_QUEUE_FLAGS; 282 283typedef struct { 284 uint32_t tqi_ver; /* hal TXQ version */ 285 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 286 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 287 uint32_t tqi_priority; /* (not used) */ 288 uint32_t tqi_aifs; /* aifs */ 289 uint32_t tqi_cwmin; /* cwMin */ 290 uint32_t tqi_cwmax; /* cwMax */ 291 uint16_t tqi_shretry; /* rts retry limit */ 292 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 293 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 294 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 295 uint32_t tqi_burstTime; /* max burst duration (us) */ 296 uint32_t tqi_readyTime; /* frame schedule time (us) */ 297 uint32_t tqi_compBuf; /* comp buffer phys addr */ 298} HAL_TXQ_INFO; 299 300#define HAL_TQI_NONVAL 0xffff 301 302/* token to use for aifs, cwmin, cwmax */ 303#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 304 305/* compression definitions */ 306#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 307#define HAL_COMP_BUF_ALIGN_SIZE 512 308 309/* 310 * Transmit packet types. This belongs in ah_desc.h, but 311 * is here so we can give a proper type to various parameters 312 * (and not require everyone include the file). 313 * 314 * NB: These values are intentionally assigned for 315 * direct use when setting up h/w descriptors. 316 */ 317typedef enum { 318 HAL_PKT_TYPE_NORMAL = 0, 319 HAL_PKT_TYPE_ATIM = 1, 320 HAL_PKT_TYPE_PSPOLL = 2, 321 HAL_PKT_TYPE_BEACON = 3, 322 HAL_PKT_TYPE_PROBE_RESP = 4, 323 HAL_PKT_TYPE_CHIRP = 5, 324 HAL_PKT_TYPE_GRP_POLL = 6, 325 HAL_PKT_TYPE_AMPDU = 7, 326} HAL_PKT_TYPE; 327 328/* Rx Filter Frame Types */ 329typedef enum { 330 /* 331 * These bits correspond to AR_RX_FILTER for all chips. 332 * Not all bits are supported by all chips. 333 */ 334 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 335 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 336 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 337 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 338 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 339 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 340 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 341 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 342 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 343 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 344 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 345 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 346 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 347 /* Allow all mcast/bcast frames */ 348 349 /* 350 * Magic RX filter flags that aren't targetting hardware bits 351 * but instead the HAL sets individual bits - eg PHYERR will result 352 * in OFDM/CCK timing error frames being received. 353 */ 354 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 355} HAL_RX_FILTER; 356 357typedef enum { 358 HAL_PM_AWAKE = 0, 359 HAL_PM_FULL_SLEEP = 1, 360 HAL_PM_NETWORK_SLEEP = 2, 361 HAL_PM_UNDEFINED = 3 362} HAL_POWER_MODE; 363 364/* 365 * NOTE WELL: 366 * These are mapped to take advantage of the common locations for many of 367 * the bits on all of the currently supported MAC chips. This is to make 368 * the ISR as efficient as possible, while still abstracting HW differences. 369 * When new hardware breaks this commonality this enumerated type, as well 370 * as the HAL functions using it, must be modified. All values are directly 371 * mapped unless commented otherwise. 372 */ 373typedef enum { 374 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 375 HAL_INT_RXDESC = 0x00000002, 376 HAL_INT_RXNOFRM = 0x00000008, 377 HAL_INT_RXEOL = 0x00000010, 378 HAL_INT_RXORN = 0x00000020, 379 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 380 HAL_INT_TXDESC = 0x00000080, 381 HAL_INT_TIM_TIMER= 0x00000100, 382 HAL_INT_TXURN = 0x00000800, 383 HAL_INT_MIB = 0x00001000, 384 HAL_INT_RXPHY = 0x00004000, 385 HAL_INT_RXKCM = 0x00008000, 386 HAL_INT_SWBA = 0x00010000, 387 HAL_INT_BMISS = 0x00040000, 388 HAL_INT_BNR = 0x00100000, 389 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 390 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 391 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 392 HAL_INT_GPIO = 0x01000000, 393 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 394 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 395 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 396 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 397 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 398 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 399#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 400 HAL_INT_BMISC = HAL_INT_TIM 401 | HAL_INT_DTIM 402 | HAL_INT_DTIMSYNC 403 | HAL_INT_CABEND 404 | HAL_INT_TBTT, 405 406 /* Interrupt bits that map directly to ISR/IMR bits */ 407 HAL_INT_COMMON = HAL_INT_RXNOFRM 408 | HAL_INT_RXDESC 409 | HAL_INT_RXEOL 410 | HAL_INT_RXORN 411 | HAL_INT_TXDESC 412 | HAL_INT_TXURN 413 | HAL_INT_MIB 414 | HAL_INT_RXPHY 415 | HAL_INT_RXKCM 416 | HAL_INT_SWBA 417 | HAL_INT_BMISS 418 | HAL_INT_BNR 419 | HAL_INT_GPIO, 420} HAL_INT; 421 422typedef enum { 423 HAL_GPIO_MUX_OUTPUT = 0, 424 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 425 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 426 HAL_GPIO_MUX_TX_FRAME = 3, 427 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 428 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 429 HAL_GPIO_MUX_MAC_POWER_LED = 6 430} HAL_GPIO_MUX_TYPE; 431 432typedef enum { 433 HAL_GPIO_INTR_LOW = 0, 434 HAL_GPIO_INTR_HIGH = 1, 435 HAL_GPIO_INTR_DISABLE = 2 436} HAL_GPIO_INTR_TYPE; 437 438typedef enum { 439 HAL_RFGAIN_INACTIVE = 0, 440 HAL_RFGAIN_READ_REQUESTED = 1, 441 HAL_RFGAIN_NEED_CHANGE = 2 442} HAL_RFGAIN; 443 444typedef uint16_t HAL_CTRY_CODE; /* country code */ 445typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 446 447#define HAL_ANTENNA_MIN_MODE 0 448#define HAL_ANTENNA_FIXED_A 1 449#define HAL_ANTENNA_FIXED_B 2 450#define HAL_ANTENNA_MAX_MODE 3 451 452typedef struct { 453 uint32_t ackrcv_bad; 454 uint32_t rts_bad; 455 uint32_t rts_good; 456 uint32_t fcs_bad; 457 uint32_t beacons; 458} HAL_MIB_STATS; 459 460enum { 461 HAL_MODE_11A = 0x001, /* 11a channels */ 462 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 463 HAL_MODE_11B = 0x004, /* 11b channels */ 464 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 465#ifdef notdef 466 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 467#else 468 HAL_MODE_11G = 0x008, /* XXX historical */ 469#endif 470 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 471 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 472 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 473 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 474 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 475 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 476 HAL_MODE_11NG_HT20 = 0x008000, 477 HAL_MODE_11NA_HT20 = 0x010000, 478 HAL_MODE_11NG_HT40PLUS = 0x020000, 479 HAL_MODE_11NG_HT40MINUS = 0x040000, 480 HAL_MODE_11NA_HT40PLUS = 0x080000, 481 HAL_MODE_11NA_HT40MINUS = 0x100000, 482 HAL_MODE_ALL = 0xffffff 483}; 484 485typedef struct { 486 int rateCount; /* NB: for proper padding */ 487 uint8_t rateCodeToIndex[144]; /* back mapping */ 488 struct { 489 uint8_t valid; /* valid for rate control use */ 490 uint8_t phy; /* CCK/OFDM/XR */ 491 uint32_t rateKbps; /* transfer rate in kbs */ 492 uint8_t rateCode; /* rate for h/w descriptors */ 493 uint8_t shortPreamble; /* mask for enabling short 494 * preamble in CCK rate code */ 495 uint8_t dot11Rate; /* value for supported rates 496 * info element of MLME */ 497 uint8_t controlRate; /* index of next lower basic 498 * rate; used for dur. calcs */ 499 uint16_t lpAckDuration; /* long preamble ACK duration */ 500 uint16_t spAckDuration; /* short preamble ACK duration*/ 501 } info[32]; 502} HAL_RATE_TABLE; 503 504typedef struct { 505 u_int rs_count; /* number of valid entries */ 506 uint8_t rs_rates[32]; /* rates */ 507} HAL_RATE_SET; 508 509/* 510 * 802.11n specific structures and enums 511 */ 512typedef enum { 513 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 514 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 515} HAL_CHAIN_TYPE; 516 517typedef struct { 518 u_int Tries; 519 u_int Rate; 520 u_int PktDuration; 521 u_int ChSel; 522 u_int RateFlags; 523#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 524#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 525#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 526} HAL_11N_RATE_SERIES; 527 528typedef enum { 529 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 530 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 531} HAL_HT_MACMODE; 532 533typedef enum { 534 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 535 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 536} HAL_HT_PHYMODE; 537 538typedef enum { 539 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 540 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 541} HAL_HT_EXTPROTSPACING; 542 543 544typedef enum { 545 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 546 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 547} HAL_HT_RXCLEAR; 548 549/* 550 * Antenna switch control. By default antenna selection 551 * enables multiple (2) antenna use. To force use of the 552 * A or B antenna only specify a fixed setting. Fixing 553 * the antenna will also disable any diversity support. 554 */ 555typedef enum { 556 HAL_ANT_VARIABLE = 0, /* variable by programming */ 557 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 558 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 559} HAL_ANT_SETTING; 560 561typedef enum { 562 HAL_M_STA = 1, /* infrastructure station */ 563 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 564 HAL_M_HOSTAP = 6, /* Software Access Point */ 565 HAL_M_MONITOR = 8 /* Monitor mode */ 566} HAL_OPMODE; 567 568typedef struct { 569 uint8_t kv_type; /* one of HAL_CIPHER */ 570 uint8_t kv_pad; 571 uint16_t kv_len; /* length in bits */ 572 uint8_t kv_val[16]; /* enough for 128-bit keys */ 573 uint8_t kv_mic[8]; /* TKIP MIC key */ 574 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 575} HAL_KEYVAL; 576 577typedef enum { 578 HAL_CIPHER_WEP = 0, 579 HAL_CIPHER_AES_OCB = 1, 580 HAL_CIPHER_AES_CCM = 2, 581 HAL_CIPHER_CKIP = 3, 582 HAL_CIPHER_TKIP = 4, 583 HAL_CIPHER_CLR = 5, /* no encryption */ 584 585 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 586} HAL_CIPHER; 587 588enum { 589 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 590 HAL_SLOT_TIME_9 = 9, 591 HAL_SLOT_TIME_20 = 20, 592}; 593 594/* 595 * Per-station beacon timer state. Note that the specified 596 * beacon interval (given in TU's) can also include flags 597 * to force a TSF reset and to enable the beacon xmit logic. 598 * If bs_cfpmaxduration is non-zero the hardware is setup to 599 * coexist with a PCF-capable AP. 600 */ 601typedef struct { 602 uint32_t bs_nexttbtt; /* next beacon in TU */ 603 uint32_t bs_nextdtim; /* next DTIM in TU */ 604 uint32_t bs_intval; /* beacon interval+flags */ 605#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 606#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 607#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 608 uint32_t bs_dtimperiod; 609 uint16_t bs_cfpperiod; /* CFP period in TU */ 610 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 611 uint32_t bs_cfpnext; /* next CFP in TU */ 612 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 613 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 614 uint32_t bs_sleepduration; /* max sleep duration */ 615} HAL_BEACON_STATE; 616 617/* 618 * Like HAL_BEACON_STATE but for non-station mode setup. 619 * NB: see above flag definitions for bt_intval. 620 */ 621typedef struct { 622 uint32_t bt_intval; /* beacon interval+flags */ 623 uint32_t bt_nexttbtt; /* next beacon in TU */ 624 uint32_t bt_nextatim; /* next ATIM in TU */ 625 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 626 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 627 uint32_t bt_flags; /* timer enables */ 628#define HAL_BEACON_TBTT_EN 0x00000001 629#define HAL_BEACON_DBA_EN 0x00000002 630#define HAL_BEACON_SWBA_EN 0x00000004 631} HAL_BEACON_TIMERS; 632 633/* 634 * Per-node statistics maintained by the driver for use in 635 * optimizing signal quality and other operational aspects. 636 */ 637typedef struct { 638 uint32_t ns_avgbrssi; /* average beacon rssi */ 639 uint32_t ns_avgrssi; /* average data rssi */ 640 uint32_t ns_avgtxrssi; /* average tx rssi */ 641} HAL_NODE_STATS; 642 643#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 644 645struct ath_desc; 646struct ath_tx_status; 647struct ath_rx_status; 648struct ieee80211_channel; 649 650/* 651 * This is a channel survey sample entry. 652 * 653 * The AR5212 ANI routines fill these samples. The ANI code then uses it 654 * when calculating listen time; it is also exported via a diagnostic 655 * API. 656 */ 657typedef struct { 658 uint32_t seq_num; 659 uint32_t tx_busy; 660 uint32_t rx_busy; 661 uint32_t chan_busy; 662 uint32_t cycle_count; 663} HAL_SURVEY_SAMPLE; 664 665/* 666 * This provides 3.2 seconds of sample space given an 667 * ANI time of 1/10th of a second. This may not be enough! 668 */ 669#define CHANNEL_SURVEY_SAMPLE_COUNT 32 670 671typedef struct { 672 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 673 uint32_t cur_sample; /* current sample in sequence */ 674 uint32_t cur_seq; /* current sequence number */ 675} HAL_CHANNEL_SURVEY; 676 677/* 678 * ANI commands. 679 * 680 * These are used both internally and externally via the diagnostic 681 * API. 682 * 683 * Note that this is NOT the ANI commands being used via the INTMIT 684 * capability - that has a different mapping for some reason. 685 */ 686typedef enum { 687 HAL_ANI_PRESENT = 0, /* is ANI support present */ 688 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 689 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 690 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 691 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 692 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 693 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 694 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 695} HAL_ANI_CMD; 696 697/* 698 * This is the layout of the ANI INTMIT capability. 699 * 700 * Notice that the command values differ to HAL_ANI_CMD. 701 */ 702typedef enum { 703 HAL_CAP_INTMIT_PRESENT = 0, 704 HAL_CAP_INTMIT_ENABLE = 1, 705 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 706 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 707 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 708 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 709 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 710} HAL_CAP_INTMIT_CMD; 711 712typedef struct { 713 int32_t pe_firpwr; /* FIR pwr out threshold */ 714 int32_t pe_rrssi; /* Radar rssi thresh */ 715 int32_t pe_height; /* Pulse height thresh */ 716 int32_t pe_prssi; /* Pulse rssi thresh */ 717 int32_t pe_inband; /* Inband thresh */ 718 719 /* The following params are only for AR5413 and later */ 720 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 721 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 722 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 723 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 724 int32_t pe_blockradar; /* 725 * Enable to block radar check if pkt detect is done via OFDM 726 * weak signal detect or pkt is detected immediately after tx 727 * to rx transition 728 */ 729 int32_t pe_enmaxrssi; /* 730 * Enable to use the max rssi instead of the last rssi during 731 * fine gain changes for radar detection 732 */ 733 int32_t pe_extchannel; /* Enable DFS on ext channel */ 734 int32_t pe_enabled; /* Whether radar detection is enabled */ 735} HAL_PHYERR_PARAM; 736 737#define HAL_PHYERR_PARAM_NOVAL 65535 738#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 739 740/* 741 * DFS operating mode flags. 742 */ 743typedef enum { 744 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 745 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 746 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 747 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 748} HAL_DFS_DOMAIN; 749 750/* 751 * Flag for setting QUIET period 752 */ 753typedef enum { 754 HAL_QUIET_DISABLE = 0x0, 755 HAL_QUIET_ENABLE = 0x1, 756 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 757 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 758} HAL_QUIET_FLAG; 759 760#define HAL_DFS_EVENT_PRICH 0x0000001 761#define HAL_DFS_EVENT_EXTCH 0x0000002 762#define HAL_DFS_EVENT_EXTEARLY 0x0000004 763#define HAL_DFS_EVENT_ISDC 0x0000008 764 765struct hal_dfs_event { 766 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 767 uint32_t re_ts; /* Original 15 bit recv timestamp */ 768 uint8_t re_rssi; /* rssi of radar event */ 769 uint8_t re_dur; /* duration of radar pulse */ 770 uint32_t re_flags; /* Flags (see above) */ 771}; 772typedef struct hal_dfs_event HAL_DFS_EVENT; 773 774typedef struct 775{ 776 int ah_debug; /* only used if AH_DEBUG is defined */ 777 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 778 779 /* NB: these are deprecated; they exist for now for compatibility */ 780 int ah_dma_beacon_response_time;/* in TU's */ 781 int ah_sw_beacon_response_time; /* in TU's */ 782 int ah_additional_swba_backoff; /* in TU's */ 783} HAL_OPS_CONFIG; 784 785/* 786 * Hardware Access Layer (HAL) API. 787 * 788 * Clients of the HAL call ath_hal_attach to obtain a reference to an 789 * ath_hal structure for use with the device. Hardware-related operations 790 * that follow must call back into the HAL through interface, supplying 791 * the reference as the first parameter. Note that before using the 792 * reference returned by ath_hal_attach the caller should verify the 793 * ABI version number. 794 */ 795struct ath_hal { 796 uint32_t ah_magic; /* consistency check magic number */ 797 uint16_t ah_devid; /* PCI device ID */ 798 uint16_t ah_subvendorid; /* PCI subvendor ID */ 799 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 800 HAL_BUS_TAG ah_st; /* params for register r+w */ 801 HAL_BUS_HANDLE ah_sh; 802 HAL_CTRY_CODE ah_countryCode; 803 804 uint32_t ah_macVersion; /* MAC version id */ 805 uint16_t ah_macRev; /* MAC revision */ 806 uint16_t ah_phyRev; /* PHY revision */ 807 /* NB: when only one radio is present the rev is in 5Ghz */ 808 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 809 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 810 811 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 812 813 uint32_t ah_intrstate[8]; /* last int state */ 814 815 HAL_OPS_CONFIG ah_config; 816 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 817 u_int mode); 818 void __ahdecl(*ah_detach)(struct ath_hal*); 819 820 /* Reset functions */ 821 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 822 struct ieee80211_channel *, 823 HAL_BOOL bChannelChange, HAL_STATUS *status); 824 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 825 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 826 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 827 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 828 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 829 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 830 struct ieee80211_channel *, HAL_BOOL *); 831 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 832 struct ieee80211_channel *, u_int chainMask, 833 HAL_BOOL longCal, HAL_BOOL *isCalDone); 834 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 835 const struct ieee80211_channel *); 836 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 837 const struct ieee80211_channel *, uint16_t *); 838 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 839 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 840 const struct ieee80211_channel *); 841 842 /* Transmit functions */ 843 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 844 HAL_BOOL incTrigLevel); 845 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 846 const HAL_TXQ_INFO *qInfo); 847 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 848 const HAL_TXQ_INFO *qInfo); 849 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 850 HAL_TXQ_INFO *qInfo); 851 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 852 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 853 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 854 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 855 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 856 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 857 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 858 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 859 u_int pktLen, u_int hdrLen, 860 HAL_PKT_TYPE type, u_int txPower, 861 u_int txRate0, u_int txTries0, 862 u_int keyIx, u_int antMode, u_int flags, 863 u_int rtsctsRate, u_int rtsctsDuration, 864 u_int compicvLen, u_int compivLen, 865 u_int comp); 866 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 867 u_int txRate1, u_int txTries1, 868 u_int txRate2, u_int txTries2, 869 u_int txRate3, u_int txTries3); 870 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 871 u_int segLen, HAL_BOOL firstSeg, 872 HAL_BOOL lastSeg, const struct ath_desc *); 873 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 874 struct ath_desc *, struct ath_tx_status *); 875 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 876 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 877 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 878 const struct ath_desc *ds, int *rates, int *tries); 879 880 /* Receive Functions */ 881 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 882 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 883 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 884 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 885 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 886 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 887 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 888 uint32_t filter0, uint32_t filter1); 889 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 890 uint32_t index); 891 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 892 uint32_t index); 893 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 894 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 895 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 896 uint32_t size, u_int flags); 897 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 898 struct ath_desc *, uint32_t phyAddr, 899 struct ath_desc *next, uint64_t tsf, 900 struct ath_rx_status *); 901 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 902 const HAL_NODE_STATS *, 903 const struct ieee80211_channel *); 904 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 905 const struct ieee80211_channel *); 906 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 907 const HAL_NODE_STATS *); 908 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 909 struct ath_rx_status *, 910 unsigned long, int); 911 912 /* Misc Functions */ 913 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 914 HAL_CAPABILITY_TYPE, uint32_t capability, 915 uint32_t *result); 916 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 917 HAL_CAPABILITY_TYPE, uint32_t capability, 918 uint32_t setting, HAL_STATUS *); 919 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 920 const void *args, uint32_t argsize, 921 void **result, uint32_t *resultsize); 922 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 923 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 924 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 925 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 926 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 927 uint16_t, HAL_STATUS *); 928 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 929 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 930 const uint8_t *bssid, uint16_t assocId); 931 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 932 uint32_t gpio, HAL_GPIO_MUX_TYPE); 933 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 934 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 935 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 936 uint32_t gpio, uint32_t val); 937 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 938 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 939 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 940 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 941 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 942 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 943 HAL_MIB_STATS*); 944 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 945 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 946 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 947 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 948 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 949 HAL_ANT_SETTING); 950 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 951 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 952 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 953 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 954 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 955 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 956 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 957 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 958 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 959 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 960 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 961 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 962 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 963 uint32_t duration, uint32_t nextStart, 964 HAL_QUIET_FLAG flag); 965 966 /* DFS functions */ 967 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 968 HAL_PHYERR_PARAM *pe); 969 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 970 HAL_PHYERR_PARAM *pe); 971 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 972 struct ath_rx_status *rxs, uint64_t fulltsf, 973 const char *buf, HAL_DFS_EVENT *event); 974 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 975 976 /* Key Cache Functions */ 977 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 978 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 979 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 980 uint16_t); 981 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 982 uint16_t, const HAL_KEYVAL *, 983 const uint8_t *, int); 984 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 985 uint16_t, const uint8_t *); 986 987 /* Power Management Functions */ 988 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 989 HAL_POWER_MODE mode, int setChip); 990 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 991 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 992 const struct ieee80211_channel *); 993 994 /* Beacon Management Functions */ 995 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 996 const HAL_BEACON_TIMERS *); 997 /* NB: deprecated, use ah_setBeaconTimers instead */ 998 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 999 uint32_t nexttbtt, uint32_t intval); 1000 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1001 const HAL_BEACON_STATE *); 1002 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1003 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1004 1005 /* 802.11n Functions */ 1006 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1007 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1008 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1009 HAL_BOOL); 1010 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1011 struct ath_desc *, u_int, u_int, u_int, 1012 u_int, u_int, u_int, u_int, u_int); 1013 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1014 struct ath_desc *, const struct ath_desc *); 1015 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1016 struct ath_desc *, u_int, u_int, 1017 HAL_11N_RATE_SERIES [], u_int, u_int); 1018 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1019 struct ath_desc *, u_int, u_int); 1020 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1021 struct ath_desc *, u_int); 1022 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1023 struct ath_desc *); 1024 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1025 struct ath_desc *); 1026 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1027 struct ath_desc *, u_int); 1028 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1029 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1030 HAL_HT_MACMODE); 1031 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1032 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1033 HAL_HT_RXCLEAR); 1034 1035 /* Interrupt functions */ 1036 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1037 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1038 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1039 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1040}; 1041 1042/* 1043 * Check the PCI vendor ID and device ID against Atheros' values 1044 * and return a printable description for any Atheros hardware. 1045 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1046 */ 1047extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1048 1049/* 1050 * Attach the HAL for use with the specified device. The device is 1051 * defined by the PCI device ID. The caller provides an opaque pointer 1052 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1053 * HAL state block for later use. Hardware register accesses are done 1054 * using the specified bus tag and handle. On successful return a 1055 * reference to a state block is returned that must be supplied in all 1056 * subsequent HAL calls. Storage associated with this reference is 1057 * dynamically allocated and must be freed by calling the ah_detach 1058 * method when the client is done. If the attach operation fails a 1059 * null (AH_NULL) reference will be returned and a status code will 1060 * be returned if the status parameter is non-zero. 1061 */ 1062extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1063 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1064 1065extern const char *ath_hal_mac_name(struct ath_hal *); 1066extern const char *ath_hal_rf_name(struct ath_hal *); 1067 1068/* 1069 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1070 * request a set of channels for a particular country code and/or 1071 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1072 * this list is constructed according to the contents of the EEPROM. 1073 * ath_hal_getchannels acts similarly but does not alter the operating 1074 * state; this can be used to collect information for a particular 1075 * regulatory configuration. Finally ath_hal_set_channels installs a 1076 * channel list constructed outside the driver. The HAL will adopt the 1077 * channel list and setup internal state according to the specified 1078 * regulatory configuration (e.g. conformance test limits). 1079 * 1080 * For all interfaces the channel list is returned in the supplied array. 1081 * maxchans defines the maximum size of this array. nchans contains the 1082 * actual number of channels returned. If a problem occurred then a 1083 * status code != HAL_OK is returned. 1084 */ 1085struct ieee80211_channel; 1086 1087/* 1088 * Return a list of channels according to the specified regulatory. 1089 */ 1090extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1091 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1092 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1093 HAL_BOOL enableExtendedChannels); 1094 1095/* 1096 * Return a list of channels and install it as the current operating 1097 * regulatory list. 1098 */ 1099extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1100 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1101 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1102 HAL_BOOL enableExtendedChannels); 1103 1104/* 1105 * Install the list of channels as the current operating regulatory 1106 * and setup related state according to the country code and sku. 1107 */ 1108extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1109 struct ieee80211_channel *chans, int nchans, 1110 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1111 1112/* 1113 * Fetch the ctl/ext noise floor values reported by a MIMO 1114 * radio. Returns 1 for valid results, 0 for invalid channel. 1115 */ 1116extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1117 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1118 int16_t *nf_ext); 1119 1120/* 1121 * Calibrate noise floor data following a channel scan or similar. 1122 * This must be called prior retrieving noise floor data. 1123 */ 1124extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1125 1126/* 1127 * Return bit mask of wireless modes supported by the hardware. 1128 */ 1129extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1130 1131/* 1132 * Calculate the packet TX time for a legacy or 11n frame 1133 */ 1134extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1135 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1136 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1137 1138/* 1139 * Calculate the duration of an 11n frame. 1140 */ 1141extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1142 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1143 1144/* 1145 * Calculate the transmit duration of a legacy frame. 1146 */ 1147extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1148 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1149 uint16_t rateix, HAL_BOOL shortPreamble); 1150 1151/* 1152 * Adjust the TSF. 1153 */ 1154extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1155 1156/* 1157 * Enable or disable CCA. 1158 */ 1159void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1160 1161/* 1162 * Get CCA setting. 1163 */ 1164int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1165 1166#endif /* _ATH_AH_H_ */ 1167