ah.h revision 222277
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 222277 2011-05-25 07:34:49Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MIMO_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76} HAL_STATUS; 77 78typedef enum { 79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 80 AH_TRUE = 1, 81} HAL_BOOL; 82 83typedef enum { 84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 98 HAL_CAP_TXPOW = 15, /* global tx power limit */ 99 HAL_CAP_TPC = 16, /* per-packet tx power control */ 100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 104 /* 21 was HAL_CAP_XR */ 105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 106 /* 23 was HAL_CAP_CHAN_HALFRATE */ 107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 112 113 HAL_CAP_HT = 30, /* hardware can support HT */ 114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 119 120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 121 122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 124 125 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 126 automatically after waking up to receive TIM */ 127 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 128 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 129 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 130 131 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 132 133 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 134 135 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 136 137 /* The following are private to the FreeBSD HAL (224 onward) */ 138 139 HAL_CAP_INTMIT = 229, /* interference mitigation */ 140 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 141 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 142 HAL_CAP_MAC_HANG = 236, /* can MAC hang */ 143 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 144 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 145 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 146 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 147} HAL_CAPABILITY_TYPE; 148 149/* 150 * "States" for setting the LED. These correspond to 151 * the possible 802.11 operational states and there may 152 * be a many-to-one mapping between these states and the 153 * actual hardware state for the LED's (i.e. the hardware 154 * may have fewer states). 155 */ 156typedef enum { 157 HAL_LED_INIT = 0, 158 HAL_LED_SCAN = 1, 159 HAL_LED_AUTH = 2, 160 HAL_LED_ASSOC = 3, 161 HAL_LED_RUN = 4 162} HAL_LED_STATE; 163 164/* 165 * Transmit queue types/numbers. These are used to tag 166 * each transmit queue in the hardware and to identify a set 167 * of transmit queues for operations such as start/stop dma. 168 */ 169typedef enum { 170 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 171 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 172 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 173 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 174 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 175 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 176} HAL_TX_QUEUE; 177 178#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 179 180/* 181 * Transmit queue subtype. These map directly to 182 * WME Access Categories (except for UPSD). Refer 183 * to Table 5 of the WME spec. 184 */ 185typedef enum { 186 HAL_WME_AC_BK = 0, /* background access category */ 187 HAL_WME_AC_BE = 1, /* best effort access category*/ 188 HAL_WME_AC_VI = 2, /* video access category */ 189 HAL_WME_AC_VO = 3, /* voice access category */ 190 HAL_WME_UPSD = 4, /* uplink power save */ 191} HAL_TX_QUEUE_SUBTYPE; 192 193/* 194 * Transmit queue flags that control various 195 * operational parameters. 196 */ 197typedef enum { 198 /* 199 * Per queue interrupt enables. When set the associated 200 * interrupt may be delivered for packets sent through 201 * the queue. Without these enabled no interrupts will 202 * be delivered for transmits through the queue. 203 */ 204 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 205 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 206 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 207 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 208 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 209 /* 210 * Enable hardware compression for packets sent through 211 * the queue. The compression buffer must be setup and 212 * packets must have a key entry marked in the tx descriptor. 213 */ 214 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 215 /* 216 * Disable queue when veol is hit or ready time expires. 217 * By default the queue is disabled only on reaching the 218 * physical end of queue (i.e. a null link ptr in the 219 * descriptor chain). 220 */ 221 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 222 /* 223 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 224 * event. Frames will be transmitted only when this timer 225 * fires, e.g to transmit a beacon in ap or adhoc modes. 226 */ 227 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 228 /* 229 * Each transmit queue has a counter that is incremented 230 * each time the queue is enabled and decremented when 231 * the list of frames to transmit is traversed (or when 232 * the ready time for the queue expires). This counter 233 * must be non-zero for frames to be scheduled for 234 * transmission. The following controls disable bumping 235 * this counter under certain conditions. Typically this 236 * is used to gate frames based on the contents of another 237 * queue (e.g. CAB traffic may only follow a beacon frame). 238 * These are meaningful only when frames are scheduled 239 * with a non-ASAP policy (e.g. DBA-gated). 240 */ 241 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 242 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 243 244 /* 245 * Fragment burst backoff policy. Normally the no backoff 246 * is done after a successful transmission, the next fragment 247 * is sent at SIFS. If this flag is set backoff is done 248 * after each fragment, regardless whether it was ack'd or 249 * not, after the backoff count reaches zero a normal channel 250 * access procedure is done before the next transmit (i.e. 251 * wait AIFS instead of SIFS). 252 */ 253 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 254 /* 255 * Disable post-tx backoff following each frame. 256 */ 257 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 258 /* 259 * DCU arbiter lockout control. This controls how 260 * lower priority tx queues are handled with respect to 261 * to a specific queue when multiple queues have frames 262 * to send. No lockout means lower priority queues arbitrate 263 * concurrently with this queue. Intra-frame lockout 264 * means lower priority queues are locked out until the 265 * current frame transmits (e.g. including backoffs and bursting). 266 * Global lockout means nothing lower can arbitrary so 267 * long as there is traffic activity on this queue (frames, 268 * backoff, etc). 269 */ 270 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 271 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 272 273 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 274 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 275} HAL_TX_QUEUE_FLAGS; 276 277typedef struct { 278 uint32_t tqi_ver; /* hal TXQ version */ 279 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 280 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 281 uint32_t tqi_priority; /* (not used) */ 282 uint32_t tqi_aifs; /* aifs */ 283 uint32_t tqi_cwmin; /* cwMin */ 284 uint32_t tqi_cwmax; /* cwMax */ 285 uint16_t tqi_shretry; /* rts retry limit */ 286 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 287 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 288 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 289 uint32_t tqi_burstTime; /* max burst duration (us) */ 290 uint32_t tqi_readyTime; /* frame schedule time (us) */ 291 uint32_t tqi_compBuf; /* comp buffer phys addr */ 292} HAL_TXQ_INFO; 293 294#define HAL_TQI_NONVAL 0xffff 295 296/* token to use for aifs, cwmin, cwmax */ 297#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 298 299/* compression definitions */ 300#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 301#define HAL_COMP_BUF_ALIGN_SIZE 512 302 303/* 304 * Transmit packet types. This belongs in ah_desc.h, but 305 * is here so we can give a proper type to various parameters 306 * (and not require everyone include the file). 307 * 308 * NB: These values are intentionally assigned for 309 * direct use when setting up h/w descriptors. 310 */ 311typedef enum { 312 HAL_PKT_TYPE_NORMAL = 0, 313 HAL_PKT_TYPE_ATIM = 1, 314 HAL_PKT_TYPE_PSPOLL = 2, 315 HAL_PKT_TYPE_BEACON = 3, 316 HAL_PKT_TYPE_PROBE_RESP = 4, 317 HAL_PKT_TYPE_CHIRP = 5, 318 HAL_PKT_TYPE_GRP_POLL = 6, 319 HAL_PKT_TYPE_AMPDU = 7, 320} HAL_PKT_TYPE; 321 322/* Rx Filter Frame Types */ 323typedef enum { 324 /* 325 * These bits correspond to AR_RX_FILTER for all chips. 326 * Not all bits are supported by all chips. 327 */ 328 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 329 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 330 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 331 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 332 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 333 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 334 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 335 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 336 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 337 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 338 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 339 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 340 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 341 /* Allow all mcast/bcast frames */ 342 343 /* 344 * Magic RX filter flags that aren't targetting hardware bits 345 * but instead the HAL sets individual bits - eg PHYERR will result 346 * in OFDM/CCK timing error frames being received. 347 */ 348 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 349} HAL_RX_FILTER; 350 351typedef enum { 352 HAL_PM_AWAKE = 0, 353 HAL_PM_FULL_SLEEP = 1, 354 HAL_PM_NETWORK_SLEEP = 2, 355 HAL_PM_UNDEFINED = 3 356} HAL_POWER_MODE; 357 358/* 359 * NOTE WELL: 360 * These are mapped to take advantage of the common locations for many of 361 * the bits on all of the currently supported MAC chips. This is to make 362 * the ISR as efficient as possible, while still abstracting HW differences. 363 * When new hardware breaks this commonality this enumerated type, as well 364 * as the HAL functions using it, must be modified. All values are directly 365 * mapped unless commented otherwise. 366 */ 367typedef enum { 368 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 369 HAL_INT_RXDESC = 0x00000002, 370 HAL_INT_RXNOFRM = 0x00000008, 371 HAL_INT_RXEOL = 0x00000010, 372 HAL_INT_RXORN = 0x00000020, 373 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 374 HAL_INT_TXDESC = 0x00000080, 375 HAL_INT_TIM_TIMER= 0x00000100, 376 HAL_INT_TXURN = 0x00000800, 377 HAL_INT_MIB = 0x00001000, 378 HAL_INT_RXPHY = 0x00004000, 379 HAL_INT_RXKCM = 0x00008000, 380 HAL_INT_SWBA = 0x00010000, 381 HAL_INT_BMISS = 0x00040000, 382 HAL_INT_BNR = 0x00100000, 383 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 384 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 385 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 386 HAL_INT_GPIO = 0x01000000, 387 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 388 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 389 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 390 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 391 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 392 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 393#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 394 HAL_INT_BMISC = HAL_INT_TIM 395 | HAL_INT_DTIM 396 | HAL_INT_DTIMSYNC 397 | HAL_INT_CABEND 398 | HAL_INT_TBTT, 399 400 /* Interrupt bits that map directly to ISR/IMR bits */ 401 HAL_INT_COMMON = HAL_INT_RXNOFRM 402 | HAL_INT_RXDESC 403 | HAL_INT_RXEOL 404 | HAL_INT_RXORN 405 | HAL_INT_TXDESC 406 | HAL_INT_TXURN 407 | HAL_INT_MIB 408 | HAL_INT_RXPHY 409 | HAL_INT_RXKCM 410 | HAL_INT_SWBA 411 | HAL_INT_BMISS 412 | HAL_INT_BNR 413 | HAL_INT_GPIO, 414} HAL_INT; 415 416typedef enum { 417 HAL_GPIO_MUX_OUTPUT = 0, 418 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 419 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 420 HAL_GPIO_MUX_TX_FRAME = 3, 421 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 422 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 423 HAL_GPIO_MUX_MAC_POWER_LED = 6 424} HAL_GPIO_MUX_TYPE; 425 426typedef enum { 427 HAL_GPIO_INTR_LOW = 0, 428 HAL_GPIO_INTR_HIGH = 1, 429 HAL_GPIO_INTR_DISABLE = 2 430} HAL_GPIO_INTR_TYPE; 431 432typedef enum { 433 HAL_RFGAIN_INACTIVE = 0, 434 HAL_RFGAIN_READ_REQUESTED = 1, 435 HAL_RFGAIN_NEED_CHANGE = 2 436} HAL_RFGAIN; 437 438typedef uint16_t HAL_CTRY_CODE; /* country code */ 439typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 440 441#define HAL_ANTENNA_MIN_MODE 0 442#define HAL_ANTENNA_FIXED_A 1 443#define HAL_ANTENNA_FIXED_B 2 444#define HAL_ANTENNA_MAX_MODE 3 445 446typedef struct { 447 uint32_t ackrcv_bad; 448 uint32_t rts_bad; 449 uint32_t rts_good; 450 uint32_t fcs_bad; 451 uint32_t beacons; 452} HAL_MIB_STATS; 453 454enum { 455 HAL_MODE_11A = 0x001, /* 11a channels */ 456 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 457 HAL_MODE_11B = 0x004, /* 11b channels */ 458 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 459#ifdef notdef 460 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 461#else 462 HAL_MODE_11G = 0x008, /* XXX historical */ 463#endif 464 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 465 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 466 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 467 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 468 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 469 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 470 HAL_MODE_11NG_HT20 = 0x008000, 471 HAL_MODE_11NA_HT20 = 0x010000, 472 HAL_MODE_11NG_HT40PLUS = 0x020000, 473 HAL_MODE_11NG_HT40MINUS = 0x040000, 474 HAL_MODE_11NA_HT40PLUS = 0x080000, 475 HAL_MODE_11NA_HT40MINUS = 0x100000, 476 HAL_MODE_ALL = 0xffffff 477}; 478 479typedef struct { 480 int rateCount; /* NB: for proper padding */ 481 uint8_t rateCodeToIndex[144]; /* back mapping */ 482 struct { 483 uint8_t valid; /* valid for rate control use */ 484 uint8_t phy; /* CCK/OFDM/XR */ 485 uint32_t rateKbps; /* transfer rate in kbs */ 486 uint8_t rateCode; /* rate for h/w descriptors */ 487 uint8_t shortPreamble; /* mask for enabling short 488 * preamble in CCK rate code */ 489 uint8_t dot11Rate; /* value for supported rates 490 * info element of MLME */ 491 uint8_t controlRate; /* index of next lower basic 492 * rate; used for dur. calcs */ 493 uint16_t lpAckDuration; /* long preamble ACK duration */ 494 uint16_t spAckDuration; /* short preamble ACK duration*/ 495 } info[32]; 496} HAL_RATE_TABLE; 497 498typedef struct { 499 u_int rs_count; /* number of valid entries */ 500 uint8_t rs_rates[32]; /* rates */ 501} HAL_RATE_SET; 502 503/* 504 * 802.11n specific structures and enums 505 */ 506typedef enum { 507 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 508 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 509} HAL_CHAIN_TYPE; 510 511typedef struct { 512 u_int Tries; 513 u_int Rate; 514 u_int PktDuration; 515 u_int ChSel; 516 u_int RateFlags; 517#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 518#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 519#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 520} HAL_11N_RATE_SERIES; 521 522typedef enum { 523 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 524 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 525} HAL_HT_MACMODE; 526 527typedef enum { 528 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 529 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 530} HAL_HT_PHYMODE; 531 532typedef enum { 533 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 534 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 535} HAL_HT_EXTPROTSPACING; 536 537 538typedef enum { 539 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 540 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 541} HAL_HT_RXCLEAR; 542 543/* 544 * Antenna switch control. By default antenna selection 545 * enables multiple (2) antenna use. To force use of the 546 * A or B antenna only specify a fixed setting. Fixing 547 * the antenna will also disable any diversity support. 548 */ 549typedef enum { 550 HAL_ANT_VARIABLE = 0, /* variable by programming */ 551 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 552 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 553} HAL_ANT_SETTING; 554 555typedef enum { 556 HAL_M_STA = 1, /* infrastructure station */ 557 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 558 HAL_M_HOSTAP = 6, /* Software Access Point */ 559 HAL_M_MONITOR = 8 /* Monitor mode */ 560} HAL_OPMODE; 561 562typedef struct { 563 uint8_t kv_type; /* one of HAL_CIPHER */ 564 uint8_t kv_pad; 565 uint16_t kv_len; /* length in bits */ 566 uint8_t kv_val[16]; /* enough for 128-bit keys */ 567 uint8_t kv_mic[8]; /* TKIP MIC key */ 568 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 569} HAL_KEYVAL; 570 571typedef enum { 572 HAL_CIPHER_WEP = 0, 573 HAL_CIPHER_AES_OCB = 1, 574 HAL_CIPHER_AES_CCM = 2, 575 HAL_CIPHER_CKIP = 3, 576 HAL_CIPHER_TKIP = 4, 577 HAL_CIPHER_CLR = 5, /* no encryption */ 578 579 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 580} HAL_CIPHER; 581 582enum { 583 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 584 HAL_SLOT_TIME_9 = 9, 585 HAL_SLOT_TIME_20 = 20, 586}; 587 588/* 589 * Per-station beacon timer state. Note that the specified 590 * beacon interval (given in TU's) can also include flags 591 * to force a TSF reset and to enable the beacon xmit logic. 592 * If bs_cfpmaxduration is non-zero the hardware is setup to 593 * coexist with a PCF-capable AP. 594 */ 595typedef struct { 596 uint32_t bs_nexttbtt; /* next beacon in TU */ 597 uint32_t bs_nextdtim; /* next DTIM in TU */ 598 uint32_t bs_intval; /* beacon interval+flags */ 599#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 600#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 601#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 602 uint32_t bs_dtimperiod; 603 uint16_t bs_cfpperiod; /* CFP period in TU */ 604 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 605 uint32_t bs_cfpnext; /* next CFP in TU */ 606 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 607 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 608 uint32_t bs_sleepduration; /* max sleep duration */ 609} HAL_BEACON_STATE; 610 611/* 612 * Like HAL_BEACON_STATE but for non-station mode setup. 613 * NB: see above flag definitions for bt_intval. 614 */ 615typedef struct { 616 uint32_t bt_intval; /* beacon interval+flags */ 617 uint32_t bt_nexttbtt; /* next beacon in TU */ 618 uint32_t bt_nextatim; /* next ATIM in TU */ 619 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 620 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 621 uint32_t bt_flags; /* timer enables */ 622#define HAL_BEACON_TBTT_EN 0x00000001 623#define HAL_BEACON_DBA_EN 0x00000002 624#define HAL_BEACON_SWBA_EN 0x00000004 625} HAL_BEACON_TIMERS; 626 627/* 628 * Per-node statistics maintained by the driver for use in 629 * optimizing signal quality and other operational aspects. 630 */ 631typedef struct { 632 uint32_t ns_avgbrssi; /* average beacon rssi */ 633 uint32_t ns_avgrssi; /* average data rssi */ 634 uint32_t ns_avgtxrssi; /* average tx rssi */ 635} HAL_NODE_STATS; 636 637#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 638 639struct ath_desc; 640struct ath_tx_status; 641struct ath_rx_status; 642struct ieee80211_channel; 643 644/* 645 * This is a channel survey sample entry. 646 * 647 * The AR5212 ANI routines fill these samples. The ANI code then uses it 648 * when calculating listen time; it is also exported via a diagnostic 649 * API. 650 */ 651typedef struct { 652 uint32_t seq_num; 653 uint32_t tx_busy; 654 uint32_t rx_busy; 655 uint32_t chan_busy; 656 uint32_t cycle_count; 657} HAL_SURVEY_SAMPLE; 658 659/* 660 * This provides 3.2 seconds of sample space given an 661 * ANI time of 1/10th of a second. This may not be enough! 662 */ 663#define CHANNEL_SURVEY_SAMPLE_COUNT 32 664 665typedef struct { 666 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 667 uint32_t cur_sample; /* current sample in sequence */ 668 uint32_t cur_seq; /* current sequence number */ 669} HAL_CHANNEL_SURVEY; 670 671/* 672 * ANI commands. 673 * 674 * These are used both internally and externally via the diagnostic 675 * API. 676 * 677 * Note that this is NOT the ANI commands being used via the INTMIT 678 * capability - that has a different mapping for some reason. 679 */ 680typedef enum { 681 HAL_ANI_PRESENT = 0, /* is ANI support present */ 682 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 683 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 684 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 685 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 686 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 687 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 688 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 689} HAL_ANI_CMD; 690 691/* 692 * This is the layout of the ANI INTMIT capability. 693 * 694 * Notice that the command values differ to HAL_ANI_CMD. 695 */ 696typedef enum { 697 HAL_CAP_INTMIT_PRESENT = 0, 698 HAL_CAP_INTMIT_ENABLE = 1, 699 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 700 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 701 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 702 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 703 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 704} HAL_CAP_INTMIT_CMD; 705 706/* 707 * Hardware Access Layer (HAL) API. 708 * 709 * Clients of the HAL call ath_hal_attach to obtain a reference to an 710 * ath_hal structure for use with the device. Hardware-related operations 711 * that follow must call back into the HAL through interface, supplying 712 * the reference as the first parameter. Note that before using the 713 * reference returned by ath_hal_attach the caller should verify the 714 * ABI version number. 715 */ 716struct ath_hal { 717 uint32_t ah_magic; /* consistency check magic number */ 718 uint16_t ah_devid; /* PCI device ID */ 719 uint16_t ah_subvendorid; /* PCI subvendor ID */ 720 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 721 HAL_BUS_TAG ah_st; /* params for register r+w */ 722 HAL_BUS_HANDLE ah_sh; 723 HAL_CTRY_CODE ah_countryCode; 724 725 uint32_t ah_macVersion; /* MAC version id */ 726 uint16_t ah_macRev; /* MAC revision */ 727 uint16_t ah_phyRev; /* PHY revision */ 728 /* NB: when only one radio is present the rev is in 5Ghz */ 729 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 730 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 731 732 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 733 734 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 735 u_int mode); 736 void __ahdecl(*ah_detach)(struct ath_hal*); 737 738 /* Reset functions */ 739 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 740 struct ieee80211_channel *, 741 HAL_BOOL bChannelChange, HAL_STATUS *status); 742 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 743 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 744 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 745 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 746 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 747 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 748 struct ieee80211_channel *, HAL_BOOL *); 749 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 750 struct ieee80211_channel *, u_int chainMask, 751 HAL_BOOL longCal, HAL_BOOL *isCalDone); 752 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 753 const struct ieee80211_channel *); 754 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 755 const struct ieee80211_channel *, uint16_t *); 756 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 757 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 758 const struct ieee80211_channel *); 759 760 /* Transmit functions */ 761 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 762 HAL_BOOL incTrigLevel); 763 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 764 const HAL_TXQ_INFO *qInfo); 765 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 766 const HAL_TXQ_INFO *qInfo); 767 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 768 HAL_TXQ_INFO *qInfo); 769 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 770 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 771 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 772 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 773 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 774 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 775 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 776 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 777 u_int pktLen, u_int hdrLen, 778 HAL_PKT_TYPE type, u_int txPower, 779 u_int txRate0, u_int txTries0, 780 u_int keyIx, u_int antMode, u_int flags, 781 u_int rtsctsRate, u_int rtsctsDuration, 782 u_int compicvLen, u_int compivLen, 783 u_int comp); 784 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 785 u_int txRate1, u_int txTries1, 786 u_int txRate2, u_int txTries2, 787 u_int txRate3, u_int txTries3); 788 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 789 u_int segLen, HAL_BOOL firstSeg, 790 HAL_BOOL lastSeg, const struct ath_desc *); 791 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 792 struct ath_desc *, struct ath_tx_status *); 793 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 794 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 795 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 796 const struct ath_desc *ds, int *rates, int *tries); 797 798 /* Receive Functions */ 799 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 800 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 801 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 802 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 803 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 804 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 805 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 806 uint32_t filter0, uint32_t filter1); 807 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 808 uint32_t index); 809 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 810 uint32_t index); 811 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 812 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 813 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 814 uint32_t size, u_int flags); 815 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 816 struct ath_desc *, uint32_t phyAddr, 817 struct ath_desc *next, uint64_t tsf, 818 struct ath_rx_status *); 819 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 820 const HAL_NODE_STATS *, 821 const struct ieee80211_channel *); 822 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 823 const struct ieee80211_channel *); 824 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 825 const HAL_NODE_STATS *); 826 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 827 struct ath_rx_status *, 828 unsigned long, int); 829 830 /* Misc Functions */ 831 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 832 HAL_CAPABILITY_TYPE, uint32_t capability, 833 uint32_t *result); 834 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 835 HAL_CAPABILITY_TYPE, uint32_t capability, 836 uint32_t setting, HAL_STATUS *); 837 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 838 const void *args, uint32_t argsize, 839 void **result, uint32_t *resultsize); 840 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 841 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 842 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 843 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 844 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 845 uint16_t, HAL_STATUS *); 846 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 847 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 848 const uint8_t *bssid, uint16_t assocId); 849 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 850 uint32_t gpio, HAL_GPIO_MUX_TYPE); 851 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 852 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 853 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 854 uint32_t gpio, uint32_t val); 855 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 856 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 857 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 858 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 859 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 860 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 861 HAL_MIB_STATS*); 862 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 863 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 864 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 865 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 866 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 867 HAL_ANT_SETTING); 868 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 869 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 870 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 871 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 872 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 873 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 874 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 875 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 876 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 877 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 878 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 879 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 880 881 /* Key Cache Functions */ 882 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 883 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 884 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 885 uint16_t); 886 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 887 uint16_t, const HAL_KEYVAL *, 888 const uint8_t *, int); 889 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 890 uint16_t, const uint8_t *); 891 892 /* Power Management Functions */ 893 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 894 HAL_POWER_MODE mode, int setChip); 895 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 896 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 897 const struct ieee80211_channel *); 898 899 /* Beacon Management Functions */ 900 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 901 const HAL_BEACON_TIMERS *); 902 /* NB: deprecated, use ah_setBeaconTimers instead */ 903 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 904 uint32_t nexttbtt, uint32_t intval); 905 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 906 const HAL_BEACON_STATE *); 907 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 908 909 /* 802.11n Functions */ 910 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 911 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 912 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 913 HAL_BOOL); 914 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 915 struct ath_desc *, u_int, u_int, u_int, 916 u_int, u_int, u_int, u_int, u_int); 917 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 918 struct ath_desc *, const struct ath_desc *); 919 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 920 struct ath_desc *, u_int, u_int, 921 HAL_11N_RATE_SERIES [], u_int, u_int); 922 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 923 struct ath_desc *, u_int); 924 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 925 struct ath_desc *); 926 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 927 struct ath_desc *, u_int); 928 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 929 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 930 HAL_HT_MACMODE); 931 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 932 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 933 HAL_HT_RXCLEAR); 934 935 /* Interrupt functions */ 936 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 937 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 938 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 939 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 940}; 941 942/* 943 * Check the PCI vendor ID and device ID against Atheros' values 944 * and return a printable description for any Atheros hardware. 945 * AH_NULL is returned if the ID's do not describe Atheros hardware. 946 */ 947extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 948 949/* 950 * Attach the HAL for use with the specified device. The device is 951 * defined by the PCI device ID. The caller provides an opaque pointer 952 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 953 * HAL state block for later use. Hardware register accesses are done 954 * using the specified bus tag and handle. On successful return a 955 * reference to a state block is returned that must be supplied in all 956 * subsequent HAL calls. Storage associated with this reference is 957 * dynamically allocated and must be freed by calling the ah_detach 958 * method when the client is done. If the attach operation fails a 959 * null (AH_NULL) reference will be returned and a status code will 960 * be returned if the status parameter is non-zero. 961 */ 962extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 963 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 964 965extern const char *ath_hal_mac_name(struct ath_hal *); 966extern const char *ath_hal_rf_name(struct ath_hal *); 967 968/* 969 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 970 * request a set of channels for a particular country code and/or 971 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 972 * this list is constructed according to the contents of the EEPROM. 973 * ath_hal_getchannels acts similarly but does not alter the operating 974 * state; this can be used to collect information for a particular 975 * regulatory configuration. Finally ath_hal_set_channels installs a 976 * channel list constructed outside the driver. The HAL will adopt the 977 * channel list and setup internal state according to the specified 978 * regulatory configuration (e.g. conformance test limits). 979 * 980 * For all interfaces the channel list is returned in the supplied array. 981 * maxchans defines the maximum size of this array. nchans contains the 982 * actual number of channels returned. If a problem occurred then a 983 * status code != HAL_OK is returned. 984 */ 985struct ieee80211_channel; 986 987/* 988 * Return a list of channels according to the specified regulatory. 989 */ 990extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 991 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 992 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 993 HAL_BOOL enableExtendedChannels); 994 995/* 996 * Return a list of channels and install it as the current operating 997 * regulatory list. 998 */ 999extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1000 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1001 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1002 HAL_BOOL enableExtendedChannels); 1003 1004/* 1005 * Install the list of channels as the current operating regulatory 1006 * and setup related state according to the country code and sku. 1007 */ 1008extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1009 struct ieee80211_channel *chans, int nchans, 1010 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1011 1012/* 1013 * Fetch the ctl/ext noise floor values reported by a MIMO 1014 * radio. Returns 1 for valid results, 0 for invalid channel. 1015 */ 1016extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1017 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1018 int16_t *nf_ext); 1019 1020/* 1021 * Calibrate noise floor data following a channel scan or similar. 1022 * This must be called prior retrieving noise floor data. 1023 */ 1024extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1025 1026/* 1027 * Return bit mask of wireless modes supported by the hardware. 1028 */ 1029extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1030 1031/* 1032 * Calculate the packet TX time for a legacy or 11n frame 1033 */ 1034extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1035 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1036 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1037 1038/* 1039 * Calculate the duration of an 11n frame. 1040 */ 1041extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1042 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1043 1044/* 1045 * Calculate the transmit duration of a legacy frame. 1046 */ 1047extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1048 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1049 uint16_t rateix, HAL_BOOL shortPreamble); 1050#endif /* _ATH_AH_H_ */ 1051