ah.h revision 217624
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 217624 2011-01-20 07:56:09Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * __ahdecl is analogous to _cdecl; it defines the calling 35 * convention used within the HAL. For most systems this 36 * can just default to be empty and the compiler will (should) 37 * use _cdecl. For systems where _cdecl is not compatible this 38 * must be defined. See linux/ah_osdep.h for an example. 39 */ 40#ifndef __ahdecl 41#define __ahdecl 42#endif 43 44/* 45 * Status codes that may be returned by the HAL. Note that 46 * interfaces that return a status code set it only when an 47 * error occurs--i.e. you cannot check it for success. 48 */ 49typedef enum { 50 HAL_OK = 0, /* No error */ 51 HAL_ENXIO = 1, /* No hardware present */ 52 HAL_ENOMEM = 2, /* Memory allocation failed */ 53 HAL_EIO = 3, /* Hardware didn't respond as expected */ 54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55 HAL_EEVERSION = 5, /* EEPROM version invalid */ 56 HAL_EELOCKED = 6, /* EEPROM unreadable */ 57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58 HAL_EEREAD = 8, /* EEPROM read problem */ 59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60 HAL_EESIZE = 10, /* EEPROM size not supported */ 61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62 HAL_EINVAL = 12, /* Invalid parameter to function */ 63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65 HAL_EINPROGRESS = 15, /* Operation incomplete */ 66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68} HAL_STATUS; 69 70typedef enum { 71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72 AH_TRUE = 1, 73} HAL_BOOL; 74 75typedef enum { 76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90 HAL_CAP_TXPOW = 15, /* global tx power limit */ 91 HAL_CAP_TPC = 16, /* per-packet tx power control */ 92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96 /* 21 was HAL_CAP_XR */ 97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98 /* 23 was HAL_CAP_CHAN_HALFRATE */ 99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104 HAL_CAP_INTMIT = 29, /* interference mitigation */ 105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106 HAL_CAP_HT = 31, /* hardware can support HT */ 107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110 HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113 HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */ 114} HAL_CAPABILITY_TYPE; 115 116/* 117 * "States" for setting the LED. These correspond to 118 * the possible 802.11 operational states and there may 119 * be a many-to-one mapping between these states and the 120 * actual hardware state for the LED's (i.e. the hardware 121 * may have fewer states). 122 */ 123typedef enum { 124 HAL_LED_INIT = 0, 125 HAL_LED_SCAN = 1, 126 HAL_LED_AUTH = 2, 127 HAL_LED_ASSOC = 3, 128 HAL_LED_RUN = 4 129} HAL_LED_STATE; 130 131/* 132 * Transmit queue types/numbers. These are used to tag 133 * each transmit queue in the hardware and to identify a set 134 * of transmit queues for operations such as start/stop dma. 135 */ 136typedef enum { 137 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 138 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 139 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 140 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 141 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 142} HAL_TX_QUEUE; 143 144#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 145 146/* 147 * Transmit queue subtype. These map directly to 148 * WME Access Categories (except for UPSD). Refer 149 * to Table 5 of the WME spec. 150 */ 151typedef enum { 152 HAL_WME_AC_BK = 0, /* background access category */ 153 HAL_WME_AC_BE = 1, /* best effort access category*/ 154 HAL_WME_AC_VI = 2, /* video access category */ 155 HAL_WME_AC_VO = 3, /* voice access category */ 156 HAL_WME_UPSD = 4, /* uplink power save */ 157} HAL_TX_QUEUE_SUBTYPE; 158 159/* 160 * Transmit queue flags that control various 161 * operational parameters. 162 */ 163typedef enum { 164 /* 165 * Per queue interrupt enables. When set the associated 166 * interrupt may be delivered for packets sent through 167 * the queue. Without these enabled no interrupts will 168 * be delivered for transmits through the queue. 169 */ 170 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 171 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 172 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 173 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 174 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 175 /* 176 * Enable hardware compression for packets sent through 177 * the queue. The compression buffer must be setup and 178 * packets must have a key entry marked in the tx descriptor. 179 */ 180 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 181 /* 182 * Disable queue when veol is hit or ready time expires. 183 * By default the queue is disabled only on reaching the 184 * physical end of queue (i.e. a null link ptr in the 185 * descriptor chain). 186 */ 187 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 188 /* 189 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 190 * event. Frames will be transmitted only when this timer 191 * fires, e.g to transmit a beacon in ap or adhoc modes. 192 */ 193 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 194 /* 195 * Each transmit queue has a counter that is incremented 196 * each time the queue is enabled and decremented when 197 * the list of frames to transmit is traversed (or when 198 * the ready time for the queue expires). This counter 199 * must be non-zero for frames to be scheduled for 200 * transmission. The following controls disable bumping 201 * this counter under certain conditions. Typically this 202 * is used to gate frames based on the contents of another 203 * queue (e.g. CAB traffic may only follow a beacon frame). 204 * These are meaningful only when frames are scheduled 205 * with a non-ASAP policy (e.g. DBA-gated). 206 */ 207 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 208 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 209 210 /* 211 * Fragment burst backoff policy. Normally the no backoff 212 * is done after a successful transmission, the next fragment 213 * is sent at SIFS. If this flag is set backoff is done 214 * after each fragment, regardless whether it was ack'd or 215 * not, after the backoff count reaches zero a normal channel 216 * access procedure is done before the next transmit (i.e. 217 * wait AIFS instead of SIFS). 218 */ 219 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 220 /* 221 * Disable post-tx backoff following each frame. 222 */ 223 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 224 /* 225 * DCU arbiter lockout control. This controls how 226 * lower priority tx queues are handled with respect to 227 * to a specific queue when multiple queues have frames 228 * to send. No lockout means lower priority queues arbitrate 229 * concurrently with this queue. Intra-frame lockout 230 * means lower priority queues are locked out until the 231 * current frame transmits (e.g. including backoffs and bursting). 232 * Global lockout means nothing lower can arbitrary so 233 * long as there is traffic activity on this queue (frames, 234 * backoff, etc). 235 */ 236 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 237 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 238 239 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 240 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 241} HAL_TX_QUEUE_FLAGS; 242 243typedef struct { 244 uint32_t tqi_ver; /* hal TXQ version */ 245 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 246 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 247 uint32_t tqi_priority; /* (not used) */ 248 uint32_t tqi_aifs; /* aifs */ 249 uint32_t tqi_cwmin; /* cwMin */ 250 uint32_t tqi_cwmax; /* cwMax */ 251 uint16_t tqi_shretry; /* rts retry limit */ 252 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 253 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 254 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 255 uint32_t tqi_burstTime; /* max burst duration (us) */ 256 uint32_t tqi_readyTime; /* frame schedule time (us) */ 257 uint32_t tqi_compBuf; /* comp buffer phys addr */ 258} HAL_TXQ_INFO; 259 260#define HAL_TQI_NONVAL 0xffff 261 262/* token to use for aifs, cwmin, cwmax */ 263#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 264 265/* compression definitions */ 266#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 267#define HAL_COMP_BUF_ALIGN_SIZE 512 268 269/* 270 * Transmit packet types. This belongs in ah_desc.h, but 271 * is here so we can give a proper type to various parameters 272 * (and not require everyone include the file). 273 * 274 * NB: These values are intentionally assigned for 275 * direct use when setting up h/w descriptors. 276 */ 277typedef enum { 278 HAL_PKT_TYPE_NORMAL = 0, 279 HAL_PKT_TYPE_ATIM = 1, 280 HAL_PKT_TYPE_PSPOLL = 2, 281 HAL_PKT_TYPE_BEACON = 3, 282 HAL_PKT_TYPE_PROBE_RESP = 4, 283 HAL_PKT_TYPE_CHIRP = 5, 284 HAL_PKT_TYPE_GRP_POLL = 6, 285 HAL_PKT_TYPE_AMPDU = 7, 286} HAL_PKT_TYPE; 287 288/* Rx Filter Frame Types */ 289typedef enum { 290 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 291 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 292 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 293 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 294 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 295 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 296 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 297 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 298 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 299 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 300 HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */ 301} HAL_RX_FILTER; 302 303typedef enum { 304 HAL_PM_AWAKE = 0, 305 HAL_PM_FULL_SLEEP = 1, 306 HAL_PM_NETWORK_SLEEP = 2, 307 HAL_PM_UNDEFINED = 3 308} HAL_POWER_MODE; 309 310/* 311 * NOTE WELL: 312 * These are mapped to take advantage of the common locations for many of 313 * the bits on all of the currently supported MAC chips. This is to make 314 * the ISR as efficient as possible, while still abstracting HW differences. 315 * When new hardware breaks this commonality this enumerated type, as well 316 * as the HAL functions using it, must be modified. All values are directly 317 * mapped unless commented otherwise. 318 */ 319typedef enum { 320 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 321 HAL_INT_RXDESC = 0x00000002, 322 HAL_INT_RXNOFRM = 0x00000008, 323 HAL_INT_RXEOL = 0x00000010, 324 HAL_INT_RXORN = 0x00000020, 325 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 326 HAL_INT_TXDESC = 0x00000080, 327 HAL_INT_TIM_TIMER= 0x00000100, 328 HAL_INT_TXURN = 0x00000800, 329 HAL_INT_MIB = 0x00001000, 330 HAL_INT_RXPHY = 0x00004000, 331 HAL_INT_RXKCM = 0x00008000, 332 HAL_INT_SWBA = 0x00010000, 333 HAL_INT_BMISS = 0x00040000, 334 HAL_INT_BNR = 0x00100000, 335 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 336 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 337 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 338 HAL_INT_GPIO = 0x01000000, 339 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 340 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 341 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 342 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 343 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 344 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 345#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 346 HAL_INT_BMISC = HAL_INT_TIM 347 | HAL_INT_DTIM 348 | HAL_INT_DTIMSYNC 349 | HAL_INT_CABEND 350 | HAL_INT_TBTT, 351 352 /* Interrupt bits that map directly to ISR/IMR bits */ 353 HAL_INT_COMMON = HAL_INT_RXNOFRM 354 | HAL_INT_RXDESC 355 | HAL_INT_RXEOL 356 | HAL_INT_RXORN 357 | HAL_INT_TXDESC 358 | HAL_INT_TXURN 359 | HAL_INT_MIB 360 | HAL_INT_RXPHY 361 | HAL_INT_RXKCM 362 | HAL_INT_SWBA 363 | HAL_INT_BMISS 364 | HAL_INT_BNR 365 | HAL_INT_GPIO, 366} HAL_INT; 367 368typedef enum { 369 HAL_GPIO_MUX_OUTPUT = 0, 370 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 371 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 372 HAL_GPIO_MUX_TX_FRAME = 3, 373 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 374 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 375 HAL_GPIO_MUX_MAC_POWER_LED = 6 376} HAL_GPIO_MUX_TYPE; 377 378typedef enum { 379 HAL_GPIO_INTR_LOW = 0, 380 HAL_GPIO_INTR_HIGH = 1, 381 HAL_GPIO_INTR_DISABLE = 2 382} HAL_GPIO_INTR_TYPE; 383 384typedef enum { 385 HAL_RFGAIN_INACTIVE = 0, 386 HAL_RFGAIN_READ_REQUESTED = 1, 387 HAL_RFGAIN_NEED_CHANGE = 2 388} HAL_RFGAIN; 389 390typedef uint16_t HAL_CTRY_CODE; /* country code */ 391typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 392 393#define HAL_ANTENNA_MIN_MODE 0 394#define HAL_ANTENNA_FIXED_A 1 395#define HAL_ANTENNA_FIXED_B 2 396#define HAL_ANTENNA_MAX_MODE 3 397 398typedef struct { 399 uint32_t ackrcv_bad; 400 uint32_t rts_bad; 401 uint32_t rts_good; 402 uint32_t fcs_bad; 403 uint32_t beacons; 404} HAL_MIB_STATS; 405 406enum { 407 HAL_MODE_11A = 0x001, /* 11a channels */ 408 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 409 HAL_MODE_11B = 0x004, /* 11b channels */ 410 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 411#ifdef notdef 412 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 413#else 414 HAL_MODE_11G = 0x008, /* XXX historical */ 415#endif 416 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 417 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 418 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 419 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 420 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 421 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 422 HAL_MODE_11NG_HT20 = 0x008000, 423 HAL_MODE_11NA_HT20 = 0x010000, 424 HAL_MODE_11NG_HT40PLUS = 0x020000, 425 HAL_MODE_11NG_HT40MINUS = 0x040000, 426 HAL_MODE_11NA_HT40PLUS = 0x080000, 427 HAL_MODE_11NA_HT40MINUS = 0x100000, 428 HAL_MODE_ALL = 0xffffff 429}; 430 431typedef struct { 432 int rateCount; /* NB: for proper padding */ 433 uint8_t rateCodeToIndex[144]; /* back mapping */ 434 struct { 435 uint8_t valid; /* valid for rate control use */ 436 uint8_t phy; /* CCK/OFDM/XR */ 437 uint32_t rateKbps; /* transfer rate in kbs */ 438 uint8_t rateCode; /* rate for h/w descriptors */ 439 uint8_t shortPreamble; /* mask for enabling short 440 * preamble in CCK rate code */ 441 uint8_t dot11Rate; /* value for supported rates 442 * info element of MLME */ 443 uint8_t controlRate; /* index of next lower basic 444 * rate; used for dur. calcs */ 445 uint16_t lpAckDuration; /* long preamble ACK duration */ 446 uint16_t spAckDuration; /* short preamble ACK duration*/ 447 } info[32]; 448} HAL_RATE_TABLE; 449 450typedef struct { 451 u_int rs_count; /* number of valid entries */ 452 uint8_t rs_rates[32]; /* rates */ 453} HAL_RATE_SET; 454 455/* 456 * 802.11n specific structures and enums 457 */ 458typedef enum { 459 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 460 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 461} HAL_CHAIN_TYPE; 462 463typedef struct { 464 u_int Tries; 465 u_int Rate; 466 u_int PktDuration; 467 u_int ChSel; 468 u_int RateFlags; 469#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 470#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 471#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 472} HAL_11N_RATE_SERIES; 473 474typedef enum { 475 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 476 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 477} HAL_HT_MACMODE; 478 479typedef enum { 480 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 481 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 482} HAL_HT_PHYMODE; 483 484typedef enum { 485 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 486 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 487} HAL_HT_EXTPROTSPACING; 488 489 490typedef enum { 491 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 492 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 493} HAL_HT_RXCLEAR; 494 495/* 496 * Antenna switch control. By default antenna selection 497 * enables multiple (2) antenna use. To force use of the 498 * A or B antenna only specify a fixed setting. Fixing 499 * the antenna will also disable any diversity support. 500 */ 501typedef enum { 502 HAL_ANT_VARIABLE = 0, /* variable by programming */ 503 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 504 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 505} HAL_ANT_SETTING; 506 507typedef enum { 508 HAL_M_STA = 1, /* infrastructure station */ 509 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 510 HAL_M_HOSTAP = 6, /* Software Access Point */ 511 HAL_M_MONITOR = 8 /* Monitor mode */ 512} HAL_OPMODE; 513 514typedef struct { 515 uint8_t kv_type; /* one of HAL_CIPHER */ 516 uint8_t kv_pad; 517 uint16_t kv_len; /* length in bits */ 518 uint8_t kv_val[16]; /* enough for 128-bit keys */ 519 uint8_t kv_mic[8]; /* TKIP MIC key */ 520 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 521} HAL_KEYVAL; 522 523typedef enum { 524 HAL_CIPHER_WEP = 0, 525 HAL_CIPHER_AES_OCB = 1, 526 HAL_CIPHER_AES_CCM = 2, 527 HAL_CIPHER_CKIP = 3, 528 HAL_CIPHER_TKIP = 4, 529 HAL_CIPHER_CLR = 5, /* no encryption */ 530 531 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 532} HAL_CIPHER; 533 534enum { 535 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 536 HAL_SLOT_TIME_9 = 9, 537 HAL_SLOT_TIME_20 = 20, 538}; 539 540/* 541 * Per-station beacon timer state. Note that the specified 542 * beacon interval (given in TU's) can also include flags 543 * to force a TSF reset and to enable the beacon xmit logic. 544 * If bs_cfpmaxduration is non-zero the hardware is setup to 545 * coexist with a PCF-capable AP. 546 */ 547typedef struct { 548 uint32_t bs_nexttbtt; /* next beacon in TU */ 549 uint32_t bs_nextdtim; /* next DTIM in TU */ 550 uint32_t bs_intval; /* beacon interval+flags */ 551#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 552#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 553#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 554 uint32_t bs_dtimperiod; 555 uint16_t bs_cfpperiod; /* CFP period in TU */ 556 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 557 uint32_t bs_cfpnext; /* next CFP in TU */ 558 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 559 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 560 uint32_t bs_sleepduration; /* max sleep duration */ 561} HAL_BEACON_STATE; 562 563/* 564 * Like HAL_BEACON_STATE but for non-station mode setup. 565 * NB: see above flag definitions for bt_intval. 566 */ 567typedef struct { 568 uint32_t bt_intval; /* beacon interval+flags */ 569 uint32_t bt_nexttbtt; /* next beacon in TU */ 570 uint32_t bt_nextatim; /* next ATIM in TU */ 571 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 572 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 573 uint32_t bt_flags; /* timer enables */ 574#define HAL_BEACON_TBTT_EN 0x00000001 575#define HAL_BEACON_DBA_EN 0x00000002 576#define HAL_BEACON_SWBA_EN 0x00000004 577} HAL_BEACON_TIMERS; 578 579/* 580 * Per-node statistics maintained by the driver for use in 581 * optimizing signal quality and other operational aspects. 582 */ 583typedef struct { 584 uint32_t ns_avgbrssi; /* average beacon rssi */ 585 uint32_t ns_avgrssi; /* average data rssi */ 586 uint32_t ns_avgtxrssi; /* average tx rssi */ 587} HAL_NODE_STATS; 588 589#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 590 591struct ath_desc; 592struct ath_tx_status; 593struct ath_rx_status; 594struct ieee80211_channel; 595 596/* 597 * Hardware Access Layer (HAL) API. 598 * 599 * Clients of the HAL call ath_hal_attach to obtain a reference to an 600 * ath_hal structure for use with the device. Hardware-related operations 601 * that follow must call back into the HAL through interface, supplying 602 * the reference as the first parameter. Note that before using the 603 * reference returned by ath_hal_attach the caller should verify the 604 * ABI version number. 605 */ 606struct ath_hal { 607 uint32_t ah_magic; /* consistency check magic number */ 608 uint16_t ah_devid; /* PCI device ID */ 609 uint16_t ah_subvendorid; /* PCI subvendor ID */ 610 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 611 HAL_BUS_TAG ah_st; /* params for register r+w */ 612 HAL_BUS_HANDLE ah_sh; 613 HAL_CTRY_CODE ah_countryCode; 614 615 uint32_t ah_macVersion; /* MAC version id */ 616 uint16_t ah_macRev; /* MAC revision */ 617 uint16_t ah_phyRev; /* PHY revision */ 618 /* NB: when only one radio is present the rev is in 5Ghz */ 619 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 620 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 621 622 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 623 624 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 625 u_int mode); 626 void __ahdecl(*ah_detach)(struct ath_hal*); 627 628 /* Reset functions */ 629 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 630 struct ieee80211_channel *, 631 HAL_BOOL bChannelChange, HAL_STATUS *status); 632 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 633 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 634 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 635 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 636 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 637 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 638 struct ieee80211_channel *, HAL_BOOL *); 639 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 640 struct ieee80211_channel *, u_int chainMask, 641 HAL_BOOL longCal, HAL_BOOL *isCalDone); 642 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 643 const struct ieee80211_channel *); 644 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 645 const struct ieee80211_channel *, uint16_t *); 646 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 647 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 648 const struct ieee80211_channel *); 649 650 /* Transmit functions */ 651 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 652 HAL_BOOL incTrigLevel); 653 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 654 const HAL_TXQ_INFO *qInfo); 655 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 656 const HAL_TXQ_INFO *qInfo); 657 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 658 HAL_TXQ_INFO *qInfo); 659 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 660 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 661 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 662 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 663 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 664 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 665 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 666 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 667 u_int pktLen, u_int hdrLen, 668 HAL_PKT_TYPE type, u_int txPower, 669 u_int txRate0, u_int txTries0, 670 u_int keyIx, u_int antMode, u_int flags, 671 u_int rtsctsRate, u_int rtsctsDuration, 672 u_int compicvLen, u_int compivLen, 673 u_int comp); 674 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 675 u_int txRate1, u_int txTries1, 676 u_int txRate2, u_int txTries2, 677 u_int txRate3, u_int txTries3); 678 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 679 u_int segLen, HAL_BOOL firstSeg, 680 HAL_BOOL lastSeg, const struct ath_desc *); 681 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 682 struct ath_desc *, struct ath_tx_status *); 683 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 684 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 685 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 686 const struct ath_desc *ds, int *rates, int *tries); 687 688 /* Receive Functions */ 689 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 690 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 691 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 692 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 693 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 694 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 695 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 696 uint32_t filter0, uint32_t filter1); 697 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 698 uint32_t index); 699 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 700 uint32_t index); 701 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 702 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 703 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 704 uint32_t size, u_int flags); 705 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 706 struct ath_desc *, uint32_t phyAddr, 707 struct ath_desc *next, uint64_t tsf, 708 struct ath_rx_status *); 709 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 710 const HAL_NODE_STATS *, 711 const struct ieee80211_channel *); 712 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 713 const HAL_NODE_STATS *); 714 715 /* Misc Functions */ 716 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 717 HAL_CAPABILITY_TYPE, uint32_t capability, 718 uint32_t *result); 719 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 720 HAL_CAPABILITY_TYPE, uint32_t capability, 721 uint32_t setting, HAL_STATUS *); 722 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 723 const void *args, uint32_t argsize, 724 void **result, uint32_t *resultsize); 725 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 726 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 727 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 728 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 729 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 730 uint16_t, HAL_STATUS *); 731 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 732 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 733 const uint8_t *bssid, uint16_t assocId); 734 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 735 uint32_t gpio, HAL_GPIO_MUX_TYPE); 736 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 737 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 738 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 739 uint32_t gpio, uint32_t val); 740 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 741 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 742 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 743 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 744 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 745 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 746 HAL_MIB_STATS*); 747 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 748 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 749 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 750 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 751 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 752 HAL_ANT_SETTING); 753 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 754 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 755 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 756 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 757 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 758 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 759 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 760 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 761 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 762 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 763 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 764 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 765 766 /* Key Cache Functions */ 767 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 768 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 769 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 770 uint16_t); 771 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 772 uint16_t, const HAL_KEYVAL *, 773 const uint8_t *, int); 774 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 775 uint16_t, const uint8_t *); 776 777 /* Power Management Functions */ 778 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 779 HAL_POWER_MODE mode, int setChip); 780 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 781 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 782 const struct ieee80211_channel *); 783 784 /* Beacon Management Functions */ 785 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 786 const HAL_BEACON_TIMERS *); 787 /* NB: deprecated, use ah_setBeaconTimers instead */ 788 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 789 uint32_t nexttbtt, uint32_t intval); 790 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 791 const HAL_BEACON_STATE *); 792 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 793 794 /* Interrupt functions */ 795 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 796 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 797 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 798 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 799}; 800 801/* 802 * Check the PCI vendor ID and device ID against Atheros' values 803 * and return a printable description for any Atheros hardware. 804 * AH_NULL is returned if the ID's do not describe Atheros hardware. 805 */ 806extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 807 808/* 809 * Attach the HAL for use with the specified device. The device is 810 * defined by the PCI device ID. The caller provides an opaque pointer 811 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 812 * HAL state block for later use. Hardware register accesses are done 813 * using the specified bus tag and handle. On successful return a 814 * reference to a state block is returned that must be supplied in all 815 * subsequent HAL calls. Storage associated with this reference is 816 * dynamically allocated and must be freed by calling the ah_detach 817 * method when the client is done. If the attach operation fails a 818 * null (AH_NULL) reference will be returned and a status code will 819 * be returned if the status parameter is non-zero. 820 */ 821extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 822 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 823 824extern const char *ath_hal_mac_name(struct ath_hal *); 825extern const char *ath_hal_rf_name(struct ath_hal *); 826 827/* 828 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 829 * request a set of channels for a particular country code and/or 830 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 831 * this list is constructed according to the contents of the EEPROM. 832 * ath_hal_getchannels acts similarly but does not alter the operating 833 * state; this can be used to collect information for a particular 834 * regulatory configuration. Finally ath_hal_set_channels installs a 835 * channel list constructed outside the driver. The HAL will adopt the 836 * channel list and setup internal state according to the specified 837 * regulatory configuration (e.g. conformance test limits). 838 * 839 * For all interfaces the channel list is returned in the supplied array. 840 * maxchans defines the maximum size of this array. nchans contains the 841 * actual number of channels returned. If a problem occurred then a 842 * status code != HAL_OK is returned. 843 */ 844struct ieee80211_channel; 845 846/* 847 * Return a list of channels according to the specified regulatory. 848 */ 849extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 850 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 851 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 852 HAL_BOOL enableExtendedChannels); 853 854/* 855 * Return a list of channels and install it as the current operating 856 * regulatory list. 857 */ 858extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 859 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 860 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 861 HAL_BOOL enableExtendedChannels); 862 863/* 864 * Install the list of channels as the current operating regulatory 865 * and setup related state according to the country code and sku. 866 */ 867extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 868 struct ieee80211_channel *chans, int nchans, 869 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 870 871/* 872 * Calibrate noise floor data following a channel scan or similar. 873 * This must be called prior retrieving noise floor data. 874 */ 875extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 876 877/* 878 * Return bit mask of wireless modes supported by the hardware. 879 */ 880extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 881 882/* 883 * Calculate the transmit duration of a frame. 884 */ 885extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 886 const HAL_RATE_TABLE *rates, uint32_t frameLen, 887 uint16_t rateix, HAL_BOOL shortPreamble); 888#endif /* _ATH_AH_H_ */ 889