ah.h revision 192396
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 192396 2009-05-19 17:30:13Z sam $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * __ahdecl is analogous to _cdecl; it defines the calling 35 * convention used within the HAL. For most systems this 36 * can just default to be empty and the compiler will (should) 37 * use _cdecl. For systems where _cdecl is not compatible this 38 * must be defined. See linux/ah_osdep.h for an example. 39 */ 40#ifndef __ahdecl 41#define __ahdecl 42#endif 43 44/* 45 * Status codes that may be returned by the HAL. Note that 46 * interfaces that return a status code set it only when an 47 * error occurs--i.e. you cannot check it for success. 48 */ 49typedef enum { 50 HAL_OK = 0, /* No error */ 51 HAL_ENXIO = 1, /* No hardware present */ 52 HAL_ENOMEM = 2, /* Memory allocation failed */ 53 HAL_EIO = 3, /* Hardware didn't respond as expected */ 54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55 HAL_EEVERSION = 5, /* EEPROM version invalid */ 56 HAL_EELOCKED = 6, /* EEPROM unreadable */ 57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58 HAL_EEREAD = 8, /* EEPROM read problem */ 59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60 HAL_EESIZE = 10, /* EEPROM size not supported */ 61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62 HAL_EINVAL = 12, /* Invalid parameter to function */ 63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65 HAL_EINPROGRESS = 15, /* Operation incomplete */ 66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68} HAL_STATUS; 69 70typedef enum { 71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72 AH_TRUE = 1, 73} HAL_BOOL; 74 75typedef enum { 76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90 HAL_CAP_TXPOW = 15, /* global tx power limit */ 91 HAL_CAP_TPC = 16, /* per-packet tx power control */ 92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96 /* 21 was HAL_CAP_XR */ 97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98 /* 23 was HAL_CAP_CHAN_HALFRATE */ 99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104 HAL_CAP_INTMIT = 29, /* interference mitigation */ 105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106 HAL_CAP_HT = 31, /* hardware can support HT */ 107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110 HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113} HAL_CAPABILITY_TYPE; 114 115/* 116 * "States" for setting the LED. These correspond to 117 * the possible 802.11 operational states and there may 118 * be a many-to-one mapping between these states and the 119 * actual hardware state for the LED's (i.e. the hardware 120 * may have fewer states). 121 */ 122typedef enum { 123 HAL_LED_INIT = 0, 124 HAL_LED_SCAN = 1, 125 HAL_LED_AUTH = 2, 126 HAL_LED_ASSOC = 3, 127 HAL_LED_RUN = 4 128} HAL_LED_STATE; 129 130/* 131 * Transmit queue types/numbers. These are used to tag 132 * each transmit queue in the hardware and to identify a set 133 * of transmit queues for operations such as start/stop dma. 134 */ 135typedef enum { 136 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 137 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 138 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 139 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 140 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 141} HAL_TX_QUEUE; 142 143#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 144 145/* 146 * Transmit queue subtype. These map directly to 147 * WME Access Categories (except for UPSD). Refer 148 * to Table 5 of the WME spec. 149 */ 150typedef enum { 151 HAL_WME_AC_BK = 0, /* background access category */ 152 HAL_WME_AC_BE = 1, /* best effort access category*/ 153 HAL_WME_AC_VI = 2, /* video access category */ 154 HAL_WME_AC_VO = 3, /* voice access category */ 155 HAL_WME_UPSD = 4, /* uplink power save */ 156} HAL_TX_QUEUE_SUBTYPE; 157 158/* 159 * Transmit queue flags that control various 160 * operational parameters. 161 */ 162typedef enum { 163 /* 164 * Per queue interrupt enables. When set the associated 165 * interrupt may be delivered for packets sent through 166 * the queue. Without these enabled no interrupts will 167 * be delivered for transmits through the queue. 168 */ 169 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 170 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 171 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 172 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 173 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 174 /* 175 * Enable hardware compression for packets sent through 176 * the queue. The compression buffer must be setup and 177 * packets must have a key entry marked in the tx descriptor. 178 */ 179 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 180 /* 181 * Disable queue when veol is hit or ready time expires. 182 * By default the queue is disabled only on reaching the 183 * physical end of queue (i.e. a null link ptr in the 184 * descriptor chain). 185 */ 186 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 187 /* 188 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 189 * event. Frames will be transmitted only when this timer 190 * fires, e.g to transmit a beacon in ap or adhoc modes. 191 */ 192 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 193 /* 194 * Each transmit queue has a counter that is incremented 195 * each time the queue is enabled and decremented when 196 * the list of frames to transmit is traversed (or when 197 * the ready time for the queue expires). This counter 198 * must be non-zero for frames to be scheduled for 199 * transmission. The following controls disable bumping 200 * this counter under certain conditions. Typically this 201 * is used to gate frames based on the contents of another 202 * queue (e.g. CAB traffic may only follow a beacon frame). 203 * These are meaningful only when frames are scheduled 204 * with a non-ASAP policy (e.g. DBA-gated). 205 */ 206 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 207 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 208 209 /* 210 * Fragment burst backoff policy. Normally the no backoff 211 * is done after a successful transmission, the next fragment 212 * is sent at SIFS. If this flag is set backoff is done 213 * after each fragment, regardless whether it was ack'd or 214 * not, after the backoff count reaches zero a normal channel 215 * access procedure is done before the next transmit (i.e. 216 * wait AIFS instead of SIFS). 217 */ 218 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 219 /* 220 * Disable post-tx backoff following each frame. 221 */ 222 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 223 /* 224 * DCU arbiter lockout control. This controls how 225 * lower priority tx queues are handled with respect to 226 * to a specific queue when multiple queues have frames 227 * to send. No lockout means lower priority queues arbitrate 228 * concurrently with this queue. Intra-frame lockout 229 * means lower priority queues are locked out until the 230 * current frame transmits (e.g. including backoffs and bursting). 231 * Global lockout means nothing lower can arbitrary so 232 * long as there is traffic activity on this queue (frames, 233 * backoff, etc). 234 */ 235 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 236 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 237 238 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 239 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 240} HAL_TX_QUEUE_FLAGS; 241 242typedef struct { 243 uint32_t tqi_ver; /* hal TXQ version */ 244 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 245 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 246 uint32_t tqi_priority; /* (not used) */ 247 uint32_t tqi_aifs; /* aifs */ 248 uint32_t tqi_cwmin; /* cwMin */ 249 uint32_t tqi_cwmax; /* cwMax */ 250 uint16_t tqi_shretry; /* rts retry limit */ 251 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 252 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 253 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 254 uint32_t tqi_burstTime; /* max burst duration (us) */ 255 uint32_t tqi_readyTime; /* frame schedule time (us) */ 256 uint32_t tqi_compBuf; /* comp buffer phys addr */ 257} HAL_TXQ_INFO; 258 259#define HAL_TQI_NONVAL 0xffff 260 261/* token to use for aifs, cwmin, cwmax */ 262#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 263 264/* compression definitions */ 265#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 266#define HAL_COMP_BUF_ALIGN_SIZE 512 267 268/* 269 * Transmit packet types. This belongs in ah_desc.h, but 270 * is here so we can give a proper type to various parameters 271 * (and not require everyone include the file). 272 * 273 * NB: These values are intentionally assigned for 274 * direct use when setting up h/w descriptors. 275 */ 276typedef enum { 277 HAL_PKT_TYPE_NORMAL = 0, 278 HAL_PKT_TYPE_ATIM = 1, 279 HAL_PKT_TYPE_PSPOLL = 2, 280 HAL_PKT_TYPE_BEACON = 3, 281 HAL_PKT_TYPE_PROBE_RESP = 4, 282 HAL_PKT_TYPE_CHIRP = 5, 283 HAL_PKT_TYPE_GRP_POLL = 6, 284 HAL_PKT_TYPE_AMPDU = 7, 285} HAL_PKT_TYPE; 286 287/* Rx Filter Frame Types */ 288typedef enum { 289 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 290 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 291 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 292 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 293 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 294 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 295 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 296 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 297 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 298 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 299} HAL_RX_FILTER; 300 301typedef enum { 302 HAL_PM_AWAKE = 0, 303 HAL_PM_FULL_SLEEP = 1, 304 HAL_PM_NETWORK_SLEEP = 2, 305 HAL_PM_UNDEFINED = 3 306} HAL_POWER_MODE; 307 308/* 309 * NOTE WELL: 310 * These are mapped to take advantage of the common locations for many of 311 * the bits on all of the currently supported MAC chips. This is to make 312 * the ISR as efficient as possible, while still abstracting HW differences. 313 * When new hardware breaks this commonality this enumerated type, as well 314 * as the HAL functions using it, must be modified. All values are directly 315 * mapped unless commented otherwise. 316 */ 317typedef enum { 318 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 319 HAL_INT_RXDESC = 0x00000002, 320 HAL_INT_RXNOFRM = 0x00000008, 321 HAL_INT_RXEOL = 0x00000010, 322 HAL_INT_RXORN = 0x00000020, 323 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 324 HAL_INT_TXDESC = 0x00000080, 325 HAL_INT_TXURN = 0x00000800, 326 HAL_INT_MIB = 0x00001000, 327 HAL_INT_RXPHY = 0x00004000, 328 HAL_INT_RXKCM = 0x00008000, 329 HAL_INT_SWBA = 0x00010000, 330 HAL_INT_BMISS = 0x00040000, 331 HAL_INT_BNR = 0x00100000, /* Non-common mapping */ 332 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 333 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 334 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 335 HAL_INT_GPIO = 0x01000000, 336 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 337 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 338 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 339 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 340 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 341#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 342 HAL_INT_BMISC = HAL_INT_TIM 343 | HAL_INT_DTIM 344 | HAL_INT_DTIMSYNC 345 | HAL_INT_CABEND, 346 347 /* Interrupt bits that map directly to ISR/IMR bits */ 348 HAL_INT_COMMON = HAL_INT_RXNOFRM 349 | HAL_INT_RXDESC 350 | HAL_INT_RXEOL 351 | HAL_INT_RXORN 352 | HAL_INT_TXDESC 353 | HAL_INT_TXURN 354 | HAL_INT_MIB 355 | HAL_INT_RXPHY 356 | HAL_INT_RXKCM 357 | HAL_INT_SWBA 358 | HAL_INT_BMISS 359 | HAL_INT_GPIO, 360} HAL_INT; 361 362typedef enum { 363 HAL_GPIO_MUX_OUTPUT = 0, 364 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 365 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 366 HAL_GPIO_MUX_TX_FRAME = 3, 367 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 368 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 369 HAL_GPIO_MUX_MAC_POWER_LED = 6 370} HAL_GPIO_MUX_TYPE; 371 372typedef enum { 373 HAL_GPIO_INTR_LOW = 0, 374 HAL_GPIO_INTR_HIGH = 1, 375 HAL_GPIO_INTR_DISABLE = 2 376} HAL_GPIO_INTR_TYPE; 377 378typedef enum { 379 HAL_RFGAIN_INACTIVE = 0, 380 HAL_RFGAIN_READ_REQUESTED = 1, 381 HAL_RFGAIN_NEED_CHANGE = 2 382} HAL_RFGAIN; 383 384typedef uint16_t HAL_CTRY_CODE; /* country code */ 385typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 386 387#define HAL_ANTENNA_MIN_MODE 0 388#define HAL_ANTENNA_FIXED_A 1 389#define HAL_ANTENNA_FIXED_B 2 390#define HAL_ANTENNA_MAX_MODE 3 391 392typedef struct { 393 uint32_t ackrcv_bad; 394 uint32_t rts_bad; 395 uint32_t rts_good; 396 uint32_t fcs_bad; 397 uint32_t beacons; 398} HAL_MIB_STATS; 399 400enum { 401 HAL_MODE_11A = 0x001, /* 11a channels */ 402 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 403 HAL_MODE_11B = 0x004, /* 11b channels */ 404 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 405#ifdef notdef 406 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 407#else 408 HAL_MODE_11G = 0x008, /* XXX historical */ 409#endif 410 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 411 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 412 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 413 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 414 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 415 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 416 HAL_MODE_11NG_HT20 = 0x008000, 417 HAL_MODE_11NA_HT20 = 0x010000, 418 HAL_MODE_11NG_HT40PLUS = 0x020000, 419 HAL_MODE_11NG_HT40MINUS = 0x040000, 420 HAL_MODE_11NA_HT40PLUS = 0x080000, 421 HAL_MODE_11NA_HT40MINUS = 0x100000, 422 HAL_MODE_ALL = 0xffffff 423}; 424 425typedef struct { 426 int rateCount; /* NB: for proper padding */ 427 uint8_t rateCodeToIndex[144]; /* back mapping */ 428 struct { 429 uint8_t valid; /* valid for rate control use */ 430 uint8_t phy; /* CCK/OFDM/XR */ 431 uint32_t rateKbps; /* transfer rate in kbs */ 432 uint8_t rateCode; /* rate for h/w descriptors */ 433 uint8_t shortPreamble; /* mask for enabling short 434 * preamble in CCK rate code */ 435 uint8_t dot11Rate; /* value for supported rates 436 * info element of MLME */ 437 uint8_t controlRate; /* index of next lower basic 438 * rate; used for dur. calcs */ 439 uint16_t lpAckDuration; /* long preamble ACK duration */ 440 uint16_t spAckDuration; /* short preamble ACK duration*/ 441 } info[32]; 442} HAL_RATE_TABLE; 443 444typedef struct { 445 u_int rs_count; /* number of valid entries */ 446 uint8_t rs_rates[32]; /* rates */ 447} HAL_RATE_SET; 448 449/* 450 * 802.11n specific structures and enums 451 */ 452typedef enum { 453 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 454 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 455} HAL_CHAIN_TYPE; 456 457typedef struct { 458 u_int Tries; 459 u_int Rate; 460 u_int PktDuration; 461 u_int ChSel; 462 u_int RateFlags; 463#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 464#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 465#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 466} HAL_11N_RATE_SERIES; 467 468typedef enum { 469 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 470 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 471} HAL_HT_MACMODE; 472 473typedef enum { 474 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 475 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 476} HAL_HT_PHYMODE; 477 478typedef enum { 479 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 480 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 481} HAL_HT_EXTPROTSPACING; 482 483 484typedef enum { 485 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 486 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 487} HAL_HT_RXCLEAR; 488 489/* 490 * Antenna switch control. By default antenna selection 491 * enables multiple (2) antenna use. To force use of the 492 * A or B antenna only specify a fixed setting. Fixing 493 * the antenna will also disable any diversity support. 494 */ 495typedef enum { 496 HAL_ANT_VARIABLE = 0, /* variable by programming */ 497 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 498 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 499} HAL_ANT_SETTING; 500 501typedef enum { 502 HAL_M_STA = 1, /* infrastructure station */ 503 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 504 HAL_M_HOSTAP = 6, /* Software Access Point */ 505 HAL_M_MONITOR = 8 /* Monitor mode */ 506} HAL_OPMODE; 507 508typedef struct { 509 uint8_t kv_type; /* one of HAL_CIPHER */ 510 uint8_t kv_pad; 511 uint16_t kv_len; /* length in bits */ 512 uint8_t kv_val[16]; /* enough for 128-bit keys */ 513 uint8_t kv_mic[8]; /* TKIP MIC key */ 514 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 515} HAL_KEYVAL; 516 517typedef enum { 518 HAL_CIPHER_WEP = 0, 519 HAL_CIPHER_AES_OCB = 1, 520 HAL_CIPHER_AES_CCM = 2, 521 HAL_CIPHER_CKIP = 3, 522 HAL_CIPHER_TKIP = 4, 523 HAL_CIPHER_CLR = 5, /* no encryption */ 524 525 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 526} HAL_CIPHER; 527 528enum { 529 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 530 HAL_SLOT_TIME_9 = 9, 531 HAL_SLOT_TIME_20 = 20, 532}; 533 534/* 535 * Per-station beacon timer state. Note that the specified 536 * beacon interval (given in TU's) can also include flags 537 * to force a TSF reset and to enable the beacon xmit logic. 538 * If bs_cfpmaxduration is non-zero the hardware is setup to 539 * coexist with a PCF-capable AP. 540 */ 541typedef struct { 542 uint32_t bs_nexttbtt; /* next beacon in TU */ 543 uint32_t bs_nextdtim; /* next DTIM in TU */ 544 uint32_t bs_intval; /* beacon interval+flags */ 545#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 546#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 547#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 548 uint32_t bs_dtimperiod; 549 uint16_t bs_cfpperiod; /* CFP period in TU */ 550 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 551 uint32_t bs_cfpnext; /* next CFP in TU */ 552 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 553 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 554 uint32_t bs_sleepduration; /* max sleep duration */ 555} HAL_BEACON_STATE; 556 557/* 558 * Like HAL_BEACON_STATE but for non-station mode setup. 559 * NB: see above flag definitions for bt_intval. 560 */ 561typedef struct { 562 uint32_t bt_intval; /* beacon interval+flags */ 563 uint32_t bt_nexttbtt; /* next beacon in TU */ 564 uint32_t bt_nextatim; /* next ATIM in TU */ 565 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 566 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 567 uint32_t bt_flags; /* timer enables */ 568#define HAL_BEACON_TBTT_EN 0x00000001 569#define HAL_BEACON_DBA_EN 0x00000002 570#define HAL_BEACON_SWBA_EN 0x00000004 571} HAL_BEACON_TIMERS; 572 573/* 574 * Per-node statistics maintained by the driver for use in 575 * optimizing signal quality and other operational aspects. 576 */ 577typedef struct { 578 uint32_t ns_avgbrssi; /* average beacon rssi */ 579 uint32_t ns_avgrssi; /* average data rssi */ 580 uint32_t ns_avgtxrssi; /* average tx rssi */ 581} HAL_NODE_STATS; 582 583#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 584 585struct ath_desc; 586struct ath_tx_status; 587struct ath_rx_status; 588struct ieee80211_channel; 589 590/* 591 * Hardware Access Layer (HAL) API. 592 * 593 * Clients of the HAL call ath_hal_attach to obtain a reference to an 594 * ath_hal structure for use with the device. Hardware-related operations 595 * that follow must call back into the HAL through interface, supplying 596 * the reference as the first parameter. Note that before using the 597 * reference returned by ath_hal_attach the caller should verify the 598 * ABI version number. 599 */ 600struct ath_hal { 601 uint32_t ah_magic; /* consistency check magic number */ 602 uint16_t ah_devid; /* PCI device ID */ 603 uint16_t ah_subvendorid; /* PCI subvendor ID */ 604 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 605 HAL_BUS_TAG ah_st; /* params for register r+w */ 606 HAL_BUS_HANDLE ah_sh; 607 HAL_CTRY_CODE ah_countryCode; 608 609 uint32_t ah_macVersion; /* MAC version id */ 610 uint16_t ah_macRev; /* MAC revision */ 611 uint16_t ah_phyRev; /* PHY revision */ 612 /* NB: when only one radio is present the rev is in 5Ghz */ 613 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 614 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 615 616 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 617 u_int mode); 618 void __ahdecl(*ah_detach)(struct ath_hal*); 619 620 /* Reset functions */ 621 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 622 struct ieee80211_channel *, 623 HAL_BOOL bChannelChange, HAL_STATUS *status); 624 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 625 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 626 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 627 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 628 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 629 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 630 struct ieee80211_channel *, HAL_BOOL *); 631 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 632 struct ieee80211_channel *, u_int chainMask, 633 HAL_BOOL longCal, HAL_BOOL *isCalDone); 634 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 635 const struct ieee80211_channel *); 636 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 637 638 /* Transmit functions */ 639 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 640 HAL_BOOL incTrigLevel); 641 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 642 const HAL_TXQ_INFO *qInfo); 643 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 644 const HAL_TXQ_INFO *qInfo); 645 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 646 HAL_TXQ_INFO *qInfo); 647 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 648 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 649 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 650 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 651 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 652 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 653 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 654 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 655 u_int pktLen, u_int hdrLen, 656 HAL_PKT_TYPE type, u_int txPower, 657 u_int txRate0, u_int txTries0, 658 u_int keyIx, u_int antMode, u_int flags, 659 u_int rtsctsRate, u_int rtsctsDuration, 660 u_int compicvLen, u_int compivLen, 661 u_int comp); 662 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 663 u_int txRate1, u_int txTries1, 664 u_int txRate2, u_int txTries2, 665 u_int txRate3, u_int txTries3); 666 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 667 u_int segLen, HAL_BOOL firstSeg, 668 HAL_BOOL lastSeg, const struct ath_desc *); 669 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 670 struct ath_desc *, struct ath_tx_status *); 671 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 672 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 673 674 /* Receive Functions */ 675 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 676 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 677 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 678 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 679 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 680 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 681 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 682 uint32_t filter0, uint32_t filter1); 683 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 684 uint32_t index); 685 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 686 uint32_t index); 687 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 688 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 689 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 690 uint32_t size, u_int flags); 691 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 692 struct ath_desc *, uint32_t phyAddr, 693 struct ath_desc *next, uint64_t tsf, 694 struct ath_rx_status *); 695 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 696 const HAL_NODE_STATS *, 697 const struct ieee80211_channel *); 698 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 699 const HAL_NODE_STATS *); 700 701 /* Misc Functions */ 702 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 703 HAL_CAPABILITY_TYPE, uint32_t capability, 704 uint32_t *result); 705 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 706 HAL_CAPABILITY_TYPE, uint32_t capability, 707 uint32_t setting, HAL_STATUS *); 708 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 709 const void *args, uint32_t argsize, 710 void **result, uint32_t *resultsize); 711 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 712 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 713 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 714 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 715 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 716 uint16_t, HAL_STATUS *); 717 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 718 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 719 const uint8_t *bssid, uint16_t assocId); 720 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 721 uint32_t gpio, HAL_GPIO_MUX_TYPE); 722 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 723 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 724 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 725 uint32_t gpio, uint32_t val); 726 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 727 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 728 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 729 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 730 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 731 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 732 HAL_MIB_STATS*); 733 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 734 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 735 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 736 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 737 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 738 HAL_ANT_SETTING); 739 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 740 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 741 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 742 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 743 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 744 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 745 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 746 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 747 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 748 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 749 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 750 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 751 752 /* Key Cache Functions */ 753 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 754 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 755 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 756 uint16_t); 757 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 758 uint16_t, const HAL_KEYVAL *, 759 const uint8_t *, int); 760 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 761 uint16_t, const uint8_t *); 762 763 /* Power Management Functions */ 764 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 765 HAL_POWER_MODE mode, int setChip); 766 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 767 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 768 const struct ieee80211_channel *); 769 770 /* Beacon Management Functions */ 771 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 772 const HAL_BEACON_TIMERS *); 773 /* NB: deprecated, use ah_setBeaconTimers instead */ 774 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 775 uint32_t nexttbtt, uint32_t intval); 776 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 777 const HAL_BEACON_STATE *); 778 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 779 780 /* Interrupt functions */ 781 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 782 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 783 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 784 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 785}; 786 787/* 788 * Check the PCI vendor ID and device ID against Atheros' values 789 * and return a printable description for any Atheros hardware. 790 * AH_NULL is returned if the ID's do not describe Atheros hardware. 791 */ 792extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 793 794/* 795 * Attach the HAL for use with the specified device. The device is 796 * defined by the PCI device ID. The caller provides an opaque pointer 797 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 798 * HAL state block for later use. Hardware register accesses are done 799 * using the specified bus tag and handle. On successful return a 800 * reference to a state block is returned that must be supplied in all 801 * subsequent HAL calls. Storage associated with this reference is 802 * dynamically allocated and must be freed by calling the ah_detach 803 * method when the client is done. If the attach operation fails a 804 * null (AH_NULL) reference will be returned and a status code will 805 * be returned if the status parameter is non-zero. 806 */ 807extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 808 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status); 809 810extern const char *ath_hal_mac_name(struct ath_hal *); 811extern const char *ath_hal_rf_name(struct ath_hal *); 812 813/* 814 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 815 * request a set of channels for a particular country code and/or 816 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 817 * this list is constructed according to the contents of the EEPROM. 818 * ath_hal_getchannels acts similarly but does not alter the operating 819 * state; this can be used to collect information for a particular 820 * regulatory configuration. Finally ath_hal_set_channels installs a 821 * channel list constructed outside the driver. The HAL will adopt the 822 * channel list and setup internal state according to the specified 823 * regulatory configuration (e.g. conformance test limits). 824 * 825 * For all interfaces the channel list is returned in the supplied array. 826 * maxchans defines the maximum size of this array. nchans contains the 827 * actual number of channels returned. If a problem occurred then a 828 * status code != HAL_OK is returned. 829 */ 830struct ieee80211_channel; 831 832/* 833 * Return a list of channels according to the specified regulatory. 834 */ 835extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 836 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 837 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 838 HAL_BOOL enableExtendedChannels); 839 840/* 841 * Return a list of channels and install it as the current operating 842 * regulatory list. 843 */ 844extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 845 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 846 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 847 HAL_BOOL enableExtendedChannels); 848 849/* 850 * Install the list of channels as the current operating regulatory 851 * and setup related state according to the country code and sku. 852 */ 853extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 854 struct ieee80211_channel *chans, int nchans, 855 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 856 857/* 858 * Calibrate noise floor data following a channel scan or similar. 859 * This must be called prior retrieving noise floor data. 860 */ 861extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 862 863/* 864 * Return bit mask of wireless modes supported by the hardware. 865 */ 866extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 867 868/* 869 * Calculate the transmit duration of a frame. 870 */ 871extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 872 const HAL_RATE_TABLE *rates, uint32_t frameLen, 873 uint16_t rateix, HAL_BOOL shortPreamble); 874#endif /* _ATH_AH_H_ */ 875