ah.h revision 239289
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 239289 2012-08-15 08:06:06Z adrian $ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _ATH_AH_H_ 21185377Ssam#define _ATH_AH_H_ 22185377Ssam/* 23185377Ssam * Atheros Hardware Access Layer 24185377Ssam * 25185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26185377Ssam * structure for use with the device. Hardware-related operations that 27185377Ssam * follow must call back into the HAL through interface, supplying the 28185377Ssam * reference as the first parameter. 29185377Ssam */ 30185377Ssam 31185377Ssam#include "ah_osdep.h" 32185377Ssam 33185377Ssam/* 34220442Sadrian * The maximum number of TX/RX chains supported. 35220442Sadrian * This is intended to be used by various statistics gathering operations 36220442Sadrian * (NF, RSSI, EVM). 37220442Sadrian */ 38220442Sadrian#define AH_MIMO_MAX_CHAINS 3 39220442Sadrian#define AH_MIMO_MAX_EVM_PILOTS 6 40220442Sadrian 41220442Sadrian/* 42185377Ssam * __ahdecl is analogous to _cdecl; it defines the calling 43185377Ssam * convention used within the HAL. For most systems this 44185377Ssam * can just default to be empty and the compiler will (should) 45185377Ssam * use _cdecl. For systems where _cdecl is not compatible this 46185377Ssam * must be defined. See linux/ah_osdep.h for an example. 47185377Ssam */ 48185377Ssam#ifndef __ahdecl 49185377Ssam#define __ahdecl 50185377Ssam#endif 51185377Ssam 52185377Ssam/* 53185377Ssam * Status codes that may be returned by the HAL. Note that 54185377Ssam * interfaces that return a status code set it only when an 55185377Ssam * error occurs--i.e. you cannot check it for success. 56185377Ssam */ 57185377Ssamtypedef enum { 58185377Ssam HAL_OK = 0, /* No error */ 59185377Ssam HAL_ENXIO = 1, /* No hardware present */ 60185377Ssam HAL_ENOMEM = 2, /* Memory allocation failed */ 61185377Ssam HAL_EIO = 3, /* Hardware didn't respond as expected */ 62185377Ssam HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63185377Ssam HAL_EEVERSION = 5, /* EEPROM version invalid */ 64185377Ssam HAL_EELOCKED = 6, /* EEPROM unreadable */ 65185377Ssam HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66185377Ssam HAL_EEREAD = 8, /* EEPROM read problem */ 67185377Ssam HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68185377Ssam HAL_EESIZE = 10, /* EEPROM size not supported */ 69185377Ssam HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70185377Ssam HAL_EINVAL = 12, /* Invalid parameter to function */ 71185377Ssam HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72185377Ssam HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73185377Ssam HAL_EINPROGRESS = 15, /* Operation incomplete */ 74187831Ssam HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75187831Ssam HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76237874Sadrian HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77185377Ssam} HAL_STATUS; 78185377Ssam 79185377Ssamtypedef enum { 80185377Ssam AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81185377Ssam AH_TRUE = 1, 82185377Ssam} HAL_BOOL; 83185377Ssam 84185377Ssamtypedef enum { 85185377Ssam HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86185377Ssam HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87185377Ssam HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88185377Ssam HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89185377Ssam HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90185377Ssam HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91185377Ssam HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92185377Ssam HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93185377Ssam HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94185377Ssam HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95185377Ssam HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96185377Ssam HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97185377Ssam HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98185377Ssam HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99185377Ssam HAL_CAP_TXPOW = 15, /* global tx power limit */ 100185377Ssam HAL_CAP_TPC = 16, /* per-packet tx power control */ 101185377Ssam HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102185377Ssam HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103185377Ssam HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104185377Ssam HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105185377Ssam /* 21 was HAL_CAP_XR */ 106185377Ssam HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107185380Ssam /* 23 was HAL_CAP_CHAN_HALFRATE */ 108185380Ssam /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109185377Ssam HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110185377Ssam HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111185377Ssam HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112185377Ssam HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113237953Sadrian HAL_CAP_PCIE_PS = 29, 114221603Sadrian HAL_CAP_HT = 30, /* hardware can support HT */ 115221603Sadrian HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116221603Sadrian HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117221603Sadrian HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118221603Sadrian HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119221603Sadrian HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120221581Sadrian 121221603Sadrian HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122221581Sadrian 123237953Sadrian HAL_CAP_RIFS_RX = 39, 124237953Sadrian HAL_CAP_RIFS_TX = 40, 125237953Sadrian HAL_CAP_FORCE_PPM = 41, 126221603Sadrian HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 127221603Sadrian HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 128222584Sadrian HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 129222584Sadrian HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 130222584Sadrian HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 131221603Sadrian 132221603Sadrian HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 133221603Sadrian automatically after waking up to receive TIM */ 134221603Sadrian HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 135221603Sadrian HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 136221603Sadrian HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 137237953Sadrian HAL_CAP_BB_RIFS_HANG = 52, 138237953Sadrian HAL_CAP_RIFS_RX_ENABLED = 53, 139237953Sadrian HAL_CAP_BB_DFS_HANG = 54, 140221603Sadrian 141221603Sadrian HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 142237953Sadrian HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 143221603Sadrian 144237953Sadrian HAL_CAP_DS = 67, /* 2 stream */ 145237953Sadrian HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 146237953Sadrian HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 147237955Sadrian HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 148237953Sadrian 149237953Sadrian HAL_CAP_TS = 72, /* 3 stream */ 150237953Sadrian 151237953Sadrian HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 152238280Sadrian HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 153238280Sadrian HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 154238280Sadrian HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 155238280Sadrian HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 156238280Sadrian HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 157238280Sadrian HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 158238280Sadrian HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 159237953Sadrian 160237953Sadrian HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 161237953Sadrian 162237953Sadrian HAL_CAP_BB_PANIC_WATCHDOG = 92, 163237953Sadrian 164221603Sadrian HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 165221603Sadrian 166221603Sadrian HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 167222584Sadrian HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 168221603Sadrian 169221581Sadrian /* The following are private to the FreeBSD HAL (224 onward) */ 170221581Sadrian 171221603Sadrian HAL_CAP_INTMIT = 229, /* interference mitigation */ 172221603Sadrian HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 173221603Sadrian HAL_CAP_BB_HANG = 235, /* can baseband hang */ 174221603Sadrian HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 175221603Sadrian HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 176221603Sadrian HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 177221603Sadrian HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 178225444Sadrian HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 179226488Sadrian HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 180227410Sadrian HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 181185377Ssam} HAL_CAPABILITY_TYPE; 182185377Ssam 183185377Ssam/* 184185377Ssam * "States" for setting the LED. These correspond to 185185377Ssam * the possible 802.11 operational states and there may 186185377Ssam * be a many-to-one mapping between these states and the 187185377Ssam * actual hardware state for the LED's (i.e. the hardware 188185377Ssam * may have fewer states). 189185377Ssam */ 190185377Ssamtypedef enum { 191185377Ssam HAL_LED_INIT = 0, 192185377Ssam HAL_LED_SCAN = 1, 193185377Ssam HAL_LED_AUTH = 2, 194185377Ssam HAL_LED_ASSOC = 3, 195185377Ssam HAL_LED_RUN = 4 196185377Ssam} HAL_LED_STATE; 197185377Ssam 198185377Ssam/* 199185377Ssam * Transmit queue types/numbers. These are used to tag 200185377Ssam * each transmit queue in the hardware and to identify a set 201185377Ssam * of transmit queues for operations such as start/stop dma. 202185377Ssam */ 203185377Ssamtypedef enum { 204185377Ssam HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 205185377Ssam HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 206185377Ssam HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 207185377Ssam HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 208185377Ssam HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 209219790Sadrian HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 210237874Sadrian HAL_TX_QUEUE_CFEND = 6, 211237874Sadrian HAL_TX_QUEUE_PAPRD = 7, 212185377Ssam} HAL_TX_QUEUE; 213185377Ssam 214185377Ssam#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 215185377Ssam 216237874Sadriantypedef enum { 217237874Sadrian HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 218238280Sadrian HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 219237874Sadrian} HAL_RX_QUEUE; 220237874Sadrian 221237874Sadrian#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 222237874Sadrian 223238857Sadrian#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 224238857Sadrian 225185377Ssam/* 226185377Ssam * Transmit queue subtype. These map directly to 227185377Ssam * WME Access Categories (except for UPSD). Refer 228185377Ssam * to Table 5 of the WME spec. 229185377Ssam */ 230185377Ssamtypedef enum { 231185377Ssam HAL_WME_AC_BK = 0, /* background access category */ 232185377Ssam HAL_WME_AC_BE = 1, /* best effort access category*/ 233185377Ssam HAL_WME_AC_VI = 2, /* video access category */ 234185377Ssam HAL_WME_AC_VO = 3, /* voice access category */ 235185377Ssam HAL_WME_UPSD = 4, /* uplink power save */ 236185377Ssam} HAL_TX_QUEUE_SUBTYPE; 237185377Ssam 238185377Ssam/* 239185377Ssam * Transmit queue flags that control various 240185377Ssam * operational parameters. 241185377Ssam */ 242185377Ssamtypedef enum { 243185377Ssam /* 244185377Ssam * Per queue interrupt enables. When set the associated 245185377Ssam * interrupt may be delivered for packets sent through 246185377Ssam * the queue. Without these enabled no interrupts will 247185377Ssam * be delivered for transmits through the queue. 248185377Ssam */ 249185377Ssam HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 250185377Ssam HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 251185377Ssam HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 252185377Ssam HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 253185377Ssam HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 254185377Ssam /* 255185377Ssam * Enable hardware compression for packets sent through 256185377Ssam * the queue. The compression buffer must be setup and 257185377Ssam * packets must have a key entry marked in the tx descriptor. 258185377Ssam */ 259185377Ssam HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 260185377Ssam /* 261185377Ssam * Disable queue when veol is hit or ready time expires. 262185377Ssam * By default the queue is disabled only on reaching the 263185377Ssam * physical end of queue (i.e. a null link ptr in the 264185377Ssam * descriptor chain). 265185377Ssam */ 266185377Ssam HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 267185377Ssam /* 268185377Ssam * Schedule frames on delivery of a DBA (DMA Beacon Alert) 269185377Ssam * event. Frames will be transmitted only when this timer 270185377Ssam * fires, e.g to transmit a beacon in ap or adhoc modes. 271185377Ssam */ 272185377Ssam HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 273185377Ssam /* 274185377Ssam * Each transmit queue has a counter that is incremented 275185377Ssam * each time the queue is enabled and decremented when 276185377Ssam * the list of frames to transmit is traversed (or when 277185377Ssam * the ready time for the queue expires). This counter 278185377Ssam * must be non-zero for frames to be scheduled for 279185377Ssam * transmission. The following controls disable bumping 280185377Ssam * this counter under certain conditions. Typically this 281185377Ssam * is used to gate frames based on the contents of another 282185377Ssam * queue (e.g. CAB traffic may only follow a beacon frame). 283185377Ssam * These are meaningful only when frames are scheduled 284185377Ssam * with a non-ASAP policy (e.g. DBA-gated). 285185377Ssam */ 286185377Ssam HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 287185377Ssam HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 288185377Ssam 289185377Ssam /* 290185377Ssam * Fragment burst backoff policy. Normally the no backoff 291185377Ssam * is done after a successful transmission, the next fragment 292185377Ssam * is sent at SIFS. If this flag is set backoff is done 293185377Ssam * after each fragment, regardless whether it was ack'd or 294185377Ssam * not, after the backoff count reaches zero a normal channel 295185377Ssam * access procedure is done before the next transmit (i.e. 296185377Ssam * wait AIFS instead of SIFS). 297185377Ssam */ 298185377Ssam HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 299185377Ssam /* 300185377Ssam * Disable post-tx backoff following each frame. 301185377Ssam */ 302185377Ssam HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 303185377Ssam /* 304185377Ssam * DCU arbiter lockout control. This controls how 305185377Ssam * lower priority tx queues are handled with respect to 306185377Ssam * to a specific queue when multiple queues have frames 307185377Ssam * to send. No lockout means lower priority queues arbitrate 308185377Ssam * concurrently with this queue. Intra-frame lockout 309185377Ssam * means lower priority queues are locked out until the 310185377Ssam * current frame transmits (e.g. including backoffs and bursting). 311185377Ssam * Global lockout means nothing lower can arbitrary so 312185377Ssam * long as there is traffic activity on this queue (frames, 313185377Ssam * backoff, etc). 314185377Ssam */ 315185377Ssam HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 316185377Ssam HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 317185377Ssam 318185377Ssam HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 319185377Ssam HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 320185377Ssam} HAL_TX_QUEUE_FLAGS; 321185377Ssam 322185377Ssamtypedef struct { 323185377Ssam uint32_t tqi_ver; /* hal TXQ version */ 324185377Ssam HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 325185377Ssam HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 326185377Ssam uint32_t tqi_priority; /* (not used) */ 327185377Ssam uint32_t tqi_aifs; /* aifs */ 328185377Ssam uint32_t tqi_cwmin; /* cwMin */ 329185377Ssam uint32_t tqi_cwmax; /* cwMax */ 330185377Ssam uint16_t tqi_shretry; /* rts retry limit */ 331185377Ssam uint16_t tqi_lgretry; /* long retry limit (not used)*/ 332185377Ssam uint32_t tqi_cbrPeriod; /* CBR period (us) */ 333185377Ssam uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 334185377Ssam uint32_t tqi_burstTime; /* max burst duration (us) */ 335185377Ssam uint32_t tqi_readyTime; /* frame schedule time (us) */ 336185377Ssam uint32_t tqi_compBuf; /* comp buffer phys addr */ 337185377Ssam} HAL_TXQ_INFO; 338185377Ssam 339185377Ssam#define HAL_TQI_NONVAL 0xffff 340185377Ssam 341185377Ssam/* token to use for aifs, cwmin, cwmax */ 342185377Ssam#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 343185377Ssam 344185377Ssam/* compression definitions */ 345185377Ssam#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 346185377Ssam#define HAL_COMP_BUF_ALIGN_SIZE 512 347185377Ssam 348185377Ssam/* 349185377Ssam * Transmit packet types. This belongs in ah_desc.h, but 350185377Ssam * is here so we can give a proper type to various parameters 351185377Ssam * (and not require everyone include the file). 352185377Ssam * 353185377Ssam * NB: These values are intentionally assigned for 354185377Ssam * direct use when setting up h/w descriptors. 355185377Ssam */ 356185377Ssamtypedef enum { 357185377Ssam HAL_PKT_TYPE_NORMAL = 0, 358185377Ssam HAL_PKT_TYPE_ATIM = 1, 359185377Ssam HAL_PKT_TYPE_PSPOLL = 2, 360185377Ssam HAL_PKT_TYPE_BEACON = 3, 361185377Ssam HAL_PKT_TYPE_PROBE_RESP = 4, 362185377Ssam HAL_PKT_TYPE_CHIRP = 5, 363185377Ssam HAL_PKT_TYPE_GRP_POLL = 6, 364185377Ssam HAL_PKT_TYPE_AMPDU = 7, 365185377Ssam} HAL_PKT_TYPE; 366185377Ssam 367185377Ssam/* Rx Filter Frame Types */ 368185377Ssamtypedef enum { 369220022Sadrian /* 370220022Sadrian * These bits correspond to AR_RX_FILTER for all chips. 371220022Sadrian * Not all bits are supported by all chips. 372220022Sadrian */ 373185377Ssam HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 374185377Ssam HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 375185377Ssam HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 376185377Ssam HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 377185377Ssam HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 378185377Ssam HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 379185377Ssam HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 380220025Sadrian HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 381185377Ssam HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 382220022Sadrian HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 383220025Sadrian HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 384220022Sadrian HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 385220022Sadrian HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 386220022Sadrian /* Allow all mcast/bcast frames */ 387220022Sadrian 388220022Sadrian /* 389220022Sadrian * Magic RX filter flags that aren't targetting hardware bits 390220022Sadrian * but instead the HAL sets individual bits - eg PHYERR will result 391220022Sadrian * in OFDM/CCK timing error frames being received. 392220022Sadrian */ 393220022Sadrian HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 394185377Ssam} HAL_RX_FILTER; 395185377Ssam 396185377Ssamtypedef enum { 397185377Ssam HAL_PM_AWAKE = 0, 398185377Ssam HAL_PM_FULL_SLEEP = 1, 399185377Ssam HAL_PM_NETWORK_SLEEP = 2, 400185377Ssam HAL_PM_UNDEFINED = 3 401185377Ssam} HAL_POWER_MODE; 402185377Ssam 403185377Ssam/* 404185377Ssam * NOTE WELL: 405185377Ssam * These are mapped to take advantage of the common locations for many of 406185377Ssam * the bits on all of the currently supported MAC chips. This is to make 407185377Ssam * the ISR as efficient as possible, while still abstracting HW differences. 408185377Ssam * When new hardware breaks this commonality this enumerated type, as well 409185377Ssam * as the HAL functions using it, must be modified. All values are directly 410185377Ssam * mapped unless commented otherwise. 411185377Ssam */ 412185377Ssamtypedef enum { 413185377Ssam HAL_INT_RX = 0x00000001, /* Non-common mapping */ 414238349Sadrian HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 415238349Sadrian HAL_INT_RXHP = 0x00000001, /* EDMA */ 416238349Sadrian HAL_INT_RXLP = 0x00000002, /* EDMA */ 417238349Sadrian HAL_INT_RXERR = 0x00000004, 418185377Ssam HAL_INT_RXNOFRM = 0x00000008, 419185377Ssam HAL_INT_RXEOL = 0x00000010, 420185377Ssam HAL_INT_RXORN = 0x00000020, 421185377Ssam HAL_INT_TX = 0x00000040, /* Non-common mapping */ 422185377Ssam HAL_INT_TXDESC = 0x00000080, 423208711Srpaulo HAL_INT_TIM_TIMER= 0x00000100, 424185377Ssam HAL_INT_TXURN = 0x00000800, 425185377Ssam HAL_INT_MIB = 0x00001000, 426185377Ssam HAL_INT_RXPHY = 0x00004000, 427185377Ssam HAL_INT_RXKCM = 0x00008000, 428185377Ssam HAL_INT_SWBA = 0x00010000, 429185377Ssam HAL_INT_BMISS = 0x00040000, 430192401Ssam HAL_INT_BNR = 0x00100000, 431185377Ssam HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 432185377Ssam HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 433185377Ssam HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 434185377Ssam HAL_INT_GPIO = 0x01000000, 435185377Ssam HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 436185377Ssam HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 437192400Ssam HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 438185377Ssam HAL_INT_CST = 0x10000000, /* Non-common mapping */ 439185377Ssam HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 440185377Ssam HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 441185377Ssam#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 442185377Ssam HAL_INT_BMISC = HAL_INT_TIM 443185377Ssam | HAL_INT_DTIM 444185377Ssam | HAL_INT_DTIMSYNC 445192400Ssam | HAL_INT_CABEND 446192400Ssam | HAL_INT_TBTT, 447185377Ssam 448185377Ssam /* Interrupt bits that map directly to ISR/IMR bits */ 449185377Ssam HAL_INT_COMMON = HAL_INT_RXNOFRM 450185377Ssam | HAL_INT_RXDESC 451185377Ssam | HAL_INT_RXEOL 452185377Ssam | HAL_INT_RXORN 453192396Ssam | HAL_INT_TXDESC 454185377Ssam | HAL_INT_TXURN 455185377Ssam | HAL_INT_MIB 456185377Ssam | HAL_INT_RXPHY 457185377Ssam | HAL_INT_RXKCM 458185377Ssam | HAL_INT_SWBA 459185377Ssam | HAL_INT_BMISS 460192397Ssam | HAL_INT_BNR 461185377Ssam | HAL_INT_GPIO, 462185377Ssam} HAL_INT; 463185377Ssam 464237622Sadrian/* 465237622Sadrian * MSI vector assignments 466237622Sadrian */ 467185377Ssamtypedef enum { 468237622Sadrian HAL_MSIVEC_MISC = 0, 469237622Sadrian HAL_MSIVEC_TX = 1, 470237622Sadrian HAL_MSIVEC_RXLP = 2, 471237622Sadrian HAL_MSIVEC_RXHP = 3, 472237622Sadrian} HAL_MSIVEC; 473237622Sadrian 474237622Sadriantypedef enum { 475237622Sadrian HAL_INT_LINE = 0, 476237622Sadrian HAL_INT_MSI = 1, 477237622Sadrian} HAL_INT_TYPE; 478237622Sadrian 479237622Sadrian/* For interrupt mitigation registers */ 480237622Sadriantypedef enum { 481237622Sadrian HAL_INT_RX_FIRSTPKT=0, 482237622Sadrian HAL_INT_RX_LASTPKT, 483237622Sadrian HAL_INT_TX_FIRSTPKT, 484237622Sadrian HAL_INT_TX_LASTPKT, 485237622Sadrian HAL_INT_THRESHOLD 486237622Sadrian} HAL_INT_MITIGATION; 487237622Sadrian 488237622Sadriantypedef enum { 489237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 490237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 491237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 492237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 493237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 494237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 495237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 496188974Ssam} HAL_GPIO_MUX_TYPE; 497188974Ssam 498188974Ssamtypedef enum { 499188974Ssam HAL_GPIO_INTR_LOW = 0, 500188974Ssam HAL_GPIO_INTR_HIGH = 1, 501188974Ssam HAL_GPIO_INTR_DISABLE = 2 502188974Ssam} HAL_GPIO_INTR_TYPE; 503188974Ssam 504188974Ssamtypedef enum { 505185377Ssam HAL_RFGAIN_INACTIVE = 0, 506185377Ssam HAL_RFGAIN_READ_REQUESTED = 1, 507185377Ssam HAL_RFGAIN_NEED_CHANGE = 2 508185377Ssam} HAL_RFGAIN; 509185377Ssam 510187831Ssamtypedef uint16_t HAL_CTRY_CODE; /* country code */ 511187831Ssamtypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 512185377Ssam 513185377Ssam#define HAL_ANTENNA_MIN_MODE 0 514185377Ssam#define HAL_ANTENNA_FIXED_A 1 515185377Ssam#define HAL_ANTENNA_FIXED_B 2 516185377Ssam#define HAL_ANTENNA_MAX_MODE 3 517185377Ssam 518185377Ssamtypedef struct { 519185377Ssam uint32_t ackrcv_bad; 520185377Ssam uint32_t rts_bad; 521185377Ssam uint32_t rts_good; 522185377Ssam uint32_t fcs_bad; 523185377Ssam uint32_t beacons; 524185377Ssam} HAL_MIB_STATS; 525185377Ssam 526185377Ssamenum { 527185377Ssam HAL_MODE_11A = 0x001, /* 11a channels */ 528185377Ssam HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 529185377Ssam HAL_MODE_11B = 0x004, /* 11b channels */ 530185377Ssam HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 531185377Ssam#ifdef notdef 532185377Ssam HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 533185377Ssam#else 534185377Ssam HAL_MODE_11G = 0x008, /* XXX historical */ 535185377Ssam#endif 536185377Ssam HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 537185377Ssam HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 538185380Ssam HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 539185380Ssam HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 540185380Ssam HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 541185380Ssam HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 542185377Ssam HAL_MODE_11NG_HT20 = 0x008000, 543185377Ssam HAL_MODE_11NA_HT20 = 0x010000, 544185377Ssam HAL_MODE_11NG_HT40PLUS = 0x020000, 545185377Ssam HAL_MODE_11NG_HT40MINUS = 0x040000, 546185377Ssam HAL_MODE_11NA_HT40PLUS = 0x080000, 547185377Ssam HAL_MODE_11NA_HT40MINUS = 0x100000, 548185377Ssam HAL_MODE_ALL = 0xffffff 549185377Ssam}; 550185377Ssam 551185377Ssamtypedef struct { 552185377Ssam int rateCount; /* NB: for proper padding */ 553239289Sadrian uint8_t rateCodeToIndex[256]; /* back mapping */ 554185377Ssam struct { 555188770Ssam uint8_t valid; /* valid for rate control use */ 556188770Ssam uint8_t phy; /* CCK/OFDM/XR */ 557185377Ssam uint32_t rateKbps; /* transfer rate in kbs */ 558185377Ssam uint8_t rateCode; /* rate for h/w descriptors */ 559185377Ssam uint8_t shortPreamble; /* mask for enabling short 560185377Ssam * preamble in CCK rate code */ 561185377Ssam uint8_t dot11Rate; /* value for supported rates 562185377Ssam * info element of MLME */ 563185377Ssam uint8_t controlRate; /* index of next lower basic 564185377Ssam * rate; used for dur. calcs */ 565185377Ssam uint16_t lpAckDuration; /* long preamble ACK duration */ 566185377Ssam uint16_t spAckDuration; /* short preamble ACK duration*/ 567239289Sadrian } info[64]; 568185377Ssam} HAL_RATE_TABLE; 569185377Ssam 570185377Ssamtypedef struct { 571185377Ssam u_int rs_count; /* number of valid entries */ 572239289Sadrian uint8_t rs_rates[64]; /* rates */ 573185377Ssam} HAL_RATE_SET; 574185377Ssam 575185377Ssam/* 576185377Ssam * 802.11n specific structures and enums 577185377Ssam */ 578185377Ssamtypedef enum { 579185377Ssam HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 580185377Ssam HAL_CHAINTYPE_RX = 2, /* RX chain type */ 581185377Ssam} HAL_CHAIN_TYPE; 582185377Ssam 583185377Ssamtypedef struct { 584185377Ssam u_int Tries; 585238840Sadrian u_int Rate; /* hardware rate code */ 586238840Sadrian u_int RateIndex; /* rate series table index */ 587185377Ssam u_int PktDuration; 588185377Ssam u_int ChSel; 589185377Ssam u_int RateFlags; 590185377Ssam#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 591185377Ssam#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 592185377Ssam#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 593238841Sadrian#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 594238839Sadrian u_int tx_power_cap; 595185377Ssam} HAL_11N_RATE_SERIES; 596185377Ssam 597185377Ssamtypedef enum { 598185377Ssam HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 599185377Ssam HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 600185377Ssam} HAL_HT_MACMODE; 601185377Ssam 602185377Ssamtypedef enum { 603185377Ssam HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 604185377Ssam HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 605185377Ssam} HAL_HT_PHYMODE; 606185377Ssam 607185377Ssamtypedef enum { 608185377Ssam HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 609185377Ssam HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 610185377Ssam} HAL_HT_EXTPROTSPACING; 611185377Ssam 612185377Ssam 613185377Ssamtypedef enum { 614185377Ssam HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 615185377Ssam HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 616185377Ssam} HAL_HT_RXCLEAR; 617185377Ssam 618185377Ssam/* 619185377Ssam * Antenna switch control. By default antenna selection 620185377Ssam * enables multiple (2) antenna use. To force use of the 621185377Ssam * A or B antenna only specify a fixed setting. Fixing 622185377Ssam * the antenna will also disable any diversity support. 623185377Ssam */ 624185377Ssamtypedef enum { 625185377Ssam HAL_ANT_VARIABLE = 0, /* variable by programming */ 626185377Ssam HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 627185377Ssam HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 628185377Ssam} HAL_ANT_SETTING; 629185377Ssam 630185377Ssamtypedef enum { 631185377Ssam HAL_M_STA = 1, /* infrastructure station */ 632185377Ssam HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 633185377Ssam HAL_M_HOSTAP = 6, /* Software Access Point */ 634185377Ssam HAL_M_MONITOR = 8 /* Monitor mode */ 635185377Ssam} HAL_OPMODE; 636185377Ssam 637185377Ssamtypedef struct { 638185377Ssam uint8_t kv_type; /* one of HAL_CIPHER */ 639237874Sadrian uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 640185377Ssam uint16_t kv_len; /* length in bits */ 641185377Ssam uint8_t kv_val[16]; /* enough for 128-bit keys */ 642185377Ssam uint8_t kv_mic[8]; /* TKIP MIC key */ 643185377Ssam uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 644185377Ssam} HAL_KEYVAL; 645185377Ssam 646185377Ssamtypedef enum { 647185377Ssam HAL_CIPHER_WEP = 0, 648185377Ssam HAL_CIPHER_AES_OCB = 1, 649185377Ssam HAL_CIPHER_AES_CCM = 2, 650185377Ssam HAL_CIPHER_CKIP = 3, 651185377Ssam HAL_CIPHER_TKIP = 4, 652185377Ssam HAL_CIPHER_CLR = 5, /* no encryption */ 653185377Ssam 654185377Ssam HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 655185377Ssam} HAL_CIPHER; 656185377Ssam 657185377Ssamenum { 658185377Ssam HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 659185377Ssam HAL_SLOT_TIME_9 = 9, 660185377Ssam HAL_SLOT_TIME_20 = 20, 661185377Ssam}; 662185377Ssam 663185377Ssam/* 664185377Ssam * Per-station beacon timer state. Note that the specified 665185377Ssam * beacon interval (given in TU's) can also include flags 666185377Ssam * to force a TSF reset and to enable the beacon xmit logic. 667185377Ssam * If bs_cfpmaxduration is non-zero the hardware is setup to 668185377Ssam * coexist with a PCF-capable AP. 669185377Ssam */ 670185377Ssamtypedef struct { 671185377Ssam uint32_t bs_nexttbtt; /* next beacon in TU */ 672185377Ssam uint32_t bs_nextdtim; /* next DTIM in TU */ 673185377Ssam uint32_t bs_intval; /* beacon interval+flags */ 674185377Ssam#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 675185377Ssam#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 676185377Ssam#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 677185377Ssam uint32_t bs_dtimperiod; 678185377Ssam uint16_t bs_cfpperiod; /* CFP period in TU */ 679185377Ssam uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 680185377Ssam uint32_t bs_cfpnext; /* next CFP in TU */ 681185377Ssam uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 682185377Ssam uint16_t bs_bmissthreshold; /* beacon miss threshold */ 683185377Ssam uint32_t bs_sleepduration; /* max sleep duration */ 684185377Ssam} HAL_BEACON_STATE; 685185377Ssam 686185377Ssam/* 687185377Ssam * Like HAL_BEACON_STATE but for non-station mode setup. 688185377Ssam * NB: see above flag definitions for bt_intval. 689185377Ssam */ 690185377Ssamtypedef struct { 691185377Ssam uint32_t bt_intval; /* beacon interval+flags */ 692185377Ssam uint32_t bt_nexttbtt; /* next beacon in TU */ 693185377Ssam uint32_t bt_nextatim; /* next ATIM in TU */ 694185377Ssam uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 695185377Ssam uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 696185377Ssam uint32_t bt_flags; /* timer enables */ 697185377Ssam#define HAL_BEACON_TBTT_EN 0x00000001 698185377Ssam#define HAL_BEACON_DBA_EN 0x00000002 699185377Ssam#define HAL_BEACON_SWBA_EN 0x00000004 700185377Ssam} HAL_BEACON_TIMERS; 701185377Ssam 702185377Ssam/* 703185377Ssam * Per-node statistics maintained by the driver for use in 704185377Ssam * optimizing signal quality and other operational aspects. 705185377Ssam */ 706185377Ssamtypedef struct { 707185377Ssam uint32_t ns_avgbrssi; /* average beacon rssi */ 708185377Ssam uint32_t ns_avgrssi; /* average data rssi */ 709185377Ssam uint32_t ns_avgtxrssi; /* average tx rssi */ 710185377Ssam} HAL_NODE_STATS; 711185377Ssam 712185377Ssam#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 713185377Ssam 714185377Ssamstruct ath_desc; 715185377Ssamstruct ath_tx_status; 716185377Ssamstruct ath_rx_status; 717187831Ssamstruct ieee80211_channel; 718185377Ssam 719185377Ssam/* 720219773Sadrian * This is a channel survey sample entry. 721219773Sadrian * 722219773Sadrian * The AR5212 ANI routines fill these samples. The ANI code then uses it 723219773Sadrian * when calculating listen time; it is also exported via a diagnostic 724219773Sadrian * API. 725219773Sadrian */ 726219773Sadriantypedef struct { 727219773Sadrian uint32_t seq_num; 728219773Sadrian uint32_t tx_busy; 729219773Sadrian uint32_t rx_busy; 730219773Sadrian uint32_t chan_busy; 731234749Sadrian uint32_t ext_chan_busy; 732219773Sadrian uint32_t cycle_count; 733234749Sadrian /* XXX TODO */ 734234749Sadrian uint32_t ofdm_phyerr_count; 735234749Sadrian uint32_t cck_phyerr_count; 736219773Sadrian} HAL_SURVEY_SAMPLE; 737219773Sadrian 738219773Sadrian/* 739219773Sadrian * This provides 3.2 seconds of sample space given an 740219773Sadrian * ANI time of 1/10th of a second. This may not be enough! 741219773Sadrian */ 742219773Sadrian#define CHANNEL_SURVEY_SAMPLE_COUNT 32 743219773Sadrian 744219773Sadriantypedef struct { 745219773Sadrian HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 746219773Sadrian uint32_t cur_sample; /* current sample in sequence */ 747219773Sadrian uint32_t cur_seq; /* current sequence number */ 748219773Sadrian} HAL_CHANNEL_SURVEY; 749219773Sadrian 750219773Sadrian/* 751222277Sadrian * ANI commands. 752222277Sadrian * 753222277Sadrian * These are used both internally and externally via the diagnostic 754222277Sadrian * API. 755222277Sadrian * 756222277Sadrian * Note that this is NOT the ANI commands being used via the INTMIT 757222277Sadrian * capability - that has a different mapping for some reason. 758222277Sadrian */ 759222277Sadriantypedef enum { 760222277Sadrian HAL_ANI_PRESENT = 0, /* is ANI support present */ 761222277Sadrian HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 762222277Sadrian HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 763222277Sadrian HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 764222277Sadrian HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 765222277Sadrian HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 766222277Sadrian HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 767222277Sadrian HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 768237874Sadrian HAL_ANI_MRC_CCK = 8, 769222277Sadrian} HAL_ANI_CMD; 770222277Sadrian 771222277Sadrian/* 772222277Sadrian * This is the layout of the ANI INTMIT capability. 773222277Sadrian * 774222277Sadrian * Notice that the command values differ to HAL_ANI_CMD. 775222277Sadrian */ 776222277Sadriantypedef enum { 777222277Sadrian HAL_CAP_INTMIT_PRESENT = 0, 778222277Sadrian HAL_CAP_INTMIT_ENABLE = 1, 779222277Sadrian HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 780222277Sadrian HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 781222277Sadrian HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 782222277Sadrian HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 783222277Sadrian HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 784222277Sadrian} HAL_CAP_INTMIT_CMD; 785222277Sadrian 786237874Sadrian/* DFS defines */ 787222584Sadriantypedef struct { 788222584Sadrian int32_t pe_firpwr; /* FIR pwr out threshold */ 789222584Sadrian int32_t pe_rrssi; /* Radar rssi thresh */ 790222584Sadrian int32_t pe_height; /* Pulse height thresh */ 791222584Sadrian int32_t pe_prssi; /* Pulse rssi thresh */ 792222584Sadrian int32_t pe_inband; /* Inband thresh */ 793222584Sadrian 794222584Sadrian /* The following params are only for AR5413 and later */ 795222584Sadrian u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 796222584Sadrian u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 797222584Sadrian u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 798224244Sadrian int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 799224244Sadrian int32_t pe_blockradar; /* 800222584Sadrian * Enable to block radar check if pkt detect is done via OFDM 801222584Sadrian * weak signal detect or pkt is detected immediately after tx 802222584Sadrian * to rx transition 803222584Sadrian */ 804224244Sadrian int32_t pe_enmaxrssi; /* 805222584Sadrian * Enable to use the max rssi instead of the last rssi during 806222584Sadrian * fine gain changes for radar detection 807222584Sadrian */ 808224244Sadrian int32_t pe_extchannel; /* Enable DFS on ext channel */ 809224244Sadrian int32_t pe_enabled; /* Whether radar detection is enabled */ 810231708Sadrian int32_t pe_enrelpwr; 811231708Sadrian int32_t pe_en_relstep_check; 812222584Sadrian} HAL_PHYERR_PARAM; 813222584Sadrian 814222584Sadrian#define HAL_PHYERR_PARAM_NOVAL 65535 815222584Sadrian 816224716Sadrian/* 817224716Sadrian * DFS operating mode flags. 818224716Sadrian */ 819224716Sadriantypedef enum { 820224716Sadrian HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 821224716Sadrian HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 822224716Sadrian HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 823224716Sadrian HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 824224716Sadrian} HAL_DFS_DOMAIN; 825222584Sadrian 826222277Sadrian/* 827222644Sadrian * Flag for setting QUIET period 828222644Sadrian */ 829222644Sadriantypedef enum { 830222644Sadrian HAL_QUIET_DISABLE = 0x0, 831222644Sadrian HAL_QUIET_ENABLE = 0x1, 832222644Sadrian HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 833222644Sadrian HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 834222644Sadrian} HAL_QUIET_FLAG; 835222644Sadrian 836222815Sadrian#define HAL_DFS_EVENT_PRICH 0x0000001 837224539Sadrian#define HAL_DFS_EVENT_EXTCH 0x0000002 838224539Sadrian#define HAL_DFS_EVENT_EXTEARLY 0x0000004 839224539Sadrian#define HAL_DFS_EVENT_ISDC 0x0000008 840222815Sadrian 841224633Sadrianstruct hal_dfs_event { 842222815Sadrian uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 843222815Sadrian uint32_t re_ts; /* Original 15 bit recv timestamp */ 844222815Sadrian uint8_t re_rssi; /* rssi of radar event */ 845222815Sadrian uint8_t re_dur; /* duration of radar pulse */ 846222815Sadrian uint32_t re_flags; /* Flags (see above) */ 847222815Sadrian}; 848224633Sadriantypedef struct hal_dfs_event HAL_DFS_EVENT; 849222815Sadrian 850237611Sadrian/* 851237611Sadrian * BT Co-existence definitions 852237611Sadrian */ 853237611Sadriantypedef enum { 854237611Sadrian HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 855237611Sadrian HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 856237611Sadrian HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 857237611Sadrian HAL_MAX_BT_MODULES 858237611Sadrian} HAL_BT_MODULE; 859237611Sadrian 860237611Sadriantypedef struct { 861237611Sadrian HAL_BT_MODULE bt_module; 862237611Sadrian u_int8_t bt_coex_config; 863237611Sadrian u_int8_t bt_gpio_bt_active; 864237611Sadrian u_int8_t bt_gpio_bt_priority; 865237611Sadrian u_int8_t bt_gpio_wlan_active; 866237611Sadrian u_int8_t bt_active_polarity; 867237611Sadrian HAL_BOOL bt_single_ant; 868237611Sadrian u_int8_t bt_dutyCycle; 869237611Sadrian u_int8_t bt_isolation; 870237611Sadrian u_int8_t bt_period; 871237611Sadrian} HAL_BT_COEX_INFO; 872237611Sadrian 873237611Sadriantypedef enum { 874237611Sadrian HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 875237611Sadrian HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 876237611Sadrian HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 877237611Sadrian HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 878237611Sadrian} HAL_BT_COEX_MODE; 879237611Sadrian 880237611Sadriantypedef enum { 881237611Sadrian HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 882237611Sadrian HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 883237611Sadrian HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 884237611Sadrian HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 885237611Sadrian HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 886237611Sadrian HAL_BT_COEX_CFG_MCI /* MCI */ 887237611Sadrian} HAL_BT_COEX_CFG; 888237611Sadrian 889237611Sadriantypedef enum { 890237611Sadrian HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 891237611Sadrian HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 892237611Sadrian HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 893237611Sadrian} HAL_BT_COEX_SET_PARAMETER; 894237611Sadrian 895237611Sadrian#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 896237611Sadrian#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 897237611Sadrian/* Check Rx Diversity is allowed */ 898237611Sadrian#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 899237611Sadrian/* Check Diversity is on or off */ 900237611Sadrian#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 901237611Sadrian 902237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 903237611Sadrian/* main: LNA1, alt: LNA2 */ 904237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 905237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 906237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 907237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 908237611Sadrian#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 909237611Sadrian 910237611Sadrian#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 911237611Sadrian 912237611Sadrian#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 913237611Sadrian 914237611Sadrian#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 915237611Sadrian 916237611Sadrian#define HAL_BT_COEX_LOW_ACK_POWER 0x0 917237611Sadrian#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 918237611Sadrian 919237611Sadriantypedef enum { 920237611Sadrian HAL_BT_COEX_NO_STOMP = 0, 921237611Sadrian HAL_BT_COEX_STOMP_ALL, 922237611Sadrian HAL_BT_COEX_STOMP_LOW, 923237611Sadrian HAL_BT_COEX_STOMP_NONE, 924237611Sadrian HAL_BT_COEX_STOMP_ALL_FORCE, 925237611Sadrian HAL_BT_COEX_STOMP_LOW_FORCE, 926237611Sadrian} HAL_BT_COEX_STOMP_TYPE; 927237611Sadrian 928237611Sadriantypedef struct { 929237611Sadrian /* extend rx_clear after tx/rx to protect the burst (in usec). */ 930237611Sadrian u_int8_t bt_time_extend; 931237611Sadrian 932237611Sadrian /* 933237611Sadrian * extend rx_clear as long as txsm is 934237611Sadrian * transmitting or waiting for ack. 935237611Sadrian */ 936237611Sadrian HAL_BOOL bt_txstate_extend; 937237611Sadrian 938237611Sadrian /* 939237611Sadrian * extend rx_clear so that when tx_frame 940237611Sadrian * is asserted, rx_clear will drop. 941237611Sadrian */ 942237611Sadrian HAL_BOOL bt_txframe_extend; 943237611Sadrian 944237611Sadrian /* 945237611Sadrian * coexistence mode 946237611Sadrian */ 947237611Sadrian HAL_BT_COEX_MODE bt_mode; 948237611Sadrian 949237611Sadrian /* 950237611Sadrian * treat BT high priority traffic as 951237611Sadrian * a quiet collision 952237611Sadrian */ 953237611Sadrian HAL_BOOL bt_quiet_collision; 954237611Sadrian 955237611Sadrian /* 956237611Sadrian * invert rx_clear as WLAN_ACTIVE 957237611Sadrian */ 958237611Sadrian HAL_BOOL bt_rxclear_polarity; 959237611Sadrian 960237611Sadrian /* 961237611Sadrian * slotted mode only. indicate the time in usec 962237611Sadrian * from the rising edge of BT_ACTIVE to the time 963237611Sadrian * BT_PRIORITY can be sampled to indicate priority. 964237611Sadrian */ 965237611Sadrian u_int8_t bt_priority_time; 966237611Sadrian 967237611Sadrian /* 968237611Sadrian * slotted mode only. indicate the time in usec 969237611Sadrian * from the rising edge of BT_ACTIVE to the time 970237611Sadrian * BT_PRIORITY can be sampled to indicate tx/rx and 971237611Sadrian * BT_FREQ is sampled. 972237611Sadrian */ 973237611Sadrian u_int8_t bt_first_slot_time; 974237611Sadrian 975237611Sadrian /* 976237611Sadrian * slotted mode only. rx_clear and bt_ant decision 977237611Sadrian * will be held the entire time that BT_ACTIVE is asserted, 978237611Sadrian * otherwise the decision is made before every slot boundry. 979237611Sadrian */ 980237611Sadrian HAL_BOOL bt_hold_rxclear; 981237611Sadrian} HAL_BT_COEX_CONFIG; 982237611Sadrian 983223459Sadriantypedef struct 984223459Sadrian{ 985223459Sadrian int ah_debug; /* only used if AH_DEBUG is defined */ 986223459Sadrian int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 987223459Sadrian 988223459Sadrian /* NB: these are deprecated; they exist for now for compatibility */ 989223459Sadrian int ah_dma_beacon_response_time;/* in TU's */ 990223459Sadrian int ah_sw_beacon_response_time; /* in TU's */ 991223459Sadrian int ah_additional_swba_backoff; /* in TU's */ 992227375Sadrian int ah_force_full_reset; /* force full chip reset rather then warm reset */ 993227410Sadrian int ah_serialise_reg_war; /* force serialisation of register IO */ 994224633Sadrian} HAL_OPS_CONFIG; 995223459Sadrian 996222644Sadrian/* 997185377Ssam * Hardware Access Layer (HAL) API. 998185377Ssam * 999185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an 1000185377Ssam * ath_hal structure for use with the device. Hardware-related operations 1001185377Ssam * that follow must call back into the HAL through interface, supplying 1002185377Ssam * the reference as the first parameter. Note that before using the 1003185377Ssam * reference returned by ath_hal_attach the caller should verify the 1004185377Ssam * ABI version number. 1005185377Ssam */ 1006185377Ssamstruct ath_hal { 1007185377Ssam uint32_t ah_magic; /* consistency check magic number */ 1008185377Ssam uint16_t ah_devid; /* PCI device ID */ 1009185377Ssam uint16_t ah_subvendorid; /* PCI subvendor ID */ 1010185377Ssam HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1011185377Ssam HAL_BUS_TAG ah_st; /* params for register r+w */ 1012185377Ssam HAL_BUS_HANDLE ah_sh; 1013185377Ssam HAL_CTRY_CODE ah_countryCode; 1014185377Ssam 1015185377Ssam uint32_t ah_macVersion; /* MAC version id */ 1016185377Ssam uint16_t ah_macRev; /* MAC revision */ 1017185377Ssam uint16_t ah_phyRev; /* PHY revision */ 1018185377Ssam /* NB: when only one radio is present the rev is in 5Ghz */ 1019185377Ssam uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1020185377Ssam uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1021185377Ssam 1022217624Sadrian uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1023217624Sadrian 1024227365Sadrian uint32_t ah_intrstate[8]; /* last int state */ 1025234088Sadrian uint32_t ah_syncstate; /* last sync intr state */ 1026227365Sadrian 1027223459Sadrian HAL_OPS_CONFIG ah_config; 1028185377Ssam const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1029185377Ssam u_int mode); 1030185377Ssam void __ahdecl(*ah_detach)(struct ath_hal*); 1031185377Ssam 1032185377Ssam /* Reset functions */ 1033185377Ssam HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1034187831Ssam struct ieee80211_channel *, 1035187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status); 1036185377Ssam HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1037185377Ssam HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1038235972Sadrian void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1039235972Sadrian HAL_BOOL power_off); 1040188979Ssam void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1041185377Ssam void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1042187831Ssam HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1043187831Ssam struct ieee80211_channel *, HAL_BOOL *); 1044187831Ssam HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1045187831Ssam struct ieee80211_channel *, u_int chainMask, 1046187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 1047187831Ssam HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1048187831Ssam const struct ieee80211_channel *); 1049203930Srpaulo HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1050203930Srpaulo const struct ieee80211_channel *, uint16_t *); 1051185377Ssam HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1052203930Srpaulo HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1053203930Srpaulo const struct ieee80211_channel *); 1054185377Ssam 1055185377Ssam /* Transmit functions */ 1056185377Ssam HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1057185377Ssam HAL_BOOL incTrigLevel); 1058185377Ssam int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1059185377Ssam const HAL_TXQ_INFO *qInfo); 1060185377Ssam HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1061185377Ssam const HAL_TXQ_INFO *qInfo); 1062185377Ssam HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1063185377Ssam HAL_TXQ_INFO *qInfo); 1064185377Ssam HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1065185377Ssam HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1066185377Ssam uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1067185377Ssam HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1068185377Ssam uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1069185377Ssam HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1070185377Ssam HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1071185377Ssam HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1072185377Ssam u_int pktLen, u_int hdrLen, 1073185377Ssam HAL_PKT_TYPE type, u_int txPower, 1074185377Ssam u_int txRate0, u_int txTries0, 1075185377Ssam u_int keyIx, u_int antMode, u_int flags, 1076185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 1077185377Ssam u_int compicvLen, u_int compivLen, 1078185377Ssam u_int comp); 1079185377Ssam HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1080185377Ssam u_int txRate1, u_int txTries1, 1081185377Ssam u_int txRate2, u_int txTries2, 1082185377Ssam u_int txRate3, u_int txTries3); 1083185377Ssam HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1084239051Sadrian HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1085239051Sadrian u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1086185377Ssam HAL_BOOL lastSeg, const struct ath_desc *); 1087185377Ssam HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1088185377Ssam struct ath_desc *, struct ath_tx_status *); 1089185377Ssam void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1090185377Ssam void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1091217621Sadrian HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1092217621Sadrian const struct ath_desc *ds, int *rates, int *tries); 1093238607Sadrian void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1094238607Sadrian uint32_t link); 1095238607Sadrian void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1096238607Sadrian uint32_t *link); 1097238607Sadrian void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1098238607Sadrian uint32_t **linkptr); 1099238731Sadrian void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1100238731Sadrian void *ts_start, uint32_t ts_paddr_start, 1101238731Sadrian uint16_t size); 1102185377Ssam 1103185377Ssam /* Receive Functions */ 1104238278Sadrian uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1105238278Sadrian void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1106185377Ssam void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1107185377Ssam HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1108185377Ssam void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1109185377Ssam void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1110185377Ssam void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1111185377Ssam uint32_t filter0, uint32_t filter1); 1112185377Ssam HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1113185377Ssam uint32_t index); 1114185377Ssam HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1115185377Ssam uint32_t index); 1116185377Ssam uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1117185377Ssam void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1118185377Ssam HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1119185377Ssam uint32_t size, u_int flags); 1120185377Ssam HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1121185377Ssam struct ath_desc *, uint32_t phyAddr, 1122185377Ssam struct ath_desc *next, uint64_t tsf, 1123185377Ssam struct ath_rx_status *); 1124185377Ssam void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1125187831Ssam const HAL_NODE_STATS *, 1126187831Ssam const struct ieee80211_channel *); 1127217684Sadrian void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1128217684Sadrian const struct ieee80211_channel *); 1129185377Ssam void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1130185377Ssam const HAL_NODE_STATS *); 1131220600Sadrian void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1132220600Sadrian struct ath_rx_status *, 1133220600Sadrian unsigned long, int); 1134185377Ssam 1135185377Ssam /* Misc Functions */ 1136185377Ssam HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1137185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1138185377Ssam uint32_t *result); 1139185377Ssam HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1140185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1141185377Ssam uint32_t setting, HAL_STATUS *); 1142185377Ssam HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1143185377Ssam const void *args, uint32_t argsize, 1144185377Ssam void **result, uint32_t *resultsize); 1145185377Ssam void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1146185377Ssam HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1147185377Ssam void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1148185377Ssam HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1149185377Ssam HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1150185377Ssam uint16_t, HAL_STATUS *); 1151185377Ssam void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1152185377Ssam void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1153185377Ssam const uint8_t *bssid, uint16_t assocId); 1154188974Ssam HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1155188974Ssam uint32_t gpio, HAL_GPIO_MUX_TYPE); 1156185377Ssam HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1157185377Ssam uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1158185377Ssam HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1159185377Ssam uint32_t gpio, uint32_t val); 1160185377Ssam void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1161185377Ssam uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1162185377Ssam uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1163185377Ssam void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1164185377Ssam HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1165185377Ssam void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1166185377Ssam HAL_MIB_STATS*); 1167185377Ssam HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1168185377Ssam u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1169185377Ssam void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1170185377Ssam HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1171185377Ssam HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1172185377Ssam HAL_ANT_SETTING); 1173185377Ssam HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1174185377Ssam u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1175185377Ssam HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1176185377Ssam u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1177185377Ssam HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1178185377Ssam u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1179185377Ssam HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1180185377Ssam u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1181185377Ssam HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1182185377Ssam u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1183185377Ssam HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1184185377Ssam void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1185222644Sadrian HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1186222644Sadrian uint32_t duration, uint32_t nextStart, 1187222644Sadrian HAL_QUIET_FLAG flag); 1188185377Ssam 1189222584Sadrian /* DFS functions */ 1190222584Sadrian void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1191222584Sadrian HAL_PHYERR_PARAM *pe); 1192222584Sadrian void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1193222584Sadrian HAL_PHYERR_PARAM *pe); 1194222815Sadrian HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1195222815Sadrian struct ath_rx_status *rxs, uint64_t fulltsf, 1196222815Sadrian const char *buf, HAL_DFS_EVENT *event); 1197224709Sadrian HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1198222584Sadrian 1199185377Ssam /* Key Cache Functions */ 1200185377Ssam uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1201185377Ssam HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1202185377Ssam HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1203185377Ssam uint16_t); 1204185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1205185377Ssam uint16_t, const HAL_KEYVAL *, 1206185377Ssam const uint8_t *, int); 1207185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1208185377Ssam uint16_t, const uint8_t *); 1209185377Ssam 1210185377Ssam /* Power Management Functions */ 1211185377Ssam HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1212185377Ssam HAL_POWER_MODE mode, int setChip); 1213185377Ssam HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1214187831Ssam int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1215187831Ssam const struct ieee80211_channel *); 1216185377Ssam 1217185377Ssam /* Beacon Management Functions */ 1218185377Ssam void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1219185377Ssam const HAL_BEACON_TIMERS *); 1220185377Ssam /* NB: deprecated, use ah_setBeaconTimers instead */ 1221185377Ssam void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1222185377Ssam uint32_t nexttbtt, uint32_t intval); 1223185377Ssam void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1224185377Ssam const HAL_BEACON_STATE *); 1225185377Ssam void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1226225444Sadrian uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1227185377Ssam 1228218066Sadrian /* 802.11n Functions */ 1229218066Sadrian HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1230239053Sadrian struct ath_desc *, 1231239053Sadrian HAL_DMA_ADDR *bufAddrList, 1232239053Sadrian uint32_t *segLenList, 1233239053Sadrian u_int, u_int, HAL_PKT_TYPE, 1234239053Sadrian u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1235233895Sadrian HAL_BOOL, HAL_BOOL); 1236218066Sadrian HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1237218066Sadrian struct ath_desc *, u_int, u_int, u_int, 1238218066Sadrian u_int, u_int, u_int, u_int, u_int); 1239218066Sadrian HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1240218066Sadrian struct ath_desc *, const struct ath_desc *); 1241218066Sadrian void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1242218066Sadrian struct ath_desc *, u_int, u_int, 1243218066Sadrian HAL_11N_RATE_SERIES [], u_int, u_int); 1244226767Sadrian void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1245238838Sadrian struct ath_desc *, u_int); 1246218066Sadrian void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1247218066Sadrian struct ath_desc *, u_int); 1248226767Sadrian void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1249226767Sadrian struct ath_desc *); 1250218066Sadrian void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1251218066Sadrian struct ath_desc *); 1252218066Sadrian void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1253218066Sadrian struct ath_desc *, u_int); 1254234873Sadrian HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1255234873Sadrian HAL_SURVEY_SAMPLE *); 1256227374Sadrian 1257218066Sadrian uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1258218066Sadrian void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1259218066Sadrian HAL_HT_MACMODE); 1260218066Sadrian HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1261218066Sadrian void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1262218066Sadrian HAL_HT_RXCLEAR); 1263218066Sadrian 1264185377Ssam /* Interrupt functions */ 1265185377Ssam HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1266185377Ssam HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1267185377Ssam HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1268185377Ssam HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1269185377Ssam}; 1270185377Ssam 1271185377Ssam/* 1272185377Ssam * Check the PCI vendor ID and device ID against Atheros' values 1273185377Ssam * and return a printable description for any Atheros hardware. 1274185377Ssam * AH_NULL is returned if the ID's do not describe Atheros hardware. 1275185377Ssam */ 1276185377Ssamextern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1277185377Ssam 1278185377Ssam/* 1279185377Ssam * Attach the HAL for use with the specified device. The device is 1280185377Ssam * defined by the PCI device ID. The caller provides an opaque pointer 1281185377Ssam * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1282185377Ssam * HAL state block for later use. Hardware register accesses are done 1283185377Ssam * using the specified bus tag and handle. On successful return a 1284185377Ssam * reference to a state block is returned that must be supplied in all 1285185377Ssam * subsequent HAL calls. Storage associated with this reference is 1286185377Ssam * dynamically allocated and must be freed by calling the ah_detach 1287185377Ssam * method when the client is done. If the attach operation fails a 1288185377Ssam * null (AH_NULL) reference will be returned and a status code will 1289185377Ssam * be returned if the status parameter is non-zero. 1290185377Ssam */ 1291185377Ssamextern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1292217624Sadrian HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1293185377Ssam 1294188968Ssamextern const char *ath_hal_mac_name(struct ath_hal *); 1295188968Ssamextern const char *ath_hal_rf_name(struct ath_hal *); 1296188968Ssam 1297185377Ssam/* 1298187831Ssam * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1299187831Ssam * request a set of channels for a particular country code and/or 1300187831Ssam * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1301187831Ssam * this list is constructed according to the contents of the EEPROM. 1302187831Ssam * ath_hal_getchannels acts similarly but does not alter the operating 1303187831Ssam * state; this can be used to collect information for a particular 1304187831Ssam * regulatory configuration. Finally ath_hal_set_channels installs a 1305187831Ssam * channel list constructed outside the driver. The HAL will adopt the 1306187831Ssam * channel list and setup internal state according to the specified 1307187831Ssam * regulatory configuration (e.g. conformance test limits). 1308185377Ssam * 1309187831Ssam * For all interfaces the channel list is returned in the supplied array. 1310187831Ssam * maxchans defines the maximum size of this array. nchans contains the 1311187831Ssam * actual number of channels returned. If a problem occurred then a 1312187831Ssam * status code != HAL_OK is returned. 1313185377Ssam */ 1314187831Ssamstruct ieee80211_channel; 1315185377Ssam 1316185377Ssam/* 1317187831Ssam * Return a list of channels according to the specified regulatory. 1318185377Ssam */ 1319187831Ssamextern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1320187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1321187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1322187831Ssam HAL_BOOL enableExtendedChannels); 1323185377Ssam 1324185377Ssam/* 1325187831Ssam * Return a list of channels and install it as the current operating 1326187831Ssam * regulatory list. 1327185377Ssam */ 1328187831Ssamextern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1329187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1330187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1331187831Ssam HAL_BOOL enableExtendedChannels); 1332185377Ssam 1333185377Ssam/* 1334187831Ssam * Install the list of channels as the current operating regulatory 1335187831Ssam * and setup related state according to the country code and sku. 1336185377Ssam */ 1337187831Ssamextern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1338187831Ssam struct ieee80211_channel *chans, int nchans, 1339187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1340185377Ssam 1341185377Ssam/* 1342220443Sadrian * Fetch the ctl/ext noise floor values reported by a MIMO 1343220443Sadrian * radio. Returns 1 for valid results, 0 for invalid channel. 1344220443Sadrian */ 1345220443Sadrianextern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1346220444Sadrian const struct ieee80211_channel *chan, int16_t *nf_ctl, 1347220444Sadrian int16_t *nf_ext); 1348220443Sadrian 1349220443Sadrian/* 1350187831Ssam * Calibrate noise floor data following a channel scan or similar. 1351187831Ssam * This must be called prior retrieving noise floor data. 1352185377Ssam */ 1353187831Ssamextern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1354185377Ssam 1355185377Ssam/* 1356187831Ssam * Return bit mask of wireless modes supported by the hardware. 1357185377Ssam */ 1358187831Ssamextern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1359185377Ssam 1360185377Ssam/* 1361218011Sadrian * Calculate the packet TX time for a legacy or 11n frame 1362185377Ssam */ 1363218011Sadrianextern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1364218011Sadrian const HAL_RATE_TABLE *rates, uint32_t frameLen, 1365218011Sadrian uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1366218011Sadrian 1367218011Sadrian/* 1368218011Sadrian * Calculate the duration of an 11n frame. 1369218011Sadrian */ 1370218011Sadrianextern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1371218011Sadrian int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1372218011Sadrian 1373218011Sadrian/* 1374218011Sadrian * Calculate the transmit duration of a legacy frame. 1375218011Sadrian */ 1376187831Ssamextern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1377187831Ssam const HAL_RATE_TABLE *rates, uint32_t frameLen, 1378187831Ssam uint16_t rateix, HAL_BOOL shortPreamble); 1379225444Sadrian 1380225444Sadrian/* 1381225444Sadrian * Adjust the TSF. 1382225444Sadrian */ 1383225444Sadrianextern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1384225444Sadrian 1385225444Sadrian/* 1386225444Sadrian * Enable or disable CCA. 1387225444Sadrian */ 1388225444Sadrianvoid __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1389225444Sadrian 1390225444Sadrian/* 1391225444Sadrian * Get CCA setting. 1392225444Sadrian */ 1393225444Sadrianint __ahdecl ath_hal_getcca(struct ath_hal *ah); 1394225444Sadrian 1395230147Sadrian/* 1396230147Sadrian * Read EEPROM data from ah_eepromdata 1397230147Sadrian */ 1398230147SadrianHAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1399230147Sadrian u_int off, uint16_t *data); 1400230147Sadrian 1401185377Ssam#endif /* _ATH_AH_H_ */ 1402