ah.h revision 217684
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 217684 2011-01-21 05:21:00Z adrian $ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _ATH_AH_H_ 21185377Ssam#define _ATH_AH_H_ 22185377Ssam/* 23185377Ssam * Atheros Hardware Access Layer 24185377Ssam * 25185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26185377Ssam * structure for use with the device. Hardware-related operations that 27185377Ssam * follow must call back into the HAL through interface, supplying the 28185377Ssam * reference as the first parameter. 29185377Ssam */ 30185377Ssam 31185377Ssam#include "ah_osdep.h" 32185377Ssam 33185377Ssam/* 34185377Ssam * __ahdecl is analogous to _cdecl; it defines the calling 35185377Ssam * convention used within the HAL. For most systems this 36185377Ssam * can just default to be empty and the compiler will (should) 37185377Ssam * use _cdecl. For systems where _cdecl is not compatible this 38185377Ssam * must be defined. See linux/ah_osdep.h for an example. 39185377Ssam */ 40185377Ssam#ifndef __ahdecl 41185377Ssam#define __ahdecl 42185377Ssam#endif 43185377Ssam 44185377Ssam/* 45185377Ssam * Status codes that may be returned by the HAL. Note that 46185377Ssam * interfaces that return a status code set it only when an 47185377Ssam * error occurs--i.e. you cannot check it for success. 48185377Ssam */ 49185377Ssamtypedef enum { 50185377Ssam HAL_OK = 0, /* No error */ 51185377Ssam HAL_ENXIO = 1, /* No hardware present */ 52185377Ssam HAL_ENOMEM = 2, /* Memory allocation failed */ 53185377Ssam HAL_EIO = 3, /* Hardware didn't respond as expected */ 54185377Ssam HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55185377Ssam HAL_EEVERSION = 5, /* EEPROM version invalid */ 56185377Ssam HAL_EELOCKED = 6, /* EEPROM unreadable */ 57185377Ssam HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58185377Ssam HAL_EEREAD = 8, /* EEPROM read problem */ 59185377Ssam HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60185377Ssam HAL_EESIZE = 10, /* EEPROM size not supported */ 61185377Ssam HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62185377Ssam HAL_EINVAL = 12, /* Invalid parameter to function */ 63185377Ssam HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64185377Ssam HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65185377Ssam HAL_EINPROGRESS = 15, /* Operation incomplete */ 66187831Ssam HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67187831Ssam HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68185377Ssam} HAL_STATUS; 69185377Ssam 70185377Ssamtypedef enum { 71185377Ssam AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72185377Ssam AH_TRUE = 1, 73185377Ssam} HAL_BOOL; 74185377Ssam 75185377Ssamtypedef enum { 76185377Ssam HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77185377Ssam HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78185377Ssam HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79185377Ssam HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80185377Ssam HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81185377Ssam HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82185377Ssam HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83185377Ssam HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84185377Ssam HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85185377Ssam HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86185377Ssam HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87185377Ssam HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88185377Ssam HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89185377Ssam HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90185377Ssam HAL_CAP_TXPOW = 15, /* global tx power limit */ 91185377Ssam HAL_CAP_TPC = 16, /* per-packet tx power control */ 92185377Ssam HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93185377Ssam HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94185377Ssam HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95185377Ssam HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96185377Ssam /* 21 was HAL_CAP_XR */ 97185377Ssam HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98185380Ssam /* 23 was HAL_CAP_CHAN_HALFRATE */ 99185380Ssam /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100185377Ssam HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101185377Ssam HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102185377Ssam HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103185377Ssam HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104185377Ssam HAL_CAP_INTMIT = 29, /* interference mitigation */ 105185377Ssam HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106185377Ssam HAL_CAP_HT = 31, /* hardware can support HT */ 107185377Ssam HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108185377Ssam HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109185377Ssam HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110185377Ssam HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111185377Ssam HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112192396Ssam HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113195114Ssam HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */ 114185377Ssam} HAL_CAPABILITY_TYPE; 115185377Ssam 116185377Ssam/* 117185377Ssam * "States" for setting the LED. These correspond to 118185377Ssam * the possible 802.11 operational states and there may 119185377Ssam * be a many-to-one mapping between these states and the 120185377Ssam * actual hardware state for the LED's (i.e. the hardware 121185377Ssam * may have fewer states). 122185377Ssam */ 123185377Ssamtypedef enum { 124185377Ssam HAL_LED_INIT = 0, 125185377Ssam HAL_LED_SCAN = 1, 126185377Ssam HAL_LED_AUTH = 2, 127185377Ssam HAL_LED_ASSOC = 3, 128185377Ssam HAL_LED_RUN = 4 129185377Ssam} HAL_LED_STATE; 130185377Ssam 131185377Ssam/* 132185377Ssam * Transmit queue types/numbers. These are used to tag 133185377Ssam * each transmit queue in the hardware and to identify a set 134185377Ssam * of transmit queues for operations such as start/stop dma. 135185377Ssam */ 136185377Ssamtypedef enum { 137185377Ssam HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 138185377Ssam HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 139185377Ssam HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 140185377Ssam HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 141185377Ssam HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 142185377Ssam} HAL_TX_QUEUE; 143185377Ssam 144185377Ssam#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 145185377Ssam 146185377Ssam/* 147185377Ssam * Transmit queue subtype. These map directly to 148185377Ssam * WME Access Categories (except for UPSD). Refer 149185377Ssam * to Table 5 of the WME spec. 150185377Ssam */ 151185377Ssamtypedef enum { 152185377Ssam HAL_WME_AC_BK = 0, /* background access category */ 153185377Ssam HAL_WME_AC_BE = 1, /* best effort access category*/ 154185377Ssam HAL_WME_AC_VI = 2, /* video access category */ 155185377Ssam HAL_WME_AC_VO = 3, /* voice access category */ 156185377Ssam HAL_WME_UPSD = 4, /* uplink power save */ 157185377Ssam} HAL_TX_QUEUE_SUBTYPE; 158185377Ssam 159185377Ssam/* 160185377Ssam * Transmit queue flags that control various 161185377Ssam * operational parameters. 162185377Ssam */ 163185377Ssamtypedef enum { 164185377Ssam /* 165185377Ssam * Per queue interrupt enables. When set the associated 166185377Ssam * interrupt may be delivered for packets sent through 167185377Ssam * the queue. Without these enabled no interrupts will 168185377Ssam * be delivered for transmits through the queue. 169185377Ssam */ 170185377Ssam HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 171185377Ssam HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 172185377Ssam HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 173185377Ssam HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 174185377Ssam HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 175185377Ssam /* 176185377Ssam * Enable hardware compression for packets sent through 177185377Ssam * the queue. The compression buffer must be setup and 178185377Ssam * packets must have a key entry marked in the tx descriptor. 179185377Ssam */ 180185377Ssam HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 181185377Ssam /* 182185377Ssam * Disable queue when veol is hit or ready time expires. 183185377Ssam * By default the queue is disabled only on reaching the 184185377Ssam * physical end of queue (i.e. a null link ptr in the 185185377Ssam * descriptor chain). 186185377Ssam */ 187185377Ssam HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 188185377Ssam /* 189185377Ssam * Schedule frames on delivery of a DBA (DMA Beacon Alert) 190185377Ssam * event. Frames will be transmitted only when this timer 191185377Ssam * fires, e.g to transmit a beacon in ap or adhoc modes. 192185377Ssam */ 193185377Ssam HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 194185377Ssam /* 195185377Ssam * Each transmit queue has a counter that is incremented 196185377Ssam * each time the queue is enabled and decremented when 197185377Ssam * the list of frames to transmit is traversed (or when 198185377Ssam * the ready time for the queue expires). This counter 199185377Ssam * must be non-zero for frames to be scheduled for 200185377Ssam * transmission. The following controls disable bumping 201185377Ssam * this counter under certain conditions. Typically this 202185377Ssam * is used to gate frames based on the contents of another 203185377Ssam * queue (e.g. CAB traffic may only follow a beacon frame). 204185377Ssam * These are meaningful only when frames are scheduled 205185377Ssam * with a non-ASAP policy (e.g. DBA-gated). 206185377Ssam */ 207185377Ssam HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 208185377Ssam HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 209185377Ssam 210185377Ssam /* 211185377Ssam * Fragment burst backoff policy. Normally the no backoff 212185377Ssam * is done after a successful transmission, the next fragment 213185377Ssam * is sent at SIFS. If this flag is set backoff is done 214185377Ssam * after each fragment, regardless whether it was ack'd or 215185377Ssam * not, after the backoff count reaches zero a normal channel 216185377Ssam * access procedure is done before the next transmit (i.e. 217185377Ssam * wait AIFS instead of SIFS). 218185377Ssam */ 219185377Ssam HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 220185377Ssam /* 221185377Ssam * Disable post-tx backoff following each frame. 222185377Ssam */ 223185377Ssam HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 224185377Ssam /* 225185377Ssam * DCU arbiter lockout control. This controls how 226185377Ssam * lower priority tx queues are handled with respect to 227185377Ssam * to a specific queue when multiple queues have frames 228185377Ssam * to send. No lockout means lower priority queues arbitrate 229185377Ssam * concurrently with this queue. Intra-frame lockout 230185377Ssam * means lower priority queues are locked out until the 231185377Ssam * current frame transmits (e.g. including backoffs and bursting). 232185377Ssam * Global lockout means nothing lower can arbitrary so 233185377Ssam * long as there is traffic activity on this queue (frames, 234185377Ssam * backoff, etc). 235185377Ssam */ 236185377Ssam HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 237185377Ssam HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 238185377Ssam 239185377Ssam HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 240185377Ssam HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 241185377Ssam} HAL_TX_QUEUE_FLAGS; 242185377Ssam 243185377Ssamtypedef struct { 244185377Ssam uint32_t tqi_ver; /* hal TXQ version */ 245185377Ssam HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 246185377Ssam HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 247185377Ssam uint32_t tqi_priority; /* (not used) */ 248185377Ssam uint32_t tqi_aifs; /* aifs */ 249185377Ssam uint32_t tqi_cwmin; /* cwMin */ 250185377Ssam uint32_t tqi_cwmax; /* cwMax */ 251185377Ssam uint16_t tqi_shretry; /* rts retry limit */ 252185377Ssam uint16_t tqi_lgretry; /* long retry limit (not used)*/ 253185377Ssam uint32_t tqi_cbrPeriod; /* CBR period (us) */ 254185377Ssam uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 255185377Ssam uint32_t tqi_burstTime; /* max burst duration (us) */ 256185377Ssam uint32_t tqi_readyTime; /* frame schedule time (us) */ 257185377Ssam uint32_t tqi_compBuf; /* comp buffer phys addr */ 258185377Ssam} HAL_TXQ_INFO; 259185377Ssam 260185377Ssam#define HAL_TQI_NONVAL 0xffff 261185377Ssam 262185377Ssam/* token to use for aifs, cwmin, cwmax */ 263185377Ssam#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 264185377Ssam 265185377Ssam/* compression definitions */ 266185377Ssam#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 267185377Ssam#define HAL_COMP_BUF_ALIGN_SIZE 512 268185377Ssam 269185377Ssam/* 270185377Ssam * Transmit packet types. This belongs in ah_desc.h, but 271185377Ssam * is here so we can give a proper type to various parameters 272185377Ssam * (and not require everyone include the file). 273185377Ssam * 274185377Ssam * NB: These values are intentionally assigned for 275185377Ssam * direct use when setting up h/w descriptors. 276185377Ssam */ 277185377Ssamtypedef enum { 278185377Ssam HAL_PKT_TYPE_NORMAL = 0, 279185377Ssam HAL_PKT_TYPE_ATIM = 1, 280185377Ssam HAL_PKT_TYPE_PSPOLL = 2, 281185377Ssam HAL_PKT_TYPE_BEACON = 3, 282185377Ssam HAL_PKT_TYPE_PROBE_RESP = 4, 283185377Ssam HAL_PKT_TYPE_CHIRP = 5, 284185377Ssam HAL_PKT_TYPE_GRP_POLL = 6, 285185377Ssam HAL_PKT_TYPE_AMPDU = 7, 286185377Ssam} HAL_PKT_TYPE; 287185377Ssam 288185377Ssam/* Rx Filter Frame Types */ 289185377Ssamtypedef enum { 290185377Ssam HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 291185377Ssam HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 292185377Ssam HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 293185377Ssam HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 294185377Ssam HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 295185377Ssam HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 296185377Ssam HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 297185377Ssam HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 298185377Ssam HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 299185377Ssam HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 300195114Ssam HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */ 301185377Ssam} HAL_RX_FILTER; 302185377Ssam 303185377Ssamtypedef enum { 304185377Ssam HAL_PM_AWAKE = 0, 305185377Ssam HAL_PM_FULL_SLEEP = 1, 306185377Ssam HAL_PM_NETWORK_SLEEP = 2, 307185377Ssam HAL_PM_UNDEFINED = 3 308185377Ssam} HAL_POWER_MODE; 309185377Ssam 310185377Ssam/* 311185377Ssam * NOTE WELL: 312185377Ssam * These are mapped to take advantage of the common locations for many of 313185377Ssam * the bits on all of the currently supported MAC chips. This is to make 314185377Ssam * the ISR as efficient as possible, while still abstracting HW differences. 315185377Ssam * When new hardware breaks this commonality this enumerated type, as well 316185377Ssam * as the HAL functions using it, must be modified. All values are directly 317185377Ssam * mapped unless commented otherwise. 318185377Ssam */ 319185377Ssamtypedef enum { 320185377Ssam HAL_INT_RX = 0x00000001, /* Non-common mapping */ 321185377Ssam HAL_INT_RXDESC = 0x00000002, 322185377Ssam HAL_INT_RXNOFRM = 0x00000008, 323185377Ssam HAL_INT_RXEOL = 0x00000010, 324185377Ssam HAL_INT_RXORN = 0x00000020, 325185377Ssam HAL_INT_TX = 0x00000040, /* Non-common mapping */ 326185377Ssam HAL_INT_TXDESC = 0x00000080, 327208711Srpaulo HAL_INT_TIM_TIMER= 0x00000100, 328185377Ssam HAL_INT_TXURN = 0x00000800, 329185377Ssam HAL_INT_MIB = 0x00001000, 330185377Ssam HAL_INT_RXPHY = 0x00004000, 331185377Ssam HAL_INT_RXKCM = 0x00008000, 332185377Ssam HAL_INT_SWBA = 0x00010000, 333185377Ssam HAL_INT_BMISS = 0x00040000, 334192401Ssam HAL_INT_BNR = 0x00100000, 335185377Ssam HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 336185377Ssam HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 337185377Ssam HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 338185377Ssam HAL_INT_GPIO = 0x01000000, 339185377Ssam HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 340185377Ssam HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 341192400Ssam HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 342185377Ssam HAL_INT_CST = 0x10000000, /* Non-common mapping */ 343185377Ssam HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 344185377Ssam HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 345185377Ssam#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 346185377Ssam HAL_INT_BMISC = HAL_INT_TIM 347185377Ssam | HAL_INT_DTIM 348185377Ssam | HAL_INT_DTIMSYNC 349192400Ssam | HAL_INT_CABEND 350192400Ssam | HAL_INT_TBTT, 351185377Ssam 352185377Ssam /* Interrupt bits that map directly to ISR/IMR bits */ 353185377Ssam HAL_INT_COMMON = HAL_INT_RXNOFRM 354185377Ssam | HAL_INT_RXDESC 355185377Ssam | HAL_INT_RXEOL 356185377Ssam | HAL_INT_RXORN 357192396Ssam | HAL_INT_TXDESC 358185377Ssam | HAL_INT_TXURN 359185377Ssam | HAL_INT_MIB 360185377Ssam | HAL_INT_RXPHY 361185377Ssam | HAL_INT_RXKCM 362185377Ssam | HAL_INT_SWBA 363185377Ssam | HAL_INT_BMISS 364192397Ssam | HAL_INT_BNR 365185377Ssam | HAL_INT_GPIO, 366185377Ssam} HAL_INT; 367185377Ssam 368185377Ssamtypedef enum { 369188974Ssam HAL_GPIO_MUX_OUTPUT = 0, 370188974Ssam HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 371188974Ssam HAL_GPIO_MUX_PCIE_POWER_LED = 2, 372188974Ssam HAL_GPIO_MUX_TX_FRAME = 3, 373188974Ssam HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 374188974Ssam HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 375188974Ssam HAL_GPIO_MUX_MAC_POWER_LED = 6 376188974Ssam} HAL_GPIO_MUX_TYPE; 377188974Ssam 378188974Ssamtypedef enum { 379188974Ssam HAL_GPIO_INTR_LOW = 0, 380188974Ssam HAL_GPIO_INTR_HIGH = 1, 381188974Ssam HAL_GPIO_INTR_DISABLE = 2 382188974Ssam} HAL_GPIO_INTR_TYPE; 383188974Ssam 384188974Ssamtypedef enum { 385185377Ssam HAL_RFGAIN_INACTIVE = 0, 386185377Ssam HAL_RFGAIN_READ_REQUESTED = 1, 387185377Ssam HAL_RFGAIN_NEED_CHANGE = 2 388185377Ssam} HAL_RFGAIN; 389185377Ssam 390187831Ssamtypedef uint16_t HAL_CTRY_CODE; /* country code */ 391187831Ssamtypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 392185377Ssam 393185377Ssam#define HAL_ANTENNA_MIN_MODE 0 394185377Ssam#define HAL_ANTENNA_FIXED_A 1 395185377Ssam#define HAL_ANTENNA_FIXED_B 2 396185377Ssam#define HAL_ANTENNA_MAX_MODE 3 397185377Ssam 398185377Ssamtypedef struct { 399185377Ssam uint32_t ackrcv_bad; 400185377Ssam uint32_t rts_bad; 401185377Ssam uint32_t rts_good; 402185377Ssam uint32_t fcs_bad; 403185377Ssam uint32_t beacons; 404185377Ssam} HAL_MIB_STATS; 405185377Ssam 406185377Ssamenum { 407185377Ssam HAL_MODE_11A = 0x001, /* 11a channels */ 408185377Ssam HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 409185377Ssam HAL_MODE_11B = 0x004, /* 11b channels */ 410185377Ssam HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 411185377Ssam#ifdef notdef 412185377Ssam HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 413185377Ssam#else 414185377Ssam HAL_MODE_11G = 0x008, /* XXX historical */ 415185377Ssam#endif 416185377Ssam HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 417185377Ssam HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 418185380Ssam HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 419185380Ssam HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 420185380Ssam HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 421185380Ssam HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 422185377Ssam HAL_MODE_11NG_HT20 = 0x008000, 423185377Ssam HAL_MODE_11NA_HT20 = 0x010000, 424185377Ssam HAL_MODE_11NG_HT40PLUS = 0x020000, 425185377Ssam HAL_MODE_11NG_HT40MINUS = 0x040000, 426185377Ssam HAL_MODE_11NA_HT40PLUS = 0x080000, 427185377Ssam HAL_MODE_11NA_HT40MINUS = 0x100000, 428185377Ssam HAL_MODE_ALL = 0xffffff 429185377Ssam}; 430185377Ssam 431185377Ssamtypedef struct { 432185377Ssam int rateCount; /* NB: for proper padding */ 433185377Ssam uint8_t rateCodeToIndex[144]; /* back mapping */ 434185377Ssam struct { 435188770Ssam uint8_t valid; /* valid for rate control use */ 436188770Ssam uint8_t phy; /* CCK/OFDM/XR */ 437185377Ssam uint32_t rateKbps; /* transfer rate in kbs */ 438185377Ssam uint8_t rateCode; /* rate for h/w descriptors */ 439185377Ssam uint8_t shortPreamble; /* mask for enabling short 440185377Ssam * preamble in CCK rate code */ 441185377Ssam uint8_t dot11Rate; /* value for supported rates 442185377Ssam * info element of MLME */ 443185377Ssam uint8_t controlRate; /* index of next lower basic 444185377Ssam * rate; used for dur. calcs */ 445185377Ssam uint16_t lpAckDuration; /* long preamble ACK duration */ 446185377Ssam uint16_t spAckDuration; /* short preamble ACK duration*/ 447185377Ssam } info[32]; 448185377Ssam} HAL_RATE_TABLE; 449185377Ssam 450185377Ssamtypedef struct { 451185377Ssam u_int rs_count; /* number of valid entries */ 452185377Ssam uint8_t rs_rates[32]; /* rates */ 453185377Ssam} HAL_RATE_SET; 454185377Ssam 455185377Ssam/* 456185377Ssam * 802.11n specific structures and enums 457185377Ssam */ 458185377Ssamtypedef enum { 459185377Ssam HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 460185377Ssam HAL_CHAINTYPE_RX = 2, /* RX chain type */ 461185377Ssam} HAL_CHAIN_TYPE; 462185377Ssam 463185377Ssamtypedef struct { 464185377Ssam u_int Tries; 465185377Ssam u_int Rate; 466185377Ssam u_int PktDuration; 467185377Ssam u_int ChSel; 468185377Ssam u_int RateFlags; 469185377Ssam#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 470185377Ssam#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 471185377Ssam#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 472185377Ssam} HAL_11N_RATE_SERIES; 473185377Ssam 474185377Ssamtypedef enum { 475185377Ssam HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 476185377Ssam HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 477185377Ssam} HAL_HT_MACMODE; 478185377Ssam 479185377Ssamtypedef enum { 480185377Ssam HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 481185377Ssam HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 482185377Ssam} HAL_HT_PHYMODE; 483185377Ssam 484185377Ssamtypedef enum { 485185377Ssam HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 486185377Ssam HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 487185377Ssam} HAL_HT_EXTPROTSPACING; 488185377Ssam 489185377Ssam 490185377Ssamtypedef enum { 491185377Ssam HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 492185377Ssam HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 493185377Ssam} HAL_HT_RXCLEAR; 494185377Ssam 495185377Ssam/* 496185377Ssam * Antenna switch control. By default antenna selection 497185377Ssam * enables multiple (2) antenna use. To force use of the 498185377Ssam * A or B antenna only specify a fixed setting. Fixing 499185377Ssam * the antenna will also disable any diversity support. 500185377Ssam */ 501185377Ssamtypedef enum { 502185377Ssam HAL_ANT_VARIABLE = 0, /* variable by programming */ 503185377Ssam HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 504185377Ssam HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 505185377Ssam} HAL_ANT_SETTING; 506185377Ssam 507185377Ssamtypedef enum { 508185377Ssam HAL_M_STA = 1, /* infrastructure station */ 509185377Ssam HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 510185377Ssam HAL_M_HOSTAP = 6, /* Software Access Point */ 511185377Ssam HAL_M_MONITOR = 8 /* Monitor mode */ 512185377Ssam} HAL_OPMODE; 513185377Ssam 514185377Ssamtypedef struct { 515185377Ssam uint8_t kv_type; /* one of HAL_CIPHER */ 516185377Ssam uint8_t kv_pad; 517185377Ssam uint16_t kv_len; /* length in bits */ 518185377Ssam uint8_t kv_val[16]; /* enough for 128-bit keys */ 519185377Ssam uint8_t kv_mic[8]; /* TKIP MIC key */ 520185377Ssam uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 521185377Ssam} HAL_KEYVAL; 522185377Ssam 523185377Ssamtypedef enum { 524185377Ssam HAL_CIPHER_WEP = 0, 525185377Ssam HAL_CIPHER_AES_OCB = 1, 526185377Ssam HAL_CIPHER_AES_CCM = 2, 527185377Ssam HAL_CIPHER_CKIP = 3, 528185377Ssam HAL_CIPHER_TKIP = 4, 529185377Ssam HAL_CIPHER_CLR = 5, /* no encryption */ 530185377Ssam 531185377Ssam HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 532185377Ssam} HAL_CIPHER; 533185377Ssam 534185377Ssamenum { 535185377Ssam HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 536185377Ssam HAL_SLOT_TIME_9 = 9, 537185377Ssam HAL_SLOT_TIME_20 = 20, 538185377Ssam}; 539185377Ssam 540185377Ssam/* 541185377Ssam * Per-station beacon timer state. Note that the specified 542185377Ssam * beacon interval (given in TU's) can also include flags 543185377Ssam * to force a TSF reset and to enable the beacon xmit logic. 544185377Ssam * If bs_cfpmaxduration is non-zero the hardware is setup to 545185377Ssam * coexist with a PCF-capable AP. 546185377Ssam */ 547185377Ssamtypedef struct { 548185377Ssam uint32_t bs_nexttbtt; /* next beacon in TU */ 549185377Ssam uint32_t bs_nextdtim; /* next DTIM in TU */ 550185377Ssam uint32_t bs_intval; /* beacon interval+flags */ 551185377Ssam#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 552185377Ssam#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 553185377Ssam#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 554185377Ssam uint32_t bs_dtimperiod; 555185377Ssam uint16_t bs_cfpperiod; /* CFP period in TU */ 556185377Ssam uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 557185377Ssam uint32_t bs_cfpnext; /* next CFP in TU */ 558185377Ssam uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 559185377Ssam uint16_t bs_bmissthreshold; /* beacon miss threshold */ 560185377Ssam uint32_t bs_sleepduration; /* max sleep duration */ 561185377Ssam} HAL_BEACON_STATE; 562185377Ssam 563185377Ssam/* 564185377Ssam * Like HAL_BEACON_STATE but for non-station mode setup. 565185377Ssam * NB: see above flag definitions for bt_intval. 566185377Ssam */ 567185377Ssamtypedef struct { 568185377Ssam uint32_t bt_intval; /* beacon interval+flags */ 569185377Ssam uint32_t bt_nexttbtt; /* next beacon in TU */ 570185377Ssam uint32_t bt_nextatim; /* next ATIM in TU */ 571185377Ssam uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 572185377Ssam uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 573185377Ssam uint32_t bt_flags; /* timer enables */ 574185377Ssam#define HAL_BEACON_TBTT_EN 0x00000001 575185377Ssam#define HAL_BEACON_DBA_EN 0x00000002 576185377Ssam#define HAL_BEACON_SWBA_EN 0x00000004 577185377Ssam} HAL_BEACON_TIMERS; 578185377Ssam 579185377Ssam/* 580185377Ssam * Per-node statistics maintained by the driver for use in 581185377Ssam * optimizing signal quality and other operational aspects. 582185377Ssam */ 583185377Ssamtypedef struct { 584185377Ssam uint32_t ns_avgbrssi; /* average beacon rssi */ 585185377Ssam uint32_t ns_avgrssi; /* average data rssi */ 586185377Ssam uint32_t ns_avgtxrssi; /* average tx rssi */ 587185377Ssam} HAL_NODE_STATS; 588185377Ssam 589185377Ssam#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 590185377Ssam 591185377Ssamstruct ath_desc; 592185377Ssamstruct ath_tx_status; 593185377Ssamstruct ath_rx_status; 594187831Ssamstruct ieee80211_channel; 595185377Ssam 596185377Ssam/* 597185377Ssam * Hardware Access Layer (HAL) API. 598185377Ssam * 599185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an 600185377Ssam * ath_hal structure for use with the device. Hardware-related operations 601185377Ssam * that follow must call back into the HAL through interface, supplying 602185377Ssam * the reference as the first parameter. Note that before using the 603185377Ssam * reference returned by ath_hal_attach the caller should verify the 604185377Ssam * ABI version number. 605185377Ssam */ 606185377Ssamstruct ath_hal { 607185377Ssam uint32_t ah_magic; /* consistency check magic number */ 608185377Ssam uint16_t ah_devid; /* PCI device ID */ 609185377Ssam uint16_t ah_subvendorid; /* PCI subvendor ID */ 610185377Ssam HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 611185377Ssam HAL_BUS_TAG ah_st; /* params for register r+w */ 612185377Ssam HAL_BUS_HANDLE ah_sh; 613185377Ssam HAL_CTRY_CODE ah_countryCode; 614185377Ssam 615185377Ssam uint32_t ah_macVersion; /* MAC version id */ 616185377Ssam uint16_t ah_macRev; /* MAC revision */ 617185377Ssam uint16_t ah_phyRev; /* PHY revision */ 618185377Ssam /* NB: when only one radio is present the rev is in 5Ghz */ 619185377Ssam uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 620185377Ssam uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 621185377Ssam 622217624Sadrian uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 623217624Sadrian 624185377Ssam const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 625185377Ssam u_int mode); 626185377Ssam void __ahdecl(*ah_detach)(struct ath_hal*); 627185377Ssam 628185377Ssam /* Reset functions */ 629185377Ssam HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 630187831Ssam struct ieee80211_channel *, 631187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status); 632185377Ssam HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 633185377Ssam HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 634188979Ssam void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 635188979Ssam void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 636185377Ssam void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 637187831Ssam HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 638187831Ssam struct ieee80211_channel *, HAL_BOOL *); 639187831Ssam HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 640187831Ssam struct ieee80211_channel *, u_int chainMask, 641187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 642187831Ssam HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 643187831Ssam const struct ieee80211_channel *); 644203930Srpaulo HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 645203930Srpaulo const struct ieee80211_channel *, uint16_t *); 646185377Ssam HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 647203930Srpaulo HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 648203930Srpaulo const struct ieee80211_channel *); 649185377Ssam 650185377Ssam /* Transmit functions */ 651185377Ssam HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 652185377Ssam HAL_BOOL incTrigLevel); 653185377Ssam int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 654185377Ssam const HAL_TXQ_INFO *qInfo); 655185377Ssam HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 656185377Ssam const HAL_TXQ_INFO *qInfo); 657185377Ssam HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 658185377Ssam HAL_TXQ_INFO *qInfo); 659185377Ssam HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 660185377Ssam HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 661185377Ssam uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 662185377Ssam HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 663185377Ssam uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 664185377Ssam HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 665185377Ssam HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 666185377Ssam HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 667185377Ssam u_int pktLen, u_int hdrLen, 668185377Ssam HAL_PKT_TYPE type, u_int txPower, 669185377Ssam u_int txRate0, u_int txTries0, 670185377Ssam u_int keyIx, u_int antMode, u_int flags, 671185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 672185377Ssam u_int compicvLen, u_int compivLen, 673185377Ssam u_int comp); 674185377Ssam HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 675185377Ssam u_int txRate1, u_int txTries1, 676185377Ssam u_int txRate2, u_int txTries2, 677185377Ssam u_int txRate3, u_int txTries3); 678185377Ssam HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 679185377Ssam u_int segLen, HAL_BOOL firstSeg, 680185377Ssam HAL_BOOL lastSeg, const struct ath_desc *); 681185377Ssam HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 682185377Ssam struct ath_desc *, struct ath_tx_status *); 683185377Ssam void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 684185377Ssam void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 685217621Sadrian HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 686217621Sadrian const struct ath_desc *ds, int *rates, int *tries); 687185377Ssam 688185377Ssam /* Receive Functions */ 689185377Ssam uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 690185377Ssam void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 691185377Ssam void __ahdecl(*ah_enableReceive)(struct ath_hal*); 692185377Ssam HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 693185377Ssam void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 694185377Ssam void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 695185377Ssam void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 696185377Ssam uint32_t filter0, uint32_t filter1); 697185377Ssam HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 698185377Ssam uint32_t index); 699185377Ssam HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 700185377Ssam uint32_t index); 701185377Ssam uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 702185377Ssam void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 703185377Ssam HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 704185377Ssam uint32_t size, u_int flags); 705185377Ssam HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 706185377Ssam struct ath_desc *, uint32_t phyAddr, 707185377Ssam struct ath_desc *next, uint64_t tsf, 708185377Ssam struct ath_rx_status *); 709185377Ssam void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 710187831Ssam const HAL_NODE_STATS *, 711187831Ssam const struct ieee80211_channel *); 712217684Sadrian void __ahdecl(*ah_aniPoll)(struct ath_hal *, 713217684Sadrian const struct ieee80211_channel *); 714185377Ssam void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 715185377Ssam const HAL_NODE_STATS *); 716185377Ssam 717185377Ssam /* Misc Functions */ 718185377Ssam HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 719185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 720185377Ssam uint32_t *result); 721185377Ssam HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 722185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 723185377Ssam uint32_t setting, HAL_STATUS *); 724185377Ssam HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 725185377Ssam const void *args, uint32_t argsize, 726185377Ssam void **result, uint32_t *resultsize); 727185377Ssam void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 728185377Ssam HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 729185377Ssam void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 730185377Ssam HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 731185377Ssam HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 732185377Ssam uint16_t, HAL_STATUS *); 733185377Ssam void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 734185377Ssam void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 735185377Ssam const uint8_t *bssid, uint16_t assocId); 736188974Ssam HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 737188974Ssam uint32_t gpio, HAL_GPIO_MUX_TYPE); 738185377Ssam HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 739185377Ssam uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 740185377Ssam HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 741185377Ssam uint32_t gpio, uint32_t val); 742185377Ssam void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 743185377Ssam uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 744185377Ssam uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 745185377Ssam void __ahdecl(*ah_resetTsf)(struct ath_hal*); 746185377Ssam HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 747185377Ssam void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 748185377Ssam HAL_MIB_STATS*); 749185377Ssam HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 750185377Ssam u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 751185377Ssam void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 752185377Ssam HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 753185377Ssam HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 754185377Ssam HAL_ANT_SETTING); 755185377Ssam HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 756185377Ssam u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 757185377Ssam HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 758185377Ssam u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 759185377Ssam HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 760185377Ssam u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 761185377Ssam HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 762185377Ssam u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 763185377Ssam HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 764185377Ssam u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 765185377Ssam HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 766185377Ssam void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 767185377Ssam 768185377Ssam /* Key Cache Functions */ 769185377Ssam uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 770185377Ssam HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 771185377Ssam HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 772185377Ssam uint16_t); 773185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 774185377Ssam uint16_t, const HAL_KEYVAL *, 775185377Ssam const uint8_t *, int); 776185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 777185377Ssam uint16_t, const uint8_t *); 778185377Ssam 779185377Ssam /* Power Management Functions */ 780185377Ssam HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 781185377Ssam HAL_POWER_MODE mode, int setChip); 782185377Ssam HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 783187831Ssam int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 784187831Ssam const struct ieee80211_channel *); 785185377Ssam 786185377Ssam /* Beacon Management Functions */ 787185377Ssam void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 788185377Ssam const HAL_BEACON_TIMERS *); 789185377Ssam /* NB: deprecated, use ah_setBeaconTimers instead */ 790185377Ssam void __ahdecl(*ah_beaconInit)(struct ath_hal *, 791185377Ssam uint32_t nexttbtt, uint32_t intval); 792185377Ssam void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 793185377Ssam const HAL_BEACON_STATE *); 794185377Ssam void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 795185377Ssam 796185377Ssam /* Interrupt functions */ 797185377Ssam HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 798185377Ssam HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 799185377Ssam HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 800185377Ssam HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 801185377Ssam}; 802185377Ssam 803185377Ssam/* 804185377Ssam * Check the PCI vendor ID and device ID against Atheros' values 805185377Ssam * and return a printable description for any Atheros hardware. 806185377Ssam * AH_NULL is returned if the ID's do not describe Atheros hardware. 807185377Ssam */ 808185377Ssamextern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 809185377Ssam 810185377Ssam/* 811185377Ssam * Attach the HAL for use with the specified device. The device is 812185377Ssam * defined by the PCI device ID. The caller provides an opaque pointer 813185377Ssam * to an upper-layer data structure (HAL_SOFTC) that is stored in the 814185377Ssam * HAL state block for later use. Hardware register accesses are done 815185377Ssam * using the specified bus tag and handle. On successful return a 816185377Ssam * reference to a state block is returned that must be supplied in all 817185377Ssam * subsequent HAL calls. Storage associated with this reference is 818185377Ssam * dynamically allocated and must be freed by calling the ah_detach 819185377Ssam * method when the client is done. If the attach operation fails a 820185377Ssam * null (AH_NULL) reference will be returned and a status code will 821185377Ssam * be returned if the status parameter is non-zero. 822185377Ssam */ 823185377Ssamextern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 824217624Sadrian HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 825185377Ssam 826188968Ssamextern const char *ath_hal_mac_name(struct ath_hal *); 827188968Ssamextern const char *ath_hal_rf_name(struct ath_hal *); 828188968Ssam 829185377Ssam/* 830187831Ssam * Regulatory interfaces. Drivers should use ath_hal_init_channels to 831187831Ssam * request a set of channels for a particular country code and/or 832187831Ssam * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 833187831Ssam * this list is constructed according to the contents of the EEPROM. 834187831Ssam * ath_hal_getchannels acts similarly but does not alter the operating 835187831Ssam * state; this can be used to collect information for a particular 836187831Ssam * regulatory configuration. Finally ath_hal_set_channels installs a 837187831Ssam * channel list constructed outside the driver. The HAL will adopt the 838187831Ssam * channel list and setup internal state according to the specified 839187831Ssam * regulatory configuration (e.g. conformance test limits). 840185377Ssam * 841187831Ssam * For all interfaces the channel list is returned in the supplied array. 842187831Ssam * maxchans defines the maximum size of this array. nchans contains the 843187831Ssam * actual number of channels returned. If a problem occurred then a 844187831Ssam * status code != HAL_OK is returned. 845185377Ssam */ 846187831Ssamstruct ieee80211_channel; 847185377Ssam 848185377Ssam/* 849187831Ssam * Return a list of channels according to the specified regulatory. 850185377Ssam */ 851187831Ssamextern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 852187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 853187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 854187831Ssam HAL_BOOL enableExtendedChannels); 855185377Ssam 856185377Ssam/* 857187831Ssam * Return a list of channels and install it as the current operating 858187831Ssam * regulatory list. 859185377Ssam */ 860187831Ssamextern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 861187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 862187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 863187831Ssam HAL_BOOL enableExtendedChannels); 864185377Ssam 865185377Ssam/* 866187831Ssam * Install the list of channels as the current operating regulatory 867187831Ssam * and setup related state according to the country code and sku. 868185377Ssam */ 869187831Ssamextern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 870187831Ssam struct ieee80211_channel *chans, int nchans, 871187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 872185377Ssam 873185377Ssam/* 874187831Ssam * Calibrate noise floor data following a channel scan or similar. 875187831Ssam * This must be called prior retrieving noise floor data. 876185377Ssam */ 877187831Ssamextern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 878185377Ssam 879185377Ssam/* 880187831Ssam * Return bit mask of wireless modes supported by the hardware. 881185377Ssam */ 882187831Ssamextern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 883185377Ssam 884185377Ssam/* 885187831Ssam * Calculate the transmit duration of a frame. 886185377Ssam */ 887187831Ssamextern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 888187831Ssam const HAL_RATE_TABLE *rates, uint32_t frameLen, 889187831Ssam uint16_t rateix, HAL_BOOL shortPreamble); 890185377Ssam#endif /* _ATH_AH_H_ */ 891