1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _ATH_AH_H_ 21185377Ssam#define _ATH_AH_H_ 22185377Ssam/* 23185377Ssam * Atheros Hardware Access Layer 24185377Ssam * 25185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26185377Ssam * structure for use with the device. Hardware-related operations that 27185377Ssam * follow must call back into the HAL through interface, supplying the 28185377Ssam * reference as the first parameter. 29185377Ssam */ 30185377Ssam 31185377Ssam#include "ah_osdep.h" 32185377Ssam 33185377Ssam/* 34220442Sadrian * The maximum number of TX/RX chains supported. 35220442Sadrian * This is intended to be used by various statistics gathering operations 36220442Sadrian * (NF, RSSI, EVM). 37220442Sadrian */ 38240623Sadrian#define AH_MAX_CHAINS 3 39220442Sadrian#define AH_MIMO_MAX_EVM_PILOTS 6 40220442Sadrian 41220442Sadrian/* 42185377Ssam * __ahdecl is analogous to _cdecl; it defines the calling 43185377Ssam * convention used within the HAL. For most systems this 44185377Ssam * can just default to be empty and the compiler will (should) 45185377Ssam * use _cdecl. For systems where _cdecl is not compatible this 46185377Ssam * must be defined. See linux/ah_osdep.h for an example. 47185377Ssam */ 48185377Ssam#ifndef __ahdecl 49185377Ssam#define __ahdecl 50185377Ssam#endif 51185377Ssam 52185377Ssam/* 53185377Ssam * Status codes that may be returned by the HAL. Note that 54185377Ssam * interfaces that return a status code set it only when an 55185377Ssam * error occurs--i.e. you cannot check it for success. 56185377Ssam */ 57185377Ssamtypedef enum { 58185377Ssam HAL_OK = 0, /* No error */ 59185377Ssam HAL_ENXIO = 1, /* No hardware present */ 60185377Ssam HAL_ENOMEM = 2, /* Memory allocation failed */ 61185377Ssam HAL_EIO = 3, /* Hardware didn't respond as expected */ 62185377Ssam HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63185377Ssam HAL_EEVERSION = 5, /* EEPROM version invalid */ 64185377Ssam HAL_EELOCKED = 6, /* EEPROM unreadable */ 65185377Ssam HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66185377Ssam HAL_EEREAD = 8, /* EEPROM read problem */ 67185377Ssam HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68185377Ssam HAL_EESIZE = 10, /* EEPROM size not supported */ 69185377Ssam HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70185377Ssam HAL_EINVAL = 12, /* Invalid parameter to function */ 71185377Ssam HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72185377Ssam HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73185377Ssam HAL_EINPROGRESS = 15, /* Operation incomplete */ 74187831Ssam HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75187831Ssam HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76237874Sadrian HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77185377Ssam} HAL_STATUS; 78185377Ssam 79185377Ssamtypedef enum { 80185377Ssam AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81185377Ssam AH_TRUE = 1, 82185377Ssam} HAL_BOOL; 83185377Ssam 84185377Ssamtypedef enum { 85185377Ssam HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86185377Ssam HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87185377Ssam HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88185377Ssam HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89185377Ssam HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90185377Ssam HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91185377Ssam HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92185377Ssam HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93185377Ssam HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94185377Ssam HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95185377Ssam HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96185377Ssam HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97185377Ssam HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98185377Ssam HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99185377Ssam HAL_CAP_TXPOW = 15, /* global tx power limit */ 100185377Ssam HAL_CAP_TPC = 16, /* per-packet tx power control */ 101185377Ssam HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102185377Ssam HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103185377Ssam HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104185377Ssam HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105185377Ssam /* 21 was HAL_CAP_XR */ 106185377Ssam HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107185380Ssam /* 23 was HAL_CAP_CHAN_HALFRATE */ 108185380Ssam /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109185377Ssam HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110185377Ssam HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111185377Ssam HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112185377Ssam HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113237953Sadrian HAL_CAP_PCIE_PS = 29, 114221603Sadrian HAL_CAP_HT = 30, /* hardware can support HT */ 115221603Sadrian HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116221603Sadrian HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117221603Sadrian HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118221603Sadrian HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119221603Sadrian HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120221581Sadrian 121221603Sadrian HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122237953Sadrian HAL_CAP_RIFS_RX = 39, 123237953Sadrian HAL_CAP_RIFS_TX = 40, 124237953Sadrian HAL_CAP_FORCE_PPM = 41, 125221603Sadrian HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126221603Sadrian HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127222584Sadrian HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128222584Sadrian HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129222584Sadrian HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130221603Sadrian 131221603Sadrian HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132221603Sadrian automatically after waking up to receive TIM */ 133221603Sadrian HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134221603Sadrian HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135221603Sadrian HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136237953Sadrian HAL_CAP_BB_RIFS_HANG = 52, 137237953Sadrian HAL_CAP_RIFS_RX_ENABLED = 53, 138237953Sadrian HAL_CAP_BB_DFS_HANG = 54, 139221603Sadrian 140247366Sadrian HAL_CAP_RX_STBC = 58, 141247366Sadrian HAL_CAP_TX_STBC = 59, 142247366Sadrian 143221603Sadrian HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144237953Sadrian HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145221603Sadrian 146237953Sadrian HAL_CAP_DS = 67, /* 2 stream */ 147237953Sadrian HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148237953Sadrian HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149237955Sadrian HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150237953Sadrian 151237953Sadrian HAL_CAP_TS = 72, /* 3 stream */ 152237953Sadrian 153237953Sadrian HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154238280Sadrian HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155238280Sadrian HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156238280Sadrian HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157238280Sadrian HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158238280Sadrian HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159238280Sadrian HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160238280Sadrian HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161237953Sadrian HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162244854Sadrian HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163237953Sadrian 164237953Sadrian HAL_CAP_BB_PANIC_WATCHDOG = 92, 165237953Sadrian 166221603Sadrian HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167221603Sadrian 168239631Sadrian HAL_CAP_LDPC = 99, 169239631Sadrian 170221603Sadrian HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171239631Sadrian 172251360Sadrian HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 173239631Sadrian HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 174239631Sadrian HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 175239631Sadrian HAL_CAP_LDPCWAR = 108, 176239631Sadrian HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 177239631Sadrian HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 178239631Sadrian HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 179239631Sadrian HAL_CAP_PCIE_LCR_OFFSET = 112, 180239631Sadrian 181222584Sadrian HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 182239632Sadrian HAL_CAP_MCI = 118, 183239632Sadrian HAL_CAP_SMARTANTENNA = 119, 184239632Sadrian HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 185239632Sadrian HAL_CAP_TX_DIVERSITY = 121, 186239632Sadrian HAL_CAP_CRDC = 122, 187221603Sadrian 188221581Sadrian /* The following are private to the FreeBSD HAL (224 onward) */ 189221581Sadrian 190221603Sadrian HAL_CAP_INTMIT = 229, /* interference mitigation */ 191221603Sadrian HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 192221603Sadrian HAL_CAP_BB_HANG = 235, /* can baseband hang */ 193221603Sadrian HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 194221603Sadrian HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 195221603Sadrian HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 196221603Sadrian HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 197225444Sadrian HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 198226488Sadrian HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 199227410Sadrian HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 200243743Sadrian HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 201251400Sadrian HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 202265032Sadrian HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 203185377Ssam} HAL_CAPABILITY_TYPE; 204185377Ssam 205185377Ssam/* 206185377Ssam * "States" for setting the LED. These correspond to 207185377Ssam * the possible 802.11 operational states and there may 208185377Ssam * be a many-to-one mapping between these states and the 209185377Ssam * actual hardware state for the LED's (i.e. the hardware 210185377Ssam * may have fewer states). 211185377Ssam */ 212185377Ssamtypedef enum { 213185377Ssam HAL_LED_INIT = 0, 214185377Ssam HAL_LED_SCAN = 1, 215185377Ssam HAL_LED_AUTH = 2, 216185377Ssam HAL_LED_ASSOC = 3, 217185377Ssam HAL_LED_RUN = 4 218185377Ssam} HAL_LED_STATE; 219185377Ssam 220185377Ssam/* 221185377Ssam * Transmit queue types/numbers. These are used to tag 222185377Ssam * each transmit queue in the hardware and to identify a set 223185377Ssam * of transmit queues for operations such as start/stop dma. 224185377Ssam */ 225185377Ssamtypedef enum { 226185377Ssam HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 227185377Ssam HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 228185377Ssam HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 229185377Ssam HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 230185377Ssam HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 231219790Sadrian HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 232237874Sadrian HAL_TX_QUEUE_CFEND = 6, 233237874Sadrian HAL_TX_QUEUE_PAPRD = 7, 234185377Ssam} HAL_TX_QUEUE; 235185377Ssam 236185377Ssam#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 237185377Ssam 238242407Sadrian/* 239242407Sadrian * Receive queue types. These are used to tag 240242407Sadrian * each transmit queue in the hardware and to identify a set 241242407Sadrian * of transmit queues for operations such as start/stop dma. 242242407Sadrian */ 243237874Sadriantypedef enum { 244237874Sadrian HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 245238280Sadrian HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 246237874Sadrian} HAL_RX_QUEUE; 247237874Sadrian 248237874Sadrian#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 249237874Sadrian 250238857Sadrian#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 251238857Sadrian 252185377Ssam/* 253185377Ssam * Transmit queue subtype. These map directly to 254185377Ssam * WME Access Categories (except for UPSD). Refer 255185377Ssam * to Table 5 of the WME spec. 256185377Ssam */ 257185377Ssamtypedef enum { 258185377Ssam HAL_WME_AC_BK = 0, /* background access category */ 259185377Ssam HAL_WME_AC_BE = 1, /* best effort access category*/ 260185377Ssam HAL_WME_AC_VI = 2, /* video access category */ 261185377Ssam HAL_WME_AC_VO = 3, /* voice access category */ 262185377Ssam HAL_WME_UPSD = 4, /* uplink power save */ 263185377Ssam} HAL_TX_QUEUE_SUBTYPE; 264185377Ssam 265185377Ssam/* 266185377Ssam * Transmit queue flags that control various 267185377Ssam * operational parameters. 268185377Ssam */ 269185377Ssamtypedef enum { 270185377Ssam /* 271185377Ssam * Per queue interrupt enables. When set the associated 272185377Ssam * interrupt may be delivered for packets sent through 273185377Ssam * the queue. Without these enabled no interrupts will 274185377Ssam * be delivered for transmits through the queue. 275185377Ssam */ 276185377Ssam HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 277185377Ssam HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 278185377Ssam HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 279185377Ssam HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 280185377Ssam HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 281185377Ssam /* 282185377Ssam * Enable hardware compression for packets sent through 283185377Ssam * the queue. The compression buffer must be setup and 284185377Ssam * packets must have a key entry marked in the tx descriptor. 285185377Ssam */ 286185377Ssam HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 287185377Ssam /* 288185377Ssam * Disable queue when veol is hit or ready time expires. 289185377Ssam * By default the queue is disabled only on reaching the 290185377Ssam * physical end of queue (i.e. a null link ptr in the 291185377Ssam * descriptor chain). 292185377Ssam */ 293185377Ssam HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 294185377Ssam /* 295185377Ssam * Schedule frames on delivery of a DBA (DMA Beacon Alert) 296185377Ssam * event. Frames will be transmitted only when this timer 297185377Ssam * fires, e.g to transmit a beacon in ap or adhoc modes. 298185377Ssam */ 299185377Ssam HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 300185377Ssam /* 301185377Ssam * Each transmit queue has a counter that is incremented 302185377Ssam * each time the queue is enabled and decremented when 303185377Ssam * the list of frames to transmit is traversed (or when 304185377Ssam * the ready time for the queue expires). This counter 305185377Ssam * must be non-zero for frames to be scheduled for 306185377Ssam * transmission. The following controls disable bumping 307185377Ssam * this counter under certain conditions. Typically this 308185377Ssam * is used to gate frames based on the contents of another 309185377Ssam * queue (e.g. CAB traffic may only follow a beacon frame). 310185377Ssam * These are meaningful only when frames are scheduled 311185377Ssam * with a non-ASAP policy (e.g. DBA-gated). 312185377Ssam */ 313185377Ssam HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 314185377Ssam HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 315185377Ssam 316185377Ssam /* 317185377Ssam * Fragment burst backoff policy. Normally the no backoff 318185377Ssam * is done after a successful transmission, the next fragment 319185377Ssam * is sent at SIFS. If this flag is set backoff is done 320185377Ssam * after each fragment, regardless whether it was ack'd or 321185377Ssam * not, after the backoff count reaches zero a normal channel 322185377Ssam * access procedure is done before the next transmit (i.e. 323185377Ssam * wait AIFS instead of SIFS). 324185377Ssam */ 325185377Ssam HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 326185377Ssam /* 327185377Ssam * Disable post-tx backoff following each frame. 328185377Ssam */ 329185377Ssam HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 330185377Ssam /* 331185377Ssam * DCU arbiter lockout control. This controls how 332185377Ssam * lower priority tx queues are handled with respect to 333185377Ssam * to a specific queue when multiple queues have frames 334185377Ssam * to send. No lockout means lower priority queues arbitrate 335185377Ssam * concurrently with this queue. Intra-frame lockout 336185377Ssam * means lower priority queues are locked out until the 337185377Ssam * current frame transmits (e.g. including backoffs and bursting). 338185377Ssam * Global lockout means nothing lower can arbitrary so 339185377Ssam * long as there is traffic activity on this queue (frames, 340185377Ssam * backoff, etc). 341185377Ssam */ 342185377Ssam HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 343185377Ssam HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 344185377Ssam 345185377Ssam HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 346185377Ssam HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 347185377Ssam} HAL_TX_QUEUE_FLAGS; 348185377Ssam 349185377Ssamtypedef struct { 350185377Ssam uint32_t tqi_ver; /* hal TXQ version */ 351185377Ssam HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 352185377Ssam HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 353185377Ssam uint32_t tqi_priority; /* (not used) */ 354185377Ssam uint32_t tqi_aifs; /* aifs */ 355185377Ssam uint32_t tqi_cwmin; /* cwMin */ 356185377Ssam uint32_t tqi_cwmax; /* cwMax */ 357185377Ssam uint16_t tqi_shretry; /* rts retry limit */ 358185377Ssam uint16_t tqi_lgretry; /* long retry limit (not used)*/ 359185377Ssam uint32_t tqi_cbrPeriod; /* CBR period (us) */ 360185377Ssam uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 361185377Ssam uint32_t tqi_burstTime; /* max burst duration (us) */ 362185377Ssam uint32_t tqi_readyTime; /* frame schedule time (us) */ 363185377Ssam uint32_t tqi_compBuf; /* comp buffer phys addr */ 364185377Ssam} HAL_TXQ_INFO; 365185377Ssam 366185377Ssam#define HAL_TQI_NONVAL 0xffff 367185377Ssam 368185377Ssam/* token to use for aifs, cwmin, cwmax */ 369185377Ssam#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 370185377Ssam 371185377Ssam/* compression definitions */ 372185377Ssam#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 373185377Ssam#define HAL_COMP_BUF_ALIGN_SIZE 512 374185377Ssam 375185377Ssam/* 376185377Ssam * Transmit packet types. This belongs in ah_desc.h, but 377185377Ssam * is here so we can give a proper type to various parameters 378185377Ssam * (and not require everyone include the file). 379185377Ssam * 380185377Ssam * NB: These values are intentionally assigned for 381185377Ssam * direct use when setting up h/w descriptors. 382185377Ssam */ 383185377Ssamtypedef enum { 384185377Ssam HAL_PKT_TYPE_NORMAL = 0, 385185377Ssam HAL_PKT_TYPE_ATIM = 1, 386185377Ssam HAL_PKT_TYPE_PSPOLL = 2, 387185377Ssam HAL_PKT_TYPE_BEACON = 3, 388185377Ssam HAL_PKT_TYPE_PROBE_RESP = 4, 389185377Ssam HAL_PKT_TYPE_CHIRP = 5, 390185377Ssam HAL_PKT_TYPE_GRP_POLL = 6, 391185377Ssam HAL_PKT_TYPE_AMPDU = 7, 392185377Ssam} HAL_PKT_TYPE; 393185377Ssam 394185377Ssam/* Rx Filter Frame Types */ 395185377Ssamtypedef enum { 396220022Sadrian /* 397220022Sadrian * These bits correspond to AR_RX_FILTER for all chips. 398220022Sadrian * Not all bits are supported by all chips. 399220022Sadrian */ 400185377Ssam HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 401185377Ssam HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 402185377Ssam HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 403185377Ssam HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 404185377Ssam HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 405185377Ssam HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 406185377Ssam HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 407220025Sadrian HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 408265032Sadrian HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 409185377Ssam HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 410220022Sadrian HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 411220025Sadrian HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 412220022Sadrian HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 413220022Sadrian HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 414220022Sadrian /* Allow all mcast/bcast frames */ 415220022Sadrian 416220022Sadrian /* 417298939Spfg * Magic RX filter flags that aren't targeting hardware bits 418220022Sadrian * but instead the HAL sets individual bits - eg PHYERR will result 419220022Sadrian * in OFDM/CCK timing error frames being received. 420220022Sadrian */ 421220022Sadrian HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 422185377Ssam} HAL_RX_FILTER; 423185377Ssam 424185377Ssamtypedef enum { 425185377Ssam HAL_PM_AWAKE = 0, 426185377Ssam HAL_PM_FULL_SLEEP = 1, 427185377Ssam HAL_PM_NETWORK_SLEEP = 2, 428185377Ssam HAL_PM_UNDEFINED = 3 429185377Ssam} HAL_POWER_MODE; 430185377Ssam 431185377Ssam/* 432242407Sadrian * Enterprise mode flags 433242407Sadrian */ 434242407Sadrian#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 435242407Sadrian#define AH_ENT_CHAIN2_DISABLE 0x00000002 436242407Sadrian#define AH_ENT_5MHZ_DISABLE 0x00000004 437242407Sadrian#define AH_ENT_10MHZ_DISABLE 0x00000008 438242407Sadrian#define AH_ENT_49GHZ_DISABLE 0x00000010 439242407Sadrian#define AH_ENT_LOOPBACK_DISABLE 0x00000020 440242407Sadrian#define AH_ENT_TPC_PERF_DISABLE 0x00000040 441242407Sadrian#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 442242407Sadrian#define AH_ENT_SPECTRAL_PRECISION 0x00000300 443242407Sadrian#define AH_ENT_SPECTRAL_PRECISION_S 8 444242407Sadrian#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 445242407Sadrian 446242407Sadrian#define AH_FIRST_DESC_NDELIMS 60 447242407Sadrian 448242407Sadrian/* 449185377Ssam * NOTE WELL: 450185377Ssam * These are mapped to take advantage of the common locations for many of 451185377Ssam * the bits on all of the currently supported MAC chips. This is to make 452185377Ssam * the ISR as efficient as possible, while still abstracting HW differences. 453185377Ssam * When new hardware breaks this commonality this enumerated type, as well 454185377Ssam * as the HAL functions using it, must be modified. All values are directly 455185377Ssam * mapped unless commented otherwise. 456185377Ssam */ 457185377Ssamtypedef enum { 458185377Ssam HAL_INT_RX = 0x00000001, /* Non-common mapping */ 459238349Sadrian HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 460239605Sadrian HAL_INT_RXERR = 0x00000004, 461238349Sadrian HAL_INT_RXHP = 0x00000001, /* EDMA */ 462238349Sadrian HAL_INT_RXLP = 0x00000002, /* EDMA */ 463185377Ssam HAL_INT_RXNOFRM = 0x00000008, 464185377Ssam HAL_INT_RXEOL = 0x00000010, 465185377Ssam HAL_INT_RXORN = 0x00000020, 466185377Ssam HAL_INT_TX = 0x00000040, /* Non-common mapping */ 467185377Ssam HAL_INT_TXDESC = 0x00000080, 468208711Srpaulo HAL_INT_TIM_TIMER= 0x00000100, 469239605Sadrian HAL_INT_MCI = 0x00000200, 470239605Sadrian HAL_INT_BBPANIC = 0x00000400, 471185377Ssam HAL_INT_TXURN = 0x00000800, 472185377Ssam HAL_INT_MIB = 0x00001000, 473185377Ssam HAL_INT_RXPHY = 0x00004000, 474185377Ssam HAL_INT_RXKCM = 0x00008000, 475185377Ssam HAL_INT_SWBA = 0x00010000, 476239605Sadrian HAL_INT_BRSSI = 0x00020000, 477185377Ssam HAL_INT_BMISS = 0x00040000, 478192401Ssam HAL_INT_BNR = 0x00100000, 479185377Ssam HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 480185377Ssam HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 481185377Ssam HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 482185377Ssam HAL_INT_GPIO = 0x01000000, 483185377Ssam HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 484185377Ssam HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 485192400Ssam HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 486239605Sadrian /* Atheros ref driver has a generic timer interrupt now..*/ 487242407Sadrian HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 488185377Ssam HAL_INT_CST = 0x10000000, /* Non-common mapping */ 489185377Ssam HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 490185377Ssam HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 491185377Ssam#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 492185377Ssam HAL_INT_BMISC = HAL_INT_TIM 493185377Ssam | HAL_INT_DTIM 494185377Ssam | HAL_INT_DTIMSYNC 495192400Ssam | HAL_INT_CABEND 496192400Ssam | HAL_INT_TBTT, 497185377Ssam 498185377Ssam /* Interrupt bits that map directly to ISR/IMR bits */ 499185377Ssam HAL_INT_COMMON = HAL_INT_RXNOFRM 500185377Ssam | HAL_INT_RXDESC 501185377Ssam | HAL_INT_RXEOL 502185377Ssam | HAL_INT_RXORN 503192396Ssam | HAL_INT_TXDESC 504185377Ssam | HAL_INT_TXURN 505185377Ssam | HAL_INT_MIB 506185377Ssam | HAL_INT_RXPHY 507185377Ssam | HAL_INT_RXKCM 508185377Ssam | HAL_INT_SWBA 509185377Ssam | HAL_INT_BMISS 510239605Sadrian | HAL_INT_BRSSI 511192397Ssam | HAL_INT_BNR 512185377Ssam | HAL_INT_GPIO, 513185377Ssam} HAL_INT; 514185377Ssam 515237622Sadrian/* 516237622Sadrian * MSI vector assignments 517237622Sadrian */ 518185377Ssamtypedef enum { 519237622Sadrian HAL_MSIVEC_MISC = 0, 520237622Sadrian HAL_MSIVEC_TX = 1, 521237622Sadrian HAL_MSIVEC_RXLP = 2, 522237622Sadrian HAL_MSIVEC_RXHP = 3, 523237622Sadrian} HAL_MSIVEC; 524237622Sadrian 525237622Sadriantypedef enum { 526237622Sadrian HAL_INT_LINE = 0, 527237622Sadrian HAL_INT_MSI = 1, 528237622Sadrian} HAL_INT_TYPE; 529237622Sadrian 530237622Sadrian/* For interrupt mitigation registers */ 531237622Sadriantypedef enum { 532237622Sadrian HAL_INT_RX_FIRSTPKT=0, 533237622Sadrian HAL_INT_RX_LASTPKT, 534237622Sadrian HAL_INT_TX_FIRSTPKT, 535237622Sadrian HAL_INT_TX_LASTPKT, 536237622Sadrian HAL_INT_THRESHOLD 537237622Sadrian} HAL_INT_MITIGATION; 538237622Sadrian 539242407Sadrian/* XXX this is duplicate information! */ 540242407Sadriantypedef struct { 541242407Sadrian u_int32_t cyclecnt_diff; /* delta cycle count */ 542242407Sadrian u_int32_t rxclr_cnt; /* rx clear count */ 543280827Sadrian u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 544242407Sadrian u_int32_t txframecnt_diff; /* delta tx frame count */ 545242407Sadrian u_int32_t rxframecnt_diff; /* delta rx frame count */ 546242407Sadrian u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 547242407Sadrian u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 548242407Sadrian u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 549242407Sadrian u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 550242407Sadrian HAL_BOOL valid; /* if the stats are valid*/ 551242407Sadrian} HAL_ANISTATS; 552242407Sadrian 553242407Sadriantypedef struct { 554242407Sadrian u_int8_t txctl_offset; 555242407Sadrian u_int8_t txctl_numwords; 556242407Sadrian u_int8_t txstatus_offset; 557242407Sadrian u_int8_t txstatus_numwords; 558242407Sadrian 559242407Sadrian u_int8_t rxctl_offset; 560242407Sadrian u_int8_t rxctl_numwords; 561242407Sadrian u_int8_t rxstatus_offset; 562242407Sadrian u_int8_t rxstatus_numwords; 563242407Sadrian 564242407Sadrian u_int8_t macRevision; 565242407Sadrian} HAL_DESC_INFO; 566242407Sadrian 567237622Sadriantypedef enum { 568237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 569237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 570237611Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 571237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 572237611Sadrian HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 573237611Sadrian HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 574249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 575249131Sadrian 576249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 577249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 578249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 579249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 580249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 581249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 582249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 583249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 584249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 585249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 586249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 587249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 588249131Sadrian HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 589249131Sadrian HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 590188974Ssam} HAL_GPIO_MUX_TYPE; 591188974Ssam 592188974Ssamtypedef enum { 593188974Ssam HAL_GPIO_INTR_LOW = 0, 594188974Ssam HAL_GPIO_INTR_HIGH = 1, 595188974Ssam HAL_GPIO_INTR_DISABLE = 2 596188974Ssam} HAL_GPIO_INTR_TYPE; 597188974Ssam 598242509Sadriantypedef struct halCounters { 599242509Sadrian u_int32_t tx_frame_count; 600242509Sadrian u_int32_t rx_frame_count; 601242509Sadrian u_int32_t rx_clear_count; 602242509Sadrian u_int32_t cycle_count; 603242509Sadrian u_int8_t is_rx_active; // true (1) or false (0) 604242509Sadrian u_int8_t is_tx_active; // true (1) or false (0) 605242509Sadrian} HAL_COUNTERS; 606242509Sadrian 607188974Ssamtypedef enum { 608185377Ssam HAL_RFGAIN_INACTIVE = 0, 609185377Ssam HAL_RFGAIN_READ_REQUESTED = 1, 610185377Ssam HAL_RFGAIN_NEED_CHANGE = 2 611185377Ssam} HAL_RFGAIN; 612185377Ssam 613187831Ssamtypedef uint16_t HAL_CTRY_CODE; /* country code */ 614187831Ssamtypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 615185377Ssam 616185377Ssam#define HAL_ANTENNA_MIN_MODE 0 617185377Ssam#define HAL_ANTENNA_FIXED_A 1 618185377Ssam#define HAL_ANTENNA_FIXED_B 2 619185377Ssam#define HAL_ANTENNA_MAX_MODE 3 620185377Ssam 621185377Ssamtypedef struct { 622185377Ssam uint32_t ackrcv_bad; 623185377Ssam uint32_t rts_bad; 624185377Ssam uint32_t rts_good; 625185377Ssam uint32_t fcs_bad; 626185377Ssam uint32_t beacons; 627185377Ssam} HAL_MIB_STATS; 628185377Ssam 629242407Sadrian/* 630242407Sadrian * These bits represent what's in ah_currentRDext. 631242407Sadrian */ 632242407Sadriantypedef enum { 633242407Sadrian REG_EXT_FCC_MIDBAND = 0, 634242407Sadrian REG_EXT_JAPAN_MIDBAND = 1, 635242407Sadrian REG_EXT_FCC_DFS_HT40 = 2, 636242407Sadrian REG_EXT_JAPAN_NONDFS_HT40 = 3, 637242407Sadrian REG_EXT_JAPAN_DFS_HT40 = 4 638242407Sadrian} REG_EXT_BITMAP; 639242407Sadrian 640185377Ssamenum { 641185377Ssam HAL_MODE_11A = 0x001, /* 11a channels */ 642185377Ssam HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 643185377Ssam HAL_MODE_11B = 0x004, /* 11b channels */ 644185377Ssam HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 645185377Ssam#ifdef notdef 646185377Ssam HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 647185377Ssam#else 648185377Ssam HAL_MODE_11G = 0x008, /* XXX historical */ 649185377Ssam#endif 650185377Ssam HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 651185377Ssam HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 652185380Ssam HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 653185380Ssam HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 654185380Ssam HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 655185380Ssam HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 656185377Ssam HAL_MODE_11NG_HT20 = 0x008000, 657185377Ssam HAL_MODE_11NA_HT20 = 0x010000, 658185377Ssam HAL_MODE_11NG_HT40PLUS = 0x020000, 659185377Ssam HAL_MODE_11NG_HT40MINUS = 0x040000, 660185377Ssam HAL_MODE_11NA_HT40PLUS = 0x080000, 661185377Ssam HAL_MODE_11NA_HT40MINUS = 0x100000, 662185377Ssam HAL_MODE_ALL = 0xffffff 663185377Ssam}; 664185377Ssam 665185377Ssamtypedef struct { 666185377Ssam int rateCount; /* NB: for proper padding */ 667239289Sadrian uint8_t rateCodeToIndex[256]; /* back mapping */ 668185377Ssam struct { 669188770Ssam uint8_t valid; /* valid for rate control use */ 670188770Ssam uint8_t phy; /* CCK/OFDM/XR */ 671185377Ssam uint32_t rateKbps; /* transfer rate in kbs */ 672185377Ssam uint8_t rateCode; /* rate for h/w descriptors */ 673185377Ssam uint8_t shortPreamble; /* mask for enabling short 674185377Ssam * preamble in CCK rate code */ 675185377Ssam uint8_t dot11Rate; /* value for supported rates 676185377Ssam * info element of MLME */ 677185377Ssam uint8_t controlRate; /* index of next lower basic 678185377Ssam * rate; used for dur. calcs */ 679185377Ssam uint16_t lpAckDuration; /* long preamble ACK duration */ 680185377Ssam uint16_t spAckDuration; /* short preamble ACK duration*/ 681239289Sadrian } info[64]; 682185377Ssam} HAL_RATE_TABLE; 683185377Ssam 684185377Ssamtypedef struct { 685185377Ssam u_int rs_count; /* number of valid entries */ 686239289Sadrian uint8_t rs_rates[64]; /* rates */ 687185377Ssam} HAL_RATE_SET; 688185377Ssam 689185377Ssam/* 690185377Ssam * 802.11n specific structures and enums 691185377Ssam */ 692185377Ssamtypedef enum { 693185377Ssam HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 694185377Ssam HAL_CHAINTYPE_RX = 2, /* RX chain type */ 695185377Ssam} HAL_CHAIN_TYPE; 696185377Ssam 697185377Ssamtypedef struct { 698185377Ssam u_int Tries; 699238840Sadrian u_int Rate; /* hardware rate code */ 700238840Sadrian u_int RateIndex; /* rate series table index */ 701185377Ssam u_int PktDuration; 702185377Ssam u_int ChSel; 703185377Ssam u_int RateFlags; 704185377Ssam#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 705185377Ssam#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 706185377Ssam#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 707238841Sadrian#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 708242407Sadrian u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 709185377Ssam} HAL_11N_RATE_SERIES; 710185377Ssam 711185377Ssamtypedef enum { 712185377Ssam HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 713185377Ssam HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 714185377Ssam} HAL_HT_MACMODE; 715185377Ssam 716185377Ssamtypedef enum { 717185377Ssam HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 718185377Ssam HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 719185377Ssam} HAL_HT_PHYMODE; 720185377Ssam 721185377Ssamtypedef enum { 722185377Ssam HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 723185377Ssam HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 724185377Ssam} HAL_HT_EXTPROTSPACING; 725185377Ssam 726185377Ssam 727185377Ssamtypedef enum { 728185377Ssam HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 729185377Ssam HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 730185377Ssam} HAL_HT_RXCLEAR; 731185377Ssam 732242407Sadriantypedef enum { 733242407Sadrian HAL_FREQ_BAND_5GHZ = 0, 734242407Sadrian HAL_FREQ_BAND_2GHZ = 1, 735242407Sadrian} HAL_FREQ_BAND; 736242407Sadrian 737185377Ssam/* 738185377Ssam * Antenna switch control. By default antenna selection 739185377Ssam * enables multiple (2) antenna use. To force use of the 740185377Ssam * A or B antenna only specify a fixed setting. Fixing 741185377Ssam * the antenna will also disable any diversity support. 742185377Ssam */ 743185377Ssamtypedef enum { 744185377Ssam HAL_ANT_VARIABLE = 0, /* variable by programming */ 745185377Ssam HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 746185377Ssam HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 747185377Ssam} HAL_ANT_SETTING; 748185377Ssam 749185377Ssamtypedef enum { 750185377Ssam HAL_M_STA = 1, /* infrastructure station */ 751185377Ssam HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 752185377Ssam HAL_M_HOSTAP = 6, /* Software Access Point */ 753185377Ssam HAL_M_MONITOR = 8 /* Monitor mode */ 754185377Ssam} HAL_OPMODE; 755185377Ssam 756290612Sadriantypedef enum { 757290612Sadrian HAL_RESET_NORMAL = 0, /* Do normal reset */ 758290612Sadrian HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 759290612Sadrian HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 760290612Sadrian} HAL_RESET_TYPE; 761290612Sadrian 762185377Ssamtypedef struct { 763185377Ssam uint8_t kv_type; /* one of HAL_CIPHER */ 764237874Sadrian uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 765185377Ssam uint16_t kv_len; /* length in bits */ 766185377Ssam uint8_t kv_val[16]; /* enough for 128-bit keys */ 767185377Ssam uint8_t kv_mic[8]; /* TKIP MIC key */ 768185377Ssam uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 769185377Ssam} HAL_KEYVAL; 770185377Ssam 771242407Sadrian/* 772242407Sadrian * This is the TX descriptor field which marks the key padding requirement. 773242407Sadrian * The naming is unfortunately unclear. 774242407Sadrian */ 775242407Sadrian#define AH_KEYTYPE_MASK 0x0F 776185377Ssamtypedef enum { 777242407Sadrian HAL_KEY_TYPE_CLEAR, 778242407Sadrian HAL_KEY_TYPE_WEP, 779242407Sadrian HAL_KEY_TYPE_AES, 780242407Sadrian HAL_KEY_TYPE_TKIP, 781242407Sadrian} HAL_KEY_TYPE; 782242407Sadrian 783242407Sadriantypedef enum { 784185377Ssam HAL_CIPHER_WEP = 0, 785185377Ssam HAL_CIPHER_AES_OCB = 1, 786185377Ssam HAL_CIPHER_AES_CCM = 2, 787185377Ssam HAL_CIPHER_CKIP = 3, 788185377Ssam HAL_CIPHER_TKIP = 4, 789185377Ssam HAL_CIPHER_CLR = 5, /* no encryption */ 790185377Ssam 791185377Ssam HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 792185377Ssam} HAL_CIPHER; 793185377Ssam 794185377Ssamenum { 795185377Ssam HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 796185377Ssam HAL_SLOT_TIME_9 = 9, 797185377Ssam HAL_SLOT_TIME_20 = 20, 798185377Ssam}; 799185377Ssam 800185377Ssam/* 801185377Ssam * Per-station beacon timer state. Note that the specified 802185377Ssam * beacon interval (given in TU's) can also include flags 803185377Ssam * to force a TSF reset and to enable the beacon xmit logic. 804185377Ssam * If bs_cfpmaxduration is non-zero the hardware is setup to 805185377Ssam * coexist with a PCF-capable AP. 806185377Ssam */ 807185377Ssamtypedef struct { 808185377Ssam uint32_t bs_nexttbtt; /* next beacon in TU */ 809185377Ssam uint32_t bs_nextdtim; /* next DTIM in TU */ 810185377Ssam uint32_t bs_intval; /* beacon interval+flags */ 811243589Sadrian/* 812243589Sadrian * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 813243589Sadrian * are all 1:1 correspondances with the pre-11n chip AR_BEACON 814243589Sadrian * register. 815243589Sadrian */ 816185377Ssam#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 817242407Sadrian#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 818185377Ssam#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 819185377Ssam#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 820242407Sadrian#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 821185377Ssam uint32_t bs_dtimperiod; 822185377Ssam uint16_t bs_cfpperiod; /* CFP period in TU */ 823185377Ssam uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 824185377Ssam uint32_t bs_cfpnext; /* next CFP in TU */ 825185377Ssam uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 826185377Ssam uint16_t bs_bmissthreshold; /* beacon miss threshold */ 827185377Ssam uint32_t bs_sleepduration; /* max sleep duration */ 828242407Sadrian uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 829185377Ssam} HAL_BEACON_STATE; 830185377Ssam 831185377Ssam/* 832185377Ssam * Like HAL_BEACON_STATE but for non-station mode setup. 833185377Ssam * NB: see above flag definitions for bt_intval. 834185377Ssam */ 835185377Ssamtypedef struct { 836185377Ssam uint32_t bt_intval; /* beacon interval+flags */ 837185377Ssam uint32_t bt_nexttbtt; /* next beacon in TU */ 838185377Ssam uint32_t bt_nextatim; /* next ATIM in TU */ 839185377Ssam uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 840185377Ssam uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 841185377Ssam uint32_t bt_flags; /* timer enables */ 842185377Ssam#define HAL_BEACON_TBTT_EN 0x00000001 843185377Ssam#define HAL_BEACON_DBA_EN 0x00000002 844185377Ssam#define HAL_BEACON_SWBA_EN 0x00000004 845185377Ssam} HAL_BEACON_TIMERS; 846185377Ssam 847185377Ssam/* 848185377Ssam * Per-node statistics maintained by the driver for use in 849185377Ssam * optimizing signal quality and other operational aspects. 850185377Ssam */ 851185377Ssamtypedef struct { 852185377Ssam uint32_t ns_avgbrssi; /* average beacon rssi */ 853185377Ssam uint32_t ns_avgrssi; /* average data rssi */ 854185377Ssam uint32_t ns_avgtxrssi; /* average tx rssi */ 855185377Ssam} HAL_NODE_STATS; 856185377Ssam 857185377Ssam#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 858185377Ssam 859280940Sadrian/* 860280940Sadrian * This is the ANI state and MIB stats. 861280940Sadrian * 862280940Sadrian * It's used by the HAL modules to keep state /and/ by the debug ioctl 863280940Sadrian * to fetch ANI information. 864280940Sadrian */ 865280940Sadriantypedef struct { 866280940Sadrian uint32_t ast_ani_niup; /* ANI increased noise immunity */ 867280940Sadrian uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 868280940Sadrian uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 869280940Sadrian uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 870280940Sadrian uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 871280940Sadrian uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 872280940Sadrian uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 873280940Sadrian uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 874280940Sadrian uint32_t ast_ani_stepup; /* ANI increased first step level */ 875280940Sadrian uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 876280940Sadrian uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 877280940Sadrian uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 878280940Sadrian uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 879280940Sadrian uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 880280940Sadrian uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 881280940Sadrian HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 882280940Sadrian HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 883280940Sadrian} HAL_ANI_STATS; 884242407Sadrian 885280940Sadriantypedef struct { 886280940Sadrian uint8_t noiseImmunityLevel; 887280940Sadrian uint8_t spurImmunityLevel; 888280940Sadrian uint8_t firstepLevel; 889280940Sadrian uint8_t ofdmWeakSigDetectOff; 890280940Sadrian uint8_t cckWeakSigThreshold; 891280940Sadrian uint32_t listenTime; 892280940Sadrian 893280940Sadrian /* NB: intentionally ordered so data exported to user space is first */ 894280940Sadrian uint32_t txFrameCount; /* Last txFrameCount */ 895280940Sadrian uint32_t rxFrameCount; /* Last rx Frame count */ 896280940Sadrian uint32_t cycleCount; /* Last cycleCount 897280940Sadrian (to detect wrap-around) */ 898280940Sadrian uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 899280940Sadrian uint32_t cckPhyErrCount; /* CCK err count since last reset */ 900280940Sadrian} HAL_ANI_STATE; 901280940Sadrian 902185377Ssamstruct ath_desc; 903185377Ssamstruct ath_tx_status; 904185377Ssamstruct ath_rx_status; 905187831Ssamstruct ieee80211_channel; 906185377Ssam 907185377Ssam/* 908219773Sadrian * This is a channel survey sample entry. 909219773Sadrian * 910219773Sadrian * The AR5212 ANI routines fill these samples. The ANI code then uses it 911219773Sadrian * when calculating listen time; it is also exported via a diagnostic 912219773Sadrian * API. 913219773Sadrian */ 914219773Sadriantypedef struct { 915219773Sadrian uint32_t seq_num; 916219773Sadrian uint32_t tx_busy; 917219773Sadrian uint32_t rx_busy; 918219773Sadrian uint32_t chan_busy; 919234749Sadrian uint32_t ext_chan_busy; 920219773Sadrian uint32_t cycle_count; 921234749Sadrian /* XXX TODO */ 922234749Sadrian uint32_t ofdm_phyerr_count; 923234749Sadrian uint32_t cck_phyerr_count; 924219773Sadrian} HAL_SURVEY_SAMPLE; 925219773Sadrian 926219773Sadrian/* 927219773Sadrian * This provides 3.2 seconds of sample space given an 928219773Sadrian * ANI time of 1/10th of a second. This may not be enough! 929219773Sadrian */ 930219773Sadrian#define CHANNEL_SURVEY_SAMPLE_COUNT 32 931219773Sadrian 932219773Sadriantypedef struct { 933219773Sadrian HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 934219773Sadrian uint32_t cur_sample; /* current sample in sequence */ 935219773Sadrian uint32_t cur_seq; /* current sequence number */ 936219773Sadrian} HAL_CHANNEL_SURVEY; 937219773Sadrian 938219773Sadrian/* 939222277Sadrian * ANI commands. 940222277Sadrian * 941222277Sadrian * These are used both internally and externally via the diagnostic 942222277Sadrian * API. 943222277Sadrian * 944222277Sadrian * Note that this is NOT the ANI commands being used via the INTMIT 945222277Sadrian * capability - that has a different mapping for some reason. 946222277Sadrian */ 947222277Sadriantypedef enum { 948222277Sadrian HAL_ANI_PRESENT = 0, /* is ANI support present */ 949222277Sadrian HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 950222277Sadrian HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 951222277Sadrian HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 952222277Sadrian HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 953222277Sadrian HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 954222277Sadrian HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 955222277Sadrian HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 956237874Sadrian HAL_ANI_MRC_CCK = 8, 957222277Sadrian} HAL_ANI_CMD; 958222277Sadrian 959242407Sadrian#define HAL_ANI_ALL 0xffffffff 960242407Sadrian 961222277Sadrian/* 962222277Sadrian * This is the layout of the ANI INTMIT capability. 963222277Sadrian * 964222277Sadrian * Notice that the command values differ to HAL_ANI_CMD. 965222277Sadrian */ 966222277Sadriantypedef enum { 967222277Sadrian HAL_CAP_INTMIT_PRESENT = 0, 968222277Sadrian HAL_CAP_INTMIT_ENABLE = 1, 969222277Sadrian HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 970222277Sadrian HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 971222277Sadrian HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 972222277Sadrian HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 973222277Sadrian HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 974222277Sadrian} HAL_CAP_INTMIT_CMD; 975222277Sadrian 976222584Sadriantypedef struct { 977222584Sadrian int32_t pe_firpwr; /* FIR pwr out threshold */ 978222584Sadrian int32_t pe_rrssi; /* Radar rssi thresh */ 979222584Sadrian int32_t pe_height; /* Pulse height thresh */ 980222584Sadrian int32_t pe_prssi; /* Pulse rssi thresh */ 981222584Sadrian int32_t pe_inband; /* Inband thresh */ 982222584Sadrian 983222584Sadrian /* The following params are only for AR5413 and later */ 984222584Sadrian u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 985222584Sadrian u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 986222584Sadrian u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 987224244Sadrian int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 988224244Sadrian int32_t pe_blockradar; /* 989222584Sadrian * Enable to block radar check if pkt detect is done via OFDM 990222584Sadrian * weak signal detect or pkt is detected immediately after tx 991222584Sadrian * to rx transition 992222584Sadrian */ 993224244Sadrian int32_t pe_enmaxrssi; /* 994222584Sadrian * Enable to use the max rssi instead of the last rssi during 995222584Sadrian * fine gain changes for radar detection 996222584Sadrian */ 997224244Sadrian int32_t pe_extchannel; /* Enable DFS on ext channel */ 998224244Sadrian int32_t pe_enabled; /* Whether radar detection is enabled */ 999231708Sadrian int32_t pe_enrelpwr; 1000231708Sadrian int32_t pe_en_relstep_check; 1001222584Sadrian} HAL_PHYERR_PARAM; 1002222584Sadrian 1003222584Sadrian#define HAL_PHYERR_PARAM_NOVAL 65535 1004222584Sadrian 1005244854Sadriantypedef struct { 1006244854Sadrian u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1007244854Sadrian u_int16_t ss_period; /* Spectral scan period */ 1008244854Sadrian u_int16_t ss_count; /* # of reports to return from ss_active */ 1009244854Sadrian u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 1010244854Sadrian u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1011244854Sadrian u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1012244854Sadrian int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1013244854Sadrian int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1014244854Sadrian int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1015245281Sadrian int ss_enabled; 1016245281Sadrian int ss_active; 1017244854Sadrian} HAL_SPECTRAL_PARAM; 1018244854Sadrian#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1019244854Sadrian#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1020244854Sadrian 1021224716Sadrian/* 1022224716Sadrian * DFS operating mode flags. 1023224716Sadrian */ 1024224716Sadriantypedef enum { 1025224716Sadrian HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1026224716Sadrian HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1027224716Sadrian HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1028224716Sadrian HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1029224716Sadrian} HAL_DFS_DOMAIN; 1030222584Sadrian 1031242407Sadrian 1032222277Sadrian/* 1033239606Sadrian * MFP decryption options for initializing the MAC. 1034239606Sadrian */ 1035239606Sadriantypedef enum { 1036239606Sadrian HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1037239606Sadrian HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1038239606Sadrian HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1039239606Sadrian} HAL_MFP_OPT_T; 1040239606Sadrian 1041239890Sadrian/* LNA config supported */ 1042239890Sadriantypedef enum { 1043239890Sadrian HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1044239890Sadrian HAL_ANT_DIV_COMB_LNA2 = 1, 1045239890Sadrian HAL_ANT_DIV_COMB_LNA1 = 2, 1046239890Sadrian HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1047239890Sadrian} HAL_ANT_DIV_COMB_LNA_CONF; 1048239890Sadrian 1049239890Sadriantypedef struct { 1050239890Sadrian u_int8_t main_lna_conf; 1051239890Sadrian u_int8_t alt_lna_conf; 1052239890Sadrian u_int8_t fast_div_bias; 1053239890Sadrian u_int8_t main_gaintb; 1054239890Sadrian u_int8_t alt_gaintb; 1055239890Sadrian u_int8_t antdiv_configgroup; 1056239890Sadrian int8_t lna1_lna2_delta; 1057239890Sadrian} HAL_ANT_COMB_CONFIG; 1058239890Sadrian 1059239890Sadrian#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1060239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1061239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1062239890Sadrian#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1063239890Sadrian 1064239606Sadrian/* 1065222644Sadrian * Flag for setting QUIET period 1066222644Sadrian */ 1067222644Sadriantypedef enum { 1068222644Sadrian HAL_QUIET_DISABLE = 0x0, 1069222644Sadrian HAL_QUIET_ENABLE = 0x1, 1070222644Sadrian HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1071222644Sadrian HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1072222644Sadrian} HAL_QUIET_FLAG; 1073222644Sadrian 1074222815Sadrian#define HAL_DFS_EVENT_PRICH 0x0000001 1075224539Sadrian#define HAL_DFS_EVENT_EXTCH 0x0000002 1076224539Sadrian#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1077224539Sadrian#define HAL_DFS_EVENT_ISDC 0x0000008 1078222815Sadrian 1079224633Sadrianstruct hal_dfs_event { 1080222815Sadrian uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1081222815Sadrian uint32_t re_ts; /* Original 15 bit recv timestamp */ 1082222815Sadrian uint8_t re_rssi; /* rssi of radar event */ 1083222815Sadrian uint8_t re_dur; /* duration of radar pulse */ 1084222815Sadrian uint32_t re_flags; /* Flags (see above) */ 1085222815Sadrian}; 1086224633Sadriantypedef struct hal_dfs_event HAL_DFS_EVENT; 1087222815Sadrian 1088237611Sadrian/* 1089242407Sadrian * Generic Timer domain 1090242407Sadrian */ 1091242407Sadriantypedef enum { 1092242407Sadrian HAL_GEN_TIMER_TSF = 0, 1093242407Sadrian HAL_GEN_TIMER_TSF2, 1094242407Sadrian HAL_GEN_TIMER_TSF_ANY 1095242407Sadrian} HAL_GEN_TIMER_DOMAIN; 1096242407Sadrian 1097242407Sadrian/* 1098237611Sadrian * BT Co-existence definitions 1099237611Sadrian */ 1100301014Sadrian#include "ath_hal/ah_btcoex.h" 1101237611Sadrian 1102242407Sadrianstruct hal_bb_panic_info { 1103242407Sadrian u_int32_t status; 1104242407Sadrian u_int32_t tsf; 1105242407Sadrian u_int32_t phy_panic_wd_ctl1; 1106242407Sadrian u_int32_t phy_panic_wd_ctl2; 1107242407Sadrian u_int32_t phy_gen_ctrl; 1108242407Sadrian u_int32_t rxc_pcnt; 1109242407Sadrian u_int32_t rxf_pcnt; 1110242407Sadrian u_int32_t txf_pcnt; 1111242407Sadrian u_int32_t cycles; 1112242407Sadrian u_int32_t wd; 1113242407Sadrian u_int32_t det; 1114242407Sadrian u_int32_t rdar; 1115242407Sadrian u_int32_t r_odfm; 1116242407Sadrian u_int32_t r_cck; 1117242407Sadrian u_int32_t t_odfm; 1118242407Sadrian u_int32_t t_cck; 1119242407Sadrian u_int32_t agc; 1120242407Sadrian u_int32_t src; 1121242407Sadrian}; 1122242407Sadrian 1123242407Sadrian/* Serialize Register Access Mode */ 1124242407Sadriantypedef enum { 1125242407Sadrian SER_REG_MODE_OFF = 0, 1126242407Sadrian SER_REG_MODE_ON = 1, 1127242407Sadrian SER_REG_MODE_AUTO = 2, 1128242407Sadrian} SER_REG_MODE; 1129242407Sadrian 1130223459Sadriantypedef struct 1131223459Sadrian{ 1132223459Sadrian int ah_debug; /* only used if AH_DEBUG is defined */ 1133223459Sadrian int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1134223459Sadrian 1135223459Sadrian /* NB: these are deprecated; they exist for now for compatibility */ 1136223459Sadrian int ah_dma_beacon_response_time;/* in TU's */ 1137223459Sadrian int ah_sw_beacon_response_time; /* in TU's */ 1138223459Sadrian int ah_additional_swba_backoff; /* in TU's */ 1139227375Sadrian int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1140227410Sadrian int ah_serialise_reg_war; /* force serialisation of register IO */ 1141242407Sadrian 1142242407Sadrian /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1143242407Sadrian int ath_hal_desc_tpc; /* Per-packet TPC */ 1144242407Sadrian int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1145242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1146242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1147242407Sadrian int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1148242407Sadrian 1149242407Sadrian /* I'm not sure what the default values for these should be */ 1150242407Sadrian int ath_hal_pll_pwr_save; 1151242407Sadrian int ath_hal_pcie_power_save_enable; 1152242407Sadrian int ath_hal_intr_mitigation_rx; 1153242407Sadrian int ath_hal_intr_mitigation_tx; 1154242407Sadrian 1155242407Sadrian int ath_hal_pcie_clock_req; 1156242407Sadrian#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1157242407Sadrian#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1158242407Sadrian#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1159242407Sadrian 1160242407Sadrian int ath_hal_pcie_waen; 1161242407Sadrian int ath_hal_pcie_ser_des_write; 1162242407Sadrian 1163242407Sadrian /* these are important for correct AR9300 behaviour */ 1164242407Sadrian int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1165242407Sadrian int ath_hal_diversity_control; 1166242407Sadrian int ath_hal_antenna_switch_swap; 1167242407Sadrian int ath_hal_ext_lna_ctl_gpio; 1168242407Sadrian int ath_hal_spur_mode; 1169242407Sadrian int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1170242407Sadrian int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1171242407Sadrian int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1172242407Sadrian 1173242407Sadrian /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1174242407Sadrian int ath_hal_mfp_support; 1175242407Sadrian 1176242407Sadrian int ath_hal_enable_ani; /* should set this.. */ 1177242407Sadrian int ath_hal_cwm_ignore_ext_cca; 1178242407Sadrian int ath_hal_show_bb_panic; 1179242689Sadrian int ath_hal_ant_ctrl_comm2g_switch_enable; 1180242689Sadrian int ath_hal_ext_atten_margin_cfg; 1181272292Sadrian int ath_hal_min_gainidx; 1182242689Sadrian int ath_hal_war70c; 1183249131Sadrian uint32_t ath_hal_mci_config; 1184224633Sadrian} HAL_OPS_CONFIG; 1185223459Sadrian 1186222644Sadrian/* 1187185377Ssam * Hardware Access Layer (HAL) API. 1188185377Ssam * 1189185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an 1190185377Ssam * ath_hal structure for use with the device. Hardware-related operations 1191185377Ssam * that follow must call back into the HAL through interface, supplying 1192185377Ssam * the reference as the first parameter. Note that before using the 1193185377Ssam * reference returned by ath_hal_attach the caller should verify the 1194185377Ssam * ABI version number. 1195185377Ssam */ 1196185377Ssamstruct ath_hal { 1197185377Ssam uint32_t ah_magic; /* consistency check magic number */ 1198185377Ssam uint16_t ah_devid; /* PCI device ID */ 1199185377Ssam uint16_t ah_subvendorid; /* PCI subvendor ID */ 1200185377Ssam HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1201185377Ssam HAL_BUS_TAG ah_st; /* params for register r+w */ 1202185377Ssam HAL_BUS_HANDLE ah_sh; 1203185377Ssam HAL_CTRY_CODE ah_countryCode; 1204185377Ssam 1205185377Ssam uint32_t ah_macVersion; /* MAC version id */ 1206185377Ssam uint16_t ah_macRev; /* MAC revision */ 1207185377Ssam uint16_t ah_phyRev; /* PHY revision */ 1208185377Ssam /* NB: when only one radio is present the rev is in 5Ghz */ 1209185377Ssam uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1210185377Ssam uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1211185377Ssam 1212217624Sadrian uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1213217624Sadrian 1214227365Sadrian uint32_t ah_intrstate[8]; /* last int state */ 1215234088Sadrian uint32_t ah_syncstate; /* last sync intr state */ 1216227365Sadrian 1217262969Sadrian /* Current powerstate from HAL calls */ 1218262969Sadrian HAL_POWER_MODE ah_powerMode; 1219262969Sadrian 1220223459Sadrian HAL_OPS_CONFIG ah_config; 1221185377Ssam const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1222185377Ssam u_int mode); 1223185377Ssam void __ahdecl(*ah_detach)(struct ath_hal*); 1224185377Ssam 1225185377Ssam /* Reset functions */ 1226185377Ssam HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1227187831Ssam struct ieee80211_channel *, 1228290612Sadrian HAL_BOOL bChannelChange, 1229290612Sadrian HAL_RESET_TYPE resetType, 1230290612Sadrian HAL_STATUS *status); 1231185377Ssam HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1232185377Ssam HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1233235972Sadrian void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1234235972Sadrian HAL_BOOL power_off); 1235188979Ssam void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1236185377Ssam void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1237187831Ssam HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1238187831Ssam struct ieee80211_channel *, HAL_BOOL *); 1239187831Ssam HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1240187831Ssam struct ieee80211_channel *, u_int chainMask, 1241187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 1242187831Ssam HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1243187831Ssam const struct ieee80211_channel *); 1244203930Srpaulo HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1245203930Srpaulo const struct ieee80211_channel *, uint16_t *); 1246185377Ssam HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1247203930Srpaulo HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1248203930Srpaulo const struct ieee80211_channel *); 1249185377Ssam 1250185377Ssam /* Transmit functions */ 1251185377Ssam HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1252185377Ssam HAL_BOOL incTrigLevel); 1253185377Ssam int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1254185377Ssam const HAL_TXQ_INFO *qInfo); 1255185377Ssam HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1256185377Ssam const HAL_TXQ_INFO *qInfo); 1257185377Ssam HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1258185377Ssam HAL_TXQ_INFO *qInfo); 1259185377Ssam HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1260185377Ssam HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1261185377Ssam uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1262185377Ssam HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1263185377Ssam uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1264185377Ssam HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1265185377Ssam HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1266185377Ssam HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1267185377Ssam u_int pktLen, u_int hdrLen, 1268185377Ssam HAL_PKT_TYPE type, u_int txPower, 1269185377Ssam u_int txRate0, u_int txTries0, 1270185377Ssam u_int keyIx, u_int antMode, u_int flags, 1271185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 1272185377Ssam u_int compicvLen, u_int compivLen, 1273185377Ssam u_int comp); 1274185377Ssam HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1275185377Ssam u_int txRate1, u_int txTries1, 1276185377Ssam u_int txRate2, u_int txTries2, 1277185377Ssam u_int txRate3, u_int txTries3); 1278185377Ssam HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1279239051Sadrian HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1280239051Sadrian u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1281185377Ssam HAL_BOOL lastSeg, const struct ath_desc *); 1282185377Ssam HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1283185377Ssam struct ath_desc *, struct ath_tx_status *); 1284185377Ssam void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1285185377Ssam void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1286217621Sadrian HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1287217621Sadrian const struct ath_desc *ds, int *rates, int *tries); 1288238607Sadrian void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1289238607Sadrian uint32_t link); 1290238607Sadrian void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1291238607Sadrian uint32_t *link); 1292238607Sadrian void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1293238607Sadrian uint32_t **linkptr); 1294238731Sadrian void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1295238731Sadrian void *ts_start, uint32_t ts_paddr_start, 1296238731Sadrian uint16_t size); 1297242509Sadrian void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1298185377Ssam 1299185377Ssam /* Receive Functions */ 1300238278Sadrian uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1301238278Sadrian void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1302185377Ssam void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1303185377Ssam HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1304185377Ssam void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1305185377Ssam void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1306185377Ssam void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1307185377Ssam uint32_t filter0, uint32_t filter1); 1308185377Ssam HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1309185377Ssam uint32_t index); 1310185377Ssam HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1311185377Ssam uint32_t index); 1312185377Ssam uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1313185377Ssam void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1314185377Ssam HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1315185377Ssam uint32_t size, u_int flags); 1316185377Ssam HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1317185377Ssam struct ath_desc *, uint32_t phyAddr, 1318185377Ssam struct ath_desc *next, uint64_t tsf, 1319185377Ssam struct ath_rx_status *); 1320185377Ssam void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1321187831Ssam const HAL_NODE_STATS *, 1322187831Ssam const struct ieee80211_channel *); 1323217684Sadrian void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1324217684Sadrian const struct ieee80211_channel *); 1325185377Ssam void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1326185377Ssam const HAL_NODE_STATS *); 1327185377Ssam 1328185377Ssam /* Misc Functions */ 1329185377Ssam HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1330185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1331185377Ssam uint32_t *result); 1332185377Ssam HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1333185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 1334185377Ssam uint32_t setting, HAL_STATUS *); 1335185377Ssam HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1336185377Ssam const void *args, uint32_t argsize, 1337185377Ssam void **result, uint32_t *resultsize); 1338185377Ssam void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1339185377Ssam HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1340185377Ssam void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1341185377Ssam HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1342185377Ssam HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1343185377Ssam uint16_t, HAL_STATUS *); 1344185377Ssam void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1345185377Ssam void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1346185377Ssam const uint8_t *bssid, uint16_t assocId); 1347188974Ssam HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1348188974Ssam uint32_t gpio, HAL_GPIO_MUX_TYPE); 1349185377Ssam HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1350185377Ssam uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1351185377Ssam HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1352185377Ssam uint32_t gpio, uint32_t val); 1353185377Ssam void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1354185377Ssam uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1355185377Ssam uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1356243424Sadrian void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1357185377Ssam void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1358185377Ssam HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1359185377Ssam void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1360185377Ssam HAL_MIB_STATS*); 1361185377Ssam HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1362185377Ssam u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1363185377Ssam void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1364185377Ssam HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1365185377Ssam HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1366185377Ssam HAL_ANT_SETTING); 1367185377Ssam HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1368185377Ssam u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1369185377Ssam HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1370185377Ssam u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1371185377Ssam HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1372185377Ssam u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1373185377Ssam HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1374185377Ssam u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1375185377Ssam HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1376185377Ssam u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1377185377Ssam HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1378185377Ssam void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1379222644Sadrian HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1380222644Sadrian uint32_t duration, uint32_t nextStart, 1381222644Sadrian HAL_QUIET_FLAG flag); 1382247286Sadrian void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1383247286Sadrian uint32_t, uint32_t); 1384185377Ssam 1385222584Sadrian /* DFS functions */ 1386222584Sadrian void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1387222584Sadrian HAL_PHYERR_PARAM *pe); 1388222584Sadrian void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1389222584Sadrian HAL_PHYERR_PARAM *pe); 1390239638Sadrian HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1391239638Sadrian HAL_PHYERR_PARAM *pe); 1392222815Sadrian HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1393222815Sadrian struct ath_rx_status *rxs, uint64_t fulltsf, 1394222815Sadrian const char *buf, HAL_DFS_EVENT *event); 1395224709Sadrian HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1396222584Sadrian 1397244854Sadrian /* Spectral Scan functions */ 1398244854Sadrian void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1399244854Sadrian HAL_SPECTRAL_PARAM *sp); 1400244854Sadrian void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1401244854Sadrian HAL_SPECTRAL_PARAM *sp); 1402244854Sadrian void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1403244854Sadrian void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1404244854Sadrian HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1405244854Sadrian HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1406244854Sadrian /* XXX getNfPri() and getNfExt() */ 1407244854Sadrian 1408185377Ssam /* Key Cache Functions */ 1409185377Ssam uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1410185377Ssam HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1411185377Ssam HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1412185377Ssam uint16_t); 1413185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1414185377Ssam uint16_t, const HAL_KEYVAL *, 1415185377Ssam const uint8_t *, int); 1416185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1417185377Ssam uint16_t, const uint8_t *); 1418185377Ssam 1419185377Ssam /* Power Management Functions */ 1420185377Ssam HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1421185377Ssam HAL_POWER_MODE mode, int setChip); 1422185377Ssam HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1423187831Ssam int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1424187831Ssam const struct ieee80211_channel *); 1425185377Ssam 1426185377Ssam /* Beacon Management Functions */ 1427185377Ssam void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1428185377Ssam const HAL_BEACON_TIMERS *); 1429185377Ssam /* NB: deprecated, use ah_setBeaconTimers instead */ 1430185377Ssam void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1431185377Ssam uint32_t nexttbtt, uint32_t intval); 1432185377Ssam void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1433185377Ssam const HAL_BEACON_STATE *); 1434185377Ssam void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1435225444Sadrian uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1436185377Ssam 1437218066Sadrian /* 802.11n Functions */ 1438218066Sadrian HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1439239053Sadrian struct ath_desc *, 1440239053Sadrian HAL_DMA_ADDR *bufAddrList, 1441239053Sadrian uint32_t *segLenList, 1442239053Sadrian u_int, u_int, HAL_PKT_TYPE, 1443239053Sadrian u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1444233895Sadrian HAL_BOOL, HAL_BOOL); 1445218066Sadrian HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1446218066Sadrian struct ath_desc *, u_int, u_int, u_int, 1447218066Sadrian u_int, u_int, u_int, u_int, u_int); 1448218066Sadrian HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1449218066Sadrian struct ath_desc *, const struct ath_desc *); 1450218066Sadrian void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1451218066Sadrian struct ath_desc *, u_int, u_int, 1452218066Sadrian HAL_11N_RATE_SERIES [], u_int, u_int); 1453242407Sadrian 1454242407Sadrian /* 1455242407Sadrian * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1456242407Sadrian * to the EDMA HAL. Descriptors are chained together by 1457242407Sadrian * using filltxdesc (not ChainTxDesc) and then setting the 1458242407Sadrian * aggregate flags appropriately using first/middle/last. 1459242407Sadrian */ 1460242407Sadrian void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1461242407Sadrian void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1462242407Sadrian u_int); 1463226767Sadrian void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1464242509Sadrian struct ath_desc *, u_int, u_int); 1465218066Sadrian void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1466218066Sadrian struct ath_desc *, u_int); 1467226767Sadrian void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1468226767Sadrian struct ath_desc *); 1469218066Sadrian void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1470218066Sadrian struct ath_desc *); 1471218066Sadrian void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1472218066Sadrian struct ath_desc *, u_int); 1473247774Sadrian void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1474247774Sadrian struct ath_desc *, u_int); 1475247774Sadrian 1476234873Sadrian HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1477234873Sadrian HAL_SURVEY_SAMPLE *); 1478227374Sadrian 1479218066Sadrian uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1480218066Sadrian void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1481218066Sadrian HAL_HT_MACMODE); 1482218066Sadrian HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1483218066Sadrian void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1484218066Sadrian HAL_HT_RXCLEAR); 1485218066Sadrian 1486185377Ssam /* Interrupt functions */ 1487185377Ssam HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1488185377Ssam HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1489185377Ssam HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1490185377Ssam HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1491243840Sadrian 1492243840Sadrian /* Bluetooth Coexistence functions */ 1493243840Sadrian void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1494243840Sadrian HAL_BT_COEX_INFO *); 1495243840Sadrian void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1496243840Sadrian HAL_BT_COEX_CONFIG *); 1497243840Sadrian void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1498243840Sadrian int); 1499243840Sadrian void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1500243840Sadrian uint32_t); 1501243840Sadrian void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1502243840Sadrian uint32_t); 1503251483Sadrian void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1504243840Sadrian uint32_t, uint32_t); 1505243840Sadrian void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1506243840Sadrian int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1507251655Sadrian 1508277275Sadrian /* Bluetooth MCI methods */ 1509277275Sadrian void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1510277275Sadrian uint32_t, void *, uint16_t, uint32_t); 1511277275Sadrian HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1512277275Sadrian uint8_t, uint32_t, uint32_t *, uint8_t, 1513277275Sadrian HAL_BOOL, HAL_BOOL); 1514277275Sadrian uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1515277275Sadrian uint32_t *, uint32_t *); 1516301043Sadrian uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1517277275Sadrian uint32_t, uint32_t *); 1518277275Sadrian void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1519277275Sadrian 1520251655Sadrian /* LNA diversity configuration */ 1521251655Sadrian void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1522251655Sadrian HAL_ANT_COMB_CONFIG *); 1523251655Sadrian void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1524251655Sadrian HAL_ANT_COMB_CONFIG *); 1525185377Ssam}; 1526185377Ssam 1527185377Ssam/* 1528185377Ssam * Check the PCI vendor ID and device ID against Atheros' values 1529185377Ssam * and return a printable description for any Atheros hardware. 1530185377Ssam * AH_NULL is returned if the ID's do not describe Atheros hardware. 1531185377Ssam */ 1532185377Ssamextern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1533185377Ssam 1534185377Ssam/* 1535185377Ssam * Attach the HAL for use with the specified device. The device is 1536185377Ssam * defined by the PCI device ID. The caller provides an opaque pointer 1537185377Ssam * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1538185377Ssam * HAL state block for later use. Hardware register accesses are done 1539185377Ssam * using the specified bus tag and handle. On successful return a 1540185377Ssam * reference to a state block is returned that must be supplied in all 1541185377Ssam * subsequent HAL calls. Storage associated with this reference is 1542185377Ssam * dynamically allocated and must be freed by calling the ah_detach 1543185377Ssam * method when the client is done. If the attach operation fails a 1544185377Ssam * null (AH_NULL) reference will be returned and a status code will 1545185377Ssam * be returned if the status parameter is non-zero. 1546185377Ssam */ 1547185377Ssamextern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1548272292Sadrian HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1549272292Sadrian HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1550185377Ssam 1551188968Ssamextern const char *ath_hal_mac_name(struct ath_hal *); 1552188968Ssamextern const char *ath_hal_rf_name(struct ath_hal *); 1553188968Ssam 1554185377Ssam/* 1555187831Ssam * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1556187831Ssam * request a set of channels for a particular country code and/or 1557187831Ssam * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1558187831Ssam * this list is constructed according to the contents of the EEPROM. 1559187831Ssam * ath_hal_getchannels acts similarly but does not alter the operating 1560187831Ssam * state; this can be used to collect information for a particular 1561187831Ssam * regulatory configuration. Finally ath_hal_set_channels installs a 1562187831Ssam * channel list constructed outside the driver. The HAL will adopt the 1563187831Ssam * channel list and setup internal state according to the specified 1564187831Ssam * regulatory configuration (e.g. conformance test limits). 1565185377Ssam * 1566187831Ssam * For all interfaces the channel list is returned in the supplied array. 1567187831Ssam * maxchans defines the maximum size of this array. nchans contains the 1568187831Ssam * actual number of channels returned. If a problem occurred then a 1569187831Ssam * status code != HAL_OK is returned. 1570185377Ssam */ 1571187831Ssamstruct ieee80211_channel; 1572185377Ssam 1573185377Ssam/* 1574187831Ssam * Return a list of channels according to the specified regulatory. 1575185377Ssam */ 1576187831Ssamextern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1577187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1578187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1579187831Ssam HAL_BOOL enableExtendedChannels); 1580185377Ssam 1581185377Ssam/* 1582187831Ssam * Return a list of channels and install it as the current operating 1583187831Ssam * regulatory list. 1584185377Ssam */ 1585187831Ssamextern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1586187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1587187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1588187831Ssam HAL_BOOL enableExtendedChannels); 1589185377Ssam 1590185377Ssam/* 1591187831Ssam * Install the list of channels as the current operating regulatory 1592187831Ssam * and setup related state according to the country code and sku. 1593185377Ssam */ 1594187831Ssamextern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1595187831Ssam struct ieee80211_channel *chans, int nchans, 1596187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1597185377Ssam 1598185377Ssam/* 1599220443Sadrian * Fetch the ctl/ext noise floor values reported by a MIMO 1600220443Sadrian * radio. Returns 1 for valid results, 0 for invalid channel. 1601220443Sadrian */ 1602220443Sadrianextern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1603220444Sadrian const struct ieee80211_channel *chan, int16_t *nf_ctl, 1604220444Sadrian int16_t *nf_ext); 1605220443Sadrian 1606220443Sadrian/* 1607187831Ssam * Calibrate noise floor data following a channel scan or similar. 1608187831Ssam * This must be called prior retrieving noise floor data. 1609185377Ssam */ 1610187831Ssamextern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1611185377Ssam 1612185377Ssam/* 1613187831Ssam * Return bit mask of wireless modes supported by the hardware. 1614185377Ssam */ 1615187831Ssamextern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1616185377Ssam 1617185377Ssam/* 1618239634Sadrian * Get the HAL wireless mode for the given channel. 1619239634Sadrian */ 1620239635Sadrianextern int ath_hal_get_curmode(struct ath_hal *ah, 1621239634Sadrian const struct ieee80211_channel *chan); 1622239634Sadrian 1623239634Sadrian/* 1624218011Sadrian * Calculate the packet TX time for a legacy or 11n frame 1625185377Ssam */ 1626218011Sadrianextern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1627218011Sadrian const HAL_RATE_TABLE *rates, uint32_t frameLen, 1628218011Sadrian uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1629218011Sadrian 1630218011Sadrian/* 1631218011Sadrian * Calculate the duration of an 11n frame. 1632218011Sadrian */ 1633218011Sadrianextern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1634218011Sadrian int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1635218011Sadrian 1636218011Sadrian/* 1637218011Sadrian * Calculate the transmit duration of a legacy frame. 1638218011Sadrian */ 1639187831Ssamextern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1640187831Ssam const HAL_RATE_TABLE *rates, uint32_t frameLen, 1641187831Ssam uint16_t rateix, HAL_BOOL shortPreamble); 1642225444Sadrian 1643225444Sadrian/* 1644225444Sadrian * Adjust the TSF. 1645225444Sadrian */ 1646225444Sadrianextern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1647225444Sadrian 1648225444Sadrian/* 1649225444Sadrian * Enable or disable CCA. 1650225444Sadrian */ 1651225444Sadrianvoid __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1652225444Sadrian 1653225444Sadrian/* 1654225444Sadrian * Get CCA setting. 1655225444Sadrian */ 1656225444Sadrianint __ahdecl ath_hal_getcca(struct ath_hal *ah); 1657225444Sadrian 1658230147Sadrian/* 1659230147Sadrian * Read EEPROM data from ah_eepromdata 1660230147Sadrian */ 1661230147SadrianHAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1662230147Sadrian u_int off, uint16_t *data); 1663230147Sadrian 1664239606Sadrian/* 1665239606Sadrian * For now, simply pass through MFP frames. 1666239606Sadrian */ 1667239606Sadrianstatic inline u_int32_t 1668239606Sadrianath_hal_get_mfp_qos(struct ath_hal *ah) 1669239606Sadrian{ 1670239606Sadrian //return AH_PRIVATE(ah)->ah_mfp_qos; 1671239606Sadrian return HAL_MFP_QOSDATA; 1672239606Sadrian} 1673239606Sadrian 1674185377Ssam#endif /* _ATH_AH_H_ */ 1675