1162413Ssam/*- 2178354Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3162413Ssam * All rights reserved. 4162413Ssam * 5162413Ssam * Redistribution and use in source and binary forms, with or without 6162413Ssam * modification, are permitted provided that the following conditions 7162413Ssam * are met: 8162413Ssam * 1. Redistributions of source code must retain the above copyright 9162413Ssam * notice, this list of conditions and the following disclaimer, 10162413Ssam * without modification. 11162413Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12162413Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13162413Ssam * redistribution must be conditioned upon including a substantially 14162413Ssam * similar Disclaimer requirement for further binary redistribution. 15162413Ssam * 16162413Ssam * NO WARRANTY 17162413Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18162413Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19162413Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20162413Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21162413Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22162413Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23162413Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24162413Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25162413Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26162413Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27162413Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28162413Ssam * 29162413Ssam * $FreeBSD$ 30162413Ssam */ 31162413Ssam#ifndef _ATH_AH_OSDEP_H_ 32162413Ssam#define _ATH_AH_OSDEP_H_ 33162413Ssam/* 34162413Ssam * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35162413Ssam */ 36185522Ssam#include <sys/cdefs.h> 37162413Ssam#include <sys/param.h> 38162413Ssam#include <sys/systm.h> 39162413Ssam#include <sys/endian.h> 40185522Ssam#include <sys/linker_set.h> 41162413Ssam 42162413Ssam#include <machine/bus.h> 43162413Ssam 44162413Ssam/* 45185522Ssam * Bus i/o type definitions. 46185522Ssam */ 47185522Ssamtypedef void *HAL_SOFTC; 48185522Ssamtypedef bus_space_tag_t HAL_BUS_TAG; 49185522Ssamtypedef bus_space_handle_t HAL_BUS_HANDLE; 50185522Ssam 51185522Ssam/* 52239051Sadrian * Although the underlying hardware may support 64 bit DMA, the 53239051Sadrian * current Atheros hardware only supports 32 bit addressing. 54239051Sadrian */ 55239051Sadriantypedef uint32_t HAL_DMA_ADDR; 56239051Sadrian 57239051Sadrian/* 58185522Ssam * Linker set writearounds for chip and RF backend registration. 59185522Ssam */ 60185522Ssam#define OS_DATA_SET(set, item) DATA_SET(set, item) 61185522Ssam#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 62185522Ssam#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 63185522Ssam 64185522Ssam/* 65162413Ssam * Delay n microseconds. 66162413Ssam */ 67191909Ssam#define OS_DELAY(_n) DELAY(_n) 68162413Ssam 69162413Ssam#define OS_INLINE __inline 70191909Ssam#define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 71191909Ssam#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 72237865Sadrian#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l)) 73162413Ssam 74162413Ssam#define abs(_a) __builtin_abs(_a) 75162413Ssam 76162413Ssamstruct ath_hal; 77162413Ssam 78162413Ssam/* 79195418Ssam * The hardware registers are native little-endian byte order. 80195418Ssam * Big-endian hosts are handled by enabling hardware byte-swap 81195418Ssam * of register reads and writes at reset. But the PCI clock 82195418Ssam * domain registers are not byte swapped! Thus, on big-endian 83195418Ssam * platforms we have to explicitly byte-swap those registers. 84195418Ssam * OS_REG_UNSWAPPED identifies the registers that need special handling. 85234663Sadrian * 86234663Sadrian * This is not currently used by the FreeBSD HAL osdep code; the HAL 87234663Sadrian * currently does not configure hardware byteswapping for register space 88234663Sadrian * accesses and instead does it through the FreeBSD bus space code. 89195418Ssam */ 90195418Ssam#if _BYTE_ORDER == _BIG_ENDIAN 91195418Ssam#define OS_REG_UNSWAPPED(_reg) \ 92195418Ssam (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 93195418Ssam ((_reg) >= 0x7000 && (_reg) < 0x8000)) 94195418Ssam#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 95195418Ssam#define OS_REG_UNSWAPPED(_reg) (0) 96195418Ssam#endif /* _BYTE_ORDER */ 97195418Ssam 98195418Ssam/* 99234664Sadrian * For USB/SDIO support (where access latencies are quite high); 100234664Sadrian * some write accesses may be buffered and then flushed when 101234664Sadrian * either a read is done, or an explicit flush is done. 102234664Sadrian * 103234664Sadrian * These are simply placeholders for now. 104234664Sadrian */ 105234664Sadrian#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \ 106234664Sadrian do { } while (0) 107234664Sadrian#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \ 108234664Sadrian do { } while (0) 109234664Sadrian#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \ 110234664Sadrian do { } while (0) 111234664Sadrian 112234664Sadrian/* 113293050Sadrian * Read and write barriers. Some platforms require more strongly ordered 114293050Sadrian * operations and unfortunately most of the HAL is written assuming everything 115293050Sadrian * is either an x86 or the bus layer will do the barriers for you. 116293050Sadrian * 117293050Sadrian * Read barriers should occur before each read, and write barriers 118293050Sadrian * occur after each write. 119293050Sadrian * 120293050Sadrian * Later on for SDIO/USB parts we will methodize this and make them no-ops; 121293050Sadrian * register accesses will go via USB commands. 122293050Sadrian */ 123293050Sadrian#define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ 124293050Sadrian#define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE 125293050Sadrian#define OS_BUS_BARRIER_RW \ 126293050Sadrian (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 127293050Sadrian#define OS_BUS_BARRIER(_ah, _start, _len, _t) \ 128293050Sadrian bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \ 129293050Sadrian (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t)) 130293050Sadrian#define OS_BUS_BARRIER_REG(_ah, _reg, _t) \ 131293050Sadrian OS_BUS_BARRIER((_ah), (_reg), 4, (_t)) 132293050Sadrian 133293050Sadrian/* 134293111Sadrian * Register read/write operations are handled through 135293111Sadrian * platform-dependent routines. 136162413Ssam */ 137162413Ssam#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 138162413Ssam#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 139162413Ssam 140162413Ssamextern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 141162413Ssamextern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 142162413Ssam 143162413Ssam#ifdef AH_DEBUG_ALQ 144162413Ssamextern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 145162413Ssam#else 146162413Ssam#define OS_MARK(_ah, _id, _v) 147162413Ssam#endif 148162413Ssam 149162413Ssam#endif /* _ATH_AH_OSDEP_H_ */ 150