1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
29 * $FreeBSD$
30 */
31#ifndef _ATH_AH_OSDEP_H_
32#define _ATH_AH_OSDEP_H_
33/*
34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
35 */
36#include <sys/cdefs.h>
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/endian.h>
40#include <sys/linker_set.h>
41
42#include <machine/bus.h>
43
44/*
45 * Bus i/o type definitions.
46 */
47typedef void *HAL_SOFTC;
48typedef bus_space_tag_t HAL_BUS_TAG;
49typedef bus_space_handle_t HAL_BUS_HANDLE;
50
51/*
52 * Although the underlying hardware may support 64 bit DMA, the
53 * current Atheros hardware only supports 32 bit addressing.
54 */
55typedef uint32_t HAL_DMA_ADDR;
56
57/*
58 * Linker set writearounds for chip and RF backend registration.
59 */
60#define	OS_DATA_SET(set, item)	DATA_SET(set, item)
61#define	OS_SET_DECLARE(set, ptype)	SET_DECLARE(set, ptype)
62#define	OS_SET_FOREACH(pvar, set)	SET_FOREACH(pvar, set)
63
64/*
65 * Delay n microseconds.
66 */
67#define	OS_DELAY(_n)	DELAY(_n)
68
69#define	OS_INLINE	__inline
70#define	OS_MEMZERO(_a, _n)	bzero((_a), (_n))
71#define	OS_MEMCPY(_d, _s, _n)	memcpy(_d,_s,_n)
72#define	OS_MEMCMP(_a, _b, _l)	memcmp((_a), (_b), (_l))
73
74#define	abs(_a)		__builtin_abs(_a)
75
76struct ath_hal;
77
78/*
79 * The hardware registers are native little-endian byte order.
80 * Big-endian hosts are handled by enabling hardware byte-swap
81 * of register reads and writes at reset.  But the PCI clock
82 * domain registers are not byte swapped!  Thus, on big-endian
83 * platforms we have to explicitly byte-swap those registers.
84 * OS_REG_UNSWAPPED identifies the registers that need special handling.
85 *
86 * This is not currently used by the FreeBSD HAL osdep code; the HAL
87 * currently does not configure hardware byteswapping for register space
88 * accesses and instead does it through the FreeBSD bus space code.
89 */
90#if _BYTE_ORDER == _BIG_ENDIAN
91#define	OS_REG_UNSWAPPED(_reg) \
92	(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
93	 ((_reg) >= 0x7000 && (_reg) < 0x8000))
94#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
95#define	OS_REG_UNSWAPPED(_reg)	(0)
96#endif /* _BYTE_ORDER */
97
98/*
99 * For USB/SDIO support (where access latencies are quite high);
100 * some write accesses may be buffered and then flushed when
101 * either a read is done, or an explicit flush is done.
102 *
103 * These are simply placeholders for now.
104 */
105#define	OS_REG_WRITE_BUFFER_ENABLE(_ah)		\
106	    do { } while (0)
107#define	OS_REG_WRITE_BUFFER_DISABLE(_ah)	\
108	    do { } while (0)
109#define	OS_REG_WRITE_BUFFER_FLUSH(_ah)		\
110	    do { } while (0)
111
112/*
113 * Read and write barriers.  Some platforms require more strongly ordered
114 * operations and unfortunately most of the HAL is written assuming everything
115 * is either an x86 or the bus layer will do the barriers for you.
116 *
117 * Read barriers should occur before each read, and write barriers
118 * occur after each write.
119 *
120 * Later on for SDIO/USB parts we will methodize this and make them no-ops;
121 * register accesses will go via USB commands.
122 */
123#define	OS_BUS_BARRIER_READ	BUS_SPACE_BARRIER_READ
124#define	OS_BUS_BARRIER_WRITE	BUS_SPACE_BARRIER_WRITE
125#define	OS_BUS_BARRIER_RW \
126	    (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
127#define	OS_BUS_BARRIER(_ah, _start, _len, _t) \
128	bus_space_barrier((bus_space_tag_t)(_ah)->ah_st,	\
129	    (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
130#define	OS_BUS_BARRIER_REG(_ah, _reg, _t) \
131	OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
132
133/*
134 * Register read/write operations are handled through
135 * platform-dependent routines.
136 */
137#define	OS_REG_WRITE(_ah, _reg, _val)	ath_hal_reg_write(_ah, _reg, _val)
138#define	OS_REG_READ(_ah, _reg)		ath_hal_reg_read(_ah, _reg)
139
140extern	void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
141extern	u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
142
143#ifdef AH_DEBUG_ALQ
144extern	void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
145#else
146#define	OS_MARK(_ah, _id, _v)
147#endif
148
149#endif /* _ATH_AH_OSDEP_H_ */
150