ah_osdep.c revision 220367
1/*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/ah_osdep.c 220367 2011-04-05 16:14:54Z adrian $ 30 */ 31#include "opt_ah.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/sysctl.h> 38#include <sys/bus.h> 39#include <sys/malloc.h> 40#include <sys/proc.h> 41 42#include <machine/stdarg.h> 43 44#include <net/ethernet.h> /* XXX for ether_sprintf */ 45 46#include <dev/ath/ath_hal/ah.h> 47 48/* 49 * WiSoC boards overload the bus tag with information about the 50 * board layout. We must extract the bus space tag from that 51 * indirect structure. For everyone else the tag is passed in 52 * directly. 53 * XXX cache indirect ref privately 54 */ 55#ifdef AH_SUPPORT_AR5312 56#define BUSTAG(ah) \ 57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag) 58#else 59#define BUSTAG(ah) ((ah)->ah_st) 60#endif 61 62extern void ath_hal_printf(struct ath_hal *, const char*, ...) 63 __printflike(2,3); 64extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 65 __printflike(2, 0); 66extern const char* ath_hal_ether_sprintf(const u_int8_t *mac); 67extern void *ath_hal_malloc(size_t); 68extern void ath_hal_free(void *); 69#ifdef AH_ASSERT 70extern void ath_hal_assert_failed(const char* filename, 71 int lineno, const char* msg); 72#endif 73#ifdef AH_DEBUG 74extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...); 75#endif /* AH_DEBUG */ 76 77/* NB: put this here instead of the driver to avoid circular references */ 78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters"); 79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters"); 80 81#ifdef AH_DEBUG 82int ath_hal_debug = 0; 83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug, 84 0, "Atheros HAL debugging printfs"); 85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug); 86#endif /* AH_DEBUG */ 87 88int ath_hal_ar5416_biasadj = 0; 89SYSCTL_INT(_hw_ath_hal, OID_AUTO, ar5416_biasadj, CTLFLAG_RW, 90 &ath_hal_ar5416_biasadj, 0, "Enable 2ghz AR5416 direction sensitivity" 91 " bias adjust"); 92 93/* NB: these are deprecated; they exist for now for compatibility */ 94int ath_hal_dma_beacon_response_time = 2; /* in TU's */ 95SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW, 96 &ath_hal_dma_beacon_response_time, 0, 97 "Atheros HAL DMA beacon response time"); 98int ath_hal_sw_beacon_response_time = 10; /* in TU's */ 99SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW, 100 &ath_hal_sw_beacon_response_time, 0, 101 "Atheros HAL software beacon response time"); 102int ath_hal_additional_swba_backoff = 0; /* in TU's */ 103SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW, 104 &ath_hal_additional_swba_backoff, 0, 105 "Atheros HAL additional SWBA backoff time"); 106 107MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data"); 108 109void* 110ath_hal_malloc(size_t size) 111{ 112 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO); 113} 114 115void 116ath_hal_free(void* p) 117{ 118 free(p, M_ATH_HAL); 119} 120 121void 122ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap) 123{ 124 vprintf(fmt, ap); 125} 126 127void 128ath_hal_printf(struct ath_hal *ah, const char* fmt, ...) 129{ 130 va_list ap; 131 va_start(ap, fmt); 132 ath_hal_vprintf(ah, fmt, ap); 133 va_end(ap); 134} 135 136const char* 137ath_hal_ether_sprintf(const u_int8_t *mac) 138{ 139 return ether_sprintf(mac); 140} 141 142#ifdef AH_DEBUG 143void 144DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 145{ 146 if (ath_hal_debug & mask) { 147 __va_list ap; 148 va_start(ap, fmt); 149 ath_hal_vprintf(ah, fmt, ap); 150 va_end(ap); 151 } 152} 153#endif /* AH_DEBUG */ 154 155#ifdef AH_DEBUG_ALQ 156/* 157 * ALQ register tracing support. 158 * 159 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 160 * writes to the file /tmp/ath_hal.log. The file format is a simple 161 * fixed-size array of records. When done logging set hw.ath.hal.alq=0 162 * and then decode the file with the arcode program (that is part of the 163 * HAL). If you start+stop tracing the data will be appended to an 164 * existing file. 165 * 166 * NB: doesn't handle multiple devices properly; only one DEVICE record 167 * is emitted and the different devices are not identified. 168 */ 169#include <sys/alq.h> 170#include <sys/pcpu.h> 171#include <dev/ath/ath_hal/ah_decode.h> 172 173static struct alq *ath_hal_alq; 174static int ath_hal_alq_emitdev; /* need to emit DEVICE record */ 175static u_int ath_hal_alq_lost; /* count of lost records */ 176static char ath_hal_logfile[MAXPATHLEN] = "/tmp/ath_hal.log"; 177 178SYSCTL_STRING(_hw_ath_hal, OID_AUTO, alq_logfile, CTLFLAG_RW, 179 &ath_hal_logfile, sizeof(kernelname), "Name of ALQ logfile"); 180 181static u_int ath_hal_alq_qsize = 64*1024; 182 183static int 184ath_hal_setlogging(int enable) 185{ 186 int error; 187 188 if (enable) { 189 error = alq_open(&ath_hal_alq, ath_hal_logfile, 190 curthread->td_ucred, ALQ_DEFAULT_CMODE, 191 sizeof (struct athregrec), ath_hal_alq_qsize); 192 ath_hal_alq_lost = 0; 193 ath_hal_alq_emitdev = 1; 194 printf("ath_hal: logging to %s enabled\n", 195 ath_hal_logfile); 196 } else { 197 if (ath_hal_alq) 198 alq_close(ath_hal_alq); 199 ath_hal_alq = NULL; 200 printf("ath_hal: logging disabled\n"); 201 error = 0; 202 } 203 return (error); 204} 205 206static int 207sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS) 208{ 209 int error, enable; 210 211 enable = (ath_hal_alq != NULL); 212 error = sysctl_handle_int(oidp, &enable, 0, req); 213 if (error || !req->newptr) 214 return (error); 215 else 216 return (ath_hal_setlogging(enable)); 217} 218SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW, 219 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging"); 220SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW, 221 &ath_hal_alq_qsize, 0, "In-memory log size (#records)"); 222SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW, 223 &ath_hal_alq_lost, 0, "Register operations not logged"); 224 225static struct ale * 226ath_hal_alq_get(struct ath_hal *ah) 227{ 228 struct ale *ale; 229 230 if (ath_hal_alq_emitdev) { 231 ale = alq_get(ath_hal_alq, ALQ_NOWAIT); 232 if (ale) { 233 struct athregrec *r = 234 (struct athregrec *) ale->ae_data; 235 r->op = OP_DEVICE; 236 r->reg = 0; 237 r->val = ah->ah_devid; 238 alq_post(ath_hal_alq, ale); 239 ath_hal_alq_emitdev = 0; 240 } else 241 ath_hal_alq_lost++; 242 } 243 ale = alq_get(ath_hal_alq, ALQ_NOWAIT); 244 if (!ale) 245 ath_hal_alq_lost++; 246 return ale; 247} 248 249void 250ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) 251{ 252 bus_space_tag_t tag = BUSTAG(ah); 253 bus_space_handle_t h = ah->ah_sh; 254 255 if (ath_hal_alq) { 256 struct ale *ale = ath_hal_alq_get(ah); 257 if (ale) { 258 struct athregrec *r = (struct athregrec *) ale->ae_data; 259 r->op = OP_WRITE; 260 r->reg = reg; 261 r->val = val; 262 alq_post(ath_hal_alq, ale); 263 } 264 } 265#if _BYTE_ORDER == _BIG_ENDIAN 266 if (OS_REG_UNSWAPPED(reg)) 267 bus_space_write_4(tag, h, reg, val); 268 else 269#endif 270 bus_space_write_stream_4(tag, h, reg, val); 271} 272 273u_int32_t 274ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) 275{ 276 bus_space_tag_t tag = BUSTAG(ah); 277 bus_space_handle_t h = ah->ah_sh; 278 u_int32_t val; 279 280#if _BYTE_ORDER == _BIG_ENDIAN 281 if (OS_REG_UNSWAPPED(reg)) 282 val = bus_space_read_4(tag, h, reg); 283 else 284#endif 285 val = bus_space_read_stream_4(tag, h, reg); 286 if (ath_hal_alq) { 287 struct ale *ale = ath_hal_alq_get(ah); 288 if (ale) { 289 struct athregrec *r = (struct athregrec *) ale->ae_data; 290 r->op = OP_READ; 291 r->reg = reg; 292 r->val = val; 293 alq_post(ath_hal_alq, ale); 294 } 295 } 296 return val; 297} 298 299void 300OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v) 301{ 302 if (ath_hal_alq) { 303 struct ale *ale = ath_hal_alq_get(ah); 304 if (ale) { 305 struct athregrec *r = (struct athregrec *) ale->ae_data; 306 r->op = OP_MARK; 307 r->reg = id; 308 r->val = v; 309 alq_post(ath_hal_alq, ale); 310 } 311 } 312} 313#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) 314/* 315 * Memory-mapped device register read/write. These are here 316 * as routines when debugging support is enabled and/or when 317 * explicitly configured to use function calls. The latter is 318 * for architectures that might need to do something before 319 * referencing memory (e.g. remap an i/o window). 320 * 321 * NB: see the comments in ah_osdep.h about byte-swapping register 322 * reads and writes to understand what's going on below. 323 */ 324 325void 326ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) 327{ 328 bus_space_tag_t tag = BUSTAG(ah); 329 bus_space_handle_t h = ah->ah_sh; 330 331#if _BYTE_ORDER == _BIG_ENDIAN 332 if (OS_REG_UNSWAPPED(reg)) 333 bus_space_write_4(tag, h, reg, val); 334 else 335#endif 336 bus_space_write_stream_4(tag, h, reg, val); 337} 338 339u_int32_t 340ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) 341{ 342 bus_space_tag_t tag = BUSTAG(ah); 343 bus_space_handle_t h = ah->ah_sh; 344 u_int32_t val; 345 346#if _BYTE_ORDER == _BIG_ENDIAN 347 if (OS_REG_UNSWAPPED(reg)) 348 val = bus_space_read_4(tag, h, reg); 349 else 350#endif 351 val = bus_space_read_stream_4(tag, h, reg); 352 return val; 353} 354#endif /* AH_DEBUG || AH_REGOPS_FUNC */ 355 356#ifdef AH_ASSERT 357void 358ath_hal_assert_failed(const char* filename, int lineno, const char *msg) 359{ 360 printf("Atheros HAL assertion failure: %s: line %u: %s\n", 361 filename, lineno, msg); 362 panic("ath_hal_assert"); 363} 364#endif /* AH_ASSERT */ 365