ata-all.c revision 286448
1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/ata-all.c 286448 2015-08-08 11:48:11Z mav $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/ata.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/endian.h> 36#include <sys/ctype.h> 37#include <sys/conf.h> 38#include <sys/bus.h> 39#include <sys/bio.h> 40#include <sys/malloc.h> 41#include <sys/sysctl.h> 42#include <sys/sema.h> 43#include <sys/taskqueue.h> 44#include <vm/uma.h> 45#include <machine/stdarg.h> 46#include <machine/resource.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <dev/ata/ata-all.h> 50#include <dev/pci/pcivar.h> 51#include <ata_if.h> 52 53#include <cam/cam.h> 54#include <cam/cam_ccb.h> 55#include <cam/cam_sim.h> 56#include <cam/cam_xpt_sim.h> 57#include <cam/cam_debug.h> 58 59/* prototypes */ 60static void ataaction(struct cam_sim *sim, union ccb *ccb); 61static void atapoll(struct cam_sim *sim); 62static void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 63static void ata_cam_end_transaction(device_t dev, struct ata_request *request); 64static void ata_cam_request_sense(device_t dev, struct ata_request *request); 65static int ata_check_ids(device_t dev, union ccb *ccb); 66static void ata_conn_event(void *context, int dummy); 67static void ata_init(void); 68static void ata_interrupt_locked(void *data); 69static int ata_module_event_handler(module_t mod, int what, void *arg); 70static void ata_periodic_poll(void *data); 71static int ata_str2mode(const char *str); 72static void ata_uninit(void); 73 74/* global vars */ 75MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer"); 76int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data) = NULL; 77devclass_t ata_devclass; 78uma_zone_t ata_request_zone; 79int ata_dma_check_80pin = 1; 80 81/* sysctl vars */ 82static SYSCTL_NODE(_hw, OID_AUTO, ata, CTLFLAG_RD, 0, "ATA driver parameters"); 83SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma_check_80pin, 84 CTLFLAG_RWTUN, &ata_dma_check_80pin, 0, 85 "Check for 80pin cable before setting ATA DMA mode"); 86FEATURE(ata_cam, "ATA devices are accessed through the cam(4) driver"); 87 88/* 89 * newbus device interface related functions 90 */ 91int 92ata_probe(device_t dev) 93{ 94 return (BUS_PROBE_LOW_PRIORITY); 95} 96 97int 98ata_attach(device_t dev) 99{ 100 struct ata_channel *ch = device_get_softc(dev); 101 int error, rid; 102 struct cam_devq *devq; 103 const char *res; 104 char buf[64]; 105 int i, mode; 106 107 /* check that we have a virgin channel to attach */ 108 if (ch->r_irq) 109 return EEXIST; 110 111 /* initialize the softc basics */ 112 ch->dev = dev; 113 ch->state = ATA_IDLE; 114 bzero(&ch->state_mtx, sizeof(struct mtx)); 115 mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF); 116 TASK_INIT(&ch->conntask, 0, ata_conn_event, dev); 117 for (i = 0; i < 16; i++) { 118 ch->user[i].revision = 0; 119 snprintf(buf, sizeof(buf), "dev%d.sata_rev", i); 120 if (resource_int_value(device_get_name(dev), 121 device_get_unit(dev), buf, &mode) != 0 && 122 resource_int_value(device_get_name(dev), 123 device_get_unit(dev), "sata_rev", &mode) != 0) 124 mode = -1; 125 if (mode >= 0) 126 ch->user[i].revision = mode; 127 ch->user[i].mode = 0; 128 snprintf(buf, sizeof(buf), "dev%d.mode", i); 129 if (resource_string_value(device_get_name(dev), 130 device_get_unit(dev), buf, &res) == 0) 131 mode = ata_str2mode(res); 132 else if (resource_string_value(device_get_name(dev), 133 device_get_unit(dev), "mode", &res) == 0) 134 mode = ata_str2mode(res); 135 else 136 mode = -1; 137 if (mode >= 0) 138 ch->user[i].mode = mode; 139 if (ch->flags & ATA_SATA) 140 ch->user[i].bytecount = 8192; 141 else 142 ch->user[i].bytecount = MAXPHYS; 143 ch->user[i].caps = 0; 144 ch->curr[i] = ch->user[i]; 145 if (ch->flags & ATA_SATA) { 146 if (ch->pm_level > 0) 147 ch->user[i].caps |= CTS_SATA_CAPS_H_PMREQ; 148 if (ch->pm_level > 1) 149 ch->user[i].caps |= CTS_SATA_CAPS_D_PMREQ; 150 } else { 151 if (!(ch->flags & ATA_NO_48BIT_DMA)) 152 ch->user[i].caps |= CTS_ATA_CAPS_H_DMA48; 153 } 154 } 155 callout_init(&ch->poll_callout, 1); 156 157 /* allocate DMA resources if DMA HW present*/ 158 if (ch->dma.alloc) 159 ch->dma.alloc(dev); 160 161 /* setup interrupt delivery */ 162 rid = ATA_IRQ_RID; 163 ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 164 RF_SHAREABLE | RF_ACTIVE); 165 if (!ch->r_irq) { 166 device_printf(dev, "unable to allocate interrupt\n"); 167 return ENXIO; 168 } 169 if ((error = bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 170 ata_interrupt, ch, &ch->ih))) { 171 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 172 device_printf(dev, "unable to setup interrupt\n"); 173 return error; 174 } 175 176 if (ch->flags & ATA_PERIODIC_POLL) 177 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 178 mtx_lock(&ch->state_mtx); 179 /* Create the device queue for our SIM. */ 180 devq = cam_simq_alloc(1); 181 if (devq == NULL) { 182 device_printf(dev, "Unable to allocate simq\n"); 183 error = ENOMEM; 184 goto err1; 185 } 186 /* Construct SIM entry */ 187 ch->sim = cam_sim_alloc(ataaction, atapoll, "ata", ch, 188 device_get_unit(dev), &ch->state_mtx, 1, 0, devq); 189 if (ch->sim == NULL) { 190 device_printf(dev, "unable to allocate sim\n"); 191 cam_simq_free(devq); 192 error = ENOMEM; 193 goto err1; 194 } 195 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 196 device_printf(dev, "unable to register xpt bus\n"); 197 error = ENXIO; 198 goto err2; 199 } 200 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 201 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 202 device_printf(dev, "unable to create path\n"); 203 error = ENXIO; 204 goto err3; 205 } 206 mtx_unlock(&ch->state_mtx); 207 return (0); 208 209err3: 210 xpt_bus_deregister(cam_sim_path(ch->sim)); 211err2: 212 cam_sim_free(ch->sim, /*free_devq*/TRUE); 213 ch->sim = NULL; 214err1: 215 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 216 mtx_unlock(&ch->state_mtx); 217 if (ch->flags & ATA_PERIODIC_POLL) 218 callout_drain(&ch->poll_callout); 219 return (error); 220} 221 222int 223ata_detach(device_t dev) 224{ 225 struct ata_channel *ch = device_get_softc(dev); 226 227 /* check that we have a valid channel to detach */ 228 if (!ch->r_irq) 229 return ENXIO; 230 231 /* grap the channel lock so no new requests gets launched */ 232 mtx_lock(&ch->state_mtx); 233 ch->state |= ATA_STALL_QUEUE; 234 mtx_unlock(&ch->state_mtx); 235 if (ch->flags & ATA_PERIODIC_POLL) 236 callout_drain(&ch->poll_callout); 237 238 taskqueue_drain(taskqueue_thread, &ch->conntask); 239 240 mtx_lock(&ch->state_mtx); 241 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 242 xpt_free_path(ch->path); 243 xpt_bus_deregister(cam_sim_path(ch->sim)); 244 cam_sim_free(ch->sim, /*free_devq*/TRUE); 245 ch->sim = NULL; 246 mtx_unlock(&ch->state_mtx); 247 248 /* release resources */ 249 bus_teardown_intr(dev, ch->r_irq, ch->ih); 250 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 251 ch->r_irq = NULL; 252 253 /* free DMA resources if DMA HW present*/ 254 if (ch->dma.free) 255 ch->dma.free(dev); 256 257 mtx_destroy(&ch->state_mtx); 258 return 0; 259} 260 261static void 262ata_conn_event(void *context, int dummy) 263{ 264 device_t dev = (device_t)context; 265 struct ata_channel *ch = device_get_softc(dev); 266 union ccb *ccb; 267 268 mtx_lock(&ch->state_mtx); 269 if (ch->sim == NULL) { 270 mtx_unlock(&ch->state_mtx); 271 return; 272 } 273 ata_reinit(dev); 274 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 275 return; 276 if (xpt_create_path(&ccb->ccb_h.path, NULL, 277 cam_sim_path(ch->sim), 278 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 279 xpt_free_ccb(ccb); 280 return; 281 } 282 xpt_rescan(ccb); 283 mtx_unlock(&ch->state_mtx); 284} 285 286int 287ata_reinit(device_t dev) 288{ 289 struct ata_channel *ch = device_get_softc(dev); 290 struct ata_request *request; 291 292 xpt_freeze_simq(ch->sim, 1); 293 if ((request = ch->running)) { 294 ch->running = NULL; 295 if (ch->state == ATA_ACTIVE) 296 ch->state = ATA_IDLE; 297 callout_stop(&request->callout); 298 if (ch->dma.unload) 299 ch->dma.unload(request); 300 request->result = ERESTART; 301 ata_cam_end_transaction(dev, request); 302 } 303 /* reset the controller HW, the channel and device(s) */ 304 ATA_RESET(dev); 305 /* Tell the XPT about the event */ 306 xpt_async(AC_BUS_RESET, ch->path, NULL); 307 xpt_release_simq(ch->sim, TRUE); 308 return(0); 309} 310 311int 312ata_suspend(device_t dev) 313{ 314 struct ata_channel *ch; 315 316 /* check for valid device */ 317 if (!dev || !(ch = device_get_softc(dev))) 318 return ENXIO; 319 320 if (ch->flags & ATA_PERIODIC_POLL) 321 callout_drain(&ch->poll_callout); 322 mtx_lock(&ch->state_mtx); 323 xpt_freeze_simq(ch->sim, 1); 324 while (ch->state != ATA_IDLE) 325 msleep(ch, &ch->state_mtx, PRIBIO, "atasusp", hz/100); 326 mtx_unlock(&ch->state_mtx); 327 return(0); 328} 329 330int 331ata_resume(device_t dev) 332{ 333 struct ata_channel *ch; 334 int error; 335 336 /* check for valid device */ 337 if (!dev || !(ch = device_get_softc(dev))) 338 return ENXIO; 339 340 mtx_lock(&ch->state_mtx); 341 error = ata_reinit(dev); 342 xpt_release_simq(ch->sim, TRUE); 343 mtx_unlock(&ch->state_mtx); 344 if (ch->flags & ATA_PERIODIC_POLL) 345 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 346 return error; 347} 348 349void 350ata_interrupt(void *data) 351{ 352 struct ata_channel *ch = (struct ata_channel *)data; 353 354 mtx_lock(&ch->state_mtx); 355 ata_interrupt_locked(data); 356 mtx_unlock(&ch->state_mtx); 357} 358 359static void 360ata_interrupt_locked(void *data) 361{ 362 struct ata_channel *ch = (struct ata_channel *)data; 363 struct ata_request *request; 364 365 /* ignore interrupt if its not for us */ 366 if (ch->hw.status && !ch->hw.status(ch->dev)) 367 return; 368 369 /* do we have a running request */ 370 if (!(request = ch->running)) 371 return; 372 373 ATA_DEBUG_RQ(request, "interrupt"); 374 375 /* safetycheck for the right state */ 376 if (ch->state == ATA_IDLE) { 377 device_printf(request->dev, "interrupt on idle channel ignored\n"); 378 return; 379 } 380 381 /* 382 * we have the HW locks, so end the transaction for this request 383 * if it finishes immediately otherwise wait for next interrupt 384 */ 385 if (ch->hw.end_transaction(request) == ATA_OP_FINISHED) { 386 ch->running = NULL; 387 if (ch->state == ATA_ACTIVE) 388 ch->state = ATA_IDLE; 389 ata_cam_end_transaction(ch->dev, request); 390 return; 391 } 392} 393 394static void 395ata_periodic_poll(void *data) 396{ 397 struct ata_channel *ch = (struct ata_channel *)data; 398 399 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 400 ata_interrupt(ch); 401} 402 403void 404ata_print_cable(device_t dev, u_int8_t *who) 405{ 406 device_printf(dev, 407 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 408} 409 410/* 411 * misc support functions 412 */ 413void 414ata_default_registers(device_t dev) 415{ 416 struct ata_channel *ch = device_get_softc(dev); 417 418 /* fill in the defaults from whats setup already */ 419 ch->r_io[ATA_ERROR].res = ch->r_io[ATA_FEATURE].res; 420 ch->r_io[ATA_ERROR].offset = ch->r_io[ATA_FEATURE].offset; 421 ch->r_io[ATA_IREASON].res = ch->r_io[ATA_COUNT].res; 422 ch->r_io[ATA_IREASON].offset = ch->r_io[ATA_COUNT].offset; 423 ch->r_io[ATA_STATUS].res = ch->r_io[ATA_COMMAND].res; 424 ch->r_io[ATA_STATUS].offset = ch->r_io[ATA_COMMAND].offset; 425 ch->r_io[ATA_ALTSTAT].res = ch->r_io[ATA_CONTROL].res; 426 ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_CONTROL].offset; 427} 428 429void 430ata_udelay(int interval) 431{ 432 /* for now just use DELAY, the timer/sleep subsytems are not there yet */ 433 if (1 || interval < (1000000/hz) || ata_delayed_attach) 434 DELAY(interval); 435 else 436 pause("ataslp", interval/(1000000/hz)); 437} 438 439const char * 440ata_cmd2str(struct ata_request *request) 441{ 442 static char buffer[20]; 443 444 if (request->flags & ATA_R_ATAPI) { 445 switch (request->u.atapi.sense.key ? 446 request->u.atapi.saved_cmd : request->u.atapi.ccb[0]) { 447 case 0x00: return ("TEST_UNIT_READY"); 448 case 0x01: return ("REZERO"); 449 case 0x03: return ("REQUEST_SENSE"); 450 case 0x04: return ("FORMAT"); 451 case 0x08: return ("READ"); 452 case 0x0a: return ("WRITE"); 453 case 0x10: return ("WEOF"); 454 case 0x11: return ("SPACE"); 455 case 0x12: return ("INQUIRY"); 456 case 0x15: return ("MODE_SELECT"); 457 case 0x19: return ("ERASE"); 458 case 0x1a: return ("MODE_SENSE"); 459 case 0x1b: return ("START_STOP"); 460 case 0x1e: return ("PREVENT_ALLOW"); 461 case 0x23: return ("ATAPI_READ_FORMAT_CAPACITIES"); 462 case 0x25: return ("READ_CAPACITY"); 463 case 0x28: return ("READ_BIG"); 464 case 0x2a: return ("WRITE_BIG"); 465 case 0x2b: return ("LOCATE"); 466 case 0x34: return ("READ_POSITION"); 467 case 0x35: return ("SYNCHRONIZE_CACHE"); 468 case 0x3b: return ("WRITE_BUFFER"); 469 case 0x3c: return ("READ_BUFFER"); 470 case 0x42: return ("READ_SUBCHANNEL"); 471 case 0x43: return ("READ_TOC"); 472 case 0x45: return ("PLAY_10"); 473 case 0x47: return ("PLAY_MSF"); 474 case 0x48: return ("PLAY_TRACK"); 475 case 0x4b: return ("PAUSE"); 476 case 0x51: return ("READ_DISK_INFO"); 477 case 0x52: return ("READ_TRACK_INFO"); 478 case 0x53: return ("RESERVE_TRACK"); 479 case 0x54: return ("SEND_OPC_INFO"); 480 case 0x55: return ("MODE_SELECT_BIG"); 481 case 0x58: return ("REPAIR_TRACK"); 482 case 0x59: return ("READ_MASTER_CUE"); 483 case 0x5a: return ("MODE_SENSE_BIG"); 484 case 0x5b: return ("CLOSE_TRACK/SESSION"); 485 case 0x5c: return ("READ_BUFFER_CAPACITY"); 486 case 0x5d: return ("SEND_CUE_SHEET"); 487 case 0x96: return ("SERVICE_ACTION_IN"); 488 case 0xa1: return ("BLANK_CMD"); 489 case 0xa3: return ("SEND_KEY"); 490 case 0xa4: return ("REPORT_KEY"); 491 case 0xa5: return ("PLAY_12"); 492 case 0xa6: return ("LOAD_UNLOAD"); 493 case 0xad: return ("READ_DVD_STRUCTURE"); 494 case 0xb4: return ("PLAY_CD"); 495 case 0xbb: return ("SET_SPEED"); 496 case 0xbd: return ("MECH_STATUS"); 497 case 0xbe: return ("READ_CD"); 498 case 0xff: return ("POLL_DSC"); 499 } 500 } else { 501 switch (request->u.ata.command) { 502 case 0x00: return ("NOP"); 503 case 0x08: return ("DEVICE_RESET"); 504 case 0x20: return ("READ"); 505 case 0x24: return ("READ48"); 506 case 0x25: return ("READ_DMA48"); 507 case 0x26: return ("READ_DMA_QUEUED48"); 508 case 0x27: return ("READ_NATIVE_MAX_ADDRESS48"); 509 case 0x29: return ("READ_MUL48"); 510 case 0x30: return ("WRITE"); 511 case 0x34: return ("WRITE48"); 512 case 0x35: return ("WRITE_DMA48"); 513 case 0x36: return ("WRITE_DMA_QUEUED48"); 514 case 0x37: return ("SET_MAX_ADDRESS48"); 515 case 0x39: return ("WRITE_MUL48"); 516 case 0x70: return ("SEEK"); 517 case 0xa0: return ("PACKET_CMD"); 518 case 0xa1: return ("ATAPI_IDENTIFY"); 519 case 0xa2: return ("SERVICE"); 520 case 0xb0: return ("SMART"); 521 case 0xc0: return ("CFA ERASE"); 522 case 0xc4: return ("READ_MUL"); 523 case 0xc5: return ("WRITE_MUL"); 524 case 0xc6: return ("SET_MULTI"); 525 case 0xc7: return ("READ_DMA_QUEUED"); 526 case 0xc8: return ("READ_DMA"); 527 case 0xca: return ("WRITE_DMA"); 528 case 0xcc: return ("WRITE_DMA_QUEUED"); 529 case 0xe6: return ("SLEEP"); 530 case 0xe7: return ("FLUSHCACHE"); 531 case 0xea: return ("FLUSHCACHE48"); 532 case 0xec: return ("ATA_IDENTIFY"); 533 case 0xef: 534 switch (request->u.ata.feature) { 535 case 0x03: return ("SETFEATURES SET TRANSFER MODE"); 536 case 0x02: return ("SETFEATURES ENABLE WCACHE"); 537 case 0x82: return ("SETFEATURES DISABLE WCACHE"); 538 case 0xaa: return ("SETFEATURES ENABLE RCACHE"); 539 case 0x55: return ("SETFEATURES DISABLE RCACHE"); 540 } 541 sprintf(buffer, "SETFEATURES 0x%02x", 542 request->u.ata.feature); 543 return (buffer); 544 case 0xf5: return ("SECURITY_FREE_LOCK"); 545 case 0xf8: return ("READ_NATIVE_MAX_ADDRESS"); 546 case 0xf9: return ("SET_MAX_ADDRESS"); 547 } 548 } 549 sprintf(buffer, "unknown CMD (0x%02x)", request->u.ata.command); 550 return (buffer); 551} 552 553const char * 554ata_mode2str(int mode) 555{ 556 switch (mode) { 557 case -1: return "UNSUPPORTED"; 558 case ATA_PIO0: return "PIO0"; 559 case ATA_PIO1: return "PIO1"; 560 case ATA_PIO2: return "PIO2"; 561 case ATA_PIO3: return "PIO3"; 562 case ATA_PIO4: return "PIO4"; 563 case ATA_WDMA0: return "WDMA0"; 564 case ATA_WDMA1: return "WDMA1"; 565 case ATA_WDMA2: return "WDMA2"; 566 case ATA_UDMA0: return "UDMA16"; 567 case ATA_UDMA1: return "UDMA25"; 568 case ATA_UDMA2: return "UDMA33"; 569 case ATA_UDMA3: return "UDMA40"; 570 case ATA_UDMA4: return "UDMA66"; 571 case ATA_UDMA5: return "UDMA100"; 572 case ATA_UDMA6: return "UDMA133"; 573 case ATA_SA150: return "SATA150"; 574 case ATA_SA300: return "SATA300"; 575 case ATA_SA600: return "SATA600"; 576 default: 577 if (mode & ATA_DMA_MASK) 578 return "BIOSDMA"; 579 else 580 return "BIOSPIO"; 581 } 582} 583 584static int 585ata_str2mode(const char *str) 586{ 587 588 if (!strcasecmp(str, "PIO0")) return (ATA_PIO0); 589 if (!strcasecmp(str, "PIO1")) return (ATA_PIO1); 590 if (!strcasecmp(str, "PIO2")) return (ATA_PIO2); 591 if (!strcasecmp(str, "PIO3")) return (ATA_PIO3); 592 if (!strcasecmp(str, "PIO4")) return (ATA_PIO4); 593 if (!strcasecmp(str, "WDMA0")) return (ATA_WDMA0); 594 if (!strcasecmp(str, "WDMA1")) return (ATA_WDMA1); 595 if (!strcasecmp(str, "WDMA2")) return (ATA_WDMA2); 596 if (!strcasecmp(str, "UDMA0")) return (ATA_UDMA0); 597 if (!strcasecmp(str, "UDMA16")) return (ATA_UDMA0); 598 if (!strcasecmp(str, "UDMA1")) return (ATA_UDMA1); 599 if (!strcasecmp(str, "UDMA25")) return (ATA_UDMA1); 600 if (!strcasecmp(str, "UDMA2")) return (ATA_UDMA2); 601 if (!strcasecmp(str, "UDMA33")) return (ATA_UDMA2); 602 if (!strcasecmp(str, "UDMA3")) return (ATA_UDMA3); 603 if (!strcasecmp(str, "UDMA44")) return (ATA_UDMA3); 604 if (!strcasecmp(str, "UDMA4")) return (ATA_UDMA4); 605 if (!strcasecmp(str, "UDMA66")) return (ATA_UDMA4); 606 if (!strcasecmp(str, "UDMA5")) return (ATA_UDMA5); 607 if (!strcasecmp(str, "UDMA100")) return (ATA_UDMA5); 608 if (!strcasecmp(str, "UDMA6")) return (ATA_UDMA6); 609 if (!strcasecmp(str, "UDMA133")) return (ATA_UDMA6); 610 return (-1); 611} 612 613int 614ata_atapi(device_t dev, int target) 615{ 616 struct ata_channel *ch = device_get_softc(dev); 617 618 return (ch->devices & (ATA_ATAPI_MASTER << target)); 619} 620 621void 622ata_timeout(struct ata_request *request) 623{ 624 struct ata_channel *ch; 625 626 ch = device_get_softc(request->parent); 627 //request->flags |= ATA_R_DEBUG; 628 ATA_DEBUG_RQ(request, "timeout"); 629 630 /* 631 * If we have an ATA_ACTIVE request running, we flag the request 632 * ATA_R_TIMEOUT so ata_cam_end_transaction() will handle it correctly. 633 * Also, NULL out the running request so we wont loose the race with 634 * an eventual interrupt arriving late. 635 */ 636 if (ch->state == ATA_ACTIVE) { 637 request->flags |= ATA_R_TIMEOUT; 638 if (ch->dma.unload) 639 ch->dma.unload(request); 640 ch->running = NULL; 641 ch->state = ATA_IDLE; 642 ata_cam_end_transaction(ch->dev, request); 643 } 644 mtx_unlock(&ch->state_mtx); 645} 646 647static void 648ata_cam_begin_transaction(device_t dev, union ccb *ccb) 649{ 650 struct ata_channel *ch = device_get_softc(dev); 651 struct ata_request *request; 652 653 if (!(request = ata_alloc_request())) { 654 device_printf(dev, "FAILURE - out of memory in start\n"); 655 ccb->ccb_h.status = CAM_REQ_INVALID; 656 xpt_done(ccb); 657 return; 658 } 659 bzero(request, sizeof(*request)); 660 661 /* setup request */ 662 request->dev = NULL; 663 request->parent = dev; 664 request->unit = ccb->ccb_h.target_id; 665 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 666 request->data = ccb->ataio.data_ptr; 667 request->bytecount = ccb->ataio.dxfer_len; 668 request->u.ata.command = ccb->ataio.cmd.command; 669 request->u.ata.feature = ((uint16_t)ccb->ataio.cmd.features_exp << 8) | 670 (uint16_t)ccb->ataio.cmd.features; 671 request->u.ata.count = ((uint16_t)ccb->ataio.cmd.sector_count_exp << 8) | 672 (uint16_t)ccb->ataio.cmd.sector_count; 673 if (ccb->ataio.cmd.flags & CAM_ATAIO_48BIT) { 674 request->flags |= ATA_R_48BIT; 675 request->u.ata.lba = 676 ((uint64_t)ccb->ataio.cmd.lba_high_exp << 40) | 677 ((uint64_t)ccb->ataio.cmd.lba_mid_exp << 32) | 678 ((uint64_t)ccb->ataio.cmd.lba_low_exp << 24); 679 } else { 680 request->u.ata.lba = 681 ((uint64_t)(ccb->ataio.cmd.device & 0x0f) << 24); 682 } 683 request->u.ata.lba |= ((uint64_t)ccb->ataio.cmd.lba_high << 16) | 684 ((uint64_t)ccb->ataio.cmd.lba_mid << 8) | 685 (uint64_t)ccb->ataio.cmd.lba_low; 686 if (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT) 687 request->flags |= ATA_R_NEEDRESULT; 688 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 689 ccb->ataio.cmd.flags & CAM_ATAIO_DMA) 690 request->flags |= ATA_R_DMA; 691 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 692 request->flags |= ATA_R_READ; 693 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 694 request->flags |= ATA_R_WRITE; 695 if (ccb->ataio.cmd.command == ATA_READ_MUL || 696 ccb->ataio.cmd.command == ATA_READ_MUL48 || 697 ccb->ataio.cmd.command == ATA_WRITE_MUL || 698 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 699 request->transfersize = min(request->bytecount, 700 ch->curr[ccb->ccb_h.target_id].bytecount); 701 } else 702 request->transfersize = min(request->bytecount, 512); 703 } else { 704 request->data = ccb->csio.data_ptr; 705 request->bytecount = ccb->csio.dxfer_len; 706 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 707 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 708 request->u.atapi.ccb, ccb->csio.cdb_len); 709 request->flags |= ATA_R_ATAPI; 710 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 711 request->flags |= ATA_R_ATAPI16; 712 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 713 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 714 request->flags |= ATA_R_DMA; 715 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 716 request->flags |= ATA_R_READ; 717 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 718 request->flags |= ATA_R_WRITE; 719 request->transfersize = min(request->bytecount, 720 ch->curr[ccb->ccb_h.target_id].bytecount); 721 } 722 request->retries = 0; 723 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 724 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 725 request->ccb = ccb; 726 request->flags |= ATA_R_DATA_IN_CCB; 727 728 ch->running = request; 729 ch->state = ATA_ACTIVE; 730 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 731 ch->running = NULL; 732 ch->state = ATA_IDLE; 733 ata_cam_end_transaction(dev, request); 734 return; 735 } 736} 737 738static void 739ata_cam_request_sense(device_t dev, struct ata_request *request) 740{ 741 struct ata_channel *ch = device_get_softc(dev); 742 union ccb *ccb = request->ccb; 743 744 ch->requestsense = 1; 745 746 bzero(request, sizeof(*request)); 747 request->dev = NULL; 748 request->parent = dev; 749 request->unit = ccb->ccb_h.target_id; 750 request->data = (void *)&ccb->csio.sense_data; 751 request->bytecount = ccb->csio.sense_len; 752 request->u.atapi.ccb[0] = ATAPI_REQUEST_SENSE; 753 request->u.atapi.ccb[4] = ccb->csio.sense_len; 754 request->flags |= ATA_R_ATAPI; 755 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 756 request->flags |= ATA_R_ATAPI16; 757 if (ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 758 request->flags |= ATA_R_DMA; 759 request->flags |= ATA_R_READ; 760 request->transfersize = min(request->bytecount, 761 ch->curr[ccb->ccb_h.target_id].bytecount); 762 request->retries = 0; 763 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 764 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 765 request->ccb = ccb; 766 767 ch->running = request; 768 ch->state = ATA_ACTIVE; 769 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 770 ch->running = NULL; 771 ch->state = ATA_IDLE; 772 ata_cam_end_transaction(dev, request); 773 return; 774 } 775} 776 777static void 778ata_cam_process_sense(device_t dev, struct ata_request *request) 779{ 780 struct ata_channel *ch = device_get_softc(dev); 781 union ccb *ccb = request->ccb; 782 int fatalerr = 0; 783 784 ch->requestsense = 0; 785 786 if (request->flags & ATA_R_TIMEOUT) 787 fatalerr = 1; 788 if ((request->flags & ATA_R_TIMEOUT) == 0 && 789 (request->status & ATA_S_ERROR) == 0 && 790 request->result == 0) { 791 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 792 } else { 793 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 794 ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; 795 } 796 797 ata_free_request(request); 798 xpt_done(ccb); 799 /* Do error recovery if needed. */ 800 if (fatalerr) 801 ata_reinit(dev); 802} 803 804static void 805ata_cam_end_transaction(device_t dev, struct ata_request *request) 806{ 807 struct ata_channel *ch = device_get_softc(dev); 808 union ccb *ccb = request->ccb; 809 int fatalerr = 0; 810 811 if (ch->requestsense) { 812 ata_cam_process_sense(dev, request); 813 return; 814 } 815 816 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 817 if (request->flags & ATA_R_TIMEOUT) { 818 xpt_freeze_simq(ch->sim, 1); 819 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 820 ccb->ccb_h.status |= CAM_CMD_TIMEOUT | CAM_RELEASE_SIMQ; 821 fatalerr = 1; 822 } else if (request->status & ATA_S_ERROR) { 823 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 824 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 825 } else { 826 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 827 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 828 } 829 } else if (request->result == ERESTART) 830 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 831 else if (request->result != 0) 832 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 833 else 834 ccb->ccb_h.status |= CAM_REQ_CMP; 835 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP && 836 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 837 xpt_freeze_devq(ccb->ccb_h.path, 1); 838 ccb->ccb_h.status |= CAM_DEV_QFRZN; 839 } 840 if (ccb->ccb_h.func_code == XPT_ATA_IO && 841 ((request->status & ATA_S_ERROR) || 842 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT))) { 843 struct ata_res *res = &ccb->ataio.res; 844 res->status = request->status; 845 res->error = request->error; 846 res->lba_low = request->u.ata.lba; 847 res->lba_mid = request->u.ata.lba >> 8; 848 res->lba_high = request->u.ata.lba >> 16; 849 res->device = request->u.ata.lba >> 24; 850 res->lba_low_exp = request->u.ata.lba >> 24; 851 res->lba_mid_exp = request->u.ata.lba >> 32; 852 res->lba_high_exp = request->u.ata.lba >> 40; 853 res->sector_count = request->u.ata.count; 854 res->sector_count_exp = request->u.ata.count >> 8; 855 } 856 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 857 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 858 ccb->ataio.resid = 859 ccb->ataio.dxfer_len - request->donecount; 860 } else { 861 ccb->csio.resid = 862 ccb->csio.dxfer_len - request->donecount; 863 } 864 } 865 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 866 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) 867 ata_cam_request_sense(dev, request); 868 else { 869 ata_free_request(request); 870 xpt_done(ccb); 871 } 872 /* Do error recovery if needed. */ 873 if (fatalerr) 874 ata_reinit(dev); 875} 876 877static int 878ata_check_ids(device_t dev, union ccb *ccb) 879{ 880 struct ata_channel *ch = device_get_softc(dev); 881 882 if (ccb->ccb_h.target_id > ((ch->flags & ATA_NO_SLAVE) ? 0 : 1)) { 883 ccb->ccb_h.status = CAM_TID_INVALID; 884 xpt_done(ccb); 885 return (-1); 886 } 887 if (ccb->ccb_h.target_lun != 0) { 888 ccb->ccb_h.status = CAM_LUN_INVALID; 889 xpt_done(ccb); 890 return (-1); 891 } 892 return (0); 893} 894 895static void 896ataaction(struct cam_sim *sim, union ccb *ccb) 897{ 898 device_t dev, parent; 899 struct ata_channel *ch; 900 901 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ataaction func_code=%x\n", 902 ccb->ccb_h.func_code)); 903 904 ch = (struct ata_channel *)cam_sim_softc(sim); 905 dev = ch->dev; 906 switch (ccb->ccb_h.func_code) { 907 /* Common cases first */ 908 case XPT_ATA_IO: /* Execute the requested I/O operation */ 909 case XPT_SCSI_IO: 910 if (ata_check_ids(dev, ccb)) 911 return; 912 if ((ch->devices & ((ATA_ATA_MASTER | ATA_ATAPI_MASTER) 913 << ccb->ccb_h.target_id)) == 0) { 914 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 915 break; 916 } 917 if (ch->running) 918 device_printf(dev, "already running!\n"); 919 if (ccb->ccb_h.func_code == XPT_ATA_IO && 920 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 921 (ccb->ataio.cmd.control & ATA_A_RESET)) { 922 struct ata_res *res = &ccb->ataio.res; 923 924 bzero(res, sizeof(*res)); 925 if (ch->devices & (ATA_ATA_MASTER << ccb->ccb_h.target_id)) { 926 res->lba_high = 0; 927 res->lba_mid = 0; 928 } else { 929 res->lba_high = 0xeb; 930 res->lba_mid = 0x14; 931 } 932 ccb->ccb_h.status = CAM_REQ_CMP; 933 break; 934 } 935 ata_cam_begin_transaction(dev, ccb); 936 return; 937 case XPT_EN_LUN: /* Enable LUN as a target */ 938 case XPT_TARGET_IO: /* Execute target I/O request */ 939 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 940 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 941 case XPT_ABORT: /* Abort the specified CCB */ 942 /* XXX Implement */ 943 ccb->ccb_h.status = CAM_REQ_INVALID; 944 break; 945 case XPT_SET_TRAN_SETTINGS: 946 { 947 struct ccb_trans_settings *cts = &ccb->cts; 948 struct ata_cam_device *d; 949 950 if (ata_check_ids(dev, ccb)) 951 return; 952 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 953 d = &ch->curr[ccb->ccb_h.target_id]; 954 else 955 d = &ch->user[ccb->ccb_h.target_id]; 956 if (ch->flags & ATA_SATA) { 957 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 958 d->revision = cts->xport_specific.sata.revision; 959 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) { 960 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 961 d->mode = ATA_SETMODE(ch->dev, 962 ccb->ccb_h.target_id, 963 cts->xport_specific.sata.mode); 964 } else 965 d->mode = cts->xport_specific.sata.mode; 966 } 967 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 968 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 969 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 970 d->atapi = cts->xport_specific.sata.atapi; 971 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 972 d->caps = cts->xport_specific.sata.caps; 973 } else { 974 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_MODE) { 975 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 976 d->mode = ATA_SETMODE(ch->dev, 977 ccb->ccb_h.target_id, 978 cts->xport_specific.ata.mode); 979 } else 980 d->mode = cts->xport_specific.ata.mode; 981 } 982 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_BYTECOUNT) 983 d->bytecount = cts->xport_specific.ata.bytecount; 984 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_ATAPI) 985 d->atapi = cts->xport_specific.ata.atapi; 986 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_CAPS) 987 d->caps = cts->xport_specific.ata.caps; 988 } 989 ccb->ccb_h.status = CAM_REQ_CMP; 990 break; 991 } 992 case XPT_GET_TRAN_SETTINGS: 993 { 994 struct ccb_trans_settings *cts = &ccb->cts; 995 struct ata_cam_device *d; 996 997 if (ata_check_ids(dev, ccb)) 998 return; 999 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1000 d = &ch->curr[ccb->ccb_h.target_id]; 1001 else 1002 d = &ch->user[ccb->ccb_h.target_id]; 1003 cts->protocol = PROTO_UNSPECIFIED; 1004 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1005 if (ch->flags & ATA_SATA) { 1006 cts->transport = XPORT_SATA; 1007 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1008 cts->xport_specific.sata.valid = 0; 1009 cts->xport_specific.sata.mode = d->mode; 1010 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1011 cts->xport_specific.sata.bytecount = d->bytecount; 1012 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1013 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1014 cts->xport_specific.sata.revision = 1015 ATA_GETREV(dev, ccb->ccb_h.target_id); 1016 if (cts->xport_specific.sata.revision != 0xff) { 1017 cts->xport_specific.sata.valid |= 1018 CTS_SATA_VALID_REVISION; 1019 } 1020 cts->xport_specific.sata.caps = 1021 d->caps & CTS_SATA_CAPS_D; 1022 if (ch->pm_level) { 1023 cts->xport_specific.sata.caps |= 1024 CTS_SATA_CAPS_H_PMREQ; 1025 } 1026 cts->xport_specific.sata.caps &= 1027 ch->user[ccb->ccb_h.target_id].caps; 1028 } else { 1029 cts->xport_specific.sata.revision = d->revision; 1030 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1031 cts->xport_specific.sata.caps = d->caps; 1032 } 1033 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1034 cts->xport_specific.sata.atapi = d->atapi; 1035 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1036 } else { 1037 cts->transport = XPORT_ATA; 1038 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1039 cts->xport_specific.ata.valid = 0; 1040 cts->xport_specific.ata.mode = d->mode; 1041 cts->xport_specific.ata.valid |= CTS_ATA_VALID_MODE; 1042 cts->xport_specific.ata.bytecount = d->bytecount; 1043 cts->xport_specific.ata.valid |= CTS_ATA_VALID_BYTECOUNT; 1044 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1045 cts->xport_specific.ata.caps = 1046 d->caps & CTS_ATA_CAPS_D; 1047 if (!(ch->flags & ATA_NO_48BIT_DMA)) 1048 cts->xport_specific.ata.caps |= 1049 CTS_ATA_CAPS_H_DMA48; 1050 cts->xport_specific.ata.caps &= 1051 ch->user[ccb->ccb_h.target_id].caps; 1052 } else 1053 cts->xport_specific.ata.caps = d->caps; 1054 cts->xport_specific.ata.valid |= CTS_ATA_VALID_CAPS; 1055 cts->xport_specific.ata.atapi = d->atapi; 1056 cts->xport_specific.ata.valid |= CTS_ATA_VALID_ATAPI; 1057 } 1058 ccb->ccb_h.status = CAM_REQ_CMP; 1059 break; 1060 } 1061 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1062 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1063 ata_reinit(dev); 1064 ccb->ccb_h.status = CAM_REQ_CMP; 1065 break; 1066 case XPT_TERM_IO: /* Terminate the I/O process */ 1067 /* XXX Implement */ 1068 ccb->ccb_h.status = CAM_REQ_INVALID; 1069 break; 1070 case XPT_PATH_INQ: /* Path routing inquiry */ 1071 { 1072 struct ccb_pathinq *cpi = &ccb->cpi; 1073 1074 parent = device_get_parent(dev); 1075 cpi->version_num = 1; /* XXX??? */ 1076 cpi->hba_inquiry = PI_SDTR_ABLE; 1077 cpi->target_sprt = 0; 1078 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 1079 cpi->hba_eng_cnt = 0; 1080 if (ch->flags & ATA_NO_SLAVE) 1081 cpi->max_target = 0; 1082 else 1083 cpi->max_target = 1; 1084 cpi->max_lun = 0; 1085 cpi->initiator_id = 0; 1086 cpi->bus_id = cam_sim_bus(sim); 1087 if (ch->flags & ATA_SATA) 1088 cpi->base_transfer_speed = 150000; 1089 else 1090 cpi->base_transfer_speed = 3300; 1091 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1092 strncpy(cpi->hba_vid, "ATA", HBA_IDLEN); 1093 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1094 cpi->unit_number = cam_sim_unit(sim); 1095 if (ch->flags & ATA_SATA) 1096 cpi->transport = XPORT_SATA; 1097 else 1098 cpi->transport = XPORT_ATA; 1099 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1100 cpi->protocol = PROTO_ATA; 1101 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1102 cpi->maxio = ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS; 1103 if (device_get_devclass(device_get_parent(parent)) == 1104 devclass_find("pci")) { 1105 cpi->hba_vendor = pci_get_vendor(parent); 1106 cpi->hba_device = pci_get_device(parent); 1107 cpi->hba_subvendor = pci_get_subvendor(parent); 1108 cpi->hba_subdevice = pci_get_subdevice(parent); 1109 } 1110 cpi->ccb_h.status = CAM_REQ_CMP; 1111 break; 1112 } 1113 default: 1114 ccb->ccb_h.status = CAM_REQ_INVALID; 1115 break; 1116 } 1117 xpt_done(ccb); 1118} 1119 1120static void 1121atapoll(struct cam_sim *sim) 1122{ 1123 struct ata_channel *ch = (struct ata_channel *)cam_sim_softc(sim); 1124 1125 ata_interrupt_locked(ch); 1126} 1127 1128/* 1129 * module handeling 1130 */ 1131static int 1132ata_module_event_handler(module_t mod, int what, void *arg) 1133{ 1134 1135 switch (what) { 1136 case MOD_LOAD: 1137 return 0; 1138 1139 case MOD_UNLOAD: 1140 return 0; 1141 1142 default: 1143 return EOPNOTSUPP; 1144 } 1145} 1146 1147static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL }; 1148DECLARE_MODULE(ata, ata_moduledata, SI_SUB_CONFIGURE, SI_ORDER_SECOND); 1149MODULE_VERSION(ata, 1); 1150MODULE_DEPEND(ata, cam, 1, 1, 1); 1151 1152static void 1153ata_init(void) 1154{ 1155 ata_request_zone = uma_zcreate("ata_request", sizeof(struct ata_request), 1156 NULL, NULL, NULL, NULL, 0, 0); 1157} 1158SYSINIT(ata_register, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_init, NULL); 1159 1160static void 1161ata_uninit(void) 1162{ 1163 uma_zdestroy(ata_request_zone); 1164} 1165SYSUNINIT(ata_unregister, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_uninit, NULL); 1166